WO2015089997A1 - 阵列基板制作方法、膜层刻蚀监控方法及设备 - Google Patents

阵列基板制作方法、膜层刻蚀监控方法及设备 Download PDF

Info

Publication number
WO2015089997A1
WO2015089997A1 PCT/CN2014/078263 CN2014078263W WO2015089997A1 WO 2015089997 A1 WO2015089997 A1 WO 2015089997A1 CN 2014078263 W CN2014078263 W CN 2014078263W WO 2015089997 A1 WO2015089997 A1 WO 2015089997A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
etching
monitoring
active layer
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2014/078263
Other languages
English (en)
French (fr)
Inventor
刘政
任章淳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US14/402,872 priority Critical patent/US9646847B2/en
Publication of WO2015089997A1 publication Critical patent/WO2015089997A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32917—Plasma diagnostics
    • H01J37/32935—Monitoring and controlling tubes by information coming from the object and/or discharge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32917—Plasma diagnostics
    • H01J37/32935—Monitoring and controlling tubes by information coming from the object and/or discharge
    • H01J37/32972—Spectral analysis
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
    • H10P72/0604—Process monitoring, e.g. flow or thickness monitoring
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
    • H10P74/238—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes comprising acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection or in-situ thickness measurement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334—Etching
    • H01J2237/3343—Problems associated with etching

Definitions

  • Embodiments of the present invention relate to a method of fabricating an array substrate, a method and apparatus for monitoring a film layer. Background technique
  • FIG. 1 is a schematic structural view of a typical top gate structure array substrate.
  • the array substrate includes a transparent substrate 101 such as glass, a buffer layer 102, a polysilicon active layer 103, a gate insulating layer 104, a gate metal 105, and an interlayer insulating layer 106.
  • a transparent substrate 101 such as glass
  • a buffer layer 102 such as glass
  • a polysilicon active layer 103 such as glass
  • a gate insulating layer 104 such as a gate insulating layer
  • a gate metal 105 such as a substrate
  • interlayer insulating layer 106 When the via is etched, a mask is formed on the interlayer insulating layer 106 by a photolithography process, and the etched region is etched and removed by dry etching to form a via hole, which can be formed in a subsequent process.
  • a metal is deposited into the via to achieve connection to the polysilicon active layer.
  • the etching process is difficult and difficult. Effectively monitoring whether it is just etched to the surface of the polysilicon active layer causes the active layer over-etching problem to occur easily, and the manufacturing yield of the polycrystalline silicon substrate is lowered. Especially when the substrate size is large, the etching of the entire substrate is more difficult to grasp.
  • Embodiments of the present invention provide a method for fabricating an array substrate, a method and a device for monitoring a film layer, to control the degree of etching of a film layer such as an active layer, thereby avoiding over-etching and affecting the active layer. Equal film properties.
  • At least one embodiment of the present invention provides a film layer etching monitoring method, comprising: monitoring and recording a transmittance reference value of the film layer after forming a film layer pattern; forming a barrier layer on the film layer pattern Thereafter, in the process of etching the barrier layer to form via holes, the current value of the transmittance of the film layer is monitored in real time, and the change between the existing value of the transmittance and the transmittance reference value is determined. the amount To monitor the degree of etching of the film layer.
  • a plurality of transmittance values at different locations of the film layer are monitored.
  • a 9 to 25 point transmittance value for different locations of the film layer is monitored.
  • the current value of the transmittance of the film layer is monitored in real time, and the etching is stopped when the existing value of the light transmittance reaches 100% to 120% of the transmittance reference value.
  • the film layer is an active layer
  • the barrier layer is a gate insulating layer and an interlayer insulating layer.
  • the ratio of the sum of the thicknesses of the gate insulating layer and the interlayer insulating layer to the thickness of the active layer is 10:1 or more.
  • forming the active layer pattern includes: depositing an amorphous silicon layer, crystallizing the amorphous silicon to form a polysilicon layer, and forming a active layer pattern on the polysilicon layer by a patterning process.
  • monitoring and recording the transmittance reference value of the active layer includes: illuminating the active layer with a light beam, sensing transmittance of the active layer pattern, and using the transmittance as an active The transmittance of the layer is the reference value.
  • Another embodiment of the present invention further provides a method for fabricating an array substrate, comprising: forming a pattern of an active layer on a substrate, monitoring and recording a transmittance reference value of the active layer; Depositing a barrier layer and a gate electrode layer, the barrier layer includes a gate insulating layer and an interlayer insulating layer; etching the barrier layer to form a via hole, and monitoring the transmittance of the active layer in real time during the etching process Having a value, when the existing value of the transmittance reaches a predetermined value of the transmittance reference value, stopping the etching; forming a source/drain electrode layer on the substrate on which the above steps are completed, the source and drain electrodes passing through the via and the active layer Electrical connection.
  • a buffer layer is first deposited on the substrate, and then a pattern of the active layer is formed on the buffer layer.
  • Another embodiment of the present invention also provides a film etching monitoring apparatus including a chamber, and a light source and a plurality of light sensing probes disposed in the chamber, the light source illuminating a film layer on the substrate The light sensing probe is used to sense the light transmittance of the film layer.
  • the chamber is a vacuum chamber
  • the vacuum chamber is in communication with a source of reactive gas and an etching device is provided in the vacuum chamber.
  • the etching device includes: an opposite upper plate and a lower plate, wherein one plate is grounded, and the other plate is connected to a radio frequency power source, so that the upper plate and the lower plate are A plasma is formed to etch the substrate; the substrate to be etched is placed on the lower plate.
  • the light source is on the upper plate; or the light source is located on a sidewall of the vacuum chamber; or the light source is located on an upper wall of the vacuum chamber.
  • the light sensing probe is disposed on a side of the lower plate away from the substrate.
  • the number of light sensing probes is 5-25 and the light sensing probes are evenly distributed.
  • the film layer etching monitoring device further includes a radio frequency power source that uses a method of intermittent supply, the RF power source provides a radio frequency current to generate a plasma during a power supply period, and the film layer is etched and monitored. The device monitors the transmittance of the film during the power off period.
  • FIG. 1 is a schematic view of a top gate type array substrate
  • 2A-2D are schematic structural views of steps in a method of fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of an active layer etching monitoring device according to an embodiment of the present invention. detailed description
  • Embodiments of the present invention provide a film layer etching monitoring method, including: monitoring and recording a transmittance reference value of the film layer after forming a film layer pattern; forming a barrier layer on the film layer pattern, and then During the etching of the barrier layer to form via holes, the transmittance of the film layer is monitored in real time. There is a value that monitors the degree of etching of the film layer by determining the amount of change between the existing value of the light transmittance and the light transmittance reference value.
  • a plurality of transmittance values at different locations of the film layer may be monitored. For example, 9 to 25 point transmittance values at different locations of the film layer can be monitored. Of course, the number of specific locations can be determined according to actual needs.
  • the current value of the transmittance of the film layer is monitored in real time, for example, when the existing value of the light transmittance reaches 100% to 120% of the transmittance reference value, the etching is stopped.
  • the monitoring method of this embodiment is generally directed to a substrate structure having a relatively thin film layer and a relatively thick thickness of the barrier layer.
  • the film layer may be, for example, an active layer, a source/drain electrode layer or the like involved in the process of preparing a thin film transistor, and the barrier layer may be a gate insulating layer, a passivation layer or the like formed over the above film layer. Since the barrier layer is thicker than the film layer, in the process of forming the via hole by etching the barrier layer, if the monitoring means is not used, it is easy to over-etch the thin film layer underneath, thereby affecting the film layer. Normal use performance.
  • the film layer etching monitoring method provided by the embodiment of the invention can effectively monitor the etching degree of the film layer by comparing the light transmittance of the film layer in different states, so as to ensure that the film layer is not over-etched, and the film layer is ensured.
  • the performance which in turn increases the yield of the product.
  • the film layer to be monitored is taken as an active layer, and the film layer etching monitoring method will be described in detail.
  • An active layer etch monitoring method provided by an embodiment of the present invention includes the following steps.
  • Step S201 The transmittance reference value of the active layer is monitored and recorded after the active layer pattern is formed.
  • a specific example of forming an active layer pattern includes: a deposition temperature of less than 600 ° C by PECVD (plasma enhanced chemical vapor deposition), LPCVD (low pressure chemical vapor deposition) or sputtering method
  • PECVD plasma enhanced chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • sputtering method The amorphous silicon layer is deposited to a thickness of 100A to 3000A, preferably 500A to 1000A.
  • the amorphous silicon layer can then be converted into a polysilicon layer by excimer laser crystallization, metal induced crystallization, solid phase crystallization, and the like. It should be noted that the process of different crystallization methods and the structure of the thin film transistor may be different. In the preparation process, heat treatment dehydrogenation, deposition induction metal, heat treatment crystallization, excimer laser irradiation crystallization may be added according to the situation. Doping of source and drain regions (P-type or N-type doping Miscellaneous) and activation of doping impurities.
  • a mask is formed by a photolithography process, and then an active layer pattern is formed by a dry etching method.
  • an example of monitoring and recording the transmittance reference value of the active layer includes: monitoring and recording the transmittance of the polysilicon region.
  • a light beam may be irradiated onto the substrate, and the light transmittance of the active layer pattern may be induced and measured, and the light transmittance may be used as a light transmittance reference value of the active layer.
  • a plurality of data values at different positions of the active layer can be monitored, such as measuring 9 to 25 points of data. These locations can for example be hooked on the active layer.
  • Step S202 forming a barrier layer on the active layer pattern.
  • real-time monitoring the existing value of the transmittance of the active layer by determining the existing value of the transmittance and The amount of change between the transmittance reference values monitors the degree of etching of the active layer.
  • the barrier layer is selected from a plasma etching, a reactive ion etching or an inductively coupled ion etching method, and the etching gas is a fluorine-containing or chlorine-containing gas.
  • the existing value of the transmittance of the active layer is monitored in real time, for example, when the existing value of the transmittance reaches a predetermined value of the transmittance reference value (for example, 100% to 120%), it indicates that Etching to the active layer stops etching.
  • the active layer etching monitoring method provided by the embodiment of the present invention can effectively monitor the etching degree of the active layer by comparing the light transmittance of the active layer in different states, and ensure that the active layer is not excessively carved.
  • the eclipse ensures the performance of the active layer, which in turn increases the yield of the product.
  • Embodiments of the present invention provide a method of fabricating an array substrate.
  • the array substrate uses a top gate structure.
  • the method for fabricating the array substrate includes the following steps.
  • Step S301 depositing a buffer layer on the substrate.
  • a pre-cleaned, for example, glass substrate or the like is a transparent substrate 301, and is formed by PECVD, LPCVD, APCVD (Atmospheric Pressure Chemical Vapor Deposition), ECR-CVD (Electron Cyclotron Resonance Chemical Vapor Deposition) or sputtering.
  • the punch layer 302 blocks diffusion of impurities contained in the transparent substrate into the active layer formed thereafter, thereby preventing influence on characteristics such as a threshold voltage and a leakage current of the TFT element.
  • the buffer layer can be a single layer of silicon oxide, silicon nitride or a laminate of the two.
  • the layer may have a thickness of 300A to 10000A, preferably a thickness of 500 A to 4000A, and a deposition temperature of 600 ° C or lower. Degree.
  • the alkali-free glass can be used as the transparent substrate.
  • Step S302 forming a pattern of the active layer on the buffer layer, and monitoring and recording the transmittance reference value of the active layer.
  • an amorphous silicon layer 303 is deposited on the buffer layer 302 by a PEC VD, LPCVD or sputtering method at a deposition temperature of 600 ° C or less, and has a thickness of 100 A to 3000 A, preferably 500 A to 1000 A.
  • the amorphous silicon layer 303 can then be converted into a polysilicon layer by excimer laser crystallization, metal induced crystallization, solid phase crystallization, or the like. It should be noted that the process of different crystallization methods and the structure of the thin film transistor may be different. In the preparation process, heat treatment dehydrogenation, deposition induction metal, heat treatment crystallization, excimer laser irradiation crystallization, etc.
  • Doping of source and drain regions (germanium or germanium doping) and activation of dopant impurities.
  • a mask is formed by a photolithography process, and then a pattern is formed by a dry etching method as an active layer pattern of the TFT.
  • the transmittance of the polysilicon region at this time was monitored and recorded.
  • a light beam may be irradiated onto the substrate, the light transmittance of the active layer pattern may be induced, and the light transmittance may be used as a light transmittance reference value of the active layer. This value of the transmittance will be used as a reference for subsequent monitoring of the etch.
  • multiple data values at different positions are monitored, such as measuring 9 to 25 points of data.
  • Step S303 depositing a gate insulating layer, a gate electrode layer, and an interlayer insulating layer to form a back plate to be etched.
  • the gate insulating layer 304 is deposited by PECVD, LPCVD, APCVD, or ECR-CVD; then, a gate is deposited on the gate insulating layer by sputtering, thermal evaporation, or PECVD, LPCVD, APCVD, ECR-CVD, or the like.
  • the electrode layer 305 is formed by a photolithography process, and the gate electrode layer 305 is etched to form a pattern by wet etching or dry etching.
  • a suitable thickness of the gate insulating layer 304 can be selected according to the specific process requirements.
  • the gate insulating layer 304 has a thickness of 300A to 3000A.
  • the gate insulating layer 304 may be a single layer of silicon oxide, silicon nitride or a laminate of the two, and the deposition temperature is generally below 600 °C.
  • the gate electrode layer 305 is made of a conductive material such as a metal or a metal alloy such as molybdenum, molybdenum alloy or the like or doped polysilicon, and has a thickness in the range of 1000 A to 8000 A, preferably 2500 A to 4000 A.
  • the gate insulating layer is an interlayer insulating layer 306 having a thickness of 3000 A to 9000 A, preferably a thickness of 4000 A to 6000 A.
  • the interlayer insulating layer may be deposited by a deposition method such as PECVD, LPCVD, APCVD, or ECR-CVD at a deposition temperature of 600 ° C or less.
  • the interlayer insulating layer 306 may include a single layer of silicon oxide or a stack of silicon oxide and silicon nitride.
  • Step S304 forming a mask by photolithography, etching the via hole by dry etching, and monitoring the transmittance of the via hole, and when the light transmittance reaches 100% of the reference value of the transmittance of the active layer recorded before ⁇ Stop at 120%.
  • a photoresist (photoresist) mask layer 307 is formed over the interlayer insulating layer 306 by a photolithography process, and the thickness of the photoresist mask layer 307 is, for example, 10,000 A to 20,000 A.
  • the etched region can be removed by dry etching.
  • the dry etching may be plasma etching, reactive ion etching, inductively coupled plasma etching, or the like.
  • the etching gas may be a fluorine- or chlorine-containing gas such as CF 4 , CHF 3 , SF 6 , CC 1 2 F 2 or the like or a mixed gas of these gases and 0 2 .
  • the light transmittance of 9 to 25 points is monitored by the same method in step S302, and compared with the data recorded in step S302, that is, by determining the current value of the transmittance of the active layer in real time and
  • the amount of change between the transmittance reference values monitors the degree of etching of the active layer.
  • this monitoring method even when the sum of the thicknesses of the gate insulating layer and the interlayer insulating layer is very different from the thickness of the active layer (for example, the ratio of the two is 10:1 or more), it is good.
  • the degree of etching of the active layer is monitored, thereby correspondingly controlling the progress of the etching.
  • the existing value of the light transmittance reaches 100% to 120% of the previously recorded transmittance reference value, it indicates that the polysilicon layer (active layer) has been etched, and the etching can be stopped.
  • Step S305 forming a source/drain electrode layer on the substrate on which the above steps are completed, and the source/drain electrode is electrically connected to the active layer through the via hole.
  • the array substrate is fabricated by the above method, and the etching degree of the active layer can be controlled in real time to ensure that the active layer is not over-etched, thereby improving the yield of the product.
  • a buffer layer may not be formed on the surface of the substrate as needed, i.e., an active layer is directly formed on the surface of the substrate.
  • an embodiment of the present invention provides a film layer etching monitoring device including a chamber, and a light source 3 and a plurality of light sensing probes 4 disposed in the chamber, wherein the light source 3 is illuminated. a film layer on the substrate, the light sensing probe 4 is for sensing the light transmittance of the film layer.
  • the light source 3 includes, for example, a fluorescent lamp or a light emitting diode (LED), and the like, and may be a point light source, a line light source, or a surface light source, etc.
  • the light sensing probe 4 includes a photodiode or the like.
  • the film etch monitoring device can be implemented independently of the etch device and as a separate light transmittance monitoring device.
  • another embodiment of the present invention can integrate the device for monitoring light transmittance with the etching device.
  • the chamber is a vacuum chamber 1, the vacuum chamber is connected to a source of reactive gas 2, and the vacuum chamber 1 is further provided with an etching device.
  • the etching device in this embodiment is a dry etching device, which comprises an upper plate 5 and a lower plate 6 which are oppositely disposed; the upper plate 5 is grounded, the lower plate 6 is connected to the RF power source 7; and the substrate 8 is located at the lower plate 6 Above, the RF power source 7 provides a radio frequency current to generate a plasma that etches the substrate 8.
  • the light source 3 may be located above the upper plate 5 or the upper wall of the vacuum chamber 1 such that its beam is directed downward to form a vertical light source.
  • the light source 3 can also be located on the side wall of the vacuum chamber 1 so that its beam is obliquely illuminated to form a tilted light source.
  • the etching apparatus in the embodiment of the present invention may also select other dry etching equipment, such as plasma etching (PE) mode equipment, inductively coupled plasma etching (ICP) mode equipment, and the like.
  • PE plasma etching
  • ICP inductively coupled plasma etching
  • the number of the light sensing probes 4 can be set to 5 to 25, which are evenly distributed on the lower plate 6. Of course, the number of the light sensing probes 4 can be determined according to requirements. Additionally, in at least one embodiment, the apparatus further includes a flow meter 9 for controlling the amount of reactive gas flowing into the vacuum chamber 1 by the reactive gas source 2.
  • the vacuum chamber 1 is connected to a vacuum pump 10, a vacuum gauge 11 and a pressure switch 12 for maintaining and controlling the degree of vacuum in the vacuum chamber 1.
  • the reference data of the light transmittance is obtained after the dry etching in the above step S302, and then the current value of the light transmittance is detected when the dry etching is performed in step S304.
  • the current value of the light rate is compared to the baseline data.
  • At least one embodiment of the present invention also includes a radio frequency power source that utilizes an intermittent supply method.
  • the RF power source provides RF current during the power supply period to generate a plasma.
  • the film etching monitoring device of the embodiment monitors the transmittance of the film during the power-off period.
  • the etching condition is beneficial to the simple and effective control of the etching degree, and the etching can be stopped in time when etching to the active layer to ensure that the performance of the active layer is not destroyed.
  • the etching uniformity of the entire substrate can be ensured, which is advantageous for improving the yield of preparing a large-area polycrystalline silicon substrate.
  • the method for fabricating the array substrate and the method for monitoring the etching of the film layer provided by the embodiments of the present invention can effectively monitor the etching degree of the film layer by comparing the light transmittance of the film layer in different states to ensure that the film layer is not Excessive etching ensures the performance of the film layer, which in turn increases the yield of the product.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

提供一种阵列基板的制作方法、膜层刻蚀监控方法及设备。该监控方法包括：在形成膜层图形之后监测并记录所述膜层的透光率基准值；在所述膜层图形上形成阻挡层，对阻挡层进行刻蚀过孔的过程中，实时监测所述膜层的透光率现有值，通过透光率现有值和透光率基准值之间的变化量来监控对所述膜层的刻蚀程度，从而防止过度刻蚀。所述设备包括若干个光源（3）和光感探头（4），所述光源（3）向基板上的所述膜层照射，所述光感探头（4）用于感应所述膜层的透光率。

Description

阵列基板制作方法、 膜层刻蚀监控方法及设备 技术领域
本发明的实施例涉及一种阵列基板的制作方法、 膜层刻蚀监控方法及设 备。 背景技术
目前， 由于低温多晶硅显示基板相对非晶硅显示基板具有更高的驱动能 力， 可较容易获得更高的显示质量， 因此， 越来越受到用户的追捧。 图 1为 一种典型的顶栅结构阵列基板的结构示意图。 该阵列基板包括例如为玻璃等 的透明基板 101， 、 緩冲层 102， 、 多晶硅有源层 103， 、 栅极绝缘层 104， 、 栅极金属 105， 和层间绝缘层 106， 。 在刻蚀过孔时， 在层间绝缘层 106， 之 上用光刻工艺形成掩膜， 釆用干法刻蚀将带刻蚀区域刻蚀去除， 从而形成过 孔， 在后续工艺中即可沉积金属至过孔内从而实现与多晶硅有源层的连接。
由于栅极绝缘层 104' 和层间绝缘层 106' 的厚度之和与有源层的厚度差 别非常大（二者比值在 10: 1以上）， 刻蚀工艺的难度 4艮大， 而且较难有效监 测是否刚好刻蚀至多晶硅有源层表面， 导致很容易出现有源层过刻问题， 降 低了多晶硅基板的制造良率。 特别是基板尺寸较大时， 整个基板的刻蚀情况 更难以把握。
当然，除了有源层，其他膜层也存在于刻蚀过程中发生过度刻蚀的现象。 发明内容
本发明的实施例提供了一种阵列基板的制作方法、 膜层刻蚀监控方法及 设备， 以掌控对例如有源层等的膜层的刻蚀程度， 从而避免出现过刻， 影响 有源层等膜层性能。
本发明的至少一个实施例提供了一种膜层刻蚀监控方法， 包括： 在形成 膜层图形之后监测并记录所述膜层的透光率基准值； 在所述膜层图形上形成 阻挡层之后， 在对阻挡层进行刻蚀以形成过孔的过程中， 实时监测所述膜层 的透光率现有值， 以及通过确定透光率现有值和透光率基准值之间的变化量 来监控对所述膜层的刻蚀程度。
在一个实施例中， 例如， 监测所述膜层的不同位置的多个透光率值。 在一个实施例中， 例如， 监测所述膜层的不同位置的 9~25点透光率值。 在一个实施例中， 例如， 实时监测膜层的透光率现有值， 当透光率现有 值达到透光率基准值的 100%~120%时， 停止刻蚀。
在一个实施例中， 例如， 所述膜层为有源层， 所述阻挡层为栅绝缘层和 层间绝缘层。
在一个实施例中， 例如， 所述栅绝缘层和层间绝缘层的厚度之和与所述 有源层的厚度的比值在 10: 1以上。
在一个实施例中， 例如， 形成有源层图形包括： 沉积非晶硅层， 将非晶 硅晶化形成多晶硅层， 对多晶硅层釆用构图工艺形成有源层图形。
在一个实施例中， 例如， 监测并记录有源层的透光率基准值包括： 用光 束照射有源层， 感应所述有源层图形的透光率， 并将该透光率作为有源层的 透光率基准值。
本发明的另一个实施例还提供了一种阵列基板制作方法， 包括： 在基板 上形成有源层的图形， 监测并记录所述有源层的透光率基准值； 在完成上述 步骤的基板上沉积阻挡层和栅电极层， 所述阻挡层包括栅绝缘层和层间绝缘 层； 对阻挡层进行刻蚀以形成过孔， 在刻蚀过程中， 实时监测有源层的透光 率现有值， 当透光率现有值达到透光率基准值的预定值时， 停止刻蚀； 在完 成上述步骤的基板上形成源漏电极层， 所述源漏电极通过过孔与有源层电连 接。
在一个实施例中， 首先在基板上沉积緩冲层， 然后在緩冲层上形成所述 有源层的图形。
本发明的另一个实施例还提供了一种膜层刻蚀监控设备， 其包括腔室， 以及设置在所述腔室中的光源和多个光感探头，所述光源照射基板上的膜层， 所述光感探头用于感应所述膜层的透光率。
在一个实施例中， 例如， 所述腔室为真空腔室， 所述真空腔室连通反应 气体源且所述真空腔室中设有刻蚀装置。
在一个实施例中， 例如， 所述刻蚀装置包括： 相对设置的上极板和下极 板， 其中一个极板接地， 另外一个极板接射频电源， 使得上极板和下极板之 间生成对基板进行刻蚀的等离子体； 待刻蚀的基板放置在所述下极板上。 在一个实施例中， 例如， 所述光源位于所述上极板上； 或者， 所述光源 位于真空腔室的侧壁； 或者， 所述光源位于真空腔室的上壁。
在一个实施例中， 例如， 所述光感探头设置于所述下极板远离所述基板 的一侧。
在一个实施例中， 例如， 所述光感探头的数量为 5-25个且所述光感探头 均匀分布。
在一个实施例中， 例如， 所述膜层刻蚀监控设备还包括釆用间断供给的 方法的射频电源， 该射频电源在供电时间段提供射频电流以产生等离子体， 所述膜层刻蚀监控设备在断电时间段进行膜层的透光率的监测。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为一种顶栅型阵列基板示意图；
图 2A~2D 为本发明实施例的阵列基板的制作方法过程中各步骤的结构 示意图；
图 3为本发明实施例的有源层刻蚀监控设备结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图， 对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
实施例一
本发明实施例提供了一种膜层刻蚀监控方法， 包括： 在形成膜层图形之 后监测并记录所述膜层的透光率基准值； 在所述膜层图形上形成阻挡层， 之 后在对阻挡层进行刻蚀以形成过孔的过程中， 实时监测所述膜层的透光率现 有值， 通过确定透光率现有值和透光率基准值之间的变化量来监控对所述膜 层的刻蚀程度。
在本发明的实施例中， 为了确保整个基板的刻蚀均匀性， 可监测所述膜 层的不同位置的多个透光率值。 例如， 可监测所述膜层的不同位置的 9~25 点透光率值。 当然， 该具体位置的数量可根据实际需求而定。
在实际刻蚀过程中， 实时监测膜层的透光率现有值， 例如， 当透光率现 有值达到透光率基准值的 100%~120%时， 停止刻蚀。
在实际应用中， 本实施例的监控方法通常针对膜层厚度较薄， 而阻挡层 的厚度相对较厚的基板结构。 该膜层例如可以为制备薄膜晶体管的过程中涉 及的有源层、 源漏电极层等等， 而阻挡层则可能为形成在上述膜层之上的栅 绝缘层、 钝化层等。 由于阻挡层与膜层相比较厚， 这样在刻蚀阻挡层形成过 孔的过程中， 若不釆用监控手段， 则很容易将在下的较薄的膜层过刻蚀， 从 而影响该膜层的正常使用性能。
本发明的实施例提供的膜层刻蚀监控方法， 通过对比不同状态下膜层的 透光率， 可有效监控对膜层的刻蚀程度， 以确保膜层不被过度刻蚀， 确保膜 层的性能， 进而提高产品的良品率。
实施例二
下面以被监控的膜层为有源层为例， 对该膜层刻蚀监控方法进行详细说 明。
本发明的实施例提供的一种有源层刻蚀监控方法包括如下步骤。
步骤 S201 : 在形成有源层图形之后监测并记录该有源层的透光率基准 值。
在本发明的实施例中， 形成有源层图形的一个具体示例包括： 通过 PECVD (等离子体增强化学气相沉积） 、 LPCVD (低压化学气相沉积）或 者溅射方法， 在 600 °C以下的沉积温度沉积非晶硅层， 其厚度可为 100A ~ 3000A, 优选厚度为 500A ~ 1000A。
随后可通过准分子激光晶化、 金属诱导晶化、 固相晶化等方法将非晶硅 层转变为多晶硅层。 需要注意的是， 不同的晶化方法的工艺过程及薄膜晶体 管的结构会有所不同， 在制备过程中可根据情况增加热处理脱氢、 沉积诱导 金属、 热处理晶化、 准分子激光照射晶化、 源漏区的掺杂（P型或者 N型掺 杂）及掺杂杂质的激活等工艺。
将非晶硅转化为多晶硅层之后以光刻工艺形成掩膜， 继而釆用干法刻蚀 方法形成有源层图形。
在本发明的实施例中， 监测并记录该有源层的透光率基准值的一个示例 包括： 监测并记录多晶硅区域的透光率。 例如， 可向基板照射光束， 感应并 测量所述有源层图形的透光率， 并将该透光率作为有源层的透光率基准值。 为了确保整个基板的刻蚀均匀性，可监测该有源层的不同位置的多个数据值， 如测量 9~25点数据。 这些位置例如可均勾分别在有源层上。
步骤 S202: 在有源层图形上形成阻挡层， 在对阻挡层进行刻蚀以形成过 孔的过程中， 实时监测有源层的透光率现有值， 通过确定透光率现有值和透 光率基准值之间的变化量来监控对有源层的刻蚀程度。
在本发明的实施例中， 对阻挡层选用等离子刻蚀、 反应离子刻蚀或电感 耦合离子体刻蚀方法， 刻蚀气体为含氟、 氯的气体。 在刻蚀过程中， 实时监 测有源层的透光率现有值， 例如当透光率现有值达到透光率基准值的的预定 值（例如 100%~120% ) 时， 则表示已经刻蚀至有源层， 停止刻蚀。
本发明的实施例提供的有源层刻蚀监控方法， 通过对比不同状态下有源 层的透光率， 可有效监控对有源层的刻蚀程度， 最大程度确保有源层不被过 度刻蚀， 确保有源层的性能， 进而提高产品的良品率。
实施例三
本发明的实施例提供了一种阵列基板制作方法， 为了凸显出该有源层监 控的效果， 该阵列基板釆用顶栅型结构。
该阵列基板的制作方法包括如下步骤。
步骤 S301 : 在基板上沉积緩冲层。
参照图 2A， 在经过预先清洗的例如玻璃基板等是透明基板 301 上， 以 PECVD、 LPCVD、 APCVD (大气压化学气相沉积）、 ECR-CVD (电子回旋 谐振化学气相沉积）或者溅射等方法形成緩冲层 302， 以阻挡透明基板中所 含的杂质扩散进入之后形成的有源层中，防止对 TFT元件的阔值电压和漏电 流等特性产生影响。
该緩冲层可以为单层的氧化硅、 氮化硅或者二者的叠层。 该层的厚度可 为 300A ~ 10000A, 优选厚度为 500 A ~ 4000A, 沉积温度在 600 °C或更低温 度下。
除引入了緩冲层外， 因传统碱玻璃中铝、 钡和钠等金属杂质含量较高， 容易在高温处理工艺中发生金属杂质的扩散， 还可以釆用无碱玻璃作为透明 基板。
步骤 S302: 在緩冲层上形成有源层的图形， 监测并记录所述有源层的透 光率基准值。
参照图 2B， 通过 PEC VD、 LPCVD或者溅射方法， 在 600 °C以下的沉积 温度， 在緩冲层 302上沉积非晶硅层 303， 其厚度为 100A ~ 3000A， 优选厚 度为 500A ~ 1000A。 随后可通过准分子激光晶化、 金属诱导晶化、 固相晶化 等方法将非晶硅层 303转变为多晶硅层。 需要说明的是， 不同的晶化方法的 工艺过程及薄膜晶体管的结构会有所不同， 在制备过程中需要根据情况增加 热处理脱氢、 沉积诱导金属、 热处理晶化、 准分子激光照射晶化、 源漏区的 掺杂（Ρ型或者 Ν型掺杂）及掺杂杂质的激活等工艺。 在将非晶硅层转变为 多晶硅层之后以光刻工艺形成掩膜， 继而釆用干法刻蚀方法形成图形， 作为 TFT的有源层图形。
监测并记录此时多晶硅区域的透光率。 例如， 可向基板照射光束， 感应 所述有源层图形的透光率， 并将该透光率作为有源层的透光率基准值。 此透 光率数值将作为后续监控刻蚀情况的基准值。 为了确保整个基板的刻蚀均匀 性， 监测不同位置的多个数据值， 如测量 9~25点数据。
步骤 S303: 沉积栅绝缘层、 栅电极层、 层间绝缘层， 形成待刻蚀过孔的 背板。
参照图 2C， 釆用 PECVD、 LPCVD、 APCVD或 ECR-CVD等方法沉积 栅绝缘层 304;然后釆用溅射、热蒸发或 PECVD、 LPCVD、APCVD、ECR-CVD 等方法在栅绝缘层上沉积栅电极层 305; 以光刻工艺形成掩膜， 通过湿法刻 蚀或干法刻蚀的方法将栅电极层 305刻蚀形成图形。
可根据具体工艺需要选择栅绝缘层 304的合适的厚度。 例如， 栅绝缘层 304的厚度为 300A ~ 3000A。 栅绝缘层 304可釆用单层的氧化硅、 氮化硅或 者二者的叠层， 沉积温度一般在 600 °C以下。 栅电极层 305 由金属、 金属合 金如钼、 钼合金等或掺杂的多晶硅等导电材料构成， 厚度在 1000A - 8000A 范围内， 优选厚度为 2500A ~ 4000A。 栅绝缘层之上为层间绝缘层 306， 其厚度为 3000 A ~9000 A， 优选厚度 为 4000 A -6000 A。 可釆用 PECVD、 LPCVD、 APCVD或 ECR-CVD等方法 在 600 °C以下的沉积温度沉积层间绝缘层。 层间绝缘层 306可包括单层的氧 化硅或者氧化硅和氮化硅的叠层。
步骤 S304: 以光刻法形成掩膜， 釆用干法刻蚀刻蚀出过孔， 并监测过孔 透光率，当透光率达到之前记录的有源层透光率基准值的 100%~120%时停止 刻独。
参照图 2D，在层间绝缘层 306之上以光刻工艺形成光刻胶（光致抗蚀剂） 掩膜层 307， 光刻胶掩膜层 307的厚度例如为 10000 A -20000 A。 在掩膜层 的遮蔽下， 被刻蚀区域可釆用干法刻蚀去除。 干法刻蚀可为等离子刻蚀、 反 应离子刻蚀、 电感耦合等离子体刻蚀等方法。 刻蚀气体可为含氟、 氯的气体， 如 CF4、 CHF3、 SF6、 CC12F2等或者这些气体与 02的混合气体。 在刻蚀过程 中， 用步骤 S302中同样的方法监测 9~25点的透光率， 并与步骤 S302中记 录的数据相比较， 即通过确定实时监测有源层的透光率现有值和透光率基准 值之间的变化量来监控对所述有源层的刻蚀程度。 通过这种监控方法， 即使 在栅极绝缘层和层间绝缘层的厚度之和与有源层的厚度差别非常大（例如， 二者比率为 10: 1以上）的情况下， 也能很好的监测到有源层的刻蚀程度， 从 而相应的控制刻蚀的进度。
进一步地，当透光率现有值达到之前记录的透光率基准值的 100%~120% 时表示已经刻蚀至多晶硅层（有源层） ， 即可停止刻蚀。
步骤 S305: 在完成上述步骤的基板上形成源漏电极层， 所述源漏电极通 过过孔与有源层电连接。
釆用上述方法制作阵列基板， 可实时控制对有源层的刻蚀程度， 确保有 源层不被过度刻蚀， 进而提高产品的良品率。
在本发明的另一个实施例中， 根据需要也可以在基板的表面上不形成緩 冲层， 即在基板表面上直接形成有源层。
实施例四
如图 3所示，本发明实施例提供了一种膜层刻蚀监控设备，其包括腔室， 以及设置在所述腔室中的光源 3和多个光感探头 4， 所述光源 3照射基板上 的膜层， 所述光感探头 4用于感应所述膜层的透光率。 该光源 3例如包括荧光灯或发光二极管 （LED )等， 可以为点光源、 线 光源或面光源等； 光感探头 4包括光电二极管等。
在本发明的实施例中， 膜层刻蚀监控设备可独立于刻蚀装置且实现为单 独的透光率监控设备。 然而， 考虑到生产效率， 本发明的另一实施例还可以 将监测透光率的装置与刻蚀装置集成为一体。
例如，设置腔室为真空腔室 1， 所述真空腔室连通反应气体源 2; 真空腔 室 1中还设有刻蚀装置。
本实施例中的刻蚀装置为干刻设备， 其包括相对设置的上极板 5和下极 板 6; 上极板 5接地， 下极板 6接射频电源 7; 基板 8位于下极板 6上， 射频 电源 7提供射频电流以产生对基板 8进行刻蚀的等离子体。
例如， 该光源 3可位于上极板 5上方或是真空腔室 1的上壁， 使其光束 向下照射， 形成垂直光源。 当然， 该光源 3也可位于真空腔室 1的侧壁， 使 其光束倾斜照射， 形成倾斜光源。
本发明的实施例中的刻蚀装置还可以选用其他干刻设备， 例如等离子体 刻蚀（PE )模式设备、 电感耦合等离子体刻蚀 (ICP)模式设备等。
为了监测整个基板透光率的均匀性， 该光感探头 4的数量可设置为 5-25 个， 其均匀分布在下极板 6上。 当然， 该光感探头 4的数量可根据需求而定。 另外， 在至少一个实施例中， 该设备还包括流量计 9， 其用于控制反应气体 源 2向真空腔室 1内流入的反应气体的量。
例如， 所述真空腔室 1连接真空泵 10、 真空计 11和压力开关 12， 用于 维持和控制真空腔室 1内的真空度。
釆用此膜层刻蚀监控设备时， 在上述步骤 S302 的干法刻蚀后取得透光 率的基准数据， 然后在步骤 S304干法刻蚀进行时检测透光率现有值并将该 透光率现有值与基准数据进行比较。
由于干刻设备在工作时产生的等离子体会干扰光源产生的光， 所以在检 测时需要暂停等离子体的产生。 因此， 本发明的至少一个实施例还包括釆用 间断供给方法的射频电源。 该射频电源在供电时间段提供射频电流以产生等 离子体， 本实施例的膜层刻蚀监控设备在断电时间段进行膜层的透光率的监 测。
通过在刻蚀设备中增设光源和光感探头， 可实时监测在过孔刻蚀过程中 的刻蚀情况， 有利于简单有效的控制刻蚀程度， 能够在刻蚀至有源层时及时 停止刻蚀， 确保有源层的性能不被破坏。 另外， 通过设置若干个监测点， 可 确保整个基板的刻蚀均匀性， 有利于提高制备大面积多晶硅基板的良率。
本发明的实施例提供的阵列基板的制作方法、膜层刻蚀监控方法及设备， 通过对比不同状态下膜层的透光率， 可有效监控对膜层的刻蚀程度， 以确保 膜层不被过度刻蚀， 确保膜层的性能， 进而提高产品的良品率。
上述描述是为了示例和描述起见而给出的， 而并不是无遗漏的或者将本 发明限于所公开的形式。 很多修改和变化对于本领域的普通技术人员而言是 显然的。 选择和描述实施例是为了更好说明本发明的原理和实际应用， 并且 使本领域的普通技术人员能够理解本发明从而设计适于特定用途的带有各种 爹改的各种实施例。
本申请要求于 2013年 12月 20日递交的中国专利申请第 201310714433.9 号的优先权， 在此全文引用上述中国专利申请公开的内容以作为本申请的一 部分。

Claims

权利要求书
1、 一种膜层刻蚀监控方法， 包括：
在形成膜层图形之后监测并记录所述膜层的透光率基准值；
在所述膜层图形上形成阻挡层之后， 在对阻挡层进行刻蚀以形成过孔的 过程中， 实时监测所述膜层的透光率现有值， 以及通过确定所述透光率现有 值和所述透光率基准值之间的变化量来监控对所述膜层的刻蚀程度。
2、如权利要求 1所述的监控方法， 其中，监测所述膜层的不同位置的多 个点的透光率值。
3、 如权利要求 2 所述的监控方法， 其中， 监测所述膜层的不同位置的
9-25点的透光率值。
4、如权利要求 1所述的监控方法，其中，实时监测膜层的透光率现有值， 当所述透光率现有值达到所述透光率基准值的 100%~120%时， 停止刻蚀。
5、 如权利要求 1-4任一项所述的监控方法， 其中， 所述膜层为有源层， 所述阻挡层为栅绝缘层或层间绝缘层。
6、如权利要求 5所述的监控方法， 其中， 所述栅绝缘层和层间绝缘层的 厚度之和与所述有源层的厚度的比值在 10:1以上。
7、 如权利要求 5所述的监控方法， 其中， 形成有源层图形包括： 沉积非晶硅层， 将非晶硅进行晶化形成多晶硅层， 对多晶硅层釆用构图 工艺形成有源层图形。
8、如权利要求 5所述的监控方法， 其中，监测并记录该有源层的透光率 基准值包括：
用光束照射所述有源层， 感应所述有源层图形的透光率， 并将该透光率 作为所述有源层的透光率基准值。
9、 一种阵列基板制作方法， 包括：
在基板上形成有源层的图形， 监测并记录所述有源层的透光率基准值； 在完成上述步骤的基板上沉积阻挡层和栅电极层， 所述阻挡层包括栅绝 缘层和层间绝缘层；
对阻挡层进行刻蚀以形成过孔， 在刻蚀过程中， 实时监测所述有源层的 透光率现有值， 当所述透光率现有值达到所述透光率基准值的预定值时， 停 止刻独；
在完成上述步骤的基板上形成源漏电极层， 所述源漏电极通过所述过孔 与有源层电连接。
10、 如权利要求 9所述的方法， 还包括： 在所述基板上沉积緩冲层， 然 后在所述緩冲层上形成所述有源层的图形。
11、 一种膜层刻蚀监控设备， 包括：
腔室； 以及
设置在所述腔室中的光源和多个光感探头，
其中， 所述光源照射基板上的膜层， 所述光感探头用于感应所述膜层的 透光率。
12、 如权利要求 11所述的监控设备， 其中， 所述腔室为真空腔室， 所述 真空腔室连通反应气体源； 所述真空腔室中设有刻蚀装置。
13、 如权利要求 12所述的监控设备， 其中， 所述刻蚀装置包括： 相对设置的上极板和下极板， 其中一个极板接地， 另外一个极板接射频 电源， 使得上极板和下极板之间生成对所述基板进行刻蚀的等离子体；
待刻蚀的基板放置在所述下极板上。
14、如权利要求 13所述的监控设备，其中，所述光源位于所述上极板上； 或者， 所述光源位于真空腔室的侧壁；
或者， 所述光源位于真空腔室的上壁。
15、如权利要求 14所述的监控设备， 其中， 所述光感探头设置于所述下 极板远离所述基板的一侧。
16、 如权利要求 11或 12所述的监控设备， 其中， 所述光感探头的数量 为 5-25个且所述光感探头分布在不同的位置。
17、 如权利要求 11或 12所述的监控设备， 还包括釆用间断供给的方法 的射频电源， 其中， 所述射频电源在供电时间段提供射频电流以产生等离子 体， 所述监控设备在断电时间段进行膜层的透光率的监测。
PCT/CN2014/078263 2013-12-20 2014-05-23 阵列基板制作方法、膜层刻蚀监控方法及设备 Ceased WO2015089997A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/402,872 US9646847B2 (en) 2013-12-20 2014-05-23 Method for manufacturing array substrate, film-etching monitoring method and device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310714433.9A CN103811291B (zh) 2013-12-20 2013-12-20 一种阵列基板制作方法、膜层刻蚀防损伤监控方法及设备
CN201310714433.9 2013-12-20

Publications (1)

Publication Number Publication Date
WO2015089997A1 true WO2015089997A1 (zh) 2015-06-25

Family

ID=50707910

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/078263 Ceased WO2015089997A1 (zh) 2013-12-20 2014-05-23 阵列基板制作方法、膜层刻蚀监控方法及设备

Country Status (3)

Country Link
US (1) US9646847B2 (zh)
CN (1) CN103811291B (zh)
WO (1) WO2015089997A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117270317A (zh) * 2023-11-20 2023-12-22 深圳市龙图光罩股份有限公司 图形辅助的干法刻蚀装置及方法

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103811291B (zh) * 2013-12-20 2018-01-23 京东方科技集团股份有限公司 一种阵列基板制作方法、膜层刻蚀防损伤监控方法及设备
CN105679808B (zh) * 2016-04-18 2019-04-16 京东方科技集团股份有限公司 一种柔性显示基板的半切割损伤检测方法和制作方法
JP6749727B2 (ja) * 2016-10-14 2020-09-02 株式会社ディスコ 検査用ウエーハ及び検査用ウエーハの使用方法
TWI659258B (zh) * 2018-05-23 2019-05-11 亞智科技股份有限公司 蝕刻時間偵測方法及蝕刻時間偵測系統
CN109671640B (zh) * 2018-12-25 2020-09-08 深圳市华星光电技术有限公司 有源层厚度的监控方法
CN109950413B (zh) * 2019-04-04 2020-11-27 京东方科技集团股份有限公司 测试方法、筛选方法以及oled设计方法
CN112750738B (zh) * 2021-01-18 2024-02-23 中国电子科技集团公司第四十八研究所 一种离子束刻蚀设备及其刻蚀方法
KR102778483B1 (ko) * 2021-05-31 2025-03-06 어플라이드 머티어리얼스, 인코포레이티드 결정 두께 마이크로 밸런싱 센서의 인시튜 epi 성장률 제어
US11848202B2 (en) * 2021-11-30 2023-12-19 Applied Materials, Inc. Growth monitor system and methods for film deposition
US12577673B2 (en) * 2022-07-18 2026-03-17 Applied Materials, Inc. In-situ EPI growth rate control of crystal thickness using parametric resonance sensing
CN115655138A (zh) * 2022-09-08 2023-01-31 深圳市杰普特光电股份有限公司 激光钻孔深度监测装置、方法、控制终端及存储介质
CN115597520A (zh) * 2022-10-24 2023-01-13 成都海威华芯科技有限公司（Cn） 一种背孔过刻蚀检验方法及装置
CN116005271A (zh) * 2022-12-26 2023-04-25 西安奕斯伟材料科技有限公司 一种硅料处理方法和装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6333271B1 (en) * 2001-03-29 2001-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-step plasma etch method for plasma etch processing a microelectronic layer
US20020048960A1 (en) * 2000-03-23 2002-04-25 John Scanlan Endpoint detection in the etching of dielectric layers
US20050053847A1 (en) * 2003-09-09 2005-03-10 Martin Patrick M. Photomask having an internal substantially transparent etch stop layer
CN103811291A (zh) * 2013-12-20 2014-05-21 京东方科技集团股份有限公司 一种阵列基板制作方法、膜层刻蚀防损伤监控方法及设备

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4317698A (en) * 1980-11-13 1982-03-02 Applied Process Technology, Inc. End point detection in etching wafers and the like
JPS57116342A (en) * 1981-01-13 1982-07-20 Toshiba Corp Manufacture of photomask
JPS59144134A (ja) * 1983-02-08 1984-08-18 Nec Corp フオトマスクエツチング終点判定装置
US6979578B2 (en) * 2002-08-13 2005-12-27 Lam Research Corporation Process endpoint detection method using broadband reflectometry
US20040221957A1 (en) * 2003-05-06 2004-11-11 Tokyo Electron Limited Method system and computer readable medium for monitoring the status of a chamber process
JP4500510B2 (ja) * 2003-06-05 2010-07-14 東京エレクトロン株式会社 エッチング量検出方法，エッチング方法，およびエッチング装置
US8460945B2 (en) * 2003-09-30 2013-06-11 Tokyo Electron Limited Method for monitoring status of system components
EP1926125B1 (en) 2006-10-30 2011-02-16 Applied Materials, Inc. Endpoint detection for photomask etching
US20080099435A1 (en) * 2006-10-30 2008-05-01 Michael Grimbergen Endpoint detection for photomask etching
KR20090022471A (ko) * 2007-08-30 2009-03-04 엘지디스플레이 주식회사 액정표시장치의 데이터 구동장치
CN101459049A (zh) * 2007-12-11 2009-06-17 中芯国际集成电路制造(上海)有限公司 一种用于探测刻蚀终点的装置及方法
CN101458445B (zh) 2007-12-11 2012-04-25 中芯国际集成电路制造(上海)有限公司 一种用于探测刻蚀终点的装置及方法
KR101379915B1 (ko) * 2008-03-26 2014-04-01 엘지이노텍 주식회사 종말점 검출 장치 및 이를 구비한 식각 장치 그리고 종말점검출방법
CN102044431A (zh) * 2009-10-20 2011-05-04 中芯国际集成电路制造(上海)有限公司 刻蚀方法和刻蚀系统
CN102651337A (zh) * 2011-05-13 2012-08-29 京东方科技集团股份有限公司 一种多晶硅tft阵列基板的制造方法
CN102709283B (zh) * 2011-05-27 2015-06-10 京东方科技集团股份有限公司 低温多晶硅薄膜晶体管阵列基板及其制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020048960A1 (en) * 2000-03-23 2002-04-25 John Scanlan Endpoint detection in the etching of dielectric layers
US6333271B1 (en) * 2001-03-29 2001-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-step plasma etch method for plasma etch processing a microelectronic layer
US20050053847A1 (en) * 2003-09-09 2005-03-10 Martin Patrick M. Photomask having an internal substantially transparent etch stop layer
CN103811291A (zh) * 2013-12-20 2014-05-21 京东方科技集团股份有限公司 一种阵列基板制作方法、膜层刻蚀防损伤监控方法及设备

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117270317A (zh) * 2023-11-20 2023-12-22 深圳市龙图光罩股份有限公司 图形辅助的干法刻蚀装置及方法
CN117270317B (zh) * 2023-11-20 2024-02-09 深圳市龙图光罩股份有限公司 图形辅助的干法刻蚀装置及方法

Also Published As

Publication number Publication date
US9646847B2 (en) 2017-05-09
CN103811291B (zh) 2018-01-23
US20160268139A1 (en) 2016-09-15
CN103811291A (zh) 2014-05-21

Similar Documents

Publication Publication Date Title
CN103811291B (zh) 一种阵列基板制作方法、膜层刻蚀防损伤监控方法及设备
CN103996716B (zh) 一种多晶硅薄膜晶体管的制备方法
CN107316874B (zh) 阵列基板及其制作方法、显示装置
WO2014012320A1 (zh) 薄膜晶体管及其制作方法、阵列基板、显示装置
CN110993616B (zh) 显示背板及其制备方法和显示装置
WO2016206206A1 (zh) 薄膜晶体管及其制备方法、阵列基板、显示装置
WO2015096350A1 (zh) 阵列基板及其制备方法
CN105428313A (zh) 阵列基板及其制备方法、显示装置
WO2014169544A1 (zh) 薄膜晶体管及其制备方法、阵列基板、显示装置
WO2020042690A1 (zh) 显示器件的封装结构、显示装置
CN104064472A (zh) 薄膜晶体管及其制作方法、显示装置
CN106601823A (zh) 一种薄膜晶体管的制作方法及薄膜晶体管
CN105552035B (zh) 低温多晶硅tft阵列基板的制作方法及其结构
CN104393002A (zh) 一种显示基板及其制作方法、显示装置
CN109166802A (zh) Ltps阵列基板及其制造方法、显示面板
CN109659312B (zh) 一种阵列基板及其制备方法
US9478665B2 (en) Thin film transistor, method of manufacturing the same, display substrate and display apparatus
WO2015169023A1 (zh) Oled发光器件及其制备方法、显示装置
WO2019184380A1 (zh) 阵列基板及其制备方法、显示装置
CN107833893A (zh) 阵列基板及其制作方法、显示面板
CN203882952U (zh) 一种膜层刻蚀防损伤监控设备
CN109494231B (zh) 薄膜晶体管阵列基板及其制作方法、以及液晶显示面板
CN105957814B (zh) 薄膜晶体管及其制备方法
WO2019085009A1 (zh) 低温多晶硅薄膜及晶体管的制造方法
CN107887275B (zh) 低温多晶硅薄膜及晶体管的制造方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14402872

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14872105

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205 DATED 26.08.2016)

122 Ep: pct application non-entry in european phase

Ref document number: 14872105

Country of ref document: EP

Kind code of ref document: A1