WO2015058428A1 - 芯片结构及电路结构 - Google Patents

芯片结构及电路结构 Download PDF

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Publication number
WO2015058428A1
WO2015058428A1 PCT/CN2013/086668 CN2013086668W WO2015058428A1 WO 2015058428 A1 WO2015058428 A1 WO 2015058428A1 CN 2013086668 W CN2013086668 W CN 2013086668W WO 2015058428 A1 WO2015058428 A1 WO 2015058428A1
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Prior art keywords
power
input line
power input
chip
disposed
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Ceased
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PCT/CN2013/086668
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English (en)
French (fr)
Inventor
符俭泳
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/235,811 priority Critical patent/US9345124B2/en
Publication of WO2015058428A1 publication Critical patent/WO2015058428A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H05K1/0231—Capacitors or dielectric substances
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0209—External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10015—Non-printed capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10522—Adjacent components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10969—Metallic case or integral heatsink of component electrically connected to a pad on PCB
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/10—Arrangements for heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections

Definitions

  • the present invention relates to the field of chip design, and in particular to a chip structure and a circuit structure.
  • FIG. 1 is a schematic structural view of a conventional chip structure. The figure uses a single diagonal line to indicate the components on the copper foil ground plane.
  • the chip structure 10 includes a chip 11 (shown by double diagonal lines) disposed on a component layer of the printed circuit board 14, a bypass capacitor 12 disposed near the power supply pin of the chip 11, and a power supply line disposed on the copper foil ground layer.
  • bypass capacitor 12 is connected to the power pin, and the other end of the bypass capacitor 12 is connected to the power line 13 of the copper foil ground layer to ensure the stability of the power supply and the ground when the current is supplied. Reduce the power supply impedance.
  • the power supply line 13 of the chip structure 10 needs to be annularly packaged as shown in FIG. Specifically, the power supply line 13 reaches the copper foil ground layer through the through hole, and then the power supply line 13 is respectively introduced into each of the bypass capacitors 12 on the copper foil ground layer; thus forming a semi-annular package on the copper foil ground layer. .
  • the semi-annular package blocks the grounding of the copper foil ground layer, affecting the heat dissipation of the chip 11 and the yield of the chip 11.
  • the object of the present invention is to provide a chip structure and a circuit structure with good heat dissipation effect and high production yield, so as to solve the technical problems of poor heat dissipation effect and low production yield of the existing chip structure and circuit structure.
  • the present invention provides a chip structure that is disposed on a printed circuit board having a part layer and a copper foil ground layer, including:
  • a chip body disposed on the part layer, including a plurality of power pins
  • a power line disposed on the part layer for supplying power to the chip body
  • a body of the power input line is disposed on the copper foil ground layer, two ends of the power input line are disposed on the part layer; and a main body of the power input line passes through the printed circuit board a through hole is connected to both ends of the power input line;
  • bypass capacitor one end of the bypass capacitor is connected to the power pin of the chip body through the part layer, and the other end of the bypass capacitor is connected to the power line through the power input line;
  • the main body of the power input line is connected to one end of the power input line through a first through hole on the printed circuit board, and the main body of the power input line passes through a second through hole on the printed circuit board. Connecting the other end of the power input line;
  • One end of the power input line is connected to the bypass capacitor, and the other end of the power input line is connected to the power line.
  • the present invention also provides a chip structure disposed on a printed circuit board having a part layer and a copper foil ground layer, comprising:
  • a chip body disposed on the part layer, including a plurality of power pins
  • a power line disposed on the part layer for supplying power to the chip body
  • a body of the power input line is disposed on the copper foil ground layer, two ends of the power input line are disposed on the part layer; and a main body of the power input line passes through the printed circuit board a through hole is connected to both ends of the power input line;
  • bypass capacitor one end of the bypass capacitor is connected to the power pin of the chip body through the part layer, and the other end of the bypass capacitor is connected to the power line through the power input line.
  • the main body of the power input line is connected to one end of the power input line through a first through hole on the printed circuit board, and the main body of the power input line passes the printing
  • a second through hole on the circuit board is connected to the other end of the power input line.
  • one end of the power input line is connected to the bypass capacitor, and the other end of the power input line is connected to the power line.
  • the chip structure further includes:
  • a power supply lead is disposed on the copper foil ground layer, and the power supply lead is connected to the power line through a third through hole on the printed circuit board.
  • the chip structure further includes:
  • the heat dissipation unit is disposed on the back surface of the chip body.
  • the heat dissipation unit is a bare copper structure disposed on a back surface of the chip body.
  • the heat dissipating unit covers at least a projection area of the chip main body in a projection area of the printed circuit board in a projection area of the printed circuit board.
  • the copper foil ground layer is provided with an integrated copper foil layer.
  • the power cord has a width ranging from 1.2 mm to 2.5 mm.
  • the invention also provides a circuit structure comprising:
  • a chip structure disposed on a printed circuit board having a part layer and a copper foil ground layer comprising:
  • a chip body disposed on the part layer, including a plurality of power pins
  • a power line disposed on the part layer for supplying power to the chip body
  • a body of the power input line is disposed on the copper foil ground layer, two ends of the power input line are disposed on the part layer; and a main body of the power input line passes through the printed circuit board a through hole is connected to both ends of the power input line;
  • bypass capacitor one end of the bypass capacitor is connected to the power pin of the chip body through the part layer, and the other end of the bypass capacitor is connected to the power line through the power input line.
  • the main body of the power input line is connected to one end of the power input line through a first through hole on the printed circuit board, and the main body of the power input line passes the printing
  • a second through hole on the circuit board is connected to the other end of the power input line.
  • one end of the power input line is connected to the bypass capacitor, and the other end of the power input line is connected to the power line.
  • the chip structure further includes:
  • a power supply lead is disposed on the copper foil ground layer, and the power supply lead is connected to the power line through a third through hole on the printed circuit board.
  • the chip structure further includes:
  • the heat dissipation unit is disposed on the back surface of the chip body.
  • the heat dissipation unit is a bare copper structure disposed on a back surface of the chip body.
  • the heat dissipating unit covers at least a projection area of the chip main body in a projection area of the printed circuit board in a projection area of the printed circuit board.
  • the copper foil ground layer is provided with an integrated copper foil layer.
  • the power cord has a width ranging from 1.2 mm to 2.5 mm.
  • the power supply line of the chip structure and the circuit structure of the present invention is disposed on the component layer, so the heat dissipation effect of the copper foil ground layer is good, and the production yield of the corresponding chip and circuit is high.
  • the invention solves the technical problems of poor heat dissipation effect and low production yield of the existing chip structure and circuit structure.
  • 1 is a schematic structural view of a conventional chip structure
  • FIG. 2 is a schematic structural view of a first preferred embodiment of the chip structure of the present invention.
  • FIG. 3 is a schematic structural view of a second preferred embodiment of the chip structure of the present invention.
  • FIG. 2 is a schematic structural view of a first preferred embodiment of the chip structure of the present invention.
  • the chip structure 20 is disposed on a corresponding printed circuit board 29 that includes a component layer and a copper foil ground plane. Surface elements of the chip structure 20 are disposed on the component layer, and the ground and heat sink components of the chip structure 20 They are all placed on the copper foil ground plane.
  • the chip structure 20 described above includes a chip body 21, a power supply line 22 (completely covered by the chip body 21), a power supply input line 23, a bypass capacitor 24, and a power supply lead line 25.
  • the chip body 21 (such as a timing control chip body or the like) is disposed on the component layer and includes a plurality of power pins; the power line 22 is disposed on the component layer for supplying power to the chip body 21; and the power input line 23 includes a power input line.
  • the main body of the 23 and the two ends of the power input line 23, the main body of the power input line 23 is disposed on the copper foil ground layer, the two ends of the power input line 23 are disposed on the component layer, and the main body of the power input line 23 passes through the printed circuit board 29.
  • the through hole is connected to both ends of the power input line 23, specifically, the main body of the power input line 23 is connected to one end of the power input line 23 through the first through hole 291 on the printed circuit board 29, and the main body of the power input line 23 passes through the printed circuit.
  • the second through hole 292 on the board 29 is connected to the other end of the power input line 23; the bypass capacitor 24 is also disposed on the component layer, and one end thereof is connected to the power pin of the chip body 21 through the component layer, and the bypass capacitor 24 is The other end is connected to the power line 22 through the power input line 23, specifically, one end of the power input line 23 is connected to the bypass capacitor 24, and the other end of the power input line 23 is connected to the power line 22; the power supply lead 25 Disposed in the copper foil ground layer, the power supply line 25 is introduced through the third through-hole 22 is connected to the power source line 293 on the printed circuit board 29.
  • the power supply line 22 in the chip structure 20 of the preferred embodiment is disposed on a component layer that is connected to a power source (not shown) through a power supply lead 25, through a power supply input line 23, and a bypass capacitor 24. And a power pin connection of the chip body 21. Since the main components of the chip structure 20 (the power supply line 22, the bypass capacitor 24, and the chip body 21) are all disposed in the component layer, only the power input line 23 and the power supply lead 25 are provided on the copper foil ground layer (through a single diagonal line) The power input line 23 is connected to the power supply line 22 and the bypass capacitor 24 on the component layer through the first through hole 291 and the second through hole 292 provided in the printed circuit board 29.
  • a completely integrated copper foil layer can be disposed on the copper foil ground layer of the printed circuit board 29, which greatly enhances the heat dissipation capability of the chip structure 20, and at the same time improves the anti-electromagnetic interference capability of the chip structure 20, thereby improving the chip structure 20 Production yield.
  • the power source supplies power to the power line 22 at the component layer via the third through hole 293 of the printed circuit board 29 through the power supply lead 25 disposed on the copper foil ground plane.
  • the power supply line 22 is connected to one end of the power supply input line 23 at the component layer, and sequentially supplies power to the bypass capacitor 24 at the component layer through the main body of the power supply input line 23 located at the copper foil ground plane and the other end of the power supply input line 23.
  • the bypass capacitor 24 is connected to the power supply pin of the chip body 21 through the component layer, thereby realizing power supply to the chip body 21.
  • the main power supply line of the chip structure of the preferred embodiment is disposed on the component layer, so the heat dissipation effect of the copper foil ground layer is good, and the production yield of the corresponding chip and circuit is high.
  • FIG. 3 is a schematic structural view of a second preferred embodiment of the chip structure of the present invention.
  • the chip structure 30 is disposed on a corresponding printed circuit board 39.
  • the printed circuit board 39 includes a component layer and a copper foil ground plane. Surface elements of the chip structure 30 are disposed on the component layer, and the ground and heat dissipation components of the chip structure 30 are provided. They are all placed on the copper foil ground plane.
  • the chip structure 30 described above includes a chip body 31, a power line 32, a power input line 33, a bypass capacitor 34, a power supply lead 35, and a heat sink unit 36.
  • the chip body 31 is disposed on the component layer and includes a plurality of power pins;
  • the power line 32 is disposed on the component layer for supplying power to the chip body 31;
  • the power input line 33 includes the body of the power input line 33 and the power input line 33.
  • the main body of the power input line 33 is disposed on the copper foil ground layer, and both ends of the power input line 33 are disposed on the component layer, and the main body of the power input line 33 passes through the through hole on the printed circuit board 39 and the power input line 33.
  • the main body of the power input line 33 is connected to one end of the power input line 33 through the first through hole 391 on the printed circuit board 39.
  • the main body of the power input line 33 passes through the second through hole on the printed circuit board 39.
  • 392 is connected to the other end of the power input line 33;
  • the bypass capacitor 34 is also disposed on the component layer, one end of which is connected to the power pin of the chip body 31 through the component layer, and the other end of the bypass capacitor 34 is connected through the power input line 33.
  • the power line 32 is connected. Specifically, one end of the power input line 33 is connected to the bypass capacitor 34, and the other end of the power input line 33 is connected to the power line 32.
  • the power supply lead 35 is disposed on the copper foil ground layer.
  • the wire 35 is connected to the power line 32 through a third through hole 393 on the printed circuit board 39.
  • the heat dissipation unit 36 is a bare copper structure disposed on the back surface of the chip body 31, that is, the copper foil ground layer on the back surface of the chip body 31 is hollowed out to be set. Bare copper structure.
  • the preferred embodiment is based on the first preferred embodiment, except that the main components of the chip structure 30 are disposed in the component layer, thereby greatly enhancing the heat dissipation capability and electromagnetic interference resistance of the chip structure 30;
  • a large-area bare copper structure is used as the heat dissipation unit 36.
  • the heat dissipation unit 36 covers at least the projection area of the heat dissipation sheet of the chip main body 31 on the printed circuit board 39 in the projection area of the printed circuit board 39.
  • the bare copper structure can be used for the chip main body 31.
  • the heat dissipated during operation is conducted outward in time, thereby dissipating heat through the copper foil ground layer in time, further enhancing the heat dissipation capability of the chip structure 30.
  • the printed circuit board 39 is a two-layer printed circuit board 39 comprising a component layer disposed on the front side and a copper foil ground layer disposed on the back side (of course, the component layer may also be disposed on the printed circuit board 39.
  • the front side of the printed circuit board 39 is disposed on the front side of the printed circuit board 39.
  • the main body 31 of the power supply input line 33 and the power supply are introduced. Both the line 35 and the heat sink unit are disposed on the copper foil ground plane of the printed circuit board 39.
  • the power line 32 is disposed between the chip body 31 and the bypass capacitor 34 (covered by the chip body 31), and the width of the power line 32 is preferably 1.2 mm to 2.5 mm, which further saves on the printed circuit board 39. space.
  • the chip structure of the preferred embodiment is based on the first preferred embodiment, and a bare copper structure is disposed on the back surface of the chip body as a heat dissipation unit, thereby further enhancing the heat dissipation effect of the chip structure.
  • the present invention also provides a circuit structure including the above chip structure.
  • the working principle of the circuit structure of the present invention is the same as that in the first preferred embodiment and the second preferred embodiment of the above-mentioned chip structure.
  • the power supply line of the chip structure and the circuit structure of the invention is disposed on the component layer, so the heat dissipation effect of the copper foil ground layer is good, and the production yield of the corresponding chip and circuit is high; the existing chip structure and circuit structure are solved.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

提供一种芯片结构及电路结构，其中该芯片结构（20）设者在具有零件层和铜箔接地层的印刷电路板上，该芯片结构（20）包括：芯片主体（21），设置在零件层，包括多个电源管脚；电源线（22），设置在零件层，用于给芯片主体（21）供电；电源输入线（23），其主体设置在铜箔接地层，其两端设置在零件层；电源输入线（23）的主体通过印刷电路板（29）上的贯通孔（291、292）与电源输入线（23）的两端连接；以及旁路电容（24），其一端通过零件层与芯片主体（21）的电源管脚连接，另外一端通过电源输入线（23）与电源线（22）连接。还提供了一种与上述芯片结构类似的电路结构。上述芯片结构和电路结构的电源线设置在零件层上，因此铜箔接地层的散热效果好，同时相应的芯片和电路的生产良率高。

Description

芯片结构及电路结构 技术领域
本发明涉及芯片设计领域，特别是涉及一种芯片结构及电路结构。
 背景技术
随着市面上芯片产品的竞争越来越激烈，为了降低成本，很多芯片产品的印刷电路板已压缩到2层板，一层为零件层，另一层为铜箔接地层。如图1所示，图1为现有的芯片结构的结构示意图。图中使用单斜线表示铜箔接地层上的元件。该芯片结构10包括设置在印刷电路板14的零件层上的芯片11（用双斜线表示）、设置在芯片11的电源管脚附近的旁路电容12以及设置在铜箔接地层的电源线13（通过单斜线表示）；该旁路电容12的一端连接电源管脚，旁路电容12的另一端连接铜箔接地层的电源线13，以保证提供电流时的供电和接地的稳定，减小电源阻抗。
对于一些在四周均设置有电源管脚的芯片11（如产生LVDS（Low Voltage Differential Signaling，低压差分）高速信号的时序控制芯片），由于需要将电源管脚附近的旁路电容12作为低阻抗回路，因此该芯片结构10的电源线13需如图1所示呈环状包装。具体为：电源线13通过穿孔到达铜箔接地层，然后在铜箔接地层上将该电源线13分别引入到各个旁路电容12中；这样在铜箔接地层形成了一个半环状的包装。
故，该半环状的包装对铜箔接地层的接地进行了隔断，影响了芯片11的散热和芯片11的良率。
 技术问题
本发明的目的在于提供一种散热效果好且生产良率高的芯片结构及电路结构，以解决现有的芯片结构及电路结构的散热效果较差以及生产良率较低的技术问题。
 技术解决方案
本发明提供一种芯片结构，所述芯片结构设置在具有零件层和铜箔接地层的印刷电路板上，其包括：
芯片主体，设置在所述零件层，包括多个电源管脚；
电源线，设置在所述零件层，用于给所述芯片主体供电；
电源输入线，所述电源输入线的主体设置在所述铜箔接地层，所述电源输入线的两端设置在所述零件层；所述电源输入线的主体通过所述印刷电路板上的贯穿孔与所述电源输入线的两端连接；以及
旁路电容，所述旁路电容的一端通过所述零件层与所述芯片主体的所述电源管脚连接，所述旁路电容的另一端通过所述电源输入线与所述电源线连接；
其中所述电源输入线的主体通过所述印刷电路板上的第一贯穿孔与所述电源输入线的一端连接，所述电源输入线的主体通过所述印刷电路板上的第二贯穿孔与所述电源输入线的另一端连接；
所述电源输入线的一端与所述旁路电容连接，所述电源输入线的另一端与所述电源线连接。
本发明还提供一种芯片结构，所述芯片结构设置在具有零件层和铜箔接地层的印刷电路板上，其包括：
芯片主体，设置在所述零件层，包括多个电源管脚；
电源线，设置在所述零件层，用于给所述芯片主体供电；
电源输入线，所述电源输入线的主体设置在所述铜箔接地层，所述电源输入线的两端设置在所述零件层；所述电源输入线的主体通过所述印刷电路板上的贯穿孔与所述电源输入线的两端连接；以及
旁路电容，所述旁路电容的一端通过所述零件层与所述芯片主体的所述电源管脚连接，所述旁路电容的另一端通过所述电源输入线与所述电源线连接。
在本发明所述的芯片结构中，所述电源输入线的主体通过所述印刷电路板上的第一贯穿孔与所述电源输入线的一端连接，所述电源输入线的主体通过所述印刷电路板上的第二贯穿孔与所述电源输入线的另一端连接。
在本发明所述的芯片结构中，所述电源输入线的一端与所述旁路电容连接，所述电源输入线的另一端与所述电源线连接。
在本发明所述的芯片结构中，所述芯片结构还包括：
电源引入线，设置在所述铜箔接地层，所述电源引入线通过所述印刷电路板上的第三贯穿孔与所述电源线连接。
在本发明所述的芯片结构中，所述芯片结构还包括：
散热单元，设置在所述芯片主体的背面。
在本发明所述的芯片结构中，所述散热单元为设置在所述芯片主体背面的裸铜结构。
在本发明所述的芯片结构中，所述散热单元在所述印刷电路板的投影区域至少覆盖所述芯片主体的散热片在所述印刷电路板的投影区域。
在本发明所述的芯片结构中，所述铜箔接地层设置有一体化的铜箔层。
在本发明所述的芯片结构中，所述电源线的宽度范围为1.2毫米至2.5毫米。
本发明还提供一种电路结构，其包括：
芯片结构，所述芯片结构设置在具有零件层和铜箔接地层的印刷电路板上，其包括：
芯片主体，设置在所述零件层，包括多个电源管脚；
电源线，设置在所述零件层，用于给所述芯片主体供电；
电源输入线，所述电源输入线的主体设置在所述铜箔接地层，所述电源输入线的两端设置在所述零件层；所述电源输入线的主体通过所述印刷电路板上的贯穿孔与所述电源输入线的两端连接；以及
旁路电容，所述旁路电容的一端通过所述零件层与所述芯片主体的所述电源管脚连接，所述旁路电容的另一端通过所述电源输入线与所述电源线连接。
在本发明所述的电路结构中，所述电源输入线的主体通过所述印刷电路板上的第一贯穿孔与所述电源输入线的一端连接，所述电源输入线的主体通过所述印刷电路板上的第二贯穿孔与所述电源输入线的另一端连接。
在本发明所述的电路结构中，所述电源输入线的一端与所述旁路电容连接，所述电源输入线的另一端与所述电源线连接。
在本发明所述的电路结构中，所述芯片结构还包括：
电源引入线，设置在所述铜箔接地层，所述电源引入线通过所述印刷电路板上的第三贯穿孔与所述电源线连接。
在本发明所述的电路结构中，所述芯片结构还包括：
散热单元，设置在所述芯片主体的背面。
在本发明所述的电路结构中，所述散热单元为设置在所述芯片主体背面的裸铜结构。
在本发明所述的电路结构中，所述散热单元在所述印刷电路板的投影区域至少覆盖所述芯片主体的散热片在所述印刷电路板的投影区域。
在本发明所述的电路结构中，所述铜箔接地层设置有一体化的铜箔层。
在本发明所述的电路结构中，所述电源线的宽度范围为1.2毫米至2.5毫米。
 有益效果
相较于现有的芯片结构及电路结构，本发明的芯片结构及电路结构的电源线设置在零件层上，因此铜箔接地层的散热效果好，同时相应的芯片和电路的生产良率高；解决了现有的芯片结构及电路结构的散热效果较差以及生产良率较低的技术问题。
 附图说明
图1为现有的芯片结构的结构示意图；
图2为本发明的芯片结构的第一优选实施例的结构示意图；
图3为本发明的芯片结构的第二优选实施例的结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图2，图2为本发明的芯片结构的第一优选实施例的结构示意图。该芯片结构20设置在相应的印刷电路板29上，该印刷电路板29包括零件层和铜箔接地层，芯片结构20的表面元件均设置在零件层上，而芯片结构20的接地和散热元件均设置在铜箔接地层上。
上述的芯片结构20包括芯片主体21、电源线22（被芯片主体21完全遮住）、电源输入线23、旁路电容24以及电源引入线25。芯片主体21（如时序控制芯片主体等）设置在零件层上，其包括多个电源管脚；电源线22设置在零件层上，用于给芯片主体21供电；电源输入线23包括电源输入线23的主体以及电源输入线23的两端，电源输入线23的主体设置在铜箔接地层，电源输入线23的两端设置在零件层，电源输入线23的主体通过印刷电路板29上的贯穿孔与电源输入线23的两端连接，具体为电源输入线23的主体通过印刷电路板29上的第一贯穿孔291与电源输入线23的一端连接，电源输入线23的主体通过印刷电路板29上的第二贯穿孔292与电源输入线23的另一端连接；旁路电容24也设置在零件层上，其一端通过零件层与芯片主体21的电源管脚连接，旁路电容24的另一端通过电源输入线23与电源线22连接，具体为电源输入线23的一端与旁路电容24连接，电源输入线23的另一端与电源线22连接；电源引入线25设置在铜箔接地层，电源引入线25通过印刷电路板29上的第三贯穿孔293与电源线22连接。
本优选实施例的芯片结构20中的电源线22设置在零件层上，该电源线22通过电源引入线25与电源（图中未示出）连接，通过电源输入线23，与旁路电容24以及芯片主体21的电源管脚连接。由于芯片结构20的主要部件（电源线22、旁路电容24以及芯片主体21）均设置在零件层，在铜箔接地层上仅设置有电源输入线23和电源引入线25（通过单斜线表示），电源输入线23通过设置在印刷电路板29上的第一贯穿孔291和第二贯穿孔292，与零件层上的电源线22以及旁路电容24连接。因此可在印刷电路板29的铜箔接地层上设置完整一体化的铜箔层，大大加强芯片结构20的散热能力，同时提高了芯片结构20的抗电磁干扰的能力，因此提高了芯片结构20的生产良率。
本优选实施例的芯片结构20使用时，电源通过设置在铜箔接地层的电源引入线25，经印刷电路板29的第三贯穿孔293给位于零件层的电源线22供电。电源线22与位于零件层的电源输入线23的一端连接，并依次通过位于铜箔接地层的电源输入线23的主体、电源输入线23的另一端给位于零件层的旁路电容24供电。最后旁路电容24通过零件层与芯片主体21的电源管脚连接，实现对芯片主体21的供电。
本优选实施例的芯片结构主要的电源线设置在零件层上，因此铜箔接地层的散热效果好，同时相应的芯片和电路的生产良率高。
请参照图3，图3为本发明的芯片结构的第二优选实施例的结构示意图。该芯片结构30设置在相应的印刷电路板39上，该印刷电路板39包括零件层和铜箔接地层，芯片结构30的表面元件均设置在零件层上，而芯片结构30的接地和散热元件均设置在铜箔接地层上。
上述的芯片结构30包括芯片主体31、电源线32、电源输入线33、旁路电容34、电源引入线35以及散热单元36。芯片主体31设置在零件层上，其包括多个电源管脚；电源线32设置在零件层上，用于给芯片主体31供电；电源输入线33包括电源输入线33的主体以及电源输入线33的两端，电源输入线33的主体设置在铜箔接地层，电源输入线33的两端设置在零件层，电源输入线33的主体通过印刷电路板39上的贯穿孔与电源输入线33的两端连接，具体为电源输入线33的主体通过印刷电路板39上的第一贯穿孔391与电源输入线33的一端连接，电源输入线33的主体通过印刷电路板39上的第二贯穿孔392与电源输入线33的另一端连接；旁路电容34也设置在零件层上，其一端通过零件层与芯片主体31的电源管脚连接，旁路电容34的另一端通过电源输入线33与电源线32连接，具体为电源输入线33的一端与旁路电容34连接，电源输入线33的另一端与电源线32连接；电源引入线35设置在铜箔接地层，电源引入线35通过印刷电路板39上的第三贯穿孔393与电源线32连接；散热单元36为设置在芯片主体31背面的裸铜结构，即将芯片主体31背面的铜箔接地层挖空，以设置裸铜结构。
本优选实施例在第一优选实施例的基础上，除了将芯片结构30的主要部件设置在零件层，从而大大加强芯片结构30的散热能力和抗电磁干扰的能力；还在芯片主体31背面设置大面积的裸铜结构作为散热单元36，这里优选散热单元36在印刷电路板39的投影区域至少覆盖芯片主体31的散热片在印刷电路板39的投影区域，该裸铜结构可将芯片主体31工作时散发的热量及时向外传导，从而通过铜箔接地层及时将热量散发出去，进一步增强了芯片结构30的散热能力。
在本优选实施例中，印刷电路板39为双层的印刷电路板39，包括设置在正面的零件层以及设置在背面的铜箔接地层（当然也可将零件层设置在印刷电路板39的正面，将铜箔接地层设置在印刷电路板39的背面），芯片主体31、电源线32、旁路电容34均设置在印刷电路板39的零件层上；电源输入线33的主体、电源引入线35以及散热单元均设置在印刷电路板39的铜箔接地层上。
优选的，电源线32设置在芯片主体31和旁路电容34之间（被芯片主体31遮住），电源线32的宽度优选为1.2毫米至2.5毫米，这样可进一步节省印刷电路板39上的空间。
本优选实施例的芯片结构在第一优选实施例的基础上，在芯片主体的背面设置裸铜结构作为散热单元，进一步增强了该芯片结构的散热效果。
本发明还提供一种电路结构，该电路结构包括上述的芯片结构。本发明的电路结构的工作原理与上述的芯片结构的第一优选实施例和第二优选实施例中的相关描述相同，具体请参见上述芯片结构的第一优选实施例和第二优选实施例中的相关描述。
本发明的芯片结构及电路结构的电源线设置在零件层上，因此铜箔接地层的散热效果好，同时相应的芯片和电路的生产良率高；解决了现有的芯片结构及电路结构的散热效果较差以及生产良率较低的技术问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
工业实用性
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Claims (20)

  1. 一种芯片结构，所述芯片结构设置在具有零件层和铜箔接地层的印刷电路板上，其包括：
    芯片主体，设置在所述零件层，包括多个电源管脚；
    电源线，设置在所述零件层，用于给所述芯片主体供电；
    电源输入线，所述电源输入线的主体设置在所述铜箔接地层，所述电源输入线的两端设置在所述零件层；所述电源输入线的主体通过所述印刷电路板上的贯穿孔与所述电源输入线的两端连接；以及
    旁路电容，所述旁路电容的一端通过所述零件层与所述芯片主体的所述电源管脚连接，所述旁路电容的另一端通过所述电源输入线与所述电源线连接；
    其中所述电源输入线的主体通过所述印刷电路板上的第一贯穿孔与所述电源输入线的一端连接，所述电源输入线的主体通过所述印刷电路板上的第二贯穿孔与所述电源输入线的另一端连接；
    所述电源输入线的一端与所述旁路电容连接，所述电源输入线的另一端与所述电源线连接。
  2. 根据权利要求1所述的芯片结构，其中所述芯片结构还包括：
    电源引入线，设置在所述铜箔接地层，所述电源引入线通过所述印刷电路板上的第三贯穿孔与所述电源线连接。
  3. 一种芯片结构，所述芯片结构设置在具有零件层和铜箔接地层的印刷电路板上，其包括：
    芯片主体，设置在所述零件层，包括多个电源管脚；
    电源线，设置在所述零件层，用于给所述芯片主体供电；
    电源输入线，所述电源输入线的主体设置在所述铜箔接地层，所述电源输入线的两端设置在所述零件层；所述电源输入线的主体通过所述印刷电路板上的贯穿孔与所述电源输入线的两端连接；以及
    旁路电容，所述旁路电容的一端通过所述零件层与所述芯片主体的所述电源管脚连接，所述旁路电容的另一端通过所述电源输入线与所述电源线连接。
  4. 根据权利要求3所述的芯片结构，其中所述电源输入线的主体通过所述印刷电路板上的第一贯穿孔与所述电源输入线的一端连接，所述电源输入线的主体通过所述印刷电路板上的第二贯穿孔与所述电源输入线的另一端连接。
  5. 根据权利要求3所述的芯片结构，其中所述电源输入线的一端与所述旁路电容连接，所述电源输入线的另一端与所述电源线连接。
  6. 根据权利要求3所述的芯片结构，其中所述芯片结构还包括：
    电源引入线，设置在所述铜箔接地层，所述电源引入线通过所述印刷电路板上的第三贯穿孔与所述电源线连接。
  7. 根据权利要求3所述的芯片结构，其中所述芯片结构还包括：
    散热单元，设置在所述芯片主体的背面。
  8. 根据权利要求7所述的芯片结构，其中所述散热单元为设置在所述芯片主体背面的裸铜结构。
  9. 根据权利要求8所述的芯片结构，其中所述散热单元在所述印刷电路板的投影区域至少覆盖所述芯片主体的散热片在所述印刷电路板的投影区域。
  10. 根据权利要求3所述的芯片结构，其中所述铜箔接地层设置有一体化的铜箔层。
  11. 根据权利要求3所述的芯片结构，其中所述电源线的宽度范围为1.2毫米至2.5毫米。
  12. 一种电路结构，其包括：
    芯片结构，所述芯片结构设置在具有零件层和铜箔接地层的印刷电路板上，其包括：
    芯片主体，设置在所述零件层，包括多个电源管脚；
    电源线，设置在所述零件层，用于给所述芯片主体供电；
    电源输入线，所述电源输入线的主体设置在所述铜箔接地层，所述电源输入线的两端设置在所述零件层；所述电源输入线的主体通过所述印刷电路板上的贯穿孔与所述电源输入线的两端连接；以及
    旁路电容，所述旁路电容的一端通过所述零件层与所述芯片主体的所述电源管脚连接，所述旁路电容的另一端通过所述电源输入线与所述电源线连接。
  13. 根据权利要求12所述的电路结构，其中所述电源输入线的主体通过所述印刷电路板上的第一贯穿孔与所述电源输入线的一端连接，所述电源输入线的主体通过所述印刷电路板上的第二贯穿孔与所述电源输入线的另一端连接。
  14. 根据权利要求12所述的电路结构，其中所述电源输入线的一端与所述旁路电容连接，所述电源输入线的另一端与所述电源线连接。
  15. 根据权利要求12所述的电路结构，其中所述芯片结构还包括：
    电源引入线，设置在所述铜箔接地层，所述电源引入线通过所述印刷电路板上的第三贯穿孔与所述电源线连接。
  16. 根据权利要求12所述的电路结构，其中所述芯片结构还包括：
    散热单元，设置在所述芯片主体的背面。
  17. 根据权利要求16所述的电路结构，其中所述散热单元为设置在所述芯片主体背面的裸铜结构。
  18. 根据权利要求17所述的电路结构，其中所述散热单元在所述印刷电路板的投影区域至少覆盖所述芯片主体的散热片在所述印刷电路板的投影区域。
  19. 根据权利要求12所述的电路结构，其中所述铜箔接地层设置有一体化的铜箔层。
  20. 根据权利要求12所述的电路结构，其中所述电源线的宽度范围为1.2毫米至2.5毫米。
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