WO2023273635A1 - 一种滤波模组和电子设备 - Google Patents

一种滤波模组和电子设备 Download PDF

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Publication number
WO2023273635A1
WO2023273635A1 PCT/CN2022/092549 CN2022092549W WO2023273635A1 WO 2023273635 A1 WO2023273635 A1 WO 2023273635A1 CN 2022092549 W CN2022092549 W CN 2022092549W WO 2023273635 A1 WO2023273635 A1 WO 2023273635A1
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WO
WIPO (PCT)
Prior art keywords
chip
power
circuit board
printed circuit
conductive
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Application number
PCT/CN2022/092549
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English (en)
French (fr)
Inventor
白昕昊
眭克涵
周宴
蔡远彬
Original Assignee
华为技术有限公司
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Publication of WO2023273635A1 publication Critical patent/WO2023273635A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components

Definitions

  • the present application relates to the field of circuit technology, in particular to a filter module and electronic equipment.
  • the power supply requirements of chips also increase. For example, at present, the steady-state current of some chips exceeds 1000A, and the transient current jump exceeds 2000A/uS.
  • the large current and the rapid transient current jump need to be quickly discharged by the power supply circuit in the power supply circuit to suppress the voltage drop. Improving capacitor layout density is a key technology for product success.
  • the first aspect of the embodiment of the present application provides a filter module, the module includes a printed circuit board, a chip packaging structure, a power module, multiple capacitors, an expansion board, and at least one additional capacitor;
  • the printed circuit board has an upper surface and a lower surface opposite the upper surface;
  • the chip packaging structure is arranged on the upper surface of the printed circuit board;
  • the upper surface of the printed circuit board includes a chip power contact area
  • the chip power contact area includes a chip power contact
  • the power module supplies power to the chip packaging structure through the power contact
  • the lower surface of the printed circuit board includes a first area, and the first area is disposed opposite to the chip power contact area;
  • the plurality of capacitors are arranged in parallel in the first region, and the plurality of capacitors are arranged in parallel between the connection line of the power module for supplying power to the chip packaging structure and the ground wire;
  • the lower surface of the printed circuit board includes a second area, and the second area is set corresponding to the non-chip power contact area;
  • the expansion board is arranged in the second area
  • the at least one additional capacitor is connected in parallel with the plurality of capacitors and is arranged on the expansion board.
  • the filter module can also be called a chip module
  • the non-chip power contact area can be any one or more of the storage contact area adjacent to the chip power contact area and the high-speed input and output contact area. kind.
  • the second area may be any one or more of the storage pin area and the input/output pin area, but is not limited thereto.
  • An expansion board also called a pinch board, is a carrier for electrical interconnection of electronic components, for example, a printed circuit board.
  • a chip packaging structure may be disposed in the chip placement area.
  • connection wire and the ground wire that the power supply module supplies power to the chip packaging structure can refer to the embodiment shown in Figure 11, the conductive channel 126 as the power line is set in the PCB120, and the conductive channel 126 extends from the upper surface 121 of the PCB120 to the thickness of the PCB120 (z axis ) direction, and then extend the degree direction (y-axis), and then extend the PCB120 thickness (z-axis) direction to reach the bending channel on the upper surface 121 of the PCB120, and the inner wall of the bending channel is provided with a conductive medium, such as copper , but not limited to this. As shown in FIG. 9 , the conductive via hole 127a serves as a ground wire.
  • the embodiment of the present application can store more capacitors by adding additional capacitors, and can use The electrical energy stored in the additional capacitor reduces the instantaneous voltage drop.
  • At least one conductive via and at least one ground via are provided on the expansion board;
  • a conductive hole is provided in the printed circuit board, and one end of the conductive hole is electrically connected to the connection line that the power module supplies power to the chip packaging structure;
  • the other end of the conductive hole is electrically connected to one end of each additional capacitor in the at least one additional capacitor, and the other end of each additional capacitor in the at least one additional capacitor is connected to the printed circuit board through the ground via hole.
  • the ground wire electrical connection in the circuit board.
  • the filter module further includes a first conductive channel, and the first conductive channel does not penetrate the printed circuit board in the thickness direction of the printed circuit board;
  • the conductive via hole is located between the first conductive channel and the lower surface.
  • the first conductive channel that does not pass through the printed circuit board in the thickness direction, the position of the conductive via hole between the first conductive channel and the lower surface has a large space for the conductive channel connected to the power line ( X-axis direction, Y-axis direction, Z-axis direction) position.
  • the at least one additional capacitor is disposed on a lower surface of the expansion board.
  • part of the at least one additional capacitor is disposed on a lower surface of the expansion board, and the rest of the additional capacitance is disposed inside the expansion board.
  • the at least one additional capacitor is disposed inside the expansion board.
  • the printed circuit board has a multi-layer structure, and the conductive holes are conductive via holes that are sequentially electrically connected in partial layer structures in the printed circuit board.
  • the non-chip power contact area is a contact area adjacent to the chip power contact area.
  • non-chip power contact area may be any one or more of the storage contact area and the high-speed input/output contact area adjacent to the chip power contact area.
  • the chip package structure is an application processor, a modem processor, a graphics processor, an image signal processor, a controller, a video codec, or a digital signal processor
  • the filtering module further includes a power device, and the power device is disposed on the expansion board.
  • capacitors connected in parallel can be arranged on the expansion board, so that the above-mentioned problems of voltage drop and instantaneous voltage drop can be better reduced.
  • other power devices other than capacitors such as resistors and inductors, can also be set on the expansion board. Power devices other than capacitors can be connected in series or in parallel with additional capacitors.
  • the embodiment of the present application further provides an electronic device, which is characterized in that the electronic device includes the filtering module described in any one of the first aspect.
  • Fig. 1 shows a schematic diagram of an application scenario of a chip module mentioned in the technical solution of the present application according to some embodiments of the present application;
  • FIG. 2 shows a schematic structural diagram of a base station 1 according to an embodiment of the present application
  • Fig. 3 shows a schematic structural diagram of a general chip module according to some embodiments of the present application
  • FIG. 4 is an exploded view of the chip module 100 in FIG. 3 along the Y-axis direction;
  • FIG. 5 is based on the chip module structure of FIG. 3 , according to the different connecting devices of the pins, it shows a schematic diagram of the area distribution of different types of pins on the lower surface 111 of the chip packaging structure 110 and the upper surface 121 of the PCB 120;
  • FIG. 6 shows a schematic distribution diagram of adding expansion boards and additional capacitors on the lower surface 124 of the printed circuit board 120
  • FIG. 7 shows a cross-sectional view of the chip module 100 taken along the A-A direction shown in FIG. 3 in some embodiments;
  • FIG. 8 shows a schematic distribution diagram of adding expansion boards and additional capacitors on the lower surface 124 of the printed circuit board 120
  • Figure 9 shows a cross-sectional view of the chip module obtained along the A-A direction in Figure 3;
  • Fig. 10 shows a cross-sectional view of another chip module obtained along the A-A direction in Fig. 3;
  • FIG. 11 shows a schematic cross-sectional view of the chip module 100 obtained along the B-B direction shown in FIG. 3;
  • Fig. 12 shows a cross-sectional view of a chip module on the YZ plane
  • Fig. 13 shows a partial cross-sectional view on a YZ plane in which an additional capacitor is arranged in an expansion board
  • Fig. 14 shows a partial cross-sectional view on a YZ plane in which an additional capacitor is arranged in an expansion board
  • FIG. 15 shows a schematic diagram of adding expansion boards and additional capacitors on the lower surface 124 of the printed circuit board 120
  • Fig. 16 shows the sectional view of the universal chip module obtained along the A-A direction in Fig. 3;
  • FIG. 17 shows a schematic distribution diagram of adding expansion boards and additional capacitors on the lower surface 124 of the printed circuit board 120;
  • Fig. 18 shows the sectional view of the universal chip module obtained along the A-A direction in Fig. 3;
  • FIG. 19 shows a cross-sectional view of a chip module taken along the A-A direction in FIG. 3 corresponding to FIG. 8 according to an embodiment of the present application;
  • Fig. 20 shows a simple structural circuit diagram among a power module 140, a chip packaging structure 110, a capacitor 160, a capacitor 180, and a capacitor 190 according to an embodiment of the present application;
  • FIG. 21 is a schematic diagram of a power distribution network curve (power delivery network, PDN) without an expansion board 170 on the chip module 100;
  • PDN power delivery network
  • FIG. 22 is a schematic diagram of the PDN curve after the expansion board 170 is attached on the PCB 120 of the chip module 100 .
  • F-additional capacitor F2-capacitor body; F1-first electrode terminal; F3-second electrode terminal;
  • 170-expansion board 171-conductive via; 172-the lower surface of the expansion board; 173-the upper surface of the expansion board; 200-solder ball.
  • connection should be understood in a broad sense, for example, it can be a fixed electrical connection or a Detachable electrical connection, or integral electrical connection; may be mechanical electrical connection, or electrical connection; may be direct connection, or indirect connection through an intermediary, or internal communication between two components.
  • Illustrative embodiments of the present application include, but are not limited to, a chip module and a base station.
  • a chip module and a base station.
  • the technical solution of this application is described using a base station as an application scenario, but it can be understood that the chip module mentioned in the technical solution of this application can also be used in other electronic devices, such as servers, satellite systems, and so on.
  • Fig. 1 shows a schematic diagram of an application scenario of a chip module mentioned in the technical solution of the present application according to some embodiments of the present application.
  • the base station 1 is a public mobile communication base station, which is an interface device for the terminal 2 and the terminal 3 to access the Internet, and information is transmitted between the terminal 2 and the terminal 3 through the base station 1 .
  • FIG. 2 shows a schematic structural diagram of a base station 1 according to an embodiment of the present application.
  • the base station 1 may include a central processing unit 110 , a signal receiver 101 , a signal transmitter 102 , a power module 140 , a memory 130 , a video surveillance instrument control chip 150 and a video surveillance instrument 103 .
  • the chip module mentioned in this application may be integrated with a central processing unit 110 , a power supply module 140 , a memory 130 , a video surveillance instrument control chip 150 and a video surveillance instrument 103 .
  • the signal receiver 101 , the signal transmitter 102 , the power supply module 140 , the memory 130 and the video monitoring instrument 103 are respectively connected to the central processing unit 110 .
  • Power supply module 140 is used to supply power to central processing unit 110, signal receiver 101, signal transmitter 102, power supply module 140, memory 130, video surveillance instrument control chip 150 and video surveillance instrument 103; Part of the data sent; the video surveillance instrument control chip 150 is used to control the working state of the video surveillance instrument 103; the video surveillance instrument 103 is used to shoot video and sends the video data to the central processing unit 110 for processing by the video surveillance instrument control chip 150, and the central processing unit
  • the processor 110 may also further send the captured video data to the memory 130 for storage.
  • the signal receiver 101 is used for receiving information sent by other devices, and the signal transmitter 102 is used for forwarding the information received by the signal receiver 101 to other devices.
  • terminal 1 In the application scenario shown in FIG. 1 , assuming that user 1 wants to use terminal 1 to send information to terminal 2 of user 2, terminal 1 needs to forward the information to terminal 2 of user 2 through base station 2 .
  • user 1 uses terminal 1 to send signal receiver 101 to receive information, such as the information of terminal 1, and send the received information to central processing unit 110, after central processing unit 110 encodes the received information, to the signal transmitter 102, and the signal transmitter 102 sends the encoded information to other devices, such as the terminal 2.
  • the power supply module 140 needs to provide a large and stable current to the CPU 110 .
  • the power supply circuit for the power module 140 to supply power to the CPU 110 cannot effectively suppress the drop of the output voltage of the power module 140 to the CPU 110 .
  • the chip module may include the above-mentioned power module 140 and the central processing unit 110, and in the chip module, the power module 140 provides the central processing unit
  • An additional capacitor is added in the circuit for power supply to the central processor 110 by the power supply module 140 to reduce the impedance of the power supply circuit to the central processing unit 110, and reduce the voltage drop during the power supply process of the power supply module 140 to the central processing unit 110, and compared with the existing
  • the additional capacitors can store more capacitors.
  • the power supply module 140 supplies power to the central processing unit 110 when there is an instantaneous voltage drop, the electric energy stored in the additional capacitors can be used to reduce the instantaneous voltage. pressure drop.
  • the above-mentioned base station 1 is used as an example to illustrate the chip module in the technical solution of the present application, but it can be understood that the chip module in the technical solution of the present application can also be applied to other electronic devices, such as servers and satellite systems.
  • Fig. 3 shows a schematic structural diagram of a general chip module according to some embodiments of the present application.
  • the chip module may include the central processing unit 110 of the above-mentioned base station 1 , the memory 130 , the power supply module 140 , and the video monitoring instrument control chip 150 .
  • the chip module 100 includes a chip packaging structure 110, a printed circuit board (Printed Circuit Board, PCB) 120, a memory 130, a power module 140, and a video monitoring instrument control chip 150.
  • a printed circuit board Printed Circuit Board, PCB
  • PCB printed Circuit Board
  • the chip package structure 110 is the central processing unit 110 in the above-mentioned base station 1, which is also called a chip package (Chip package), which refers to a plurality of leads packaged and arranged to be used for electrical connection with other electronic devices. A structure of the foot.
  • Chip package Chip package
  • a die is a chip produced in a processing factory, that is, a chip that has not been packaged after the wafer has been cut and tested.
  • This kind of die has only pads for packaging, and cannot be directly packaged. used in practical circuits.
  • the bare chip is very vulnerable to the temperature, impurities and physical force of the external environment, and is easily damaged. Therefore, it must be sealed in a closed space and lead out the corresponding pins before it can be used as a basic component.
  • the bare chip is usually installed on a chip package carrier board, and the internal circuit of the bare chip is electrically connected with the package pin by a bonding wire (gold wire) (bonding). After bonding, the bare chip is packaged with black glue to ensure Form a chip package (Chip package).
  • the chip package structure 110 may refer to the modem processor, graphics processor, image signal processor, controller, Video codec, digital signal processor, baseband processor, neural network processor, etc., and application processor, modem processor, graphics processor, image signal processor, controller, video codec, digital signal Integration of at least two processors among processors, baseband processors, and neural network processors. That is, different processing units may be independent devices, or may be integrated in one or more processors.
  • a printed circuit board (Printed Circuit Board, PCB) 120 is a support for electronic components and a carrier for electrical connection with electronic components. Specifically, in some electronic structures, on the upper surface 121 of the PCB 120, a chip package structure 110, a memory 130, a power module 140, a video monitoring instrument control chip 150, etc. are arranged, but not limited thereto.
  • the chip module 100 lies substantially in a plane (XY plane), wherein the Z-axis direction (referred to as "normal") is oriented from the chip module 100 toward the viewer, i.e., the chip The thickness direction of the module 100 .
  • the X-axis direction is defined as the length direction of the chip module 100 from left to right.
  • the Y-axis direction is defined as the width direction of the chip module 100 from front to back.
  • a printed circuit board (Printed Circuit Board, PCB) 120 and a chip package structure 110 are sequentially arranged in the y-axis direction.
  • the chip package structure 110 and the printed circuit board (Printed Circuit Board, PCB) 120 can be electrically connected through a conductive medium (not shown in the figure).
  • FIG. 4 is an exploded view of the chip module 100 in FIG. 3 along the Y-axis direction.
  • the PCB 120 has an upper surface 121 facing the Z-axis direction.
  • the upper surface 121 has a chip installation area 122 on which the chip packaging structure 110 is located.
  • the non-chip setting area 123 adjacent to the chip setting area 122 on the upper surface 121 of the PCB 120 is used to set some electronic devices, such as memory 130, power module 140, video monitoring instrument control chip 150, etc., but not limited thereto.
  • the chip package structure 110 has a lower surface 111 facing the opposite direction of the Z-axis, and the lower surface 111 is used for bonding with the chip installation area 122 on the upper surface 121 of the PCB 120 .
  • the chip packaging structure 110 may be a printed circuit board (Ball Grid Array, BGA) with a ball grid array structure, which is a packaging method for integrated circuits using an organic carrier board.
  • Fig. 5 is based on the chip module structure of Fig. 3, according to the different connecting devices of the pins, it shows the regional distribution of different types of pins on the lower surface 111 of the chip packaging structure 110 and the upper surface 121 of the PCB 120 schematic diagram.
  • a chip power pin area 1112 is provided on the lower surface 111 of the chip package structure 110 , and the power module 140 can supply power to the chip package structure 110 through the power pins in the chip power pin area 1112 .
  • the upper surface 121 of the PCB 120 is provided with a chip power contact area 1212, wherein, the power contacts in the chip power contact area 1212 are used to communicate with the chip
  • the power pins in the power pin area 1112 are electrically connected, and the power module 140 can supply power to the chip package structure 110 through the power contacts and the power pins.
  • the chip power supply pin area 1112 may be arranged in the middle area of the lower surface 111 of the chip package structure 110 , but is not limited thereto.
  • the lower surface 111 of the chip package structure 110 is provided with a storage pin area 1113, and the chip package structure 110 can send the data to be stored to the memory 130 through the memory pins in the storage pin area 1113, and the storage pin
  • the area 1113 may also be referred to as a DDR area or a DDR area.
  • the upper surface 121 of the PCB 120 is provided with a storage contact area 1213, wherein the memory contacts in the storage contact area 1213 are used to communicate with the storage pin area
  • the memory pins in 1113 are connected, and the chip package structure 110 can send the data to be stored to the memory 130 through the memory pins and memory contacts.
  • the storage pin area 1113 may be arranged on the peripheral area adjacent to the chip power pin area 1112 on the lower surface 111 of the chip package structure 110 , but is not limited thereto.
  • the lower surface 111 of the chip package structure 110 is provided with an input and output pin area 1114 , and the chip package structure 110 can communicate with the video monitoring instrument control chip 150 through the input and output pins of the input and output pin area 1114 .
  • the input and output pin area 1114 may also be called a high-speed I/O (Input/output, input and output) area or a high-speed I/O area.
  • the upper surface 121 of the PCB 120 is provided with an input and output contact area 1214, wherein the input and output contacts in the input and output contact area 1214 are used for It is connected to the input and output pins, and the chip packaging structure 110 can perform command interaction and data transmission with the video monitoring instrument control chip 150 through the input and output contacts and the input and output pins.
  • the input and output pin area 1114 may be arranged on the peripheral area adjacent to the chip power pin area 1112 on the lower surface 111 of the chip package structure 110 , but is not limited thereto.
  • a power pin area 1111 is provided on the lower surface 111 of the chip package structure 110 , and the chip package structure 110 can supply power to electronic devices such as the memory 130 through the power pins of the power pin area 1111 .
  • the upper surface 121 of the PCB 120 is provided with a power contact area 1211, wherein the power contact in the power contact area 1211 can pass through the power pin and
  • the power contacts provide power to electronics such as memory 130 .
  • the input and output contact area 1214 and the storage contact area 1213 are collectively referred to as the non-chip power contact area, and the input and output pin area 1114, the input and output contact area 1214, the storage pin area 1113 and the storage contact area 1213 are collectively referred to as for the non-power area.
  • the power supply circuit between the power module 140 and the chip packaging structure 110 is provided with a plurality of parallel capacitors, and the multiple parallel capacitors are used to connect the power supply module 140 and the chip packaging structure 110
  • the electrical signal (current and/or voltage) is filtered and the voltage is stabilized, which is generally arranged in the area corresponding to the chip power contact area 1212 on the lower surface 124 of the PCB 120 shown in FIG. 4 .
  • the capacitance in the power supply circuit can be increased in the area corresponding to the area outside the power contact area 1212 on the lower surface 124 of the PCB 120.
  • FIG. A schematic diagram of the distribution of expansion boards and additional capacitors is added on the above.
  • the area on the lower surface 124 of the PCB 120 corresponds to the storage contact area 1213 .
  • FIG. 7 shows a cross-sectional view of the chip module 100 taken along the A-A direction shown in FIG. 3 in some embodiments.
  • a signal line is provided in the thickness direction (Z axis) of the non-power supply area of the PCB 120.
  • the signal line mainly refers to the line used to transmit non-power supply signals, or to transmit sensing information and control.
  • the line of information or mainly refers to the line used to transmit signals and instructions.
  • the strip is along the thickness direction of the PCB 120 (Z axis) but does not completely penetrate the conductive channel 127b of the PCB 120, and the conductive channel 127c along the length direction of the PCB 120 (X axis), and one end of a part of the conductive channel 127c can be electrically connected with one end of the conductive channel 127b, The middle portion of part of the conductive via hole 127a may be electrically connected to one end of the conductive channel 127b.
  • the conductive vias 127a and the conductive channels 127b of the storage contact area 1213 can be used as signal lines for passing other signals except the power supply.
  • the command data signal, the conductive via hole 127a and the conductive channel 127b of the storage contact area 1213 can also be used as a ground wire.
  • the additional capacitance F is arranged on the non-power supply area (such as the storage contact area 1213) of the lower surface 124 of the PCB120, then there is an additional capacitance F and the signal line on the non-power supply area of the lower surface 124 of the PCB120 is electrically connected, and the non-power supply
  • the signal is introduced between the power supply line between the power supply module 140 and the chip packaging structure 110, and because the voltage required by the signal line and the power line are different, for example, the current on the signal line is very small, but the power supply is used to drive The post-stage circuit, so the current on the power line will be large, which may easily cause short circuits in the power supply circuit and other non-power circuits.
  • the additional capacitor F is a chip capacitor, including a capacitor body F2 and a first electrode terminal F1 and a second electrode terminal arranged at both ends of the capacitor body F2. If the conductive via hole 127a is a signal line, since two adjacent The position between two conductive via holes 127a is limited. If an additional capacitor F is set between two adjacent conductive via holes 127a, there will be a first electrode terminal F1 and a second electrode terminal F3 of the additional capacitor F connected to the two electrodes respectively.
  • the conductive vias 127a serving as signal lines are electrically connected, causing non-power signals to be introduced between the power supply lines between the power module 140 and the chip packaging structure 110, and interfere with signal transmission in the signal lines. And because the voltage required by the signal line and the power line are different, for example, the current on the signal line is very small, but the power supply is used to drive the subsequent circuit, so the current on the power line will be large, which is easy to cause power supply circuit and other The problem is not a short circuit of the power supply.
  • the space of the non-power supply region that does not completely penetrate the conductive channel 127b of the PCB 120 is greater than the distance between two adjacent conductive vias 127a, for example, as shown in FIG. 9, if the space between two adjacent conductive vias 127a Including the conductive channel 127b that does not completely penetrate the PCB 120, the distance d2 between the two adjacent conductive vias 127a that includes the conductive channel 127b that does not completely penetrate the PCB 120 is greater than the distance d1 between the adjacent two conductive vias 127a, It has a large space (X-axis direction, Y-axis direction, Z-axis direction) where the conductive channel connecting the power line can be set.
  • the following describes several chip module structures that solve the above-mentioned short-circuit problem.
  • FIG. 8 shows a schematic diagram of adding expansion boards and additional capacitors on the lower surface 124 of the printed circuit board 120 .
  • an expansion board 170 is added on the lower surface 124 of the PCB 120 corresponding to the storage contact area 1213 , and an additional capacitor F is added on the expansion board.
  • FIG. 9 shows a cross-sectional view of the chip module taken along the direction A-A in FIG. 3 .
  • the expansion board 170 has an upper surface 171 facing the Y-axis direction, and a lower surface 172 facing the Y-axis direction. It is electrically connected to the lower surface 124 of the printed circuit board 120 .
  • the additional capacitor F In order to electrically connect the additional capacitor F to the power line in the printed circuit board 120, thereby reducing the impedance of the power supply line from the power module 140 to the chip packaging structure 110 and reducing the voltage drop during the power supply process of the power module 140 to the chip packaging structure 110, And when the power supply module 140 supplies power to the chip packaging structure 110 when there is an instantaneous voltage drop, the electric energy stored in the additional capacitor can be used to reduce the instantaneous voltage drop.
  • Two conductive vias 173 penetrating along the Z-axis direction are provided on the expansion board 170 , and a conductive channel 129 is provided in the PCB 120 with an opening located on the lower surface 124 and extending along the Z-axis direction.
  • the conductive channel 129 is located between two adjacent conductive vias 127 a, and the conductive channel 127 b that does not completely penetrate the PCB 120 is included between the adjacent two conductive vias 127 a.
  • the conductive channels 129 provided on the PCB 120 all appear in pairs, one conductive channel 129 is used to connect one electrode of the additional capacitor F to the power line, and the other conductive channel 129 is used to connect the other electrode of the additional capacitor F The electrode is grounded.
  • one end of the conductive via hole 173 is electrically connected to the second electrode terminal F2, for example, the electrical connection is realized through surface mount technology (Surface Mounted Technology, SMT), and the other end of the conductive via hole 173 is connected through a solder ball.
  • SMT Surface Mounted Technology
  • 200 is soldered to one end of the conductive channel 129 on the lower surface 124 of the printed circuit board 120, and the conductive channel 129 is used to electrically connect with the power line inside the PCB 120, so as to realize the electrical connection between the additional capacitor F and the power line.
  • the conductive channel 127b along the Z-axis direction of the PCB 120 and not completely passing through the PCB 120 may be on a straight line with the conductive channel 129 .
  • the conductive channel 127b and the conductive channel 129 may be two components of a conductive via hole penetrating the PCB 120 along the Z-axis direction of the PCB 120 , which will be described in detail below. It can be understood that the above-mentioned PCB120 and expansion board 170 are allocated through conductive vias, so that the pins on the PCB120 are consistent with the contacts on the expansion board 170. The number of links between the PCB120 and the expansion board 170 needs to be determined by the weight of the expansion board, adhesion, loop Comprehensive assessment of DCR impact.
  • one end of the conductive via 173 is electrically connected to the second electrode terminal F1, for example, through surface mount technology (Surface Mounted Technology) (Surface Mounted Technology, SMT) to achieve electrical connection, and the conductive The other end of the via hole 173 is soldered to one end of the conductive via hole 127 a on the lower surface 124 of the printed circuit board 120 through a solder ball 200 . In this way, an additional capacitive ground can be achieved.
  • surface mount technology Surface Mounted Technology
  • SMT Surface Mounted Technology
  • FIG. 9 only shows the smaller expansion board 170 and one or additional capacitors F set on the expansion board 170, but in the embodiment of the present application, the expansion board 170 It can be a longer printed circuit board extending along the X direction, and more parallel additional capacitors F can be set on the expansion board 170, so that the above-mentioned problems of voltage drop and instantaneous voltage drop can be better reduced .
  • other power devices other than capacitors, such as resistors and inductors, may also be provided on the expansion board 170 . Other power devices except capacitors can be connected in series or in parallel with the additional capacitor F, etc.
  • the conductive channels 129 provided on the PCB 120 are all in pairs, one conductive channel 129 is used to connect an electrode of the additional capacitor F to the power line, and the other conductive channel 129 is used to connect the electrode of the additional capacitor F The other electrode is grounded.
  • the other conductive channel for grounding may not use the one originally set in the PCB 120 for grounding. Instead of conductive vias 127, a conductive channel for grounding is newly added.
  • FIG. 10 shows a cross-sectional view of another chip module taken along the A-A direction in FIG. 3 . As shown in FIG.
  • the additional opening in the PCB 120 is located on the lower surface 124 , and a conductive channel 129 for grounding is provided extending along the Z-axis direction.
  • the conductive channel 129 is located between two adjacent conductive vias 127 a, and the conductive channel 127 b that does not completely penetrate the PCB 120 is included between the adjacent two conductive vias 127 a.
  • One end of the conductive via hole 173 is electrically connected to the second electrode terminal F1, and the other end of the conductive via hole 173 is soldered to one end of the conductive channel 129 for grounding on the lower surface 124 of the printed circuit board 120 through the solder ball 200, so, also Additional capacitance to ground can be achieved.
  • FIG. 11 shows a chip taken along the B-B direction shown in FIG.
  • the schematic cross-sectional view of the module 100 is set in the PCB120 as the conductive channel 126 of the power line, the conductive channel 126 extends from the upper surface 121 of the PCB120 along the direction of the thickness of the PCB120 (z axis), and then extends in the direction of the degree (y axis), and then extend along the thickness (z-axis) direction of the PCB 120 to reach the bending channel on the upper surface 121 of the PCB 120, and the inner wall of the bending channel is provided with a conductive medium, such as copper, but not limited thereto.
  • a conductive medium such as copper, but not limited thereto.
  • FIG. 12 shows a cross-section of a chip module on the YZ plane picture. As shown in FIG. 12 , one end of the conductive channel 129 is electrically connected to the conductive channel 126 after extending along the Y-axis direction.
  • the other end of the conductive channel 129 can be soldered to one end of the conductive via 173 on the expansion board 170 through the solder ball 200, and the other end of the conductive via 173 is electrically connected to the second electrode terminal F2, so that the additional capacitor F can be connected by conducting
  • the via hole 171 and the conductive channel 129 are connected in parallel to the conductive channel 126 as a power line for electrical connection. On the one hand, it is used to reduce the impedance of the power supply line from the power module 140 to the chip packaging structure 110, and reduce the power supply from the power module 140 to the chip packaging structure 110.
  • the additional capacitor F can store more capacitance, and an instantaneous voltage drop is generated when the power module 140 supplies power to the chip packaging structure 110 In some cases, the electric energy stored in the additional capacitor can be used to reduce the instantaneous voltage drop.
  • the above-mentioned electrical connection method is through solder balls, in addition, it can also be conductive paste, which is not limited here.
  • the additional capacitor F is arranged on the surface of the expansion board 170.
  • the additional capacitor F can also be set Inside the expansion board 170 .
  • an additional capacitor F may also be provided inside the expansion board 170 .
  • FIG. 13 shows a partial cross-sectional view on a YZ plane in which an additional capacitor is provided in an expansion board.
  • an additional capacitor F is embedded in the expansion board 170 .
  • the additional capacitor F is disposed inside the expansion board 170 .
  • One end of a conductive via 173 is electrically connected to the second electrode terminal F2 of the additional capacitor F, and the other end of the conductive via 173 is electrically connected to the conductive channel 129 through the solder ball 200, so that the additional capacitor F can pass through the conductive via 173
  • the power supply line (power channel) is connected in parallel; one end of the other conductive via 173 is electrically connected to the first electrode terminal F1 of the additional capacitor F, and the other end of the other conductive via 173 is connected to the ground via the solder ball 200
  • the conductive channel 129 is electrically connected.
  • the additional capacitor F can be set inside the expansion board 170 or outside the expansion board 170 .
  • FIG. 14 shows a partial cross-sectional view on a YZ plane in which an additional capacitor is arranged in an expansion board. As shown in FIG. Set additional capacitance F.
  • the second electrode terminal F2 of the additional capacitor F provided inside the expansion board 170 is electrically connected to the middle of the conductive via hole 173, and the second electrode terminal F2 of the additional capacitor F provided on the lower surface 172 of the expansion board 170 is connected to the conductive via hole.
  • One end of the conductive via 173 is electrically connected, and the other end of the conductive via 173 is electrically connected to the conductive channel 129 for grounding through the solder ball 200 .
  • One end of the other conductive via 173 is electrically connected to the first electrode terminal F1 of the additional capacitor F provided inside the expansion board 170 , and the middle part of the other conductive via 173 is connected to the additional capacitor F provided on the lower surface 172 of the expansion board 170 .
  • the first electrode terminal F1 of F is electrically connected.
  • the other end of the other conductive via 173 is electrically connected to the conductive channel 129 for grounding through the solder ball 200 .
  • the additional capacitor F disposed inside the expansion board 170 and the additional capacitor F disposed on the lower surface 172 of the expansion board 170 can be electrically connected to the power line (power channel) in parallel through the conductive via 173 .
  • the additional capacitor can be a 0402 high-frequency decoupling capacitor, or a 0805 or 1206 high-capacity capacitor, but it is not limited thereto.
  • the expansion board 170 may be a structure in the form of a silicon base, a thin film, or the like.
  • the conductive via 171 adopts the VIA10 large hole scheme to ensure the flow capacity of a single hole and reduce ESR, Equivalent Series Inductance (ESL), etc., to improve the filtering performance; the thickness of the expansion board 170 can be controlled within 1mm to provide excellent loop characteristics.
  • the conductive channel 127b and the conductive channel 129 can be two components of a conductive via hole that penetrates the PCB 120 along the Z-axis direction of the PCB 120.
  • the conductive channel 127b that does not pass through the thickness direction (Y-axis direction) of the PCB 120 is set in the PCB120.
  • the conductive channel 129 is set in the space along the thickness direction (the direction opposite to the Y-axis) in the PCB120.
  • the additional capacitor F is electrically connected to the power line in the printed circuit board 120 through the conductive channel 129, thereby reducing the impedance of the power supply line from the power module 140 to the chip packaging structure 110, and reducing the power supply from the power module 140 to the chip packaging structure 110
  • the voltage drop during the process, and the function of reducing the instantaneous voltage drop by using the electric energy stored in the additional capacitor when the power supply module 140 supplies power to the chip packaging structure 110 produces an instantaneous voltage drop.
  • Conductive vias 171 penetrating along the Z-axis direction are provided on the expansion board 170 .
  • a conductive channel 129 with an opening located on the lower surface 124 and extending along the Z-axis is provided in the PCB 120 .
  • the PCB 120 of the present application can also adopt a single-hole multi-signal design.
  • the conductive channel 127b in FIG. 11 is extended along the thickness direction of the PCB (direction opposite to the Y axis) to form a conductive via hole penetrating through the thickness direction of the PCB (Y axis direction).
  • the power supply channel extending along the thickness direction of the PCB (Y-axis direction) is used to connect the additional capacitor and the power module by using the conductive channel 127b.
  • the power supply channel that makes the conductive channel 127b extending along the thickness direction of the PCB (Y-axis direction) transmits the power signal.
  • Table 1 The structure shown in Table 1 is used to describe the single-hole multi-signal design of the PCB 120.
  • Table 1 is a schematic diagram of the single-signal multi-hole layer stacking of the PCB 120.
  • the PCB120 includes an 18-layer substrate, it is assumed that the instruction and data signals are in the upper half of the stack, for example, layers 1-7 in the stack in Table 1, which are signal vias (VIA5/8),
  • the conductive channel 127b that does not penetrate through the thickness direction (Y-axis direction) of the PCB 120 is used to drill the signal via holes (VIA5/8) through the back-drilling process to drill out the holes in layers 8-18.
  • the power supply via VIA10/12 is re-plated on the 10th-18th layer, and the lower power supply via is electroplated and filled and then electrically connected to the additional capacitor (capacitor 180 and/or capacitor 190), that is, a single-hole multi-signal process is used.
  • Secondary electroplating corresponding to FIG. 11 , realizes the electrical connection between the power supply via hole VIA10 / 12 in the PCB 120 and the conductive via hole 171 in the expansion board 170 .
  • the additional capacitor F is electrically connected to the power line in the printed circuit board 120, thereby reducing the impedance of the power supply line from the power module 140 to the chip packaging structure 110, reducing the voltage drop during the power supply process of the power module 140 to the chip packaging structure 110, And, when the power supply module 140 supplies power to the chip packaging structure 110 and a momentary voltage drop occurs, the electric energy stored in the additional capacitor can be used to reduce the momentary voltage drop.
  • Conductive vias 171 penetrating along the Z-axis direction are provided on the expansion board 170 .
  • a conductive channel 129 with an opening located on the lower surface 124 and extending along the Z-axis is provided in the PCB 120 .
  • FIG. 15 shows a schematic diagram of adding an expansion board and additional capacitors on the lower surface 124. As shown in FIG. The area corresponding to the input/output contact area 1214 is provided with an expansion board, and an additional capacitor is provided on the expansion board.
  • FIG. 16 shows a cross-sectional view of the universal chip module taken along the A-A direction in FIG. 3 .
  • the difference between the structure of the chip module shown in FIG. 16 and the structure shown in FIG. 7 is that an expansion board 170 is added to the area corresponding to the input and output contact area 1214 on the lower surface 124 of the PCB 120, and an expansion board 170 is set on the expansion board 170. Additional capacitance F.
  • the enlarged schematic diagram of the partial area F in FIG. 16 is the same as the technical solutions of the partial area D in FIGS. 9 and 10 , and the technical solutions in FIGS. 12 to 14 , and will not be repeated here.
  • FIG. 17 shows a schematic diagram of adding an expansion board and additional capacitors on the lower surface 124.
  • the lower surface 124 of the PCB120 is connected to An expansion board is added in the area corresponding to the storage contact area 1213 and the input/output contact area 1214 , and an additional capacitor is provided on the expansion board.
  • FIG. 18 shows a cross-sectional view of the universal chip module taken along the A-A direction in FIG. 3 .
  • the difference between the structure of the chip module shown in FIG. 21 and the structure shown in FIG. 7 is that an expansion board 180 is added in the area corresponding to the storage contact area 1213 and the storage contact area 1213 on the lower surface 124 of the PCB 120, and An additional capacitor F is provided on the expansion board 180 .
  • Fig. 9 to Fig. 18 only show the small expansion board 170 and one or more additional capacitors F set on the expansion board 170, but the embodiment of the present application Among them, the expansion board 170 can be a longer printed circuit board extending along the X direction, and more parallel additional capacitors F can be arranged on the expansion board 170, so that the above-mentioned voltage drop and Instantaneous voltage drop problem.
  • other power devices other than capacitors, such as resistors and inductors, may also be provided on the expansion board 170 . Other power devices except capacitors can be connected in series or in parallel with the additional capacitor F, etc.
  • additional capacitors F are connected in parallel on the expansion board 170 on the PCB 120 , but it can be understood that more additional capacitors F can be provided on the expansion board 170 of the PCB 120 .
  • Fig. 20 shows a simple structural circuit diagram among a power module 140, a chip packaging structure 110, a capacitor 160, a capacitor 180, and a capacitor 190 according to an embodiment of the present application.
  • the power module 140 A plurality of capacitors are connected in parallel between the chip packaging structure 110, such as capacitor 160, capacitor 180 and capacitor 190, so that the impedance between the power module 140 and the chip packaging structure 110 can be reduced, thereby reducing the distance between the power module 140 and the chip packaging structure 110.
  • multiple capacitors 1071 can store more electric energy. When the voltage between the power module 140 and the chip packaging structure 110 drops instantaneously, the multiple capacitors 1071 can provide electric energy to maintain the power module 140 and the chip packaging structure 110. The voltage between the chip package structures 110 .
  • FIG. 21 is a schematic diagram of a power delivery network (PDN) without an expansion board 170 on the chip module 100 .
  • PDN power delivery network
  • the ordinate is impedance
  • the abscissa is frequency. If the target impedance on the power supply line from the power module 140 to the chip packaging structure 110 is When there is no back-mounted expansion board 170, due to the limited layout area of the PCB120 main board and the insufficient number of low-frequency filter (BUCK) capacitors, the PDN curve exceeds the target impedance in the frequency range of 1E+4(10K)Hz-1E+6(1M)Hz.
  • the voltage drop on the power supply line of the module 140 to the chip packaging structure 110 is too large, the voltage output from the power module 140 to the chip packaging structure 110 is lower than the target voltage, and the electronic equipment where the chip module 100 is located cannot work normally, which will also affect the chip module.
  • the filtering performance in the group 100 means that the frequency point of a specific frequency in the power line or frequencies other than this frequency point cannot be effectively filtered.
  • FIG. 22 is a schematic diagram of the PDN curve after the expansion board 170 is attached on the PCB 120 of the chip module 100 .
  • the ordinate is impedance
  • the abscissa is frequency.
  • the low-frequency BUCK capacitor is placed on the expansion board 170, and the number of overall filter capacitors on the board is additionally increased.
  • the number of low-frequency filter (BUCK) capacitors is sufficient to cause the PDN curve to be at 1E+4 (10K)
  • the frequency range of Hz-1E+6(1M)Hz is basically lower than the target impedance, which effectively reduces the low-frequency impedance of the single-board PDN.
  • the power supply module 140 reduces the voltage drop on the power supply line of the chip packaging structure 110, and the power module 140 outputs to the chip package.
  • the electronic equipment where the chip module 100 is located can work normally, and the filtering performance in the chip module 100 will also be improved, that is, the frequency point of a specific frequency in the power line or other than the frequency point frequency for effective filtering.
  • the embodiment of the present application rationally utilizes the unused layout space of the non-chip power supply area on the printed circuit board 120. On the one hand, it can reduce the impedance of the power supply line from the power module 140 to the chip packaging structure 110, thereby reducing the power supply module 140.
  • the power supply module 140 supplies power to the chip packaging structure 110 and there is an instantaneous voltage drop
  • the electric energy stored in the additional capacitor can be used to reduce the instantaneous voltage drop;
  • the role of insulation between the conductive vias and other electrical components on the printed circuit board, the pins of the additional capacitor are not easy to contact with the conductive vias on the printed circuit board and other electrical components in the circuit board, reducing the power supply
  • the module 140 poses the risk of a short circuit on the power supply line of the chip packaging structure 110 .

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Abstract

本申请涉及电路技术领域，公开了一种滤波模组和电子设备。该滤波模组包括印刷电路板，芯片封装结构设置于印刷电路板的上表面；印刷电路板的上表面包括芯片电源触点区域，芯片电源触点区域中包括芯片电源触点，电源模块通过电源触点为芯片封装结构供电；印刷电路板的下表面包括第一区域，第一区域与芯片电源触点区域相对设置；多个电容并联设置于第一区域，且多个电容并联设置于电源模块给芯片封装结构供电的连线与地线之间；印刷电路板的下表面包括第二区域，第二区域与非芯片电源触点区域相对应设置；扩展板设置于第二区域；扩展板上设置至少一个与多个电容并联的附加电容。如此，在一定程度上，提高了滤波模组中的降压和稳压等性能。

Description

一种滤波模组和电子设备
本申请要求于2021年06月30日提交中国专利局、申请号为202110738263.2、申请名称为“一种滤波模组和电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电路技术领域，特别涉及一种滤波模组和电子设备。
背景技术
随着芯片能力提升和计算能力推进，芯片的供电需求也随之提升，例如，目前，一些芯片的稳态电流超1000A，瞬态电流跳变超2000A/uS。
例如，以基站中的芯片为例，在基站的供电电路向基站的芯片输出供电电流的过程中，大电流、电流瞬态快速跳变需要通过供电电路中的供电电路迅速放电来抑制电压跌落，提升电容布局密度称为产品成功的关键技术。
但是现有技术中，由于芯片所在的电路板中的空间位置有限，电路板上设置的供电电路中的滤波电容较少，存在负载电流动态性能翻番与电容容量不足的矛盾，即供电电路不能有效的抑制供电路向芯片输出电压的跌落。
发明内容
为了克服上述技术问题，本申请实施例第一方面提供了一种滤波模组，所述模组包括印刷电路板、芯片封装结构、电源模块、多个电容、扩展板和至少一个附加电容；
所述印刷电路板具有上表面和与所述上表面相对的下表面；
所述芯片封装结构设置于所述印刷电路板的上表面；
其中，所述印刷电路板的上表面包括芯片电源触点区域，所述芯片电源触点区域中包括芯片电源触点，所述电源模块通过所述电源触点为所述芯片封装结构供电；
所述印刷电路板的下表面包括第一区域，所述第一区域与所述芯片电源触点区域相对设置；
所述多个电容并联设置于所述第一区域，且所述多个电容并联设置于所述电源模块给所述芯片封装结构供电的连线与地线之间；
所述印刷电路板的下表面包括第二区域，所述第二区域与非芯片电源触点区域相对应设置；
所述扩展板设置于所述第二区域；
所述至少一个附加电容与所述多个电容并联，且设置于所述扩展板。
可以理解，滤波模组也可以叫做芯片模组，非芯片电源触点区域可以为与所述芯片电源触点区域相邻的存储触点区域、高速输入输出触点区域中的任意一种或者多种。第二区域可以为存储引脚区域、输入输出引脚区域中的任意一种或者多种，但并不限于此。扩展板也叫扣板，是电子元器件电气相互连接的载体，例如，可以为印刷电路板。芯片封装结构可以设置于该芯片设置区域。
电源模块给芯片封装结构供电的连线与地线可以参见实施例图11中所示的，PCB120中设置作为电源线的导电通道126，导电通道126为从PCB120上表面121延PCB120厚度(z轴)方向延伸后，再延长度方向(y轴)延伸，然后再延PCB120厚度(z轴)方向延伸后到达PCB120上表面121的弯折通道，且弯折通道的内壁设置有导电介质，例如铜，但不限于此。如图9所示，导电过孔127a作为接地线。
本申请实施例相比于现有技术中未设置附加电容的结构，增设的附加电容可以储存更多的电容，在电源模块给芯片封装结构供电的过程中产生瞬间压降的情况下，可以利用附加电容储存的电能降低瞬间压降。
在上述第一方面的一种可能的实现中，所述扩展板上设置至少一个导电过孔和至少一个接地过孔；
所述印刷电路板中设置导电孔，所述导电孔的一端与所述电源模块给所述芯片封装结构供电的连线电连接；
所述导电孔的另一端与所述至少一个附加电容中的每一个附加电容的一端电连接，所述至少一个附加电容中的每一个附加电容的另一端通过所述接地过孔与所述印刷电路板中的接地线电连接。
在上述第一方面的一种可能的实现中，所述滤波模组还包括第一导电通道，所述第一导电通道未在所述印刷电路板的厚度方向贯穿所述印刷电路板；
所述导电过孔位于所述第一导电通道与所述下表面之间的位置。
未在厚度方向贯穿印刷电路板的第一导电通道，所述导电过孔位于所述第一导电通道与所述下表面之间的位置具有较大的可以设置连接电源线的导电通道的空间(X轴方向、Y轴方向、Z轴方向)位置。
在上述第一方面的一种可能的实现中，所述至少一个附加电容设置于所述扩展板的下表面。
在上述第一方面的一种可能的实现中，所述至少一个附加电容中的部分附加电容设置于所述扩展板的下表面，其余附加电容设置于所述扩展板内部。
在上述第一方面的一种可能的实现中，所述至少一个附加电容设置于所述扩展板内部。
在上述第一方面的一种可能的实现中，所述印刷电路板为多层结构，所述导电孔为所述印刷电路板中的部分层结构中依次电连接的导电过孔。
在上述第一方面的一种可能的实现中，所述非芯片电源触点区域为与所述芯片电源触点区域相邻的触点区域。
可以理解，非芯片电源触点区域可以为与所述芯片电源触点区域相邻的存储触点区域、高速输入输出触点区域中的任意一种或者多种。
在上述第一方面的一种可能的实现中，所述芯片封装结构为应用处理器、调制解调处理器、图形处理器、图像信号处理器、控制器、视频编解码器，数字信号处理器、基带处理器和神经网络处理器中任意一种或者多种的集成结构。
在上述第一方面的一种可能的实现中，所述滤波模组还包括功率器件，所述功率器件设置于所述扩展板上。
可以理解，扩展板上可以设置更多的并联的附加电容，如此，便可以更好的降低上述的压降和瞬时压降的问题。此外，扩展板上还可以设置除电容之外的其他功率器件，例如，电阻和电感。除电容之外的其他功率器件可以和附加电容串联或并联等。
第二方面，本申请实施例还提供了一种电子设备，其特征在于，所述电子设备包括第一方面任意一项所述的滤波模组。
附图说明
图1根据本申请的一些实施例，示出了一种本申请技术方案中提到的芯片模组的应用场景示意图；
图2根据本申请实施例，示出了一种基站1的结构示意图；
图3根据本申请的一些实施例，示出了一种通用芯片模组的结构示意图；
图4是图3中的芯片模组100延Y轴方向的爆炸图；
图5为基于图3的芯片模组结构，按照引脚的连接器件不同，示出了不同类型的引脚在芯片封装结构110的下表面111以及PCB120的上表面121上的区域分布示意图；
图6示出了一种在印刷电路板120下表面124上增设扩展板和附加电容的分布示意图；
图7示出了在一些实施例中沿着图3所示的A-A方向得到的芯片模组100的截面图；
图8示出了一种在印刷电路板120下表面124上增设扩展板和附加电容的分布示意图；
图9示出了沿图3中的A-A方向得到的芯片模组的截面图；
图10示出了沿图3中的A-A方向得到的又一种芯片模组的截面图；
图11示出了沿图3所示的B-B方向得到的芯片模组100的截面示意图；
图12示出了一种芯片模组在YZ平面上的截面图；
图13示出了一种扩展板内设置附加电容的一种YZ平面上的局部截面图；
图14示出了一种扩展板内设置附加电容的一种YZ平面上的局部截面图；
图15示出了一种在印刷电路板120下表面124上增设扩展板和附加电容的分布示意图；
图16示出了沿图3中的A-A方向得到的通用芯片模组的截面图；
图17示出了一种在印刷电路板120下表面124上增设扩展板和附加电容的分布示意图；
图18示出了沿图3中的A-A方向得到的通用芯片模组的截面图；
图19根据本申请实施例，示出了一种对应图8，沿图3中的A-A方向得到的芯片模组的截面图；
图20根据本申请实施例，示出了一种电源模块140、芯片封装结构110、电容160、电容180以及电容190之间的简易结构电路图；
图21为芯片模组100上没有设置扩展板170的电源分配网络曲线(power delivery network，PDN)示意图；
图22为芯片模组100的PCB120上背贴扩展板170后的PDN曲线示意图。
附图标记说明：
1-基站；2-终端；3-终端；
101-信号接收机；102-信号发射机；103-视频监控仪器；100-芯片模组；110-中央处理器(芯片封装结构)；120-印制电路板；130-存储器；140-电源模块；150-视频监控仪器控制芯片；
111-芯片封装结构的下表面；121-芯片封装结构的上表面，122-芯片设置区域；123-非芯片设置区域；
1112-芯片电源引脚区域；1212-芯片电源触点区域；
1113-存储引脚区域；1213-存储触点区域；
1114-输入输出引脚区域；1214-输入输出触点区域；
1111-电源引脚区域；1211-电源触点区域；
124-下表面；
127a-导电过孔；127b-导电通道；127c-导电通道；129-导电通道；
F-附加电容；F2-电容主体；F1-第一电极端；F3-第二电极端；
170-扩展板；171-导电过孔；172-扩展板的下表面；173-扩展板的上表面；200-锡球。
具体实施方式
以下由特定的具体实施例说明本申请的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本申请的其他优点及功效。虽然本申请的描述将结合一些实施例一起介绍，但这并不代表此申请的特征仅限于该实施方式。恰恰相反，结合实施方式作申请介绍的目的是为了覆盖基于本申请的权利要求而有可能延伸出的其它选择或改造。为了提供对本申请的深度了解，以下描述中将包含许多具体的细节。本申请也可以不使用这些细节实施。此外，为了避免混乱或模糊本申请的重点，有些具体细节将在描述中被省略。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
应注意的是，在本说明书中，相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
在本申请的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“电连接”应做广义理解，例如，可以是固定电连接，也可以是可拆卸电连接，或一体地电连接；可以是机械电连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
本申请的说明性实施例包括但不限于一种芯片模组和基站。为了便于理解，本申请的技术方案以基站为应用场景来描述，但是可以理解，本申请技术方案中提到的芯片模组也可以用于其他电子设备，例如，服务器、卫星系统等等。
图1根据本申请的一些实施例，示出了一种本申请技术方案中提到的芯片模组的应用场景示意图。
如图1所示，在该应用场景中，包括内部设置芯片模组的基站1、终端2和终端3。可以理解，基站1即公用移动通信基站，是终端2和终端3接入互联网的接口设备，终端2和终端3之间通过基站1进行信息传递。
下面介绍内部设置本申请实施例提供的芯片模组的基站1的结构示意图，图2根据本申请实施例，示出了一种基站1的结构示意图。
如图2所示，基站1可以包括中央处理器110、信号接收机101、信号发射机102、电源模块140、存储器130、视频监控仪器控制芯片150和视频监控仪器103。可以理解，本申请中所提及的芯片模组中可以集成有中央处理器110、电源模块140、存储器130、视频监控仪器控制芯片150 和视频监控仪器103。
具体地，信号接收机101、信号发射机102、电源模块140、存储器130和视频监控仪器103分别与中央处理器110连接。
电源模块140用于给中央处理器110、信号接收机101、信号发射机102、电源模块140、存储器130、视频监控仪器控制芯片150和视频监控仪器103供电；存储器130用于存储中央处理器110发送的部分数据；视频监控仪器控制芯片150用于控制视频监控仪器103的工作状态；视频监控仪器103用于拍摄视频并通过视频监控仪器控制芯片150将视频数据发送到中央处理器110处理，中央处理器110也可以进一步将拍摄的视频数据发送到存储器130存储。
其中，信号接收机101用于接收其他设备发送的信息，信号发射机102用于将信号接收机101接收的信息转发给其他设备。在图1所示的应用场景中，假设用户1想要利用终端1给用户2的终端2发送信息，终端1需要通过基站2将信息转发给用户2的终端2。具体地，用户1利用终端1发送信号接收机101用于接收信息，例如终端1的信息，并且把接收的信息发送到中央处理器110，中央处理器110对接收到的信息进行信息编码后，发送到信号发射机102，信号发射机102将编码后的信息发送给其他设备，例如终端2。
可以理解，为了保证中央处理器110正常工作，需要电源模块140给中央处理器110提供较大且稳定的电流。但是，如前所述，目前存在电源模块140给中央处理器110供电的供电电路不能有效的抑制电源模块140向中央处理器110输出电压的跌落的问题。
为解决上述技术问题，在本申请实施例公开了一种芯片模组，该芯片模组可以包括上述电源模块140和中央处理器110，并且在该芯片模组中，在电源模块140给中央处理器110供电的线路中增设了附加电容，用于降低电源模块140给中央处理器110供电线路上的阻抗，降低电源模块140给中央处理器110供电过程中的压降，且相比于现有技术中未设置附加电容的结构，增设的附加电容可以储存更多的电容，在电源模块140给中央处理器110供电的过程中产生瞬间压降的情况下，可以利用附加电容储存的电能降低瞬间压降。
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请的实施方式作进一步地详细描述。为了便于说明，下文以上述基站1为例说明本申请技术方案中的芯片模组，但是可以理解，本申请技术方案中的芯片模组还可以适用于其他电子设备，如服务器、卫星系统等。
图3根据本申请的一些实施例，示出了一种通用芯片模组的结构示意图。该芯片模组可以包括有上述基站1的中央处理器110、存储器130、电源模块140、视频监控仪器控制芯片150。
如图3所示，芯片模组100包括芯片封装结构110和印制电路板(Printed Circuit Board，PCB)120、存储器130、电源模块140、视频监控仪器控制芯片150。
其中，芯片封装结构110为上述基站1中的中央处理器110，其又称为芯片封装体(Chip package)，是指将裸片封装并设置为用于与其他电子器件电连接的多个引脚的一种结构。
具体地，裸片(DIE)是在加工厂生产出来的芯片，即是晶圆经过切割测试后没有经过封装的芯片，这种裸片上只有用于封装的压焊点(pad)，是不能直接应用于实际电路当中的。然而裸片极易受外部环境的温度、杂质和物理作用力的影响，很容易遭到破坏，所以必须封入一个密闭空间内，引出相应的引脚，才能作为一个基本的元器件使用。裸片通常安装在一芯片封装载板上，通过键合线(金线)(bonding)将裸片内部电路用金线与封装管脚电连接，绑定后用黑色胶体将裸片封装，以形成芯片封装体(Chip package)。
此外，可以理解，芯片封装结构110除了指上述图2所示的基站1中的中央处理器110，可 以指其他设备中的调制解调处理器、图形处理器、图像信号处理器、控制器、视频编解码器，数字信号处理器、基带处理器、神经网络处理器等，以及应用处理器、调制解调处理器、图形处理器、图像信号处理器、控制器、视频编解码器，数字信号处理器、基带处理器、神经网络处理器中任一至少两种处理器的集成。即不同的处理单元可以是独立的器件，也可以集成在一个或多个处理器中。
印制电路板(Printed Circuit Board，PCB)120是电子元器件的支撑体，是与电子器件电连接的载体。具体地，在一些电子结构中，在PCB120上表面121上，设置有芯片封装结构110和存储器130、电源模块140、视频监控仪器控制芯片150等等，但不限于此。
在XYZ坐标系下，芯片模组100基本位于一平面(XY平面)中，其中，Z轴方向(被称为“法线”)被定向为从芯片模组100朝向观看者的方向，即芯片模组100的厚度方向。X轴方向被定义为芯片模组100从左至右的长度方向。Y轴方向被定义为芯片模组100从前至后的宽度方向。
印制电路板(Printed Circuit Board，PCB)120和芯片封装结构110在y轴方向依次设置。其中，芯片封装结构110和印制电路板(Printed Circuit Board，PCB)120可以通过导电介质(图中未示出)电连接。
图4是图3中的芯片模组100延Y轴方向的爆炸图。如图4所示，在一些电子结构中，PCB120具有朝向Z轴方向的上表面121，该上表面121上具有芯片设置区域122，芯片封装结构110设置于该芯片设置区域122。PCB120上表面121上与芯片设置区域122相邻的非芯片设置区域123上用于设置一些电子器件，例如，存储器130、电源模块140、视频监控仪器控制芯片150等等，但不限于此。
继续参阅图4，芯片封装结构110具有朝向Z轴相反方向的下表面111，该下表面111用于与PCB120上表面121上的芯片设置区域122贴合。在一些实施例中，芯片封装结构110可以为球栅阵列结构的印刷电路板(Ball Grid Array，BGA)，它是集成电路采用有机载板的一种封装法。
为了下文便于描述本申请的技术方案，下面对芯片模组100中各类引脚的分布情况进行定义。具体地，图5为基于图3的芯片模组结构，按照引脚的连接器件不同，示出了不同类型的引脚在芯片封装结构110的下表面111以及PCB120的上表面121上的区域分布示意图。
(1)芯片电源引脚区域1112和芯片电源触点区域1212
如图5所示，芯片封装结构110的下表面111上设置有芯片电源引脚区域1112，电源模块140能够通过芯片电源引脚区域1112中的电源引脚，向芯片封装结构110供电。
对应上面芯片封装结构110下表面111上的芯片电源引脚区域1112，PCB120的上表面121上设置有芯片电源触点区域1212，其中，芯片电源触点区域1212中的电源触点用于与芯片电源引脚区域1112中的电源引脚电连接，并且电源模块140能够通过电源触点和电源引脚，向芯片封装结构110供电。
可以理解，在一些实施例中，可以在芯片封装结构110的下表面111的中间区域布置芯片电源引脚区域1112，但不限于此。
(2)存储引脚区域1113和存储触点区域1213
继续参阅图5，芯片封装结构110的下表面111上设置有存储引脚区域1113，芯片封装结构110能够通过存储引脚区域1113中的存储器引脚向存储器130发送需要存储的数据，存储引脚区域1113也可以称为DDR区域或者DDR区。
对应上面芯片封装结构110下表面111上的存储引脚区域1113，PCB120的上表面121上设置 有存储触点区域1213，其中，存储触点区域1213中的存储器触点用于与存储引脚区域1113中的存储器引脚连接，并且芯片封装结构110能够通过存储器引脚和存储器触点向存储器130发送需要存储的数据。可以理解，在一些实施例中，可以在芯片封装结构110的下表面111与芯片电源引脚区域1112相邻的外围区域布置存储引脚区域1113，但不限于此。
(3)输入输出引脚区域1114和输入输出触点区域1214
继续参阅图5，芯片封装结构110的下表面111上设置有输入输出引脚区域1114，芯片封装结构110能够通过输入输出引脚区域1114的输入输出引脚与视频监控仪器控制芯片150之间进行指令交互和数据传输，输入输出引脚区域1114也可以称为高速I/O(Input/output，输入输出)区域或者高速I/O区。
对应上面芯片封装结构110的下表面111上的输入输出引脚区域1114，PCB120的上表面121上设置有输入输出触点区域1214，其中，输入输出触点区域1214中的输入输出触点用于与输入输出引脚连接，并且芯片封装结构110能够通过输入输出触点和输入输出引脚与视频监控仪器控制芯片150之间进行指令交互和数据传输。可以在芯片封装结构110的下表面111与芯片电源引脚区域1112相邻的外围区域布置输入输出引脚区域1114，但不限于此。
(4)电源引脚区域1111和电源触点区域1211
继续参阅图5，芯片封装结构110的下表面111上设置有电源引脚区域1111，芯片封装结构110能够通过电源引脚区域1111的电源引脚为存储器130等电子器件供电。
对应上面芯片封装结构110的下表面111上的电源引脚区域1111，PCB120的上表面121上设置有电源触点区域1211，其中，电源触点区域1211中的电源触点能够通过电源引脚和电源触点为存储器130等电子器件供电。
可以理解，输入输出触点区域1214和存储触点区域1213统称为非芯片电源触点区域，输入输出引脚区域1114、输入输出触点区域1214、存储引脚区域1113和存储触点区域1213统称为非电源区域。
如前所述，在相关技术中，电源模块140与芯片封装结构110之间的供电电路设置有多个并联的电容，该多个并联的电容用于对电源模块140与芯片封装结构110之间的电信号(电流和/或电压)进行滤波以及电压进行稳压，其一般设置在图4所示的PCB120下表面124上与芯片电源触点区域1212对应的区域中。
但是，目前存在PCB120上设置的供电电路中的电容较少，存在负载电流动态性能翻番与电容容量不足的矛盾，即供电电路不能有效的抑制供电路向芯片输出电压的跌落的问题。
为了解决该问题，可以在PCB120下表面124上与电源触点区域1212之外的区域对应的区域中增加供电电路中的电容，例如,图6示出了一种在印刷电路板120下表面124上增设扩展板和附加电容的分布示意图。
如图6所示，PCB120下表面124上与存储触点区域1213对应的区域。但是在PCB120下表面124上与存储触点区域1213对应的区域中为供电电路的增设附加电容存在短路的问题。下面结合图7说明该问题。
为了更清楚的说明相关技术中存在问题，对应于图6，图7示出了在一些实施例中沿着图3所示的A-A方向得到的芯片模组100的截面图。
可以理解，在PCB120非电源区域的厚度方向(Z轴)设置有信号线，与传输电流的电源线不同，信号线主要是指用于传递非电源信号的线，或者说传递传感信息与控制信息的线，或者说主 要是指用于传递信号与指令的线。
例如，如图7所示，在PCB120上表面121的存储触点区域1213至PCB120的下表面124之间，存在多条沿PCB120厚度方向(Z轴)延伸并贯穿PCB120的导电过孔127a、多条沿PCB120厚度方向(Z轴)但未完全贯穿PCB120的导电通道127b、以及延PCB120长度方向(X轴)的导电通道127c，且部分导电通道127c的一端可以与导电通道127b的一端电连接，部分导电过孔127a的中间部位可以与导电通道127b的一端电连接。且存储触点区域1213的导电过孔127a、导电通道127b可以作为信号线，用于通除电源之外的其他信号。例如，指令数据信号，存储触点区域1213的导电过孔127a、导电通道127b也可以作为接地线。
若将附加电容F设置在PCB120的下表面124的非电源区域(例如存储触点区域1213)，则存在附加电容F与PCB120的下表面124的非电源区域上的信号线电连接，将非电源信号引到电源模块140与芯片封装结构110之间的供电线路之间，且由于信号线和电源线所需的电压不同，例如，信号线上的电流时非常小的，但电源是用来驱动后级电路，所以电源线上的电流会大，容易引起供电电路和其他非电源电路短路。
例如，继续参与图7中局部区域C。如图7所示，附加电容F为贴片电容，包括电容主体F2和设置在电容主体F2两端的第一电极端F1和第二电极端，若导电过孔127a是信号线，由于相邻两个导电过孔127a之间的位置有限，若在相邻两个导电过孔127a之间的位置设置附加电容F,存在将附加电容F的第一电极端F1和第二电极端F3分别与两个作为信号线的导电过孔127a电连接，导致非电源信号引到电源模块140与芯片封装结构110之间的供电线路之间，干扰信号线中的信号传输。且由于信号线和电源线所需的电压不同，例如，信号线上的电流时非常小的，但电源是用来驱动后级电路，所以电源线上的电流会大，容易引起供电电路和其他非电源电路短路的问题。
为了避免上述短路的问题，本申请还提出了一种芯片模组的结构。在该芯片模组中，在芯片封装结构110所在的PCB120的下表面124上，且在设置未完全贯穿PCB120的导电通道127b的非电源区域，增设扩展板，可以理解，扩展板也叫扣板，是电子元器件电气相互连接的载体，例如，可以为印刷电路板。在扩展板中设置附加电容，由于扩展板隔离了附加电容和PCB120，附加电容和PCB120不直接接触，降低了电源模块140给中央处理器110供电线路上短路的风险。
且由于未完全贯穿PCB120的导电通道127b的非电源区域的空间大于相邻两个导电过孔127a之间的距离空间，例如，如图9所示，若相邻两个导电过孔127a之间包括未完全贯穿PCB120的导电通道127b，则包括未完全贯穿PCB120的导电通道127b的该相邻两个导电过孔127a之间的距离d2大于相邻两个导电过孔127a之间的距离d1，具有较大的可以设置连接电源线的导电通道的空间(X轴方向、Y轴方向、Z轴方向)位置，下面具体介绍几种解决上述短路问题的芯片模组结构。
图8示出了一种在印刷电路板120下表面124上增设扩展板和附加电容的分布示意图。如图8所示，在PCB120下表面124上与存储触点区域1213对应的区域增设扩展板170，并在扩展板上设置增设的附加电容F。
具体地，对应图8，图9示出了沿图3中的A-A方向得到的芯片模组的截面图。
如图9所示，扩展板170具有朝向Y轴方向的上表面171，以及朝向Y轴方向的下表面172，附加电容F位于扩展板170的下表面172上，而扩展板170的上表面173与印刷电路板120的下表面124电连接。为了将附加电容F与印刷电路板120中的电源线电连接，从而实现降低电源模块140给芯片封装结构110供电线路上的阻抗，降低电源模块140给芯片封装结构110供电过程 中的压降，以及在电源模块140给芯片封装结构110供电的过程中产生瞬间压降的情况下，利用附加电容储存的电能降低瞬间压降的功能。在扩展板170上设置沿Z轴方向贯穿的两个导电过孔173，在PCB120中设置开口位于下表面124，并沿Z轴方向延伸的导电通道129。导电通道129位于相邻两个导电过孔127a之间，且该相邻两个导电过孔127a之间包括未完全贯穿PCB120的导电通道127b。
可以理解的是，PCB120上设置的导电通道129均是成对出现的，一个导电通道129用于将附加电容F的一个电极接电源线，另一个导电通道129用于将附加电容F的另一个电极接地。
其中，导电过孔173的一端与第二电极端F2电连接，例如，通过表面组装技术(表面贴装技术)(Surface Mounted Technology,SMT)实现电连接，导电过孔173的另一端通过锡球200焊接于印刷电路板120下表面124上的导电通道129的一端，且该导电通道129用于与PCB120内部的电源线电连接，如此，实现附加电容F与电源线的电连接。可以理解，在一些实施例中，沿PCB120的Z轴方向，且未完全贯穿PCB120的导电通道127b可以与导电通道129在一条直线上。即导电通道127b和导电通道129可以为沿PCB120的Z轴方向贯穿PCB120的导电过孔的两个组成部分，下文将具体介绍。可以理解，上述PCB120与扩展板170通过导电过孔分配，实现PCB120上的引脚与扩展板170上的触点保持一致，PCB120与扩展板170链接数量需要通过扩展板重量、附着力、环路DCR影响综合评估。
若导电过孔127a作为接地线，则导电过孔173的一端与第二电极端F1电连接，例如，通过表面组装技术(表面贴装技术)(Surface Mounted Technology,SMT)实现电连接，而导电过孔173的另一端通过锡球200焊接于印刷电路板120下表面124上的导电过孔127a的一端。如此，可以实现附加电容接地。
可以理解的是，为了便于描述本申请技术方案，图9仅仅示出了较小的扩展板170，以及该扩展板170上设置的一个或者附加电容F，但本申请实施例中，扩展板170可以为延X方向延伸的较长的印刷电路板，进而在该扩展板170上可以设置更多的并联的附加电容F，如此，便可以更好的降低上述的压降和瞬时压降的问题。此外，扩展板170上还可以设置除电容之外的其他功率器件，例如，电阻和电感。除电容之外的其他功率器件可以和附加电容F串联或并联等。
此外，可以理解的是，PCB120上设置的导电通道129均是成对出现的，一个导电通道129用于将附加电容F的一个电极接电源线，另一个导电通道129用于将附加电容F的另一个电极接地，在附加电容F的利用其中一个导电通道129接电源线的情况下，本申请实施例中，另一个用于接地的导电通道也可以不利用PCB120中原本设置的用于接地的导电过孔127，而是重新增设用于接地的导电通道，对应图8，图10示出了沿图3中的A-A方向得到的又一种芯片模组的截面图。如图10所示，PCB120中增设开口位于下表面124，并沿Z轴方向延伸的再设置一个用于接地的导电通道129。该导电通道129位于相邻两个导电过孔127a之间，且该相邻两个导电过孔127a之间包括未完全贯穿PCB120的导电通道127b。导电过孔173的一端与第二电极端F1电连接，导电过孔173的另一端通过锡球200焊接于印刷电路板120下表面124上的用于接地的导电通道129的一端，如此，也可以实现附加电容接地。
为了更清楚的说明PCB120中电源线的结构，下面先介绍一种在PCB内部分布的电源线(电源通道)的截面图，例如，图11示出了沿图3所示的B-B方向得到的芯片模组100的截面示意图，如图11所示，PCB120中设置作为电源线的导电通道126，导电通道126为从PCB120上表面121延PCB120厚度(z轴)方向延伸后，再延长度方向(y轴)延伸，然后再延PCB120厚度(z轴) 方向延伸后到达PCB120上表面121的弯折通道，且弯折通道的内壁设置有导电介质，例如铜，但不限于此。
为了更清楚的说明PCB120中的导电通道126与导电通道129的连接结构，例如，对应于图9中的D’-D’方向，图12示出了一种芯片模组在YZ平面上的截面图。如图12所示，导电通道129的一端沿Y轴方向延伸后与导电通道126电连接。导电通道129的另一端可以通过锡球200与扩展板170上的导电过孔173的一端焊接，导电过孔173的另一端与第二电极端F2电连接，如此，附加电容F便可以通过导电过孔171和导电通道129并联接入作为电源线的导线通道126电连接，一方面，用于降低电源模块140给芯片封装结构110供电线路上的阻抗，降低电源模块140给芯片封装结构110供电过程中的压降，且相比于现有技术中未设置附加电容的结构，增设的附加电容F可以储存更多的电容，在电源模块140给芯片封装结构110供电的过程中产生瞬间压降的情况下，可以利用附加电容储存的电能降低瞬间压降。可以理解，上述电连接方式是通过锡球，除此之外，还可以为导电膏，在此不做限制。
在图9、图10和图11所示的芯片模组100的结构中，附加电容F是设置在扩展板170的表面上的方式，此外，在其他实施例中，还可以将附加电容F设置在扩展板170内部。例如，还可以将附加电容F设置在扩展板170内部。例如，图13示出了一种扩展板内设置附加电容的一种YZ平面上的局部截面图，如图13所示，扩展板170的内部埋入附加电容F。附加电容F设置于扩展板170的内部。一个导电过孔173的一端与附加电容F的第二电极端F2电连接，导电过孔173的另一端通过锡球200与导电通道129电连接，如此，附加电容F便可以通过导电过孔173并联接入电源线(电源通道)电连接；另一个导电过孔173的一端与附加电容F的第一电极端F1电连接，另一个导电过孔173的另一端通过锡球200与用于接地的导电通道129电连接。
此外，在其他实施例中，附加电容F既可以设置在扩展板170内部，也可以设置在扩展板170外部。
例如，图14示出了一种扩展板内设置附加电容的一种YZ平面上的局部截面图，如图14所示，扩展板170的下表面172设置附加电容F，扩展板170的内部也设置附加电容F。
设置于扩展板170的内部的附加电容F的第二电极端F2与导电过孔173的中部电连接，设置于扩展板170的下表面172的附加电容F的第二电极端F2与导电过孔173的一端电连接，导电过孔173的另一端通过锡球200与用于接地的导电通道129电连接。
另一个导电过孔173的一端与设置于扩展板170的内部的附加电容F的第一电极端F1电连接，另一个导电过孔173的中部与设置于扩展板170的下表面172的附加电容F的第一电极端F1电连接。
另一个导电过孔173的另一端通过锡球200与用于接地的导电通道129电连接。
如此，设置于扩展板170的内部的附加电容F和设置于扩展板170的下表面172的附加电容F便均可以通过导电过孔173并联接入电源线(电源通道)电连接。
当然，本领域技术人员可以理解，附加电容可以为0402的高频去耦电容，也可以为0805或者1206高容电容，但不限于此。
扩展板170可以是硅基、薄膜等形式的结构。导电过孔171采用VIA10大孔方案保证单个孔通流能力及降低ESR、等效电感(Equivalent Series Inductance，ESL)等，提升滤波性能；扩展板170的厚度可以控制在1mm以内，以提供优良的环路特性。
下面介绍上文中提到的技术方案：导电通道127b和导电通道129可以为沿PCB120的Z轴方 向贯穿PCB120的导电过孔的两个组成部。
如图9所示，PCB120中设置未贯穿PCB120厚度方向(Y轴方向)的导电通道127b，为了充分利用利用导电通道127b在PCB120中沿厚度方向(Y轴相反的方向)的空间设置导电通道129，以使得将附加电容F通过导电通道129与印刷电路板120中的电源线电连接，从而实现降低电源模块140给芯片封装结构110供电线路上的阻抗，降低电源模块140给芯片封装结构110供电过程中的压降，以及，在电源模块140给芯片封装结构110供电的过程中产生瞬间压降的情况下，利用附加电容储存的电能降低瞬间压降的功能。在扩展板170上设置沿Z轴方向贯穿的导电过孔171。在PCB120中设置开口位于下表面124，并沿Z轴方向延伸的导电通道129。本申请的PCB120还可以采用单孔位多信号设计，例如，图11中的导电通道127b可以与视频监控仪器控制芯片150之间进行指令交互和数据传输，通过指令和数据信号，通过钻孔技术将图11中的导电通道127b沿PCB厚度方向(Y轴相反的方向)延伸，形成贯穿PCB厚度方向(Y轴方向)的导电过孔。利用导电通道127b沿PCB厚度方向(Y轴方向)延伸的电源通道连接附加电容和电源模块。使得导电通道127b沿PCB厚度方向(Y轴方向)延伸的电源通道通电源信号。
下面通过表1所示的结构说明PCB120的单孔位多信号设计，表1为PCB120的单信号多孔位层叠示意图。
如下表1所示，若PCB120包括18层基板，假定指令和数据信号在叠层内上半部分，例如表1中层叠中的1-7层，该部分为信号过孔(VIA5/8)，例如图11所示的未贯穿PCB120厚度方向(Y轴方向)的导电通道127b，将信号过孔(VIA5/8通过背钻工艺实现将8-18层的孔钻掉。
相应地，第10层-18层重新电镀电源过孔VIA10/12，下方电源过孔电镀填平后与附加电容电(电容180和/或电容190)电连接，即采用一孔多信号工艺进行二次电镀，对应于图11，实现PCB120中的电源过孔VIA10/12与扩展板170中的导电过孔171电连接。从而将附加电容F与印刷电路板120中的电源线电连接，从而实现降低电源模块140给芯片封装结构110供电线路上的阻抗，降低电源模块140给芯片封装结构110供电过程中的压降，以及，在电源模块140给芯片封装结构110供电的过程中产生瞬间压降的情况下，利用附加电容储存的电能降低瞬间压降的功能。在扩展板170上设置沿Z轴方向贯穿的导电过孔171。在PCB120中设置开口位于下表面124，并沿Z轴方向延伸的导电通道129。
表1：
Figure PCTCN2022092549-appb-000001
Figure PCTCN2022092549-appb-000002
下面再介绍本申请实施例提供的另一种芯片模组结构，图15示出了一种在下表面124上增设扩展板和附加电容的分布示意图，如图15所示，PCB120下表面124上与输入输出触点区域1214对应的区域增设扩展板，并在扩展板上设置增设的附加电容。
具体地，图16示出了沿图3中的A-A方向得到的通用芯片模组的截面图。图16所示的芯片模组的结构与图7所示结构的不同之处在于,在PCB120下表面124上与输入输出触点区域1214对应的区域增设扩展板170，并在扩展板170上设置附加电容F。
图16中局部区域F的放大示意图与图9和图10中局部区域D的技术方案，以及图12至图14的技术方案相同，在此不再赘述。
下面再介绍本申请实施例提供的另一种芯片模组结构，图17示出了一种在下表面124上增设扩展板和附加电容的分布示意图，如图17所示，PCB120下表面124上与存储触点区域1213和输入输出触点区域1214对应的区域增设扩展板，并在扩展板上设置增设的电容。
具体地，图18示出了沿图3中的A-A方向得到的通用芯片模组的截面图。图21所示的芯片模组的结构与图7所示结构的不同之处在,在PCB120下表面124上与存储触点区域1213和存储触点区域1213对应的区域增设扩展板180，并在扩展板180上设置附加电容F。
图18中局部区域D和局部区域E的放大示意图与图9和图10中局部区域D的技术方案，以及图12至图14的技术方案相同，在此不再赘述。
可以理解的是，为了便于描述本申请技术方案，图9至图18仅仅示出了较小的扩展板170，以及该扩展板170上设置的一个或者多个附加电容F，但本申请实施例中，扩展板170可以为延X方向延伸的较长的印刷电路板，进而在该扩展板170上可以设置更多的并联的附加电容F，如此，便可以更好的降低上述的压降和瞬时压降的问题。此外，扩展板170上还可以设置除电容之外的其他功率器件，例如，电阻和电感。除电容之外的其他功率器件可以和附加电容F串联或并联等。
图19根据本申请实施例，示出了一种对应图8，沿图3中的A-A方向得到的芯片模组的截面图。
如图19中的局部区域G中所示，PCB120上的扩展板170上设置四个并联的附加电容F，但是可以理解的是，PCB120的扩展板170上还可以设置更多附加电容F。
图20根据本申请实施例，示出了一种电源模块140、芯片封装结构110、电容160、电容180以及电容190之间的简易结构电路图，如图11所示，一方面，在电源模块140和芯片封装结构110之间并联多个电容,例如电容160，电容180以及电容190，如此，可以减少电源模块140和芯片封装结构110之间的阻抗，从而降低电源模块140和芯片封装结构110之间的压降，另一方面，多个电容1071可以存储更多电能，在电源模块140和芯片封装结构110之间的电压瞬间降低时，多个电容1071便可以提供电能，维持电源模块140和芯片封装结构110之间的电压。
图21为芯片模组100上没有设置扩展板170的电源分配网络曲线(power delivery network，PDN)示意图。
如图21所示，纵坐标为阻抗，横坐标为频率。若电源模块140给芯片封装结构110供电线路上的目标阻抗为
Figure PCTCN2022092549-appb-000003
无背贴扩展板170时，由于PCB120主板布局面积有限，低频滤波(BUCK)电容数量不够导致PDN曲线在1E+4(10K)Hz-1E+6(1M)Hz频率范围内超出目标阻抗，电源模块140给芯片封装结构110供电线路上的压降过大，电源模块140输出到芯片封装结构110的电压低于目标电压，芯片模组100所在的电子设备不能够正常工作，也会影响芯片模组100中的滤波性能，即无法对电源线中特定频率的频点或该频点以外的频率进行有效滤除。
图22为芯片模组100的PCB120上背贴扩展板170后的PDN曲线示意图。
如图21所示，纵坐标为阻抗，横坐标为频率。本申请实施例引入背贴扩展板170后，将低频BUCK电容放置在扩展板170上，额外增加单板整体滤波电容数量，低频滤波(BUCK)电容数量足够导致PDN曲线在1E+4(10K)Hz-1E+6(1M)Hz频率范围内基本上低于目标阻抗，有效降低单板PDN低频阻抗，电源模块140给芯片封装结构110供电线路上的压降降低，电源模块140输出到芯片封装结构110的电压高于等于目标电压，芯片模组100所在的电子设备能够正常工作，也会提升芯片模组100中的滤波性能，即可以对电源线中特定频率的频点或该频点以外的频率进行有效滤除。
综上，本申请实施例通过合理利用印刷电路板120上非芯片电源区域未使用的布局空间，一方面，可以降低电源模块140给芯片封装结构110供电线路上的阻抗，从而降低了电源模块140给芯片封装结构110供电线路上的压降；另一方面，相比于未设置附加电容之前的芯片模组100结构，该芯片模组100设置的至少一个附加电容可以储存更多的电容，在电源模块140给芯片封装结构110供电的过程中产生瞬间压降的情况下，可以利用附加电容储存的电能降低瞬间压降；另一方面，而且，由于扩展板起到将附加电容的引脚之间绝缘以及与印刷电路板上的导电过孔和其他电器元件绝缘开来的作用，附加电容的引脚不容易与印刷电路板上的导电过孔和电路板中其他电器元件接触，降低了电源模块140给芯片封装结构110供电线路上短路的风险。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (11)

  1. 一种滤波模组，其特征在于，所述模组包括印刷电路板、芯片封装结构、电源模块、多个电容、扩展板和至少一个附加电容；
    所述印刷电路板具有上表面和与所述上表面相对的下表面；
    所述芯片封装结构设置于所述印刷电路板的上表面；
    其中，所述印刷电路板的上表面包括芯片电源触点区域，所述芯片电源触点区域中包括芯片电源触点，所述电源模块通过所述电源触点为所述芯片封装结构供电；
    所述印刷电路板的下表面包括第一区域，所述第一区域与所述芯片电源触点区域相对设置；
    所述多个电容并联设置于所述第一区域，且所述多个电容并联设置于所述电源模块给所述芯片封装结构供电的连线与地线之间；
    所述印刷电路板的下表面包括第二区域，所述第二区域与非芯片电源触点区域相对应设置；
    所述扩展板设置于所述第二区域；
    所述至少一个附加电容与所述多个电容并联，且设置于所述扩展板。
  2. 根据权利要求1所述的滤波模组，其特征在于，所述扩展板上设置至少一个导电过孔和至少一个接地过孔；
    所述印刷电路板中设置导电孔，所述导电孔的一端与所述电源模块给所述芯片封装结构供电的连线电连接；
    所述导电孔的另一端与所述至少一个附加电容中的每一个附加电容的一端电连接，所述至少一个附加电容中的每一个附加电容的另一端通过所述接地过孔与所述印刷电路板中的接地线电连接。
  3. 根据权利要求2所述的滤波模组，其特征在于，所述滤波模组还包括第一导电通道，所述第一导电通道未在所述印刷电路板的厚度方向贯穿所述印刷电路板；
    所述导电过孔位于所述第一导电通道与所述下表面之间的位置。
  4. 根据权利要求1至3中任一项所述的滤波模组，其特征在于，所述至少一个附加电容设置于所述扩展板的下表面。
  5. 根据权利要求1至3中任一项所述的滤波模组，其特征在于，所述至少一个附加电容中的部分附加电容设置于所述扩展板的下表面，其余附加电容设置于所述扩展板内部。
  6. 根据权利要求1至3中任一项所述的滤波模组，其特征在于，所述至少一个附加电容设置于所述扩展板内部。
  7. 根据权利要求2或3中任一项所述的滤波模组，其特征在于，所述印刷电路板为多层结构，所述导电孔为所述印刷电路板中的部分层结构中依次电连接的导电过孔。
  8. 根据权利要求1至7中任一项所述的滤波模组，其特征在于，所述非芯片电源触点区域为 与所述芯片电源触点区域相邻的触点区域。
  9. 根据权利要求1至8中任一项所述的滤波模组，其特征在于，所述芯片封装结构为应用处理器、调制解调处理器、图形处理器、图像信号处理器、控制器、视频编解码器，数字信号处理器、基带处理器和神经网络处理器中任意一种或者多种的集成结构。
  10. 根据权利要求1至9中任一项所述的滤波模组，其特征在于，所述滤波模组还包括功率器件，所述功率器件设置于所述扩展板上。
  11. 一种电子设备，其特征在于，所述电子设备包括权利要求1至8中任一项所述的滤波模组。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7378733B1 (en) * 2006-08-29 2008-05-27 Xilinx, Inc. Composite flip-chip package with encased components and method of fabricating same
US20120139108A1 (en) * 2010-10-15 2012-06-07 Yonghoon Kim Semiconductor package
CN104869750A (zh) * 2015-05-08 2015-08-26 华为技术有限公司 一种印刷电路板
US20190296150A1 (en) * 2015-04-02 2019-09-26 Delta Electronics, Inc. Semiconductor packaging structure
CN112788842A (zh) * 2019-11-08 2021-05-11 华为技术有限公司 一种芯片供电系统、芯片、pcb和计算机设备

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7378733B1 (en) * 2006-08-29 2008-05-27 Xilinx, Inc. Composite flip-chip package with encased components and method of fabricating same
US20120139108A1 (en) * 2010-10-15 2012-06-07 Yonghoon Kim Semiconductor package
US20190296150A1 (en) * 2015-04-02 2019-09-26 Delta Electronics, Inc. Semiconductor packaging structure
CN104869750A (zh) * 2015-05-08 2015-08-26 华为技术有限公司 一种印刷电路板
CN112788842A (zh) * 2019-11-08 2021-05-11 华为技术有限公司 一种芯片供电系统、芯片、pcb和计算机设备

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