WO2015043302A1 - 薄膜晶体管及制备方法、阵列基板及制备方法和显示装置 - Google Patents

薄膜晶体管及制备方法、阵列基板及制备方法和显示装置 Download PDF

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WO2015043302A1
WO2015043302A1 PCT/CN2014/083000 CN2014083000W WO2015043302A1 WO 2015043302 A1 WO2015043302 A1 WO 2015043302A1 CN 2014083000 W CN2014083000 W CN 2014083000W WO 2015043302 A1 WO2015043302 A1 WO 2015043302A1
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Prior art keywords
gate
layer
source
drain
electrode
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PCT/CN2014/083000
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English (en)
French (fr)
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孙宏达
成军
王美丽
孔祥永
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京东方科技集团股份有限公司
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Priority to US14/429,168 priority Critical patent/US20160043116A1/en
Publication of WO2015043302A1 publication Critical patent/WO2015043302A1/zh

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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a thin film transistor and a method for fabricating the same, an array substrate, a method for fabricating the same, and a display device. Background technique
  • CRT Cathode Ray Tube
  • LCD Liquid Crystal Display
  • 0LED Organic Light-Emitting Diode
  • both the LCD and the Active Matrix Organic Light Emission Display (AMOLED) display device include a Thin Film Transistor (TFT) formed in the array substrate.
  • Thin film transistors are the key to the display of LCD and active matrix driven OLED display devices, directly related to the development direction of high performance display devices.
  • a typical structure of a thin film transistor includes a substrate 1 and a gate electrode 2 formed on the substrate 1, a gate insulating layer 4, an active layer 5, an etch barrier layer 6, and an etch barrier layer 6 formed thereon. Source 7 and drain 8 above.
  • a process for preparing a thin film transistor is usually a patterning process, and a pattern including each film layer is sequentially formed from the bottom to the top.
  • the gate insulating layer 4 is recessed due to being engraved.
  • the source layer 5 is discontinuous in the region corresponding to the defect, thereby causing the insulation between the source 7 and the gate 2 to be broken, causing the connection of the source 7 and the gate 2.
  • the technical problem to be solved by the present invention is to provide a thin film transistor and a preparation method, an array substrate, a preparation method and a display device in view of the above-mentioned disadvantages existing in the prior art.
  • the thin film transistor and the corresponding array substrate the negative effects of the gate or the source and the drain due to the etching defects at the slope can be effectively alleviated, the possibility of discontinuity of the subsequent film layer can be eliminated, and the display device can be improved. Quality.
  • a thin film transistor includes a substrate, a gate disposed on the substrate, an active layer, a source and a drain disposed in the same layer, and a gate and the source disposed on the substrate An insulating layer between the pole and the drain; a gate pre-formed layer disposed in the same layer as the gate, the gate being formed in the gate pre-formed layer; and/or, and the source An active drain pre-formed layer is disposed in the same layer as the drain and the drain, and the source and the drain are formed in the source-drain pre-formed layer.
  • the gate is disposed on the substrate, the source and the drain are disposed above the gate; and the gate pre-formed layer is formed for forming a gate embedding trench is formed in a region of the gate, the gate is disposed in the gate embedding trench; and/or, in the source/drain pre-formed layer a source insertion groove is formed in a region where the source is formed, and a drain insertion groove is formed in a region of the source/drain pre-form layer for forming the drain, and the source is disposed at the source The pole is embedded in the groove, and the drain is disposed in the drain insertion groove.
  • the source and the drain are disposed on the substrate, the gate is disposed above the source and the drain; and the source and drain are pre-formed a source-embedded trench is formed in a region of the layer for forming the source, and the source is disposed in the source-embedded trench, and the drain is disposed in the drain-embedded trench; And/or at the gate pre-formed layer for forming the
  • the inorganic material includes silicon nitride, silicon oxide or silicon oxynitride.
  • the thickness of the gate may be the same as the thickness of the gate pre-formed layer, and the thickness of the source and the drain may be the same as the thickness of the source/drain pre-formed layer.
  • the active layer is disposed between the insulating layer and the source and the drain, and the active layer is positive with the source and the drain, respectively
  • the projection layer is at least partially overlapped, and the active layer is formed of an amorphous silicon material or by using indium gallium zinc oxide, indium zinc oxide, indium tin oxide or indium gallium tin oxide.
  • an array substrate including a gate line, a data line, and a thin film transistor disposed in a pixel region formed by the intersection of the gate line and the data line, wherein the thin film transistor adopts the above Thin film transistor.
  • the gate pre-formed layer further extends to other regions of the pixel region other than the region of the thin film transistor, the gate line is disposed in the same layer as the gate, and The gate is electrically connected; and/or the source/drain pre-form layer further extends to other regions of the pixel region other than the region of the thin film transistor, the data line is in the same layer as the source Setting and electrically connecting to the source
  • the gate line is disposed in the gate line embedding trench; and/or, in the source A data line embedding groove is formed in a region of the drain pre-formed layer for forming the data line, and the data line is disposed in the data line embedding groove.
  • the thickness of the gate line may be equal to the thickness of the gate, and the thickness of the data line may be equal to the thickness of the source.
  • a display device including the above array substrate is provided.
  • a method of fabricating a thin film transistor includes forming a gate on a substrate, forming an active layer, forming a source and a drain, and forming the gate and the source and the The step of insulating the gate insulating layer between the drains further includes: forming a gate pre-formed layer in the same layer as the gate, and forming the gate in the gate pre-formed layer; and/ Alternatively, a source-drain pre-formed layer in the same layer as the source and the drain is formed, and the source and the drain are formed in the source-drain pre-formed layer.
  • a pattern including a gate pre-formed layer and a gate embedding trench opened in the gate pre-formed layer is formed; then, embedded in the gate Forming a pattern including the gate in the trench; and/or forming a source/drain pre-formed layer and a source formed in the source-drain pre-formed layer before forming the source and the drain A pattern in which the trench and the drain are embedded in the trench; then, a pattern including the source is formed in the source embedding trench, and a pattern including the drain is formed in the drain embedding trench.
  • a pattern including the gate pre-formed layer and the gate may be formed by a patterning process, and the gate pre-formed layer and the gate may be formed using the same mask; or A pattern including the gate pre-formed layer may be formed using a patterning process, and the gate may be formed in the gate embedding trench of the gate pre-formed layer by melt infusion; and/or Forming a pattern including the source/drain pre-formed layer and the source and the drain by a patterning process, and forming the source-drain pre-formed layer and the source and the drain using the same mask; Alternatively, a pattern including the source/drain pre-formed layer may be formed by a patterning process, and the source and the drain may be respectively formed in the source-drain pre-formed layer by fusion infusion. Slot and said The drain is embedded in the slot.
  • the inorganic material comprises silicon nitride, silicon oxide or silicon oxynitride.
  • the thickness of the gate may be the same as the thickness of the gate pre-formed layer, and the thickness of the source and the drain may be the same as the thickness of the source/drain pre-formed layer.
  • a method of fabricating an array substrate includes the steps of forming a gate line, a data line, and forming a thin film transistor disposed in a pixel region formed by crossing the gate line and the data line,
  • the thin film transistor is formed by the above-described method of fabricating a thin film transistor.
  • the gate pre-formed layer is extended to other regions of the pixel region other than the region of the thin film transistor such that the gate line is formed in the same layer as the gate, and Electrically connecting to the gate; and/or extending the source/drain pre-formed layer to other regions of the pixel region other than the region of the thin film transistor such that the data line and the source
  • the pole layer is formed and electrically connected to the source.
  • a gate line embedding groove is formed in a region of the gate pre-formed layer for forming the gate line, and the gate line is formed in the gate line embedding groove; and / Alternatively, a data line embedding groove is formed in a region of the source/drain pre-formed layer for forming the data line, and the data line is formed in the data line embedding groove.
  • the thickness of the gate may be equal to the thickness of the gate, and the thickness of the data line may be equal to the thickness of the source.
  • the thin film transistor of the present invention forms a trench corresponding to the gate pattern by exposing, developing, etching by forming an inorganic material on the substrate; then forming a gate electrode such that the thickness of the gate is consistent with the depth of the trench Forming a complete pattern of gate metal material filled into the trench; then forming other film layers of the thin film transistor; and/or having the source and drain have a layer structure similar to the gate.
  • This structure can effectively alleviate the negative effects of the gate or source and drain due to etch defects at the slope, effectively solving the problem involving the gate metal film, the source and drain metal film during deposition and etching.
  • Technical problems of undesired defects can fundamentally eliminate thin film transistors The possibility of discontinuous conditions caused by protrusion or depression of the subsequent film layer improves the quality of the display device.
  • FIG. 1 is a cross-sectional view of a prior art thin film transistor.
  • Figure 2 is a cross-sectional view showing the structure of a thin film transistor in Embodiment 1 of the present invention.
  • Figure 3 is a cross-sectional view showing the structure of a thin film transistor in Embodiment 1 of the present invention.
  • Figure 4 is a cross-sectional view showing the structure of a thin film transistor in Embodiment 1 of the present invention.
  • 5A to 5H are cross-sectional views showing a process of forming a pattern including a gate electrode in the thin film transistor of Fig. 4.
  • Fig. 6 is a view showing the structure of generating a bump defect at the gate in Embodiment 1 of the present invention.
  • Fig. 7 is a view showing the structure of generating a pit defect at the gate in Embodiment 1 of the present invention.
  • Figure 8 is a cross-sectional view showing the structure of a thin film transistor in Embodiment 2 of the present invention.
  • Figure 9 is a cross-sectional view showing the structure of an array substrate in Embodiment 3 of the present invention.
  • the present embodiment provides a thin film transistor including a substrate, a gate disposed on the substrate, a source and a drain disposed in the same layer, and an insulating layer disposed between the gate and the source and the drain.
  • a gate pre-formed layer may be disposed in the same layer as the gate electrode, and a gate electrode is formed in the gate pre-formed layer.
  • an active drain pre-formed layer may be disposed in the same layer as the source and drain, and a source and a drain are formed in the source-drain pre-formed layer.
  • the thin film transistor is of a bottom gate type structure, that is, the gate is disposed on the substrate, and the source and the drain are disposed above the gate.
  • a gate, a gate insulating layer, an active layer, a source, and a drain are sequentially disposed on the substrate.
  • the active layer and the source respectively The poles and drains at least partially overlap in the forward projection direction.
  • the thin film transistor in this embodiment may specifically include the following three structures, depending on the specific process of forming the gate and the source and the drain.
  • the gate electrode 2 is disposed on the substrate 1, and a gate embedding trench is formed in a region of the gate pre-formed layer 3 for forming the gate electrode 2, and the gate electrode 2 is disposed on the gate electrode.
  • the pole is embedded in the trench, and the gate insulating layer 4, the active layer 5, the source 7 and the drain 8 are sequentially disposed above the gate 2.
  • a gate electrode 2, a gate insulating layer 4, and an active layer 5 are sequentially disposed on the substrate 1, and are opened in a region of the source/drain pre-formed layer 9 for forming the source electrode 7.
  • the source is embedded in the trench, and a drain embedding trench is formed in a region of the source/drain pre-formed layer 9 for forming the drain electrode 8, the source electrode 7 is disposed in the source embedding trench, and the drain electrode 8 is disposed in the drain embedding trench in.
  • the gate electrode 2 is disposed on the substrate 1, and a gate embedding trench is opened in a region of the gate pre-formed layer 3 for forming the gate electrode 2, and a gate electrode 2 is disposed in the gate embedding trench; above the gate 2 is a gate insulating layer 4 and an active layer 5, and a source embedding trench is opened in a region of the source/drain pre-formed layer 9 for forming the source electrode 7, and A drain embedding trench is formed in a region of the source/drain pre-formed layer 9 for forming the drain electrode 8, a source electrode 7 is disposed in the source embedding trench, and a drain electrode 8 is disposed in the drain embedding trench.
  • Both the source and drain pre-formed layers 9 are formed of an inorganic material, and the inorganic material includes silicon nitride, silicon oxide or silicon oxynitride.
  • the thickness of the gate electrode 2 may be the same as the thickness of the gate pre-formed layer 3, and the thickness of the source electrode 7 and the drain electrode 8 may be the same as the thickness of the source/drain pre-formed layer 9.
  • the gate electrode 2 is formed of molybdenum, molybdenum-niobium alloy, aluminum, aluminum-niobium alloy, titanium or copper.
  • the gate insulating layer 4 is a single layer, a double layer or more, and is formed using silicon oxide, silicon nitride, tantalum oxide, silicon oxynitride or aluminum oxide.
  • an ohmic contact layer is further disposed between the active layer 5 and the source 7 and the drain 8.
  • the active layer 5 is formed of an amorphous silicon material.
  • the ohmic contact layer is formed of an amorphous silicon material doped with phosphorus, and the electron mobility between the source 7 and the drain 8 is relatively small.
  • the active layer 5 is not damaged when the source 7 and the drain 8 are formed, and an etch barrier layer 6 is further disposed above the active layer 5.
  • the active layer 5 is made of a metal oxide semiconductor such as indium gallium zinc oxide or indium oxide. Zinc, indium tin oxide or indium gallium tin oxide is formed, so that the electron mobility between the source 7 and the drain 8 is increased, so that a good electron mobility between the source 7 and the drain 8 can be obtained, and etching is performed.
  • the barrier layer 6 is formed using silicon oxide, silicon nitride, hafnium oxide or aluminum oxide. Both source 7 and drain 8 are formed of molybdenum, molybdenum-niobium alloy, aluminum, aluminum-niobium alloy, titanium or copper.
  • the method for fabricating the above thin film transistor includes the steps of: forming a gate electrode 2 on the substrate 1, forming a source electrode 7 and a drain electrode 8, and forming a gate insulating layer 4 between the gate electrode 2 and the source electrode 7 and the drain electrode 8.
  • a step of forming a gate pre-formed layer 3 in the same layer as the gate electrode 2 and forming the gate electrode 2 in the gate pre-formed layer 3 is also included.
  • the preparation method may include the steps of forming a source-drain pre-formed layer 9 in the same layer as the source 7 and the drain 8, and forming the source 7 and the drain 8 in the source-drain pre-formed layer 9.
  • a pattern including a gate pre-formed layer 3 and a gate embedding trench formed in the gate pre-formed layer 3 is formed; then, the gate is embedded in the trench.
  • a pattern including the gate 2 is formed.
  • a pattern including a source-drain pre-formed layer 9 and source-embedded trenches and drain-embedded trenches formed in the source-drain pre-formed layer 9 is formed. Then, a pattern including the source electrode 7 is formed in the source embedding trench, and a pattern including the drain electrode 8 is formed in the drain embedding trench.
  • FIG. 1 before forming the gate electrode 2, a pattern including a gate pre-formed layer 3 and a gate embedding trench formed in the gate pre-formed layer 3 is formed; then, the gate is embedded in the trench.
  • a pattern including the gate 2 is formed.
  • a pattern including a gate pre-formed layer 3 and a gate embedding trench opened in the gate pre-formed layer 3 is formed; then, the gate is embedded in the trench Forming a pattern including the gate electrode 2; further, forming a source-drain pre-formed layer 9 and a source-embedded trench and a drain-embedded trench formed in the source-drain pre-formed layer 9 before forming the source electrode 7 and the drain electrode 8 a pattern; then, a pattern including the source 7 is formed in the source embedding trench, and a pattern including the drain 8 is formed in the drain embedding trench
  • the thin film transistor of the present invention is formed using a patterning process.
  • the patterning process of the present invention may include only a photolithography process, or may include a photolithography process and an etching step, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, and the like.
  • Photolithography process refers to the use of light including film formation (or coating), exposure, development, etc.
  • the corresponding patterning process can be selected in accordance with the structure formed in the present invention.
  • a pattern including a gate pre-formed layer and a gate is formed by a patterning process, and a gate pre-formed layer and a gate are formed by using the same mask; alternatively, a gate pre-formed layer is formed by a patterning process The pattern, and the formation of the gate in the gate pre-formed layer by fused infusion.
  • a pattern including a source/drain pre-formed layer and a source and a drain may be formed by a patterning process, and a source/drain pre-formed layer and a source and a drain are formed using the same mask; alternatively, a patterning process is used to form the source and drain.
  • a pattern of pre-formed layers, and a source and a drain are formed in the source-drain pre-formed layer by melt infusion.
  • the method of fabricating the thin film transistor shown in Fig. 4 specifically includes the following steps S1 to S4.
  • Step SI A pattern including the gate electrode 2 is formed on the substrate 1.
  • Step S11 A gate pre-formed film 30 is formed first, as shown in FIG. 5A.
  • Step S12 forming a first photoresist layer 31 over the gate pre-formed layer film 30, as shown in FIG. 5B.
  • Step S13 forming a pattern including the gate pre-formed layer 3 and the gate embedding trench 32 formed in the gate pre-formed layer in the gate pre-formed layer film 30 by the first exposure and development process, as shown in FIG. 5C Shown.
  • Step S14 The first photoresist layer 31 is removed, as shown in FIG. 5D.
  • Step S15 A gate metal layer film 20 is formed over the gate pre-formed layer 3 and the gate embedding trench 32, as shown in Fig. 5E.
  • Step S16 forming a second photoresist layer 21 over the gate metal layer film 20, as shown in FIG. 5F.
  • Step S17 by the second exposure and development process, the portion of the second photoresist layer 21 corresponding to the gate embedding groove 32 is left, and the other portions are removed, as shown in Fig. 5G.
  • Step S18 retaining a portion of the gate metal layer film 20 corresponding to the gate embedded trench 32 by an etching process, and removing other portions, and further removing the second photoresist layer 21, thereby forming a pattern including the gate 2, as shown in Fig. 5H.
  • the gate pre-formation film 30 or the gate metal film 20 is formed by deposition, sputtering or thermal evaporation.
  • the gate pre-formed layer film 30 is formed of an inorganic material including silicon nitride, silicon oxide or silicon oxynitride, and the thickness of the gate electrode 1 is the same as the thickness of the gate pre-formed layer 3.
  • the same mask is used for the patterning process of the gate pre-formed layer 3 and the gate electrode 2 for exposure.
  • the exposure property of the photoresist in the first photoresist layer 31 is opposite to the exposure property of the photoresist in the second photoresist layer 21.
  • the photoresist in the first photoresist 31 is a negative photoresist
  • the photoresist in the second photoresist 21 is a positive photoresist.
  • the step of forming the pattern including the gate pre-formed layer and the gate electrode described above employs a patterning process.
  • the gate electrode 2 is formed in the gate embedding trench 32 by molten infusion (that is, the gate metal material is melted and poured into the corresponding trench), and then corresponding Steps S15 to S18 are omitted, and the thickness of the gate 2 formed in this manner can be made thinner and flatter.
  • Step S2 A pattern including the gate insulating layer 4 is formed on the gate electrode 2.
  • the gate insulating layer 4 is formed on the substrate 1 on which the step S1 is completed.
  • the gate insulating layer 4 can be formed by plasma enhanced chemical vapor deposition.
  • Step S3 A pattern including the active layer 5 is formed on the gate insulating layer 4.
  • a composite layer film is formed on the substrate 1 in which the step S2 is completed, and the composite film layer may be formed by deposition, sputtering or thermal evaporation.
  • the composite layer film includes an active layer film and is disposed above the active layer film.
  • the etch barrier film (deposited separately during the deposition process) can form a pattern including the composite layer on the gate insulating layer 4 by a patterning process using a conventional mask.
  • a pattern including a composite layer is formed on the substrate on which the step S2 is completed, and the composite layer includes an active layer and an ohmic contact layer disposed above the active layer (deposited separately in the formation process), which can be passed through a common mask
  • a patterning process forms a pattern including a composite layer on the gate insulating layer 4.
  • Step S4 A pattern including the source electrode 7 and the drain electrode 8 is formed on the active layer 5.
  • Step S41 First, a source/drain pre-formed layer film is formed.
  • Step S42 forming a first photoresist layer over the source/drain pre-formed layer film.
  • Step S43 pre-forming the pattern of the film groove and the drain embedding groove in the source and drain by the first exposure and development process.
  • Step S44 removing the first photoresist layer.
  • Step S45 forming a source/drain metal layer film over the source drain pre-formed layer and the source embedding trench and the drain embedding trench.
  • Step S46 forming a second photoresist layer over the source/drain metal layer film.
  • Step S47 by the second exposure and development process, the portions of the source/drain metal layer film corresponding to the source embedding trench and the drain embedding trench are left, and other portions are removed, thereby forming a pattern including the source and the drain.
  • Step S48 removing the second photoresist layer.
  • a source-drain pre-formed film or a source-drain metal film is formed by deposition, sputtering or thermal evaporation.
  • the source/drain pre-formed film is formed of an inorganic material, and the inorganic material includes silicon nitride, silicon oxide or silicon oxynitride.
  • the thickness of the source 7 and the drain 8 is the same as the thickness of the source/drain pre-formed layer 9. Furthermore, the exposure properties of the photoresist in the first photoresist layer are opposite to those of the photoresist in the second photoresist layer.
  • the source 7 and the drain 8 may be formed in the source embedding trench and the drain embedding trench by means of fusion infusion, and steps S45 to S48 may be omitted correspondingly.
  • the source 7 and the drain 8 are formed in a manner that the thickness can be made thinner and the flatness is better.
  • the thin film transistor is prepared.
  • a gate pre-formed layer is formed, and a gate embedding trench required for accommodating and fixing the gate is formed by exposure, development, and etching; and forming a gate preform a layer of the same thickness of the gate, which is completely filled to the gate
  • the gate is embedded in the trench.
  • the gate surface is uneven or the pattern is broken, but the formation of the subsequent film layer is not further aggravated. defect. For example, as shown in FIG.
  • the gate in this embodiment can effectively solve the problem of leakage caused by defects in the pattern in the prior art as compared with the gate in the prior art.
  • the source and the drain in this embodiment can effectively solve the problem of leakage caused by defects in the pattern in the prior art compared with the source and the drain in the prior art.
  • the gate pre-formed layer and the gate are formed by using the same mask, and the source/drain pre-formed layer and the source/drain are formed by using the same mask, the number of masks is increased without increasing the number of masks.
  • the exposure and development processes are performed to form corresponding gate pre-formed layers or source-drain pre-formed layers, and the above-described scheme can achieve an effect of effectively preventing metal electrode connections in the thin film transistors.
  • the difference between this embodiment and the embodiment 1 is that the thin film transistor in this embodiment has a top gate type structure.
  • the thin film transistor is of a top gate type structure, that is, the source and the drain are disposed on the substrate, and the gate is disposed above the source and the drain. Specifically, a source and a drain, an active layer, a gate insulating layer, and a gate are sequentially disposed on the substrate.
  • the thin film transistor of the present embodiment specifically includes the following three structures according to the specific process of forming the gate and the source and the drain.
  • the source and drain pre-formed layer 9 and the source 7 are The drain electrode 8 is formed on the substrate 1, and a source insertion groove is formed in a region of the source/drain pre-formed layer 9 for forming a source, and a drain is formed in a region of the source/drain pre-formed layer 9 for forming a drain.
  • the pole is embedded in the slot, the source 7 is disposed in the source embedding slot, and the drain 8 is disposed in the drain embedding slot.
  • An active layer 5, a gate insulating layer 4, and a gate electrode 2 are sequentially disposed above the source electrode 7 and the drain electrode 8, respectively.
  • the source 7 and the drain 8 are formed on the substrate 1, and the active layer 5 and the gate insulating layer 4 are sequentially disposed above the source 7 and the drain 8, respectively, and the gate pre-formed layer 3 is formed.
  • a gate embedding trench is formed in a region for forming the gate electrode, and the gate electrode 2 is disposed in the gate embedding trench.
  • the source/drain pre-formed layer 9 and the source 7 and the drain 8 are formed on the substrate 1, and the source-embedded trench is opened in the region of the source-drain pre-formed layer 9 for forming the source.
  • a drain embedding trench is formed in a region of the source/drain pre-formed layer 9 for forming a drain
  • a source electrode 7 is disposed in the source embedding trench
  • a drain electrode 8 is disposed in the drain embedding trench.
  • An active layer 5 and a gate insulating layer 4 are respectively disposed above the source 7 and the drain 8, and a gate embedding trench is formed in a region of the gate pre-formed layer 3 for forming a gate, and the gate 2 is disposed.
  • the gate is embedded in the groove.
  • both the gate pre-formed layer 3 and the source/drain pre-formed layer 9 are formed of an inorganic material including silicon nitride, silicon oxide or silicon oxynitride.
  • the thickness of the gate electrode 2 may be the same as the thickness of the gate pre-formed layer 3, and the thickness of the source electrode 7 and the drain electrode 8 may be the same as the thickness of the source/drain pre-formed layer 9.
  • each film layer in the thin film transistor of this embodiment is the same as that of the first embodiment.
  • This embodiment provides an array substrate including the thin film transistor of Embodiment 1.
  • the array substrate of this embodiment includes a gate line, a data line, and a thin film transistor disposed in a pixel region formed by crossing the gate line and the data line, and the thin film transistor adopts the bottom gate type thin film transistor of Embodiment 1.
  • the gate pre-formed layer may further extend to other regions of the pixel region than the region corresponding to the thin film transistor, and the gate line and the gate are disposed in the same layer, and The gate is electrically connected.
  • the source/drain pre-formed layer may also extend to other regions of the pixel region than the region corresponding to the thin film transistor, and the data line is disposed in the same layer as the source and electrically connected to the source.
  • a gate line embedding groove is formed in a region of the gate pre-formed layer for forming a gate line, and the gate line is disposed in the gate line embedding groove.
  • a data line embedding groove is formed in a region of the source/drain pre-formed layer for forming the data line, and the data line is disposed in the data line embedding groove.
  • the thickness of the gate line is equal to the thickness of the gate, and the thickness of the data line is equal to the thickness of the source.
  • the array substrate in this embodiment includes the thin film transistor described above, and further includes a passivation layer 10 and a pixel electrode 11 .
  • the passivation layer 10 is disposed above the source 7 and the drain 8 in the passivation layer.
  • a via hole is formed in a region of 10 corresponding to the drain electrode 8, and the passivation layer 10 is formed using silicon oxide, silicon nitride, hafnium oxide or aluminum oxide.
  • the pixel electrode 11 is disposed above the passivation layer 10, and the drain electrode 8 is connected to the pixel electrode 11 through a via hole formed by indium gallium zinc oxide, indium zinc oxide, indium tin oxide or indium gallium tin oxide.
  • the array substrate provided with the pixel electrode described above can be used for forming a liquid crystal display device of a TN (Twisted Nematic) mode or a liquid crystal of VA (Vert ica ign ignment) mode.
  • the common electrode may be further provided on the basis of the above array substrate to form an ADS (ADvanced Super Dimensional Switch) mode liquid crystal display device.
  • a metal anode of an OLED Organic Light-Educing Diode
  • AMOLED Active Matr ix Organic Light Emi ss ion Di
  • the method for fabricating the above array substrate includes the method for preparing the thin film transistor of Embodiment 1, and further includes: extending the gate pre-formed layer to other regions of the pixel region other than the region corresponding to the thin film transistor, such that the gate line and The gate is formed in the same layer and electrically connected to the gate, or may further include: extending the source/drain pre-formed layer to other regions of the pixel region other than the region corresponding to the thin film transistor, so that the data line and the source are formed in the same layer, And electrically connected to the source.
  • a gate line embedding groove is formed in a region of the gate pre-formed layer for forming a gate line
  • a gate line is formed in the gate line embedding groove.
  • a data line embedding groove is formed in a region of the source/drain pre-formed layer for forming a data line, and a data line is formed in the data line embedding groove.
  • the thickness of the gate line is equal to the thickness of the gate, and the thickness of the data line is equal to the thickness of the source.
  • the thin film transistor has been prepared and pre-formed as a gate scan line and a data line, and further includes the following steps S5 and S6.
  • Step S5 forming a pattern including the passivation layer 10 and the via holes on the source electrode 7 and the drain electrode 8.
  • a passivation layer film (PVX Deposit ion) is formed on the substrate 1 on which the step S4 is completed, and the passivation layer 10 may be formed on the source electrode 7 and the drain electrode 8 by a patterning process using a common mask. A pattern is formed, and a pattern including via holes is formed in the passivation layer 10 by etching.
  • the passivation film is formed by deposition, sputtering or thermal evaporation.
  • Step S6 A pattern including the pixel electrode 11 is formed over the passivation layer 10, and the drain electrode 8 is connected to the pixel electrode 11 through the via hole.
  • a transparent conductive film is formed on the substrate 1 in which the step S5 is completed, and a pattern including the pixel electrode 11 can be formed over the passivation layer 10 by a patterning process using a common mask, and the drain 8 passes through the via and the pixel electrode. 11 connections.
  • the transparent conductive film is formed by a method of deposition, sputtering, or thermal evaporation.
  • the gate line and the gate are simultaneously formed, the data line is formed simultaneously with the source/drain, the gate line is embedded in the groove and the gate is embedded in the groove, and the data line is embedded in the groove and the source is embedded in the groove and the drain.
  • the pole insertion grooves are simultaneously formed, so that the effect of effectively preventing leakage can be achieved without increasing the number of masks.
  • This embodiment provides an array substrate including the thin film transistor of Embodiment 2.
  • the array substrate of this embodiment includes a gate line, a data line, and a thin film transistor disposed in a pixel region formed by crossing the gate line and the data line, and the thin film transistor is implemented The top gate type thin film transistor of Example 2.
  • the gate pre-formed layer may further extend to other regions of the pixel region than the region corresponding to the thin film transistor, and the gate line is disposed in the same layer as the gate and electrically connected to the gate.
  • the source-drain pre-formed layer may also extend to other regions of the pixel region than the region corresponding to the thin film transistor, and the data line is disposed in the same layer as the source and electrically connected to the source.
  • a gate line embedding groove is formed in a region of the gate pre-formed layer for forming a gate line, and the gate line is disposed in the gate line embedding groove.
  • a data line embedding groove is formed in a region of the source/drain pre-formed layer for forming the data line, and the data line is disposed in the data line embedding groove.
  • the thickness of the gate line is equal to the thickness of the gate, and the thickness of the data line is equal to the thickness of the source.
  • This embodiment provides a display device including the array substrate in Embodiments 3 and 4.
  • the display device can be: a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, and the like, or any display product or component.
  • the display device since the array substrate used therein has an effect of effectively preventing leakage, the display device has good stability and good display quality.
  • an inorganic material is first formed on the substrate, and a trench corresponding to the gate pattern is formed by exposure, development, etching; then a gate is formed, and the thickness of the gate is made The depth of the trenches is uniform to form a complete pattern of gate metal material filled into the trench; then other layers of the thin film transistor are formed.
  • a source and a drain having a layer structure similar to that of the gate. This structure can effectively alleviate the negative effects of the gate or source and drain due to etch defects at the slope, effectively solving the problem involving the gate metal film, the source and drain metal film during deposition and etching.
  • the technical problem of undesired defects can fundamentally eliminate the possibility of discontinuity of the subsequent film layer and improve the quality of the display device.
  • a gate line connected to the gate electrode and a data line connected to the source electrode are also formed in the inorganic material layer, so that each conductive film layer realizes a reduction in edge slope area during the subsequent increase of the film layer, and the gate line can be effectively slowed down.
  • the negative effect of the data line due to the defect at the slope makes it possible to obtain a perfect display screen for the display device under the background of gradually refined pixels.
  • the thin film transistor structure and the corresponding preparation method provided by the invention can be extended to the semiconductor device structure and the preparation method of various film layers, the core of which is to form the trench of the semiconductor device pattern to be formed by other materials.
  • the trench is filled with a material for forming a pattern of the semiconductor device.
  • the preparation method does not need to increase the number of masks, but can reduce the influence of the slope incompleteness of the subsequent layer on the front layer, and can effectively prevent leakage of the semiconductor device. Possible.

Abstract

提供了薄膜晶体管及制备方法、阵列基板及制备方法和显示装置。该薄膜晶体管包括基板（1）以及设置于所述基板（1）上的栅极（2）、有源层（5）、同层设置的源极（7）和漏极（8）以及设置于所述栅极（2）与所述源极（7）和所述漏极（8）之间的绝缘层。与所述栅极（2）同层设置有栅极预形成层（3），所述栅极（2）形成在所述栅极预形成层（3）中。与所述源极（7）和所述漏极（8）同层设置有源漏预形成层（9），所述源极（7）和所述漏极（8）形成在所述源漏预形成层（9）中。

Description

薄膜晶体管及制备方法、 阵列基板及制备方法和显示装置 技术领域
本发明属于显示技术领域， 具体涉及薄膜晶体管及其制备方 法、 阵列基板及其制备方法和显示装置。 背景技术
随着科学技术的发展， 平板显示装置已取代笨重的
CRT (Cathode Ray Tube ，阴极射线管）显示装置， 在人们的日常生 活中越来越普遍。 目前， 常用的平板显示装置包括 LCD (Liquid Crystal Display： 液晶 显示装置 ） 和 0LED ( Organic Light-Emitting Diode: 有机发光二极管）显示装置。
在成像过程中， LCD和有源矩阵驱动式 OLED (Active Matrix Organic Light Emission Display, 简称 AMOLED)显示装置中都 包括形成在阵列基板中的薄膜晶体管 （Thin Film Transistor: 简称 TFT) 。 薄膜晶体管是实现 LCD和有源矩阵驱动式 OLED显示 装置显示的关键， 直接关系到高性能显示装置的发展方向。
如图 1所示， 一种薄膜晶体管的典型结构包括基板 1以及在 基板 1上形成的栅极 2、 栅绝缘层 4、 有源层 5、 刻蚀阻挡层 6和 形成在刻蚀阻挡层 6上方的源极 7和漏极 8。 目前，制备薄膜晶体 管的工艺过程通常为采用构图工艺， 从下而上依次制备形成包括 各膜层的图形。 由于薄膜晶体管的膜层数较多， 因此在采用构图 工艺形成各膜层的过程中， 例如沉积和刻蚀步骤中， 很容易因为 先形成的某个膜层在图形的突变处， 例如， 图 1 中所示的斜坡处 因刻蚀不规则而形成微小的凸出或凹陷的缺陷 15 (当然， 也有可 能为凹陷至整层的缺陷） 。 图 1 中， 栅绝缘层 4 因受到过刻而形 成凹陷， 若凹陷过深或过大， 随着镀膜的进行， 由于后续膜层沉 积时沉积材料都很难进入上方有阻挡的部位， 缺陷不会得到填充， 而且刻蚀时发生的一部分过刻蚀很轻易就将沉积的膜层刻蚀掉， 形成越来越严重的缺陷， 最终导致本不该连接的膜层间相互接触， 例如可能形成图 1 中有源层 5在对应于该缺陷的区域不连续的情 况， 进而造成源极 7与栅极 2之间的绝缘被破坏， 引起源极 7与 栅极 2 的连接。 可以推断， 一旦出现了某个膜层在图形的突变处 的凸出或凹陷， 随着多个构图工艺的累积， 后续膜层的凸出状况 或凹陷造成的不连续状况会进一步加剧， 引起显示面板的不良问 题， 尤其是因凹陷而引起的金属电极之间的连接， 最终将导致显 示面板漏电。 而显示面板一旦漏电， 将导致整块显示面板的报废， 造成生产成本的极大浪费。
因此， 设计出这样一种薄膜晶体管成为目前业界亟待解决的 问题： 各膜层不会受制备工艺影响而出现绝缘被破坏的问题， 能 够有效地防止金属电极之间漏电， 从而提高产品质量。 发明内容
本发明所要解决的技术问题是针对现有技术中存在的上述不 足， 提供薄膜晶体管及制备方法、 阵列基板及制备方法和显示装 置。 在该薄膜晶体管以及相应的阵列基板中， 能够有效减緩栅极 或者源极和漏极因斜坡处的刻蚀缺陷所带来的负面效果， 杜绝后 续膜层的不连续的可能， 提高显示装置的品质。
根据本发明的一个方面， 提供一种薄膜晶体管， 包括基板以 及设置于所述基板上的栅极、 有源层、 同层设置的源极和漏极以 及设置于所述栅极与所述源极和所述漏极之间的绝缘层； 与所述 栅极同层设置有栅极预形成层， 所述栅极形成在所述栅极预形成 层中； 以及 /或者， 与所述源极和所述漏极同层设置有源漏预形成 层， 所述源极和所述漏极形成在所述源漏预形成层中。
在所述薄膜晶体管中， 例如， 所述栅极设置在所述基板上， 所述源极和所述漏极设置在所述栅极的上方； 在所述栅极预形成 层的用于形成所述栅极的区域中开设有栅极嵌入槽， 所述栅极设 置在所述栅极嵌入槽内； 以及 /或者， 在所述源漏预形成层的用于 形成所述源极的区域中开设有源极嵌入槽， 在所述源漏预形成层 的用于形成所述漏极的区域中开设有漏极嵌入槽， 所述源极设置 在所述源极嵌入槽中， 所述漏极设置在所述漏极嵌入槽中。
在所述薄膜晶体管中， 例如， 所述源极和所述漏极设置在所 述基板上， 所述栅极设置在所述源极和所述漏极的上方； 在所述 源漏预形成层的用于形成所述源极的区域中开设有源极嵌入槽， 入槽， 所述源极设置在所述源极嵌入槽中， 所述漏极设置在所述 漏极嵌入槽中； 以及 /或者， 在所述栅极预形成层的用于形成所述
Figure imgf000004_0001
形成， 所述无机材料包括氮化硅、 氧化硅或氮氧化硅。
所述栅极的厚度可以与所述栅极预形成层的厚度相同， 所述 源极和所述漏极的厚度可以与所述源漏预形成层的厚度相同。
在所述薄膜晶体管中， 所述有源层设置在所述绝缘层与所述 源极和所述漏极之间， 且所述有源层分别与所述源极和所述漏极 在正投影方向上至少部分重叠， 所述有源层采用非晶硅材料形成， 或者采用氧化铟镓锌、 氧化铟锌、 氧化铟锡或氧化铟镓锡形成。
根据本发明的另一个方面， 提供一种阵列基板， 包括栅线、 数据线以及设置在由所述栅线与所述数据线交叉形成的像素区内 的薄膜晶体管， 所述薄膜晶体管采用上述的薄膜晶体管。
在所述阵列基板中， 所述栅极预形成层还延伸至所述像素区 的对应于所述薄膜晶体管的区域以外的其他区域， 所述栅线与所 述栅极同层设置、 且与所述栅极电连接； 以及 /或者， 所述源漏预 形成层还延伸至所述像素区的对应于所述薄膜晶体管的区域以外 的其他区域， 所述数据线与所述源极同层设置、 且与所述源极电 连接
Figure imgf000004_0002
入槽， 所述栅线设置在所述栅线嵌入槽中； 以及 /或者， 在所述源 漏预形成层的用于形成数据线的区域中开设有数据线嵌入槽， 所 述数据线设置在所述数据线嵌入槽中。
所述栅线的厚度可以与所述栅极的厚度相等， 所述数据线的 厚度可以与所述源极的厚度相等。
根据本发明的还一个方面， 提供一种显示装置， 包括上述的 阵列基板。
根据本发明的又一个方面，提供一种薄膜晶体管的制备方法， 包括在基板上形成栅极、 形成有源层、 形成源极和漏极以及形成 所述栅极与所述源极和所述漏极之间的栅绝缘层的步骤， 还包括： 形成与所述栅极同层的栅极预形成层， 并将所述栅极形成在所述 栅极预形成层中的步骤； 以及 /或者， 形成与所述源极和所述漏极 同层的源漏预形成层， 并将所述源极和所述漏极形成在所述源漏 预形成层中的步骤。
在所述制备方法中， 在形成所述栅极之前， 先形成包括栅极 预形成层以及开设在所述栅极预形成层中的栅极嵌入槽的图形； 然后，在所述栅极嵌入槽内形成包括所述栅极的图形；以及 /或者， 在形成所述源极和所述漏极之前， 先形成包括源漏预形成层以及 开设在所述源漏预形成层中的源极嵌入槽和漏极嵌入槽的图形； 然后， 在所述源极嵌入槽内形成包括所述源极的图形， 以及在所 述漏极嵌入槽内形成包括所述漏极的图形。
在所述制备方法中， 可以采用构图工艺形成包括所述栅极预 形成层以及所述栅极的图形， 并且可以采用同一掩模板形成所述 栅极预形成层以及所述栅极； 或者， 可以采用构图工艺形成包括 所述栅极预形成层的图形， 以及可以采用熔融灌注方式将所述栅 极形成在所述栅极预形成层的所述栅极嵌入槽中； 以及 /或者， 可 以采用构图工艺形成包括所述源漏预形成层以及所述源极和所述 漏极的图形， 并且可以采用同一掩模板形成所述源漏预形成层以 及所述源极和所述漏极； 或者， 可以采用构图工艺形成包括所述 源漏预形成层的图形， 以及可以采用熔融灌注方式将所述源极和 所述漏极分别形成在所述源漏预形成层的所述源极嵌入槽和所述 漏极嵌入槽中。 成， 所述无机材料包括氮化硅、 氧化硅或氮氧化硅。
所述栅极的厚度可以与所述栅极预形成层的厚度相同， 所述 源极和所述漏极的厚度可以与所述源漏预形成层的厚度相同。
根据本发明的又一个方面， 提供一种阵列基板的制备方法， 包括形成栅线、 数据线以及形成设置在由所述栅线与所述数据线 交叉形成的像素区内的薄膜晶体管的步骤， 采用上述的薄膜晶体 管的制备方法形成所述薄膜晶体管。
在所述制备方法中， 将所述栅极预形成层延伸至所述像素区 的对应于所述薄膜晶体管的区域以外的其他区域， 使得所述栅线 与所述栅极同层形成、 且与所述栅极电连接； 以及 /或者， 将所述 源漏预形成层还延伸至所述像素区的对应于所述薄膜晶体管的区 域以外的其他区域， 使得所述数据线与所述源极同层形成、 且与 所述源极电连接。
在所述制备方法中， 在所述栅极预形成层的用于形成所述栅 线的区域中形成栅线嵌入槽， 并将所述栅线形成在所述栅线嵌入 槽中； 以及 /或者， 在所述源漏预形成层的用于形成所述数据线的 区域中形成数据线嵌入槽， 并将所述数据线形成在所述数据线嵌 入槽中。
所述栅极的厚度可以与所述栅极的厚度相等， 所述数据线的 厚度可以与所述源极的厚度相等。
本发明中的薄膜晶体管通过将无机材料形成在基板上， 通过 曝光、 显影、 刻蚀形成与栅极图形相对应的沟槽； 然后形成栅极， 并使得栅极的厚度与沟槽的深度一致， 以形成栅极金属材料填充 至沟槽中的完整图形； 然后再形成薄膜晶体管的其他膜层； 以及 / 或者， 使源极和漏极具有与栅极类似的层结构。 这种结构能够有 效减緩栅极或源极和漏极因斜坡处的刻蚀缺陷所带来的负面效 果， 有效解决涉及栅极金属层膜、 源漏金属层膜在沉积和刻蚀时 发生不期望的缺陷的技术问题， 能够从根本上杜绝薄膜晶体管中 后续膜层的凸出或凹陷造成的不连续状况的可能， 提高显示装置 的品质。 附图说明
图 1为现有技术中薄膜晶体管的剖视图。
图 2为本发明的实施例 1中的一种薄膜晶体管结构的剖视图。 图 3为本发明的实施例 1中的一种薄膜晶体管结构的剖视图。 图 4为本发明的实施例 1中的一种薄膜晶体管结构的剖视图。 图 5A至图 5H为图 4的薄膜晶体管中形成包括栅极的图形的 过程的剖视图。
图 6为本发明的实施例 1 中的栅极处产生凸起缺陷的结构示 意图。
图 7为本发明的实施例 1 中的栅极处产生凹陷缺陷的结构示 意图。
图 8为本发明的实施例 2中的一种薄膜晶体管结构的剖视图。 图 9为本发明的实施例 3中的一种阵列基板结构的剖视图。 具体实施方式
为使本领域技术人员更好地理解本发明的技术方案， 下面结 合附图和具体实施方式对本发明的膜晶体管及制备方法、 阵列基 板及制备方法和显示装置作进一步详细描述。
[实施例 1 ]
本实施例提供一种薄膜晶体管， 包括基板以及设置于基板上 的栅极、 同层设置的源极和漏极以及设置于栅极与源极和漏极之 间的绝缘层。 所述薄膜晶体管中， 与栅极同层可以设置有栅极预 形成层， 栅极形成在栅极预形成层中。 此外， 与源极和漏极同层 可以设置有源漏预形成层， 源极和漏极形成在源漏预形成层中。
本实施例中， 薄膜晶体管为底栅型结构， 即栅极设置在基板 上， 源极和漏极设置在栅极的上方。 具体地， 基板上依次设置有 栅极、 栅绝缘层、 有源层、 源极和漏极。 其中， 有源层分别与源 极和漏极在正投影方向上至少部分重叠。 才艮据栅极与源极和漏极 具体形成工艺的不同， 本实施例中的薄膜晶体管具体可以包括如 下三种结构。
如图 2所示， 在薄膜晶体管中， 栅极 2设置在基板 1上， 在 栅极预形成层 3的用于形成栅极 2的区域中开设有栅极嵌入槽， 栅极 2设置在栅极嵌入槽内， 并且栅极 2上方依次设置有栅绝缘 层 4、 有源层 5、 源极 7和漏极 8。
如图 3所示， 在薄膜晶体管中， 基板 1上依次设置有栅极 2、 栅绝缘层 4、 有源层 5 , 在源漏预形成层 9的用于形成源极 7的区 域中开设有源极嵌入槽，并且在源漏预形成层 9的用于形成漏极 8 的区域中开设有漏极嵌入槽， 源极 7设置在源极嵌入槽中， 漏极 8 设置在漏极嵌入槽中。
可替代地， 如图 4所示， 在薄膜晶体管中， 栅极 2设置在基 板 1上， 在栅极预形成层 3的用于形成栅极 2的区域中开设有栅 极嵌入槽，栅极 2设置在栅极嵌入槽内；栅极 2上方为栅绝缘层 4 和有源层 5 ,在源漏预形成层 9的用于形成源极 7的区域中开设有 源极嵌入槽， 并且在源漏预形成层 9的用于形成漏极 8的区域中 开设有漏极嵌入槽， 源极 7设置在源极嵌入槽中， 漏极 8设置在 漏极嵌入槽中。
在图 2至图 4所示的上述薄膜晶体管结构中， 栅极预形成层
3与源漏预形成层 9均采用无机材料形成， 无机材料包括氮化硅、 氧化硅或氮氧化硅。 栅极 2的厚度可以与栅极预形成层 3的厚度 相同， 源极 7和漏极 8的厚度可以与源漏预形成层 9的厚度相同。
在本实施例中， 栅极 2采用钼、 钼铌合金、 铝、 铝钕合金、 钛或铜形成。 栅绝缘层 4 为单层、 双层或更多层， 并采用硅氧化 物、 硅氮化物、 铪氧化物、 硅氮氧化物或铝氧化物形成。 为了保 证有源层 5与源极 7和漏极 8的良好接触， 有源层 5与源极 7和 漏极 8之间还进一步设置有欧姆接触层， 有源层 5采用非晶硅材 料形成， 欧姆接触层采用掺杂磷元素的非晶硅材料形成， 源极 7 与漏极 8之间的电子迁移率相对较小。 可替代地， 为了保证在形 成源极 7和漏极 8时有源层 5不受损坏， 有源层 5的上方还进一 步设置刻蚀阻挡层 6 ,有源层 5采用金属氧化物半导体， 例如氧化 铟镓锌、 氧化铟锌、 氧化铟锡或氧化铟镓锡形成， 使得源极 7 与 漏极 8之间的电子迁移率增加，因此能获得较好的源极 7与漏极 8 之间的电子迁移率， 刻蚀阻挡层 6 采用硅氧化物、 硅氮化物、 铪 氧化物或铝氧化物形成。 源极 7和漏极 8均采用钼、 钼铌合金、 铝、 铝钕合金、 钛或铜形成。
相应的， 上述薄膜晶体管的制备方法包括： 在基板 1上形成 栅极 2、 形成源极 7和漏极 8以及形成栅极 2与源极 7和漏极 8 之间的栅绝缘层 4的步骤， 还包括形成与栅极 2 同层的栅极预形 成层 3 , 并将栅极 2形成在栅极预形成层 3中的步骤。 此外， 所述 制备方法可以包括形成与源极 7和漏极 8同层的源漏预形成层 9 , 并将源极 7和漏极 8形成在源漏预形成层 9中的步骤。
简言之， 参照图 2 , 在形成栅极 2之前， 先形成包括栅极预 形成层 3 以及开设在栅极预形成层 3 中的栅极嵌入槽的图形； 然 后，在栅极嵌入槽内形成包括栅极 2的图形。可替代地，参照图 3 , 在形成源极 7和漏极 8之前， 先形成包括源漏预形成层 9以及开 设在源漏预形成层 9中的源极嵌入槽和漏极嵌入槽的图形； 然后， 在源极嵌入槽内形成包括源极 7 的图形， 以及在漏极嵌入槽内形 成包括漏极 8的图形。 可替代地， 参照图 4 , 在形成栅极 2之前， 先形成包括栅极预形成层 3 以及开设在栅极预形成层 3 中的栅极 嵌入槽的图形； 然后， 在栅极嵌入槽内形成包括栅极 2 的图形； 此外， 在形成源极 7和漏极 8之前， 先形成包括源漏预形成层 9 以及开设在源漏预形成层 9中的源极嵌入槽和漏极嵌入槽的图形； 然后， 在源极嵌入槽内形成包括源极 7 的图形， 以及在漏极嵌入 槽内形成包括漏极 8的图形
本发明的薄膜晶体管采用构图工艺形成。 在本发明的构图工 艺， 可只包括光刻工艺， 或者包括光刻工艺以及刻蚀步骤， 同时 还可以包括打印、 喷墨等其他用于形成预定图形的工艺。 光刻工 艺， 是指包括成膜 （或镀膜） 、 曝光、 显影等工艺过程的利用光 刻胶、 掩模板、 曝光机等形成图形的工艺。 可根据本发明中所形 成的结构选择相应的构图工艺。
在本实施例中， 采用构图工艺形成包括栅极预形成层以及栅 极的图形， 采用同一掩模板形成栅极预形成层以及栅极； 可替代 地， 采用构图工艺形成包括栅极预形成层的图形， 以及采用熔融 灌注方式将栅极形成在栅极预形成层中。 同样， 可以采用构图工 艺形成包括源漏预形成层以及源极和漏极的图形， 采用同一掩模 板形成源漏预形成层以及源极和漏极； 可替代地， 采用构图工艺 形成包括源漏预形成层的图形， 以及采用熔融灌注方式将源极和 漏极形成在源漏预形成层中。
图 4中所示的薄膜晶体管的制备方法具体包括如下步骤 S1至 步骤 S4。
步骤 SI : 在基板 1上形成包括栅极 2的图形。
在该步骤中， 具体包括如下子步骤 S11至 S18。
步骤 S11 : 先形成栅极预形成层膜 30, 如图 5A所示。
步骤 S12: 在栅极预形成层膜 30上方形成第一光刻胶层 31 , 如图 5B所示。
步骤 S13: 通过第一次曝光、 显影工艺， 在栅极预形成层膜 30中形成包括栅极预形成层 3以及开设在栅极预形成层中的栅极 嵌入槽 32的图形， 如图 5C所示。
步骤 S14: 去除第一光刻胶层 31 , 如图 5D所示。
步骤 S15: 在栅极预形成层 3和栅极嵌入槽 32上方形成栅极 金属层膜 20, 如图 5E所示。
步骤 S16: 在栅极金属层膜 20上方形成第二光刻胶层 21 , 如 图 5F所示。
步骤 S17 : 通过第二次曝光、 显影工艺， 保留第二光刻胶层 21 中对应于栅极嵌入槽 32的部分， 并且去除其他部分， 如图 5G 所示。
步骤 S18: 通过刻蚀工艺， 保留栅极金属层膜 20中对应于栅 极嵌入槽 32的部分， 并去除其他部分， 此外还去除第二光刻胶层 21 , 从而形成包括栅极 2的图形， 如图 5H所示。
在该步骤中， 采用沉积、 溅射或热蒸发的方法形成栅极预形 成层膜 30或栅极金属层膜 20。 其中， 栅极预形成层膜 30采用无 机材料形成， 无机材料包括氮化硅、 氧化硅或氮氧化硅， 并且栅 极 1的厚度与栅极预形成层 3的厚度相同。
在该步骤中， 栅极预形成层 3与栅极 2的构图工艺中采用同 一掩模板进行曝光。 同时， 为了保证曝光工艺图形的正确性， 优 选第一光刻胶层 31 中光刻胶的曝光性质与第二光刻胶层 21 中光 刻胶的曝光性质相反。 例如， 第一光刻胶 31中光刻胶为负性光刻 胶， 第二光刻胶 21中光刻胶为正性光刻胶。
上述形成包括所述栅极预形成层以及所述栅极的图形的步骤 采用构图工艺。 可替代地， 当栅极预形成层 3形成后， 采用熔融 灌注方式将栅极 2形成在栅极嵌入槽 32中（即将栅极金属材料熔 融后灌注进入相应的沟槽中），则可相应省略步骤 S15至步骤 S18 , 采用该方式形成的栅极 2 , 厚度可以制造得更薄、 平坦度更好。
步骤 S2 : 在栅极 2上形成包括栅绝缘层 4的图形。
在该步骤中， 在完成步骤 S1的基板 1上形成栅绝缘层 4。 栅 绝缘层 4可采用等离子体增强化学气相沉积法形成。
步骤 S 3: 在栅绝缘层 4上形成包括有源层 5的图形。
在该步骤中， 在完成步骤 S2的基板 1上形成复合层膜， 形成 复合膜层可以采用沉积、 溅射或热蒸发等方法， 复合层膜包括有 源层膜以及设置于有源层膜上方的刻蚀阻挡层膜（沉积过程中分 别依次沉积），可利用普通掩模板通过一次构图工艺在栅绝缘层 4 上形成包括复合层的图形。
可替代地， 在完成步骤 S2的基板上形成包括复合层的图形， 复合层包括有源层以及设置于有源层上方的欧姆接触层 （形成过 程中分别依次沉积） ， 可利用普通掩模板通过一次构图工艺在栅 极绝缘层 4上形成包括复合层的图形。
步骤 S4 : 在有源层 5上形成包括源极 7和漏极 8的图形。 在该步骤中， 具体包括如下子步骤 S41至 S48。 步骤 S41 : 先形成源漏预形成层膜。
步骤 S42: 在源漏预形成层膜上方形成第一光刻胶层。
步骤 S43: 通过第一次曝光、 显影工艺， 在源漏预形成层膜 槽和漏极嵌入槽的图形。
步骤 S44: 去除第一光刻胶层。
步骤 S45 : 在源漏预形成层和源极嵌入槽和漏极嵌入槽上方 形成源漏金属层膜。
步骤 S46: 在源漏金属层膜上方形成第二光刻胶层。
步骤 S47 : 通过第二次曝光、 显影工艺， 保留源漏金属层膜 中对应于源极嵌入槽和漏极嵌入槽的部分， 去除其他部分， 从而 形成包括源极和漏极的图形。
步骤 S48: 去除第二光刻胶层。
该步骤中各具体子步骤的图示可参考图 5A- 5H中形成包括栅 极的图形的过程剖视图， 这里略去相应附图。
在该步骤中， 采用沉积、 溅射或热蒸发的方法形成源漏预形 成层膜或源漏金属层膜。 源漏预形成层膜采用无机材料形成， 无 机材料包括氮化硅、 氧化硅或氮氧化硅。 源极 7和漏极 8的厚度 与源漏预形成层 9 的厚度相同。 此外， 第一光刻胶层中光刻胶的 曝光性质与第二光刻胶层中光刻胶的曝光性质相反。
同样， 在源漏预形成层 9形成后， 可以采用熔融灌注方式将 源极 7和漏极 8形成在源极嵌入槽和漏极嵌入槽中， 则可相应省 略步骤 S45至步骤 S48 , 采用该方式形成的源极 7和漏极 8 , 厚度 可以制的更薄、 平坦度更好。
至此， 薄膜晶体管即制备完成。
图 2和图 3中薄膜晶体管的制备方法可参考上述图 4中薄膜 晶体管的制备方法的具体步骤（图 5A至图 5H ) , 这里不再赘述。
本实施例中， 在基板上形成栅极之前， 先形成栅极预形成层， 并通过曝光、 显影和刻蚀形成容纳和固定栅极所需要的栅极嵌入 槽； 再形成与栅极预形成层同样厚度的栅极， 得到完全填充到栅 极嵌入槽内的栅极。 在此情况下， 在形成栅极图形的工艺中， 即 使在刻蚀步骤结束后， 仍然可能存在栅极表面不平整或图形突变 处存在缺陷的情况， 但后续膜层的形成也不会进一步加剧缺陷。 例如， 如图 6 所示， 当过刻量较小或曝光时掩模板（mask ) 图案 覆盖面积较大时， 会在刻蚀边缘处生成一些凸起（缺陷 15 ) , 该 凸起的高度远小于栅极的厚度， 随着薄膜晶体管中后续膜层的形 成， 该凸起逐渐变緩， 并且由于该凸起不处在其他层的边缘处， 不会因该凸起而产生漏电的可能。 又如图 7 所示， 当过刻量较大 或曝光时掩模板图案覆盖面积较小时， 会在刻蚀边缘处生成一些 凹陷 （缺陷 15 ) , 该凹陷的深度远小于栅极的厚度， 随着薄膜晶 体管中后续膜层的形成， 该凹陷逐渐变緩， 并且由于该凹陷不处 在其他层的边缘处， 也不会因该凹陷而产生漏电的可能。 因此， 本实施例中的栅极与现有技术中的栅极相比， 能有效解决现有技 术中因图形突变处出现缺陷而引起漏电的问题。 同样， 本实施例 中的源极和漏极与现有技术中的源极和漏极相比， 能有效解决现 有技术中因图形突变处出现缺陷而引起漏电的问题
此外， 由于采用同一掩模板形成栅极预形成层与栅极， 并且 采用同一掩模板形成源漏预形成层与源极 /漏极， 在不增加掩模数 量的基础上， 仅分别各增加一次曝光、 显影工艺来形成相应的栅 极预形成层或源漏预形成层， 上述方案能够达到有效地防止薄膜 晶体管中金属电极连接的效果。
[实施例 2]
本实施例与实施例 1的区别在于， 本实施例中的薄膜晶体管 为顶栅型结构。
在本实施例中， 薄膜晶体管为顶栅型结构， 即源极和漏极设 置在基板上， 栅极设置在源极和漏极的上方。 具体地， 基板上依 次设置有源极和漏极、 有源层、 栅绝缘层、 栅极。 根据栅极与源 极和漏极具体形成工艺的不同， 参考实施例 1 ,本实施例中的薄膜 晶体管具体包括如下三种结构。
如图 8所示， 在薄膜晶体管中， 源漏预形成层 9与源极 7和 漏极 8形成在基板 1上， 在源漏预形成层 9的用于形成源极的区 域中开设有源极嵌入槽， 在源漏预形成层 9 的用于形成漏极的区 域开设有漏极嵌入槽， 源极 7设置在源极嵌入槽中， 漏极 8设置 在漏极嵌入槽中。源极 7和漏极 8的上方分别依次设置有有源层 5、 栅绝缘层 4和栅极 2。
另外， 在薄膜晶体管中， 源极 7和漏极 8形成在基板 1上， 源极 7和漏极 8的上方分别依次设置有有源层 5、 栅绝缘层 4 , 在 栅极预形成层 3 的用于形成栅极的区域中开设有栅极嵌入槽， 栅 极 2设置在栅极嵌入槽内。
另外， 在薄膜晶体管中， 源漏预形成层 9与源极 7和漏极 8 形成在基板 1上， 在源漏预形成层 9的用于形成源极的区域中开 设有源极嵌入槽， 在源漏预形成层 9 的用于形成漏极的区域开设 有漏极嵌入槽， 源极 7设置在源极嵌入槽中， 漏极 8设置在漏极 嵌入槽中。 源极 7和漏极 8的上方分别依次设置有有源层 5、栅绝 缘层 4 ,在栅极预形成层 3的用于形成栅极的区域中开设有栅极嵌 入槽， 栅极 2设置在栅极嵌入槽内。
在上述薄膜晶体管结构中， 栅极预形成层 3与源漏预形成层 9均采用无机材料形成，无机材料包括氮化硅、氧化硅或氮氧化硅。 栅极 2的厚度可以与栅极预形成层 3的厚度相同，源极 7和漏极 8 的厚度可以与源漏预形成层 9的厚度相同。
本实施例的薄膜晶体管中各膜层的材料与实施例 1相同， 具 体的制备方法也可参考实施例 1 , 这里不再赘述。
[实施例 3]
本实施例提供一种阵列基板， 该阵列基板包括实施例 1 中的 薄膜晶体管。
本实施例的阵列基板包括栅线、 数据线以及设置在由栅线与 数据线交叉形成的像素区内的薄膜晶体管， 薄膜晶体管采用实施 例 1中的底栅型的薄膜晶体管。
在本实施例中， 栅极预形成层还可以延伸至像素区的对应于 薄膜晶体管的区域以外的其他区域， 栅线与栅极同层设置、 且与 栅极电连接。 此外， 源漏预形成层还可以延伸至像素区的对应于 薄膜晶体管的区域以外的其他区域， 数据线与源极同层设置、 且 与源极电连接。
具体的， 在本实施例的阵列基板中， 在栅极预形成层的用于 形成栅线的区域中开设有栅线嵌入槽， 栅线设置在栅线嵌入槽中。 此外， 在源漏预形成层的用于形成数据线的区域中开设有数据线 嵌入槽， 数据线设置在数据线嵌入槽中。 栅线的厚度与栅极的厚 度相等， 数据线的厚度与源极的厚度相等。
如图 9所示，本实施例中的阵列基板包括上述的薄膜晶体管， 还包括钝化层 10以及像素电极 11 , 钝化层 10设置在源极 7与漏 极 8的上方， 在钝化层 10的对应于漏极 8的区域中开设有过孔， 钝化层 10采用硅氧化物、 硅氮化物、 铪氧化物或铝氧化物形成。
像素电极 11设置在钝化层 10上方， 漏极 8通过过孔与像素 电极 11连接， 像素电极 11采用氧化铟镓锌、 氧化铟锌、 氧化铟 锡或氧化铟镓锡形成。
需要说明的是， 上述设置有像素电极的阵列基板， 可以用于 形成 TN ( Twi s ted Nemat ic, 扭曲向列）模式的液晶显示装置、 VA ( Vert ica l Al ignment , 垂直取向）模式的液晶显示装置。 可替 代地， 继续在上述阵列基板的基础上设置公共电极， 以形成 ADS ( ADvanced Super Dimens ion Swi tch, 高级超维场转换技术）模 式的液晶显示装置。 可替代地， 在上述阵列基板中的用于形成像 素电极的区域形成 OLED ( Organic Light-Emi t t ing Diode,有机发 光二极管） 的金属阳极， 以形成 AM0LED ( Act ive Matr ix Organic Light Emi s s ion Di splay, 有源矩阵驱动式有机发光显示装置） 。
相应的， 上述阵列基板的制备方法包括实施例 1 中薄膜晶体 管的制备方法， 还可以包括： 将栅极预形成层延伸至像素区的对 应于薄膜晶体管的区域以外的其他区域， 使得栅线与栅极同层形 成、 且与栅极电连接， 或者还可以包括： 将源漏预形成层延伸至 像素区的对应于薄膜晶体管的区域以外的其他区域， 使得数据线 与源极同层形成、 且与源极电连接。 简言之， 在栅极预形成层的用于形成栅线的区域中形成栅线 嵌入槽， 将栅线形成在栅线嵌入槽中。 此外， 在源漏预形成层的 用于形成数据线的区域中形成数据线嵌入槽， 将数据线形成在数 据线嵌入槽中。 栅线的厚度与栅极的厚度相等， 数据线的厚度与 源极的厚度相等。
具体的， 在实施例 1 中已经制备完成薄膜晶体管， 并预先形 成了栅极扫描线和数据线的基础上， 还进一步包括以下步骤 S5和 步骤 S6。
步骤 S5 : 在源极 7、 漏极 8上形成包括钝化层 10以及过孔的 图形。
在该步骤中， 在完成步骤 S4的基板 1上形成钝化层膜（PVX Depos i t ion ) , 可利用普通掩模板通过一次构图工艺在源极 7、 漏 极 8上形成包括钝化层 10的图形， 并采用刻蚀方式在钝化层 10 中形成包括过孔的图形。 采用沉积、 溅射或热蒸发的方法形成钝 化层膜。
步骤 S6 : 在钝化层 10上方形成包括像素电极 11的图形， 漏 极 8通过过孔与像素电极 11连接。
在该步骤中， 在完成步骤 S5的基板 1上形成透明导电膜， 可 利用普通掩模板通过一次构图工艺在钝化层 10上方形成包括像素 电极 11的图形， 漏极 8通过过孔与像素电极 11连接。 采用沉积、 溅射或热蒸发的方法形成透明导电膜。
本实施例的阵列基板中， 栅线与栅极同时形成， 数据线与源 极 /漏极同时形成， 栅线嵌入槽与栅极嵌入槽同时形成， 数据线嵌 入槽与源极嵌入槽和漏极嵌入槽同时形成， 从而在不增加掩模数 量的基础上， 就能达到有效地防止漏电的效果。
[实施例 4]
本实施例提供一种阵列基板， 该阵列基板包括实施例 2 中的 薄膜晶体管。
本实施例的阵列基板包括栅线、 数据线以及设置在由栅线与 数据线交叉形成的像素区内的薄膜晶体管， 薄膜晶体管采用实施 例 2中的顶栅型的薄膜晶体管。
在本实施例中， 栅极预形成层还可以延伸至像素区的对应于 薄膜晶体管的区域以外的其他区域， 栅线与栅极同层设置、 且与 栅极电连接。 此外， 源漏预形成层还可以延伸至像素区的对应于 薄膜晶体管的区域以外的其他区域， 数据线与源极同层设置、 且 与源极电连接。
具体的， 在本实施例的阵列基板中， 在栅极预形成层的用于 形成栅线的区域中开设有栅线嵌入槽， 栅线设置在栅线嵌入槽中。 此外， 在源漏预形成层的用于形成数据线的区域中开设有数据线 嵌入槽， 数据线设置在数据线嵌入槽中。 栅线的厚度与栅极的厚 度相等， 数据线的厚度与源极的厚度相等。
本实施例的阵列基板的其他结构与实施例 3相同， 具体的制 备方法也可参考实施例 3 , 这里不再赘述。
[实施例 5]
本实施例提供一种显示装置，包括实施例 3、 4中的阵列基板。 该显示装置可以为： 液晶面板、 电子纸、 0LED面板、 手机、 平板 电脑、 电视机、 显示器、 笔记本电脑、 数码相框、 导航仪等任何 具有显示功能的产品或部件。
本实施例中， 由于其中采用的阵列基板具有有效地防止漏电 的效果， 使得该显示装置具有良好的稳定性和较好的显示品质。
在本发明的薄膜晶体管的制备过程中， 先将无机材料形成在 基板上， 通过曝光、 显影、 刻蚀形成与栅极图形相对应的沟槽； 然后形成栅极， 并使得栅极的厚度与沟槽的深度一致， 以形成栅 极金属材料填充至沟槽中的完整图形； 然后再形成薄膜晶体管的 其他膜层。 此外， 也可以使源极和漏极具有与栅极类似的层结构。 这种结构能够有效减緩栅极或源极和漏极因斜坡处的刻蚀缺陷所 带来的负面效果， 有效解决涉及栅极金属层膜、 源漏金属层膜在 沉积和刻蚀时发生不期望的缺陷的技术问题， 能够从根本上杜绝 后续膜层的不连续的可能， 提高显示装置的品质。
相应的， 在本发明的采用上述薄膜晶体管的阵列基板中， 将 与栅极连接的栅线、 与源极连接的数据线也形成在无机材料层中， 在后续膜层的增加过程中使各导电膜层实现边缘斜坡面积的减 小， 能有效减緩栅线、 数据线因斜坡处的缺陷所带来的负面效果， 在像素逐步精细化的大背景下， 使得显示装置获得完美的显示屏 成为可能。
本发明所提供的薄膜晶体管结构和相应的制备方法， 可以推 广至各种较多膜层的半导体器件结构和制备方法中， 其核心在于 通过其他材料先形成待成型的半导体器件图形的沟槽， 再在沟槽 中填充形成半导体器件图形的材料， 这种制备方法无须增加掩模 数量， 但能减少后续膜层受前续膜层中存在的斜坡不完整的影响， 能有效避免半导体器件出现漏电的可能。
可以理解的是， 以上实施方式仅仅是为了说明本发明的原理 而采用的示例性实施方式， 然而本发明并不局限于此。 对于本领 域内的普通技术人员而言， 在不脱离本发明的精神和实质的情况 下， 可以做出各种变型和改进， 这些变型和改进也视为本发明的 保护范围。

Claims

1. 一种薄膜晶体管， 包括基板以及设置于所述基板上的栅 极、 有源层、 同层设置的源极和漏极、 以及设置于所述栅极与所 述源极和所述漏极之间的绝缘层， 其特征在于，
与所述栅极同层设置有栅极预形成层， 所述栅极形成在所述 栅极预形成层中； 以及 /或者
与所述源极和所述漏极同层设置有源漏预形成层， 所述源极 和所述漏极形成在所述源漏预形成层中。
2. 根据权利要求 1所述的薄膜晶体管， 其特征在于， 所述栅 极设置在所述基板上， 所述源极和所述漏极设置在所述栅极的上 方； 极嵌入槽， 所述栅极设置在所述栅极嵌入槽内； 以及 /或者
在所述源漏预形成层的用于形成所述源极的区域中开设有源 极嵌入槽， 在所述源漏预形成层的用于形成所述漏极的区域中开 设有漏极嵌入槽， 所述源极设置在所述源极嵌入槽中， 所述漏极 设置在所述漏极嵌入槽中。
3. 根据权利要求 1所述的薄膜晶体管， 其特征在于， 所述源 极和所述漏极设置在所述基板上， 所述栅极设置在所述源极和所 述漏极的上方；
在所述源漏预形成层的用于形成所述源极的区域中开设有源 极嵌入槽， 在所述源漏预形成层的用于形成所述漏极的区域中开 设有漏极嵌入槽， 所述源极设置在所述源极嵌入槽中， 所述漏极 设置在所述漏极嵌入槽中； 以及 /或者
4. 根据权利要求 2或 3所述的薄膜晶体管， 其特征在于， 所 无机材料包括氮化硅、 氧化硅或氮氧化硅。
5. 根据权利要求 4所述的薄膜晶体管， 其特征在于， 所述栅 极的厚度与所述栅极预形成层的厚度相同， 所述源极和所述漏极 的厚度与所述源漏预形成层的厚度相同。
6. 根据权利要求 5所述的薄膜晶体管， 其特征在于， 所述有 源层设置在所述绝缘层与所述源极和所述漏极之间， 且所述有源 层分别与所述源极和所述漏极在正投影方向上至少部分重叠， 所 述有源层采用非晶硅材料形成， 或者采用氧化铟镓锌、 氧化铟锌、 氧化铟锡或氧化铟镓锡形成。
7. 一种阵列基板， 包括栅线、数据线以及设置在由所述栅线 与所述数据线交叉形成的像素区内的薄膜晶体管， 其特征在于， 所述薄膜晶体管采用权利要求 1至 6中任一项所述的薄膜晶体管。
8. 根据权利要求 7所述的阵列基板， 其特征在于， 所述栅极 预形成层还延伸至所述像素区的对应于所述薄膜晶体管的区域以 外的其他区域， 所述栅线与所述栅极同层设置、 且与所述栅极电 连接； 以及 /或者
所述源漏预形成层还延伸至所述像素区的对应于所述薄膜晶 体管的区域以外的其他区域， 所述数据线与所述源极同层设置、 且与所述源极电连接。
9. 根据权利要求 8所述的阵列基板， 其特征在于， 在所述栅 极预形成层的用于形成栅线的区域中开设有栅线嵌入槽， 所述栅 线设置在所述栅线嵌入槽中； 以及 /或者
在所述源漏预形成层的用于形成数据线的区域中开设有数据 线嵌入槽， 所述数据线设置在所述数据线嵌入槽中。
10. 根据权利要求 9所述的阵列基板， 其特征在于， 所述栅 线的厚度与所述栅极的厚度相等， 所述数据线的厚度与所述源极 的厚度相等。
11. 一种显示装置， 其特征在于， 包括权利要求 7至 10中任 一项所述的阵列基板。
12. 一种薄膜晶体管的制备方法， 包括在基板上形成栅极、 形成有源层、 形成源极和漏极以及形成所述栅极与所述源极和所 述漏极之间的栅绝缘层的步骤， 其特征在于， 还包括：
形成与所述栅极同层的栅极预形成层， 并将所述栅极形成在 所述栅极预形成层中的步骤； 以及 /或者
形成与所述源极和所述漏极同层的源漏预形成层， 并将所述 源极和所述漏极形成在所述源漏预形成层中的步骤。
13. 根据权利要求 12所述的制备方法， 其特征在于， 在形成 所述栅极之前， 先形成包括栅极预形成层以及开设在所述栅极预 形成层中的栅极嵌入槽的图形； 然后， 在所述栅极嵌入槽内形成 包括所述栅极的图形； 以及 /或者
在形成所述源极和所述漏极之前， 先形成包括源漏预形成层 以及开设在所述源漏预形成层中的源极嵌入槽和漏极嵌入槽的图 形； 然后， 在所述源极嵌入槽内形成包括所述源极的图形， 以及 在所述漏极嵌入槽内形成包括所述漏极的图形。
14. 根据权利要求 13所述的制备方法， 其特征在于， 采用构 图工艺来形成包括所述栅极预形成层以及所述栅极的图形， 并且 采用同一掩模板来形成所述栅极预形成层以及所述栅极； 或者， 采用构图工艺来形成包括所述栅极预形成层的图形， 以及采用熔 融'准: ¾
入槽中； 以及 /或者
采用构图工艺来形成包括所述源漏预形成层以及所述源极和 所述漏极的图形， 并且采用同一掩模板来形成所述源漏预形成层 以及所述源极和所述漏极； 或者， 采用构图工艺来形成包括所述 源漏预形成层的图形， 以及采用熔融灌注方式来将所述源极和所 述漏极分别形成在所述源漏预形成层的所述源极嵌入槽和所述漏 极嵌入槽中。
15. 根据权利要求 14所述的制备方法， 其特征在于， 所述栅 极预形成层与所述源漏预形成层采用无机材料形成， 所述无机材 料包括氮化硅、 氧化硅或氮氧化硅。
16. 根据权利要求 15所述的制备方法， 其特征在于， 所述栅 极的厚度与所述栅极预形成层的厚度相同， 所述源极和所述漏极 的厚度与所述源漏预形成层的厚度相同。
17. 一种阵列基板的制备方法， 包括形成栅线、 数据线以及 形成设置在由所述栅线与所述数据线交叉形成的像素区内的薄膜 晶体管的步骤， 其特征在于， 采用权利要求 12至 16 中任一所述 的薄膜晶体管的制备方法来形成所述薄膜晶体管。
18. 根据权利要求 17所述的制备方法， 其特征在于， 将所述 栅极预形成层延伸至所述像素区的对应于所述薄膜晶体管的区域 以外的其他区域， 使得所述栅线与所述栅极同层形成、 且与所述 栅极电连接； 以及 /或者
将所述源漏预形成层还延伸至所述像素区的对应于所述薄膜 晶体管的区域以外的其他区域， 使得所述数据线与所述源极同层 形成、 且与所述源极电连接。
19. 根据权利要求 18所述的制备方法， 其特征在于， 在所述 将所述栅线形成在所述栅线嵌入槽中； 以及 /或者 据线嵌入槽， 并将所述数据线形成在所述数据线嵌入槽中
20. 根据权利要求 19所述的制备方法， 其特征在于， 所述栅 线的厚度与所述栅极的厚度相等， 所述数据线的厚度与所述源极 的厚度相等。
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