WO2015018316A1 - 预清洗腔室及半导体加工设备 - Google Patents

预清洗腔室及半导体加工设备 Download PDF

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Publication number
WO2015018316A1
WO2015018316A1 PCT/CN2014/083709 CN2014083709W WO2015018316A1 WO 2015018316 A1 WO2015018316 A1 WO 2015018316A1 CN 2014083709 W CN2014083709 W CN 2014083709W WO 2015018316 A1 WO2015018316 A1 WO 2015018316A1
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WIPO (PCT)
Prior art keywords
cleaning chamber
cavity
chamber according
filter plate
top cover
Prior art date
Application number
PCT/CN2014/083709
Other languages
English (en)
French (fr)
Inventor
陈鹏
吕铀
丁培军
杨敬山
边国栋
赵梦欣
余清
李伟
Original Assignee
北京北方微电子基地设备工艺研究中心有限责任公司
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Application filed by 北京北方微电子基地设备工艺研究中心有限责任公司 filed Critical 北京北方微电子基地设备工艺研究中心有限责任公司
Priority to SG11201600633WA priority Critical patent/SG11201600633WA/en
Priority to JP2016532222A priority patent/JP2016531436A/ja
Priority to KR1020167005569A priority patent/KR101780013B1/ko
Publication of WO2015018316A1 publication Critical patent/WO2015018316A1/zh
Priority to US15/012,941 priority patent/US20160148789A1/en

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Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02—Pretreatment of the material to be coated
    • C23C16/0227—Pretreatment of the material to be coated by cleaning or etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
    • H01J37/32853—Hygiene
    • H01J37/32871—Means for trapping or directing unwanted particles
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02—Pretreatment of the material to be coated
    • C23C16/0227—Pretreatment of the material to be coated by cleaning or etching
    • C23C16/0245—Pretreatment of the material to be coated by cleaning or etching by etching with a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32357—Generation remote from the workpiece, e.g. down-stream
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32422—Arrangement for selecting ions or species in the plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32458—Vessel
    • H01J37/32477—Vessel characterised by the means for protecting vessels or internal parts, e.g. coatings
    • H01J37/32495—Means for protecting the vessel against plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32623—Mechanical discharge control means
    • H01J37/32651—Shields, e.g. dark space shields, Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/335—Cleaning

Definitions

  • the present invention relates to the field of semiconductor device manufacturing, and more particularly to a pre-cleaning chamber and a semiconductor processing apparatus. Background technique
  • Semiconductor processing equipment is widely used in today's semiconductor integrated circuits, solar cells, flat panel displays and other manufacturing processes.
  • Semiconductor processing equipment that has been widely used in the industry has the following types: DC discharge type, capacitive coupling (CCP) type, inductive coupling (ICP) type, and electron cyclotron resonance (ECR) type. These types of semiconductor processing equipment are currently used in processes such as deposition, etching, and cleaning.
  • the wafer is first pre-cleaned (Preclean) to remove impurities such as oxides on the surface of the wafer before performing the deposition process.
  • the basic principle of a general pre-cleaning chamber is: a cleaning gas such as argon, helium or hydrogen that is introduced into the cleaning chamber is excited to form a plasma to chemically and physically bombard the wafer, thereby removing the surface of the wafer. Impurities.
  • FIG. 1 is a schematic view showing the structure of a pre-cleaning chamber currently used.
  • the pre-cleaning chamber is formed by a side wall 1, a bottom wall 2, and a top cover 9.
  • a susceptor 4 for carrying a wafer is disposed at the bottom of the pre-cleaning chamber, which is sequentially connected to the first matching unit 7 and the first RF power source 8;
  • the top cover 9 is made of an insulating material such as ceramic or quartz.
  • the arched top cover is provided with a coil 3 above the top cover 9, the coil 3 is a solenoid coil, and the annular outer diameter formed by the winding corresponds to the outer diameter of the side wall 1, and the coil 3 is sequentially matched with the second
  • the device 5 is connected to the second RF power source 6.
  • the second RF power source 6 is turned on to excite the gas in the chamber into a plasma, and at the same time, the first RF power source 8 is turned on to attract ions in the plasma to bombard the impurities on the wafer.
  • Low-k low dielectric
  • the constant) material acts as an interlayer dielectric, and this causes the following problems when performing pre-cleaning, namely:
  • the present invention aims to at least solve one of the technical problems existing in the prior art, and proposes a pre-cleaning chamber and a semiconductor processing apparatus which can filter plasma in a plasma as it moves from above to the direction of the carrier unit.
  • the ions can prevent the ions in the plasma from adversely affecting the Low-k material, thereby improving product performance.
  • a pre-cleaning chamber comprising a cavity, a top cover and a carrying unit, the top cover being disposed at a top end of the cavity, the carrying unit being disposed in an inner space of the cavity An area near the bottom for carrying the wafer, characterized in that an ion filtering unit is disposed above the carrying unit in the cavity, the ion filtering unit being configured to face the plasma from above When the direction of the carrying unit is moved, ions in the plasma are filtered.
  • the ion filter unit includes a filter plate, the filter plate isolates an inner space of the cavity to form an upper sub-cavity and a lower sub-cavity; and a plurality of vent holes are distributed on the filter plate for The upper sub-cavity and the lower sub-cavity are connected, and the maximum diameter of each of the vent holes is not more than twice the thickness of the sheath of the plasma.
  • the ion filter unit comprises N filter plates spaced apart in a vertical direction, N is an integer greater than 1, and the filter plate isolates the inner space of the cavity to form an upper sub-cavity arranged in order from top to bottom.
  • the maximum diameter is no more than twice the thickness of the plasma sheath.
  • vent holes are hooked on the filter plate.
  • vent holes are arranged to be distributed uniformly according to process variations between respective regions of the wafer surface.
  • the distribution density of the vent holes is set based on the process rate.
  • each of the vent holes comprises a through hole, a tapered hole or a stepped hole.
  • each of the vent holes is a through hole, and the through hole has a diameter ranging from 0.2 to 20 mm.
  • each of the vent holes is a tapered hole or a stepped hole, and the tapered hole or the stepped hole has a maximum diameter of not more than 20 mm and a minimum diameter of not less than 0.2 mm.
  • the filter plate is made of an insulating material or a metal whose surface is plated with an insulating material.
  • the thickness of the filter plate ranges from 2 to 50 mm.
  • a heating device is disposed in the carrying unit for heating the wafer.
  • the carrying unit includes an electrostatic chuck for fixing the wafer by electrostatic attraction; the heating device is built in the electrostatic chuck.
  • a protective layer is disposed on the inner surface of the cavity, and the protective layer is made of an insulating material.
  • an inner liner is provided on the inner side of the side wall of the cavity, and the inner liner is made of an insulating material or a metal whose surface is plated with an insulating material.
  • the top cover is arched, and the top cover is made of an insulating material.
  • the top cover is a barrel structure closed at the top end, and the top cover is made of an insulating material.
  • a Faraday shield is disposed on an inner side of the side wall of the barrel top cover,
  • the puller shield is made of a metal material or an insulating material whose surface is plated with a conductive material.
  • the sidewall of the Faraday shield is provided with at least one slit extending through the Faraday shield in the axial direction.
  • the pre-cleaning chamber further includes an inductive coil and a radio frequency matching device and a radio frequency power supply electrically connected thereto, wherein the inductive coil is disposed around a side wall of the top cover, and the inductive coil
  • the number of turns is one or more turns, and the diameters of the plurality of turns are the same, or increase from top to bottom; the RF power source is used to output RF power to the inductor.
  • the present invention also provides a semiconductor processing apparatus including a pre-cleaning chamber which employs the above-described pre-cleaning chamber provided by the present invention.
  • the pre-cleaning chamber provided by the invention is provided with an ion filtering unit disposed above the carrying unit in the cavity, and can be filtered during the pre-cleaning process when the plasma moves from above the ion filtering unit toward the carrying unit.
  • the ions in the plasma, and only the free radicals, atoms and molecules reach the surface of the wafer placed on the carrier unit, so that ions in the plasma can be prevented from adversely affecting the Low-k material on the wafer as an interlayer medium. In turn, product performance can be improved.
  • the plasma does not contain ions after passing through the ion filtering unit, it can reach the surface of the wafer only by particle diffusion, so that it is no longer necessary to apply a bias voltage to the wafer, thereby eliminating the need for a bias power supply and a matching device.
  • the biasing device can further reduce the production cost.
  • the semiconductor processing apparatus provided by the invention can prevent the ions in the plasma from adversely affecting the Low-k material on the wafer as an interlayer medium by using the pre-cleaning chamber provided by the invention, thereby improving product performance. . DRAWINGS
  • Figure 1 is a schematic view showing the structure of a pre-cleaning chamber currently used
  • FIG. 2A is a schematic structural view of a pre-cleaning chamber according to a first embodiment of the present invention
  • Figure 2B is a plan view of the filter plate of Figure 2A;
  • Figure 2C is an axial cross-sectional view of a vent of the filter plate of Figure 2A;
  • FIG. 3 is a schematic structural view of another pre-cleaning chamber according to a first embodiment of the present invention
  • FIG. 4 is a schematic structural view of a pre-cleaning chamber according to a second embodiment of the present invention
  • FIG. 5 is a Faraday shield of FIG. Radial section of the piece.
  • the pre-cleaning chamber includes a cavity 21, a top cover 22, a carrier unit 23, an inductive coil 25, an RF matcher 26, and an RF power source 27.
  • the top cover 22 is disposed at the top end of the cavity 21 and has an arch structure, and the top cover 22 is made of an insulating material, the insulating material includes ceramic or quartz, etc.; the carrying unit 23 is disposed in the inner space of the cavity 21 An area near the bottom for carrying the wafer; an inductor 25 is disposed around the side wall of the top cover 22, and is electrically connected to the RF power source 27 through the RF matching unit 26; the RF power source 27 is used to output RF power to the inductor 25,
  • the plasma is formed by exciting a reaction gas in the space inside the cavity 21, and the frequency of the RF power source 27 includes 400 kHz, 2 MHz, 13.56 MHz, 40 MHz, 60 MHz, or 100 MHz.
  • the ion filter unit includes a filter plate 24 made of an insulating material or made of a metal plated with an insulating material, the insulating material including ceramic or quartz, and the thickness of the filter plate 24.
  • the range is 2 ⁇ 50mm.
  • the filter plate 24 isolates the inner space of the cavity 21 into the upper sub-cavity 211 and the lower sub-cavity 212, and carries The unit 23 is located in the lower sub-cavity 212.
  • the vertical between the filter plate 24 and the carrying unit 23 is 20 mm or more.
  • a plurality of vent holes 241 are disposed on the filter plate 24 for connecting the upper sub-cavity 211 and the lower sub-cavity 212, and a plurality of vent holes 241 can be distributed on the filter plate 24 as shown in FIG. 2B.
  • a non-uniform distribution may also be used.
  • the local distribution density of the vent holes 241 may be appropriately adjusted according to the process variation between the respective regions of the wafer surface to change the position corresponding to each region of the wafer surface. The density of the plasma at the location, thereby improving the homogeneity of the process.
  • the overall distribution density of the vent holes 241 can also be set according to the process rate, that is, when the required process rate is high, the distribution density of the vent holes 241 is appropriately increased, so that the plasma can quickly pass through the vent holes 241; When the process rate is low, the distribution density of the vent holes 241 can be appropriately reduced.
  • each of the vent holes 241 is a through hole having a diameter not larger than twice the thickness of the sheath of the plasma.
  • the diameter of the through hole is in the range of 0.2 to 20 mm.
  • plasma sheath is meant a non-electrically neutral region formed between the boundary of the plasma in the chamber and the wall of the chamber.
  • each vent 241 of the filter plate 24 Since the maximum diameter of each vent 241 is not more than twice the thickness of the sheath of the plasma, the ions in the plasma are caused by the small space in the vent 241.
  • the composite is converted into an atom or the like, so that ions do not exist in the plasma passing through the vent hole 241, but only radicals, atoms, molecules, and the like exist, and these radicals, atoms, and molecules continue after entering the lower sub-cavity 212.
  • the diffusion is downward until the surface of the wafer placed on the carrier unit 23 is reached for etching. Therefore, by means of the filter plate 24, it is possible to "filter" the ions in the plasma, thereby preventing ions in the plasma from adversely affecting the Low-k material on the wafer as an interlayer medium, thereby improving product performance. .
  • a liner 28 is disposed on the inner side of the side wall of the cavity 21, and the inner liner 28 is provided by Made of insulating material or made of metal coated with an insulating material, such as ceramic or quartz.
  • an insulating material such as ceramic or quartz.
  • the carrying unit 23 includes an electrostatic chuck for holding the wafer by electrostatic attraction, and a heating device 29 is disposed in the electrostatic chuck for heating the wafer.
  • the heating means 29 By means of the heating means 29, the activity of the reaction of the plasma with the surface of the wafer can be increased, so that the process rate can be increased.
  • the heating device 29 has a heating temperature of 100 to 500 ° C and a heating time of 5 to 60 s.
  • the carrying unit may also be a base for carrying a wafer, and a heating device 29 is disposed in the base.
  • each of the vent holes 241 is a through hole, but the present invention is not limited thereto.
  • the vent hole may also be a tapered hole, and the diameter of the tapered hole may gradually increase or decrease from top to bottom; the vent hole may also be a stepped hole, and the shape of the stepped hole in the axial section thereof may be ⁇ Use any shape such as "upper and lower fine”, “upper and lower coarse”, “thin intermediate thick” or “thick intermediate thin".
  • the tapered hole or the stepped hole has a maximum diameter of not more than 20 mm and a minimum diameter of not less than 0.2 mm.
  • a through hole of any other structure as the vent hole as long as it can filter ions in the plasma.
  • the ion filtering unit includes a filter plate 24, but the present invention is not limited thereto. In practical applications, as shown in FIG. 3, the ion filtering unit may further include N edges.
  • the filter plates 24 are vertically spaced apart, N is an integer greater than 1, and the filter plate 24 isolates the inner space of the cavity 21 to form an upper sub-cavity 211 and N-1 neutron cavities arranged in order from top to bottom. 213 and the lower sub-cavity 212, preferably, the vertical spacing between the filter plate 24 located at the lowermost layer and the carrying unit 23 is 20 mm or more.
  • each A plurality of vent holes 241 are disposed on the filter plate 24 for communicating adjacent sub-cavities respectively above and below the filter plate 24, and in all of the filter plates 24, at least one of the filter plates 24 is open
  • the maximum diameter of the air holes 241 is not more than twice the thickness of the sheath of the plasma.
  • the filter plate can be fixed in the space inside the cavity by the following method, that is, a flange can be disposed at a corresponding position on the inner side wall of the cavity, under the filter plate.
  • the edge region of the surface is fixedly connected to the upper surface of the flange by means of a lap or threaded connection.
  • the number of turns of the inductor coil may be one or more turns, and the diameter of the multi-turn coil may be the same according to the distribution of the plasma in the upper sub-chamber 211, or The top-down increases in turn.
  • FIG. 4 is a schematic structural view of a pre-cleaning chamber according to a second embodiment of the present invention.
  • the main difference between this embodiment and the first embodiment described above is that the top cover structure of the pre-cleaning chamber is different.
  • Other structures of the second embodiment are the same as those of the first embodiment, and are not described herein again.
  • the top cover 30 is a barrel-like structure having an upper cover 301, and the top cover 30 is made of an insulating material including ceramic or quartz or the like.
  • the so-called barrel structure means that the side wall of the top cover 30 surrounds the circumferentially closed cylinder and the top end thereof is closed by the upper cover 301, i.e., the top cover 30 is shaped like an inverted bucket.
  • the top cover 30 of the barrel structure is easier to process than the top cover of the arch structure, so that the processing cost of the top cover can be reduced, and the manufacturing and use cost of the pre-cleaning chamber can be reduced.
  • a Faraday shield member 31 is provided on the inner side of the side wall of the top cover 30 of the barrel structure, and the Faraday shield member 31 is made of a metal material or an insulating material whose surface is plated with a conductive material including ceramic or quartz. Wait. With the Faraday shield 31, not only The electromagnetic field is shielded to reduce the erosion of the upper sub-chamber 211 by the plasma, to extend the use time of the upper sub-chamber 211, and to easily clean the chamber, thereby reducing the cost of use of the chamber.
  • a slit 311 penetrating the Faraday shield 31 in the axial direction is formed on the side wall of the Faraday shield 31.
  • the Faraday shield 31 is completely disconnected at the position of the slit 311. That is, the Faraday shield 31 is a discontinuous barrel-like structure (that is, the Faraday shield 31 is non-closed in the circumferential direction) to effectively prevent eddy current loss and heat generation of the Faraday shield 31.
  • the present invention also provides a semiconductor processing apparatus including a pre-cleaning chamber which employs the pre-cleaning chamber provided by the above various embodiments of the present invention.
  • the semiconductor processing apparatus provided by the embodiments of the present invention can avoid the adverse effect of ions in the plasma on the Low-k material on the wafer as an interlayer medium by using the pre-cleaning chamber provided by the above various embodiments of the present invention. In turn, product performance can be improved. Exemplary embodiments, however, the invention is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and scope of the invention. These modifications and improvements are also considered to be within the scope of the invention.

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  • Analytical Chemistry (AREA)
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  • Drying Of Semiconductors (AREA)
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  • Cleaning Or Drying Semiconductors (AREA)
  • Chemical Vapour Deposition (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

本发明提供的预清洗腔室及半导体加工设备，包括腔体、顶盖和承载单元，所述顶盖设置在所述腔体的顶端，所述承载单元设置在所述腔体内侧空间中的靠近底部的区域，用以承载晶片；在所述腔体内的所述承载单元的上方设置有离子过滤单元，所述离子过滤单元用于在等离子体自其上方朝向所述承载单元的方向运动时，过滤所述等离子体中的离子。本发明提供的预清洗腔室，其可以在等离子体自其上方朝向所述承载单元的方向运动时，过滤等离子体中的离子，从而可以避免等离子体中的离子对Low-k材料的不良影响，进而可以提高产品性能。

Description

预清洗腔室及半导体加工设备
技术领域
本发明涉及半导体设备制造领域，特别涉及一种预清洗腔室及半导 体加工设备。 背景技术
半导体加工设备广泛用于当今的半导体集成电路、 太阳能电池、 平 板显示器等制造工艺中。产业上已经广泛使用的半导体加工设备有以下 类型： 例如， 直流放电型， 电容耦合 （CCP ) 型， 电感耦合 （ICP ) 型 以及电子回旋共振（ECR )型。 这些类型的半导体加工设备目前被应用 于沉积、 刻蚀以及清洗等工艺。
在进行工艺的过程中，为了提高产品的质量，在实施沉积工艺之前， 首先要对晶片进行预清洗（ Preclean )，以去除晶片表面的氧化物等杂质。 一般的预清洗腔室的基本原理是： 将通入清洗腔室内的诸如氩气、 氦气 或氢气等的清洗气体激发形成等离子体，以对晶片进行化学反应和物理 轰击， 从而去除晶片表面的杂质。
图 1为目前釆用的一种预清洗腔室的结构示意图。 如图 1所示， 该 预清洗腔室由侧壁 1、 底壁 2和顶盖 9形成。 在预清洗腔室的底部设置 有用于承载晶片的基座 4， 其依次与第一匹配器 7和第一射频电源 8连 接； 顶盖 9为釆用绝缘材料（如陶瓷或石英）制成的拱形顶盖， 在顶盖 9的上方设置有线圈 3， 线圈 3为螺线管线圈， 且其缠绕形成的环形外 径与侧壁 1的外径相对应，并且线圈 3依次与第二匹配器 5和第二射频 电源 6连接。 在进行预清洗的过程中， 接通第二射频电源 6， 以将腔室 内的气体激发为等离子体， 同时， 接通第一射频电源 8， 以吸引等离子 体中的离子轰击晶片上的杂质。 在半导体制造工艺中， 随着芯片集成度提高， 互连线宽和导线间距 减小， 电阻和寄生电容增大， 会导致 RC信号延迟增加， 因此， 通常会 釆用 Low-k (低介电常数）材料作为层间介质， 而这在进行预清洗时会 出现以下问题， 即：
由于等离子体中的离子在等离子体的鞘层电压的驱动下会产生一 定的动能， 这使得当离子运动至晶片表面附近时， 会嵌入 Low-k 材料 中， 从而导致 Low-k材料劣化， 进而给产品性能带来了不良影响。 发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提出了一种 预清洗腔室及半导体加工设备，其可以在等离子体自其上方朝向承载单 元的方向运动时， 过滤等离子体中的离子， 从而可以避免等离子体中的 离子对 Low-k材料造成不良影响， 进而可以提高产品性能。
为实现本发明的目的而提供一种预清洗腔室， 包括腔体、 顶盖和承 载单元， 所述顶盖设置在所述腔体的顶端， 所述承载单元设置在所述腔 体内侧空间中的靠近底部的区域， 用以承载晶片， 其特征在于， 在所述 腔体内的所述承载单元的上方设置有离子过滤单元，所述离子过滤单元 用于在等离子体自其上方朝向所述承载单元的方向运动时，过滤所述等 离子体中的离子。
其中， 所述离子过滤单元包括一个过滤板， 所述过滤板将所述腔体 内侧空间隔离形成上子腔体和下子腔体；并且在所述过滤板上分布有多 个通气孔， 用以连通所述上子腔体和下子腔体， 并且， 每个所述通气孔 的最大直径不大于等离子体的鞘层厚度的两倍。
其中， 所述离子过滤单元包括 N个沿竖直方向间隔设置的过滤板， N为大于 1的整数，所述过滤板将所述腔体内侧空间隔离形成由上至下 依次排列的上子腔体、 N-1个中子腔体和下子腔体； 并且在每个所述过 滤板上分布有多个通气孔，用以连通分别位于该过滤板的上方和下方且 与该过滤板相邻的子腔体， 并且， 在所有过滤板中， 其中至少一个过滤 板的通气孔的最大直径不大于等离子体的鞘层厚度的两倍。
其中， 所述通气孔在所述过滤板上均勾分布。
其中，所述通气孔被设置成根据晶片表面的各个区域之间的工艺偏 差而非均匀地分布。
其中， 所述通气孔的分布密度基于工艺速率而被设定。
其中， 每个所述通气孔包括直通孔、 锥形孔或者阶梯孔。
优选地， 每个所述通气孔为直通孔， 并且所述直通孔的直径范围在 0.2~20mm。
优选地， 每个所述通气孔为锥形孔或阶梯孔， 并且所述锥形孔或阶 梯孔的最大直径不大于 20mm， 且最小直径不小于 0.2mm。
其中，所述过滤板由绝缘材料制成或者由表面镀有绝缘材料的金属 制成。
其中， 所述过滤板的厚度范围在 2~50mm。
其中， 在所述承载单元内设置有加热装置， 用以加热晶片。
其中， 所述承载单元包括静电卡盘， 用以釆用静电引力的方式固定 晶片； 所述加热装置内置在所述静电卡盘中。
其中， 在所述腔体的内表面上设置有保护层， 所述保护层釆用绝缘 材料制作。
其中， 在所述腔体的侧壁的内侧设置有内衬， 所述内衬由绝缘材料 制成或者由表面镀有绝缘材料的金属制成。
其中， 所述顶盖釆用拱形结构， 并且所述顶盖由绝缘材料制成。 其中， 所述顶盖釆用顶端封闭的桶状结构， 并且所述顶盖由绝缘材 料制成。
其中， 在所述桶状顶盖的侧壁的内侧设置有法拉第屏蔽件， 所述法 拉第屏蔽件由金属材料制成或者由表面镀有导电材料的绝缘材料制成。 其中，所述法拉第屏蔽件的侧壁上开设有至少一个沿轴向方向贯穿 该法拉第屏蔽件的开缝。
其中，所述预清洗腔室还包括电感线圈和与之依次电连接的射频匹 配器及射频电源，其中，所述电感线圈在所述顶盖的侧壁外侧环绕设置， 并且所述电感线圈的匝数为一匝或多匝， 且多匝线圈的直径相同， 或者 由上而下依次增大； 所述射频电源用于向所述电感线圈输出射频功率。
作为另一个技术方案， 本发明还提供一种半导体加工设备， 包括预 清洗腔室， 该预清洗腔室釆用了本发明提供的上述预清洗腔室。
本发明具有以下有益效果：
本发明提供的预清洗腔室，其通过在腔体内的承载单元上方设置离 子过滤单元， 可以在进行预清洗的过程中， 在等离子体自该离子过滤单 元上方朝向承载单元的方向运动时， 过滤等离子体中的离子， 并仅使自 由基、原子和分子到达置于承载单元上的晶片表面， 从而可以避免等离 子体中的离子对晶片上的作为层间介质的 Low-k 材料产生不良影响， 进而可以提高产品性能。 而且， 由于等离子体经过离子过滤单元后不再 含有离子， 因而其仅依靠粒子扩散即可到达晶片的表面， 这样， 则无需 再对晶片加载偏压， 因而可以省去偏压电源和匹配器等的偏压装置， 进 而可以降低生产成本。
本发明提供的半导体加工设备，其通过釆用本发明提供的预清洗腔 室， 可以避免等离子体中的离子对晶片上的作为层间介质的 Low-k 材 料造成不良影响， 进而可以提高产品性能。 附图说明
图 1为目前釆用的一种预清洗腔室的结构示意图；
图 2A为本发明第一实施例提供的一种预清洗腔室的结构示意图； 图 2B为图 2A中过滤板的俯视图；
图 2C为图 2A中过滤板的一个通气孔的轴向剖视图；
图 3为本发明第一实施例提供的另一种预清洗腔室的结构示意图； 图 4为本发明第二实施例提供的预清洗腔室的结构示意图； 以及 图 5为图 4中法拉第屏蔽件的径向截面图。 具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附 图来对本发明提供的预清洗腔室及半导体加工设备进行详细描述。
图 2A为本发明第一实施例提供的一种预清洗腔室的结构示意图。 请参阅图 2A， 预清洗腔室包括腔体 21、 顶盖 22、 承载单元 23、 电感 线圈 25、 射频匹配器 26和射频电源 27。 其中， 顶盖 22设置在腔体 21 的顶端， 且釆用拱形结构， 并且顶盖 22由绝缘材料制成， 绝缘材料包 括陶瓷或石英等；承载单元 23设置在腔体 21 内侧空间中的靠近底部的 区域， 用以承载晶片； 电感线圈 25在顶盖 22的侧壁外侧环绕设置， 且 通过射频匹配器 26与射频电源 27电连接； 射频电源 27用于向电感线 圈 25输出射频功率，以激发腔体 21内侧空间的反应气体形成等离子体， 射频电源 27的频率包括 400KHz、 2MHz、 13.56 MHz , 40 MHz , 60MHz 或 100 MHz。
而且， 在腔体 21 内的承载单元 23上方设置有离子过滤单元， 离子 过滤单元用于在等离子体自离子过滤单元的上方朝向承载单元的方向 运动时， 过滤等离子体中的离子。 下面对离子过滤单元的结构和功能进 行详细描述。 具体地， 在本实施例中， 离子过滤单元包括一个过滤板 24 , 其由绝缘材料制成或者由表面镀有绝缘材料的金属制成， 绝缘材料 包括陶瓷或石英等， 且过滤板 24的厚度范围在 2~50mm。 而且， 过滤 板 24将腔体 21内侧空间隔离形成上子腔体 211和下子腔体 212， 承载 单元 23位于下子腔体 212内， 优选地， 过滤板 24与承载单元 23的竖 直间 巨为 20mm以上。
在过滤板 24上分布有多个通气孔 241， 用以连通上子腔体 211和 下子腔体 212， 并且， 多个通气孔 241可以在过滤板 24上均勾分布， 如图 2B所示。 在实际应用中， 也可以釆用非均匀分布的形式， 例如， 根据晶片表面的各个区域之间的工艺偏差适当调整通气孔 241 的局部 分布密度，以改变与晶片表面的各个区域相对应的位置处的等离子体的 密度， 从而提高工艺均勾性。 另外， 还可以根据工艺速率设定通气孔 241的整体分布密度， 即： 当所要求的工艺速率较高时， 适当增大通气 孔 241的分布密度， 以使等离子体能够快速通过通气孔 241 ; 当所要求 的工艺速率较低时， 则可以适当减小通气孔 241的分布密度。
在本实施例中， 每个通气孔 241为直通孔， 且直径不大于等离子体 的鞘层厚度的两倍， 优选地， 直通孔的直径范围在 0.2~20mm。 所谓等 离子体鞘层，是指在腔室中的等离子体的边界与腔室壁之间形成的非电 中性区域。 在进行预清洗的过程中， 射频电源 27向电感线圈 25输出射 频功率， 以在上子腔体 211 内形成等离子体， 并朝向承载单元 23扩散。 当等离子体经过过滤板 24的通气孔 241时， 由于每个通气孔 241的最 大直径不大于等离子体的鞘层厚度的两倍，这使得等离子体中的离子会 因通气孔 241 内的空间狭小而复合转化为原子等形态，从而穿过通气孔 241的等离子体中不会存在离子， 而仅存在自由基、 原子和分子等， 这 些自由基、原子和分子在进入下子腔体 212后会继续向下扩散， 直至到 达置于承载单元 23上的晶片表面进行刻蚀。 因此， 借助过滤板 24， 可 以起到 "过滤" 等离子体中的离子的作用， 从而可以避免等离子体中的 离子对晶片上作为层间介质的 Low-k 材料产生不良影响， 进而可以提 高产品性能。
在本实施例中， 在腔体 21 的侧壁内侧设置有内衬 28， 内衬 28 由 绝缘材料制成或者由表面镀有绝缘材料的金属制成，绝缘材料包括陶瓷 或石英等。 借助内衬 28， 不仅可以保护腔体 21的侧壁不被等离子体刻 蚀， 从而可以提高腔体 21的使用寿命和可维护性， 而且还可以调节等 离子体中的自由基的活性。 在实际应用中， 也可以在腔体 21 的内表面 上设置由绝缘材料制作的保护层， 例如， 可以对腔体 21 的内表面进行 氧化处理。
在本实施例中， 承载单元 23 包括静电卡盘， 用以釆用静电引力的 方式固定晶片， 并且， 在静电卡盘内设置有加热装置 29， 用以加热晶 片。 借助加热装置 29， 可以提高等离子体与晶片表面反应的活性， 从 而可以提高工艺速率。 优选地， 加热装置 29的加热温度在 100~500 °C， 加热时间为 5~60s。 在实际应用中， 承载单元也可以是用于承载晶片的 基座， 且在该基座内设置加热装置 29。
需要说明的是， 在本实施例中， 每个通气孔 241为直通孔， 但是本 发明并不局限于此， 在实际应用中， 如图 2C所示， 为单个通气孔的剖 面图。 通气孔也可以为锥形孔， 且该锥形孔的直径可以由上而下逐渐增 大或减小； 通气孔还可以为阶梯孔， 且该阶梯孔在其轴向截面上的形状 可以釆用 "上粗下细"、 "上细下粗"、 "两端细中间粗" 或者 "两端粗中 间细" 等的任意形状。 优选地， 上述锥形孔或阶梯孔的最大直径不大于 20mm, 且最小直径不小于 0.2mm。 当然， 还可以釆用其他任意结构的 通孔作为通气孔， 只要其能够过滤等离子体中的离子即可。
还需要说明的是， 在本实施例中， 离子过滤单元包括一个过滤板 24 , 但是本发明并不局限于此， 在实际应用中， 如图 3所示， 离子过滤 单元还可以包括 N个沿竖直方向间隔设置的过滤板 24， N为大于 1的 整数，过滤板 24将腔体 21的内侧空间隔离形成由上至下依次排列的上 子腔体 211、 N-1个中子腔体 213和下子腔体 212， 优选地， 位于最下 层的过滤板 24与承载单元 23的竖直间距为 20mm以上。 而且， 在每个 过滤板 24上分布有多个通气孔 241， 用以连通分别位于该过滤板 24的 上方和下方且相邻的子腔体， 并且， 在所有过滤板 24中， 其中至少一 个过滤板 24的通气孔 241的最大直径不大于等离子体的鞘层厚度的两 倍。 在釆用多个过滤板 24时， 可以在保证能够过滤等离子体中的离子 的前提下， 适当减小各个过滤板 24的厚度。
进一步需要说明的是， 在实际应用中， 过滤板可以釆用下述方法固 定在腔体内侧的空间中， 即： 可以在腔体的内侧壁上的相应的位置处设 置凸缘，过滤板下表面的边缘区域釆用搭接或螺纹连接的方式与凸缘的 上表面固定连接。
进一步需要说明的是， 在实际应用中， 电感线圈的匝数可以为一匝 或多匝， 且可以根据等离子体在上子腔室 211 内的分布情况， 使多匝线 圈的直径相同， 或者由上而下依次增大。
图 4为本发明第二实施例提供的预清洗腔室的结构示意图。请参阅 图 4， 本实施例与上述第一实施例相比， 其主要区别在于： 预清洗腔室 的顶盖结构不同。除此之外，第二实施例的其它结构与第一实施例相同， 这里不再赘述。
下面对本实施例提供的预清洗腔室的顶盖进行详细描述。 具体地， 顶盖 30釆用具有上盖 301的桶状结构， 并且顶盖 30由绝缘材料制成， 绝缘材料包括陶瓷或石英等。 所谓桶状结构是指该顶盖 30的侧壁环绕 成周向闭合的圓筒且其顶端被上盖 301封闭， 即该顶盖 30的形状类似 于一个倒扣的水桶。 桶状结构的顶盖 30与拱形结构的顶盖相比， 更易 于加工， 从而可以降低顶盖的加工成本， 进而可以降低预清洗腔室的制 造和使用成本。
而且，在桶状结构的顶盖 30的侧壁的内侧设置有法拉第屏蔽件 31， 法拉第屏蔽件 31 由金属材料制成或者由表面镀有导电材料的绝缘材料 制成， 绝缘材料包括陶瓷或石英等。 借助法拉第屏蔽件 31， 不仅可以 屏蔽电磁场， 以减小等离子体对上子腔室 211 的侵蚀， 延长上子腔室 211的使用时间， 而且易于清洗腔室， 从而降低腔室的使用成本。 容易 理解， 为了保证法拉第屏蔽件 31处于悬浮电位， 应保证其高度小于顶 盖 30的侧壁高度， 且使其上、 下两端不与上盖 301和腔体 21接触。
优选地， 在法拉第屏蔽件 31 的侧壁上开设有一个沿轴向方向贯穿 该法拉第屏蔽件 31的开缝 311， 如图 5所示， 在开缝 311 的位置处法 拉第屏蔽件 31完全断开，即，法拉第屏蔽件 31为非连续的桶状结构（亦 即法拉第屏蔽件 31 在周向上非闭合）， 以有效地阻止法拉第屏蔽件 31 的涡流损耗和发热。
作为另一个技术方案， 本发明还提供一种半导体加工设备， 其包括 预清洗腔室，该预清洗腔室釆用了本发明上述各个实施例提供的预清洗 腔室。
本发明实施例提供的半导体加工设备，其通过釆用本发明上述各个 实施例提供的预清洗腔室，可以避免等离子体中的离子对晶片上作为层 间介质的 Low-k材料的不良影响， 进而可以提高产品性能。 的示例性实施方式， 然而本发明并不局限于此。 对于本领域内的普通技 术人员而言， 在不脱离本发明的精神和实质的情况下， 可以做出各种变 型和改进， 这些变型和改进也视为本发明的保护范围。

Claims

要 求 书
1. 一种预清洗腔室， 包括腔体、 顶盖和承载单元， 所述顶盖设置在所 述腔体的顶端， 所述承载单元设置在所述腔体内侧空间中的靠近底部的区 域， 用以承载晶片， 其特征在于， 在所述腔体内的所述承载单元的上方设置 有离子过滤单元，所述离子过滤单元用于在等离子体自其上方朝向所述承载 单元的方向运动时， 过滤所述等离子体中的离子。
2. 根据权利要求 1 所述的预清洗腔室， 其特征在于， 所述离子过滤单 元包括一个过滤板，所述过滤板将所述腔体内侧空间隔离形成上子腔体和下 子腔体； 并且
在所述过滤板上分布有多个通气孔， 用以连通所述上子腔体和下子腔 体， 并且， 每个所述通气孔的最大直径不大于等离子体的鞘层厚度的两倍。
3. 根据权利要求 1 所述的预清洗腔室， 其特征在于， 所述离子过滤单 元包括 N个沿竖直方向间隔设置的过滤板， N为大于 1的整数，所述过滤板 将所述腔体内侧空间隔离形成由上至下依次排列的上子腔体、 N-1个中子腔 体和下子腔体； 并且
在每个所述过滤板上分布有多个通气孔，用以连通分别位于该过滤板的 上方和下方且与该过滤板相邻的子腔体， 并且， 在所有过滤板中， 其中至少 一个过滤板的通气孔的最大直径不大于等离子体的鞘层厚度的两倍。
4. 根据权利要求 2或 3所述的预清洗腔室， 其特征在于， 所述通气孔 在所述过滤板上均匀分布。
5. 根据权利要求 2或 3所述的预清洗腔室， 其特征在于， 所述通气孔 被设置成根据晶片表面的各个区域之间的工艺偏差而非均匀地分布。
6. 根据权利要求 2或 3所述的预清洗腔室， 其特征在于， 所述通气孔 的分布密度基于工艺速率而被设定。
7. 根据权利要求 2或 3所述的预清洗腔室， 其特征在于， 每个所述通 气孔包括直通孔、 锥形孔或者阶梯孔。
8. 根据权利要求 2或 3所述的预清洗腔室， 其特征在于， 每个所述通 气孔为直通孔， 并且所述直通孔的直径范围在 0.2~20mm。
9. 根据权利要求 2或 3所述的预清洗腔室， 其特征在于， 每个所述通 气孔为锥形孔或阶梯孔，并且所述锥形孔或阶梯孔的最大直径不大于 20mm， 且最小直径不小于 0.2mm。
10. 根据权利要求 2或 3所述的预清洗腔室， 其特征在于， 所述过滤板 由绝缘材料制成或者由表面镀有绝缘材料的金属制成。
11. 根据权利要求 2或 3所述的预清洗腔室， 其特征在于， 所述过滤板 的厚度范围在 2~50mm。
12. 根据权利要求 1所述的预清洗腔室， 其特征在于， 在所述承载单元 内设置有加热装置， 用以加热晶片。
13. 根据权利要求 12所述的预清洗腔室， 其特征在于， 所述承载单元 包括静电卡盘， 用以釆用静电引力的方式固定晶片；
所述加热装置内置在所述静电卡盘中。
14. 根据权利要求 1所述的预清洗腔室， 其特征在于， 在所述腔体的内 表面上设置有保护层， 所述保护层釆用绝缘材料制作。
15. 根据权利要求 1或 14所述的预清洗腔室， 其特征在于， 在所述腔 体的侧壁的内侧设置有内衬，所述内衬由绝缘材料制成或者由表面镀有绝缘 材料的金属制成。
16. 根据权利要求 1所述的预清洗腔室， 其特征在于， 所述顶盖釆用拱 形结构， 并且所述顶盖由绝缘材料制成。
17. 根据权利要求 1所述的预清洗腔室， 其特征在于， 所述顶盖釆用顶 端封闭的桶状结构， 并且所述顶盖由绝缘材料制成。
18. 根据权利要求 17所述的预清洗腔室， 其特征在于， 在所述桶状顶 盖的侧壁的内侧设置有法拉第屏蔽件，所述法拉第屏蔽件由金属材料制成或 者由表面镀有导电材料的绝缘材料制成。
19. 根据权利要求 18所述的预清洗腔室， 其特征在于， 所述法拉第屏 蔽件的侧壁上开设有至少一个沿轴向方向贯穿该法拉第屏蔽件的开缝。
20. 根据权利要求 16或 17所述的预清洗腔室， 其特征在于， 所述预清 洗腔室还包括电感线圈和与之依次电连接的射频匹配器及射频电源， 其中 所述电感线圈在所述顶盖的侧壁外侧环绕设置，并且所述电感线圈的匝 数为一匝或多匝， 且多匝线圈的直径相同， 或者由上而下依次增大；
所述射频电源用于向所述电感线圈输出射频功率。
21. 一种半导体加工设备， 包括预清洗腔室， 其特征在于， 所述预清洗 腔室釆用权利要求 1-20任一项所述预清洗腔室。
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