WO2015010416A1 - 阵列基板及其制作方法和显示面板 - Google Patents

阵列基板及其制作方法和显示面板 Download PDF

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Publication number
WO2015010416A1
WO2015010416A1 PCT/CN2013/088839 CN2013088839W WO2015010416A1 WO 2015010416 A1 WO2015010416 A1 WO 2015010416A1 CN 2013088839 W CN2013088839 W CN 2013088839W WO 2015010416 A1 WO2015010416 A1 WO 2015010416A1
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WIPO (PCT)
Prior art keywords
spacer
substrate
layer
base material
array substrate
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Ceased
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PCT/CN2013/088839
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English (en)
French (fr)
Inventor
郭建
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to US14/387,885 priority Critical patent/US9299727B2/en
Publication of WO2015010416A1 publication Critical patent/WO2015010416A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display panel. Background technique
  • liquid crystal display technology has replaced cathode ray tube display technology as the mainstream technology in the field of daily display.
  • ADS Advanced-Super Dimensional Switching
  • the advanced super-dimensional field conversion technology is a planar electric field wide viewing angle core technology.
  • the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer form a multi-dimensional electric field, so that the slit in the liquid crystal cell All the aligned liquid crystal molecules between the electrodes and directly above the electrodes can be rotated, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field conversion technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, push mura, etc. advantage.
  • the technology is widely used in high-end mobile phone screens, mobile applications, and television.
  • the display panel includes a counter substrate 11, an array substrate 12, and a liquid crystal layer 13 disposed between the opposite substrate 11 and the array substrate 12.
  • the opposite substrate 11 is provided with a spacer 110, and the spacer 110 is generally about 2 to 3 ⁇ m in height according to actual needs.
  • the spacer 110 serves to maintain the thickness of the cell and prevent the liquid crystal from being deformed by extrusion and cannot be normally displayed.
  • the spacer is mainly formed by photolithography, and the spacer is coated on the surface of the opposite substrate, and the spacer is formed through exposure and development processes.
  • the spacer photosensitive material In a specific manufacturing process, it is usually required to perform patterning of the spacer photosensitive material through exposure of a gray mask or a semi-transmissive mask, and the main component of the spacer photosensitive material is a resin. Because the hardness of the resin is low, the prepared spacer is easily broken, and the broken spacer can not support, so that the surrounding liquid crystal is deformed by extrusion, and the deformed liquid crystal molecules cannot rotate normally, eventually leading to The display of the LCD monitor is not good enough to even display properly. Summary of the invention
  • an embodiment of the present invention provides a method for fabricating an array substrate, the method comprising: forming a pattern including a scan line and a spacer substrate on a substrate on a substrate; forming a gate insulating layer; a pattern of a source layer, a data line, a source electrode, and a drain electrode; forming a passivation layer; sequentially etching the passivation layer and the gate insulating layer by a dry etching method to form a via hole exposing the spacer substrate, An electric field formed by the spacer substrate exposed in the via hole and an etching gas used in the etching process induces deposition of a substance generated in the etching process of the reaction chamber onto the surface of the spacer substrate to form a spacer. Things.
  • the passivation layer, the active layer, and the gate insulating layer are sequentially etched to form via holes exposing the spacer substrate.
  • the active layer is etched using a first etching gas including sulfur hexafluoride and chlorine.
  • the gate insulating layer and the passivation layer are etched using a second etching gas including hexafluoride, chlorine, and oxygen.
  • the second etching gas further includes helium gas.
  • the temperature in the reaction chamber is 30 ° C ⁇ 50 ° C
  • the pressure is 50 ⁇ 70 Pa
  • the flow rate of sulfur hexafluoride gas in the second etching gas is 50 ⁇ 200 ml per minute sccm
  • the gas flow rate of oxygen For 100 ⁇ 300sccm
  • the gas flow rate of helium is 50 ⁇ 100sccm
  • the gas flow rate of chlorine gas is 10 ⁇ 50sccm
  • the power applied by plasma etching equipment is 5000 ⁇ 9000 watts
  • the growth rate of the spacer is 150 ⁇ 250. Ang / sec.
  • the spacer comprises silicon chloride, which is a reactant of a material for forming a gate insulating layer and a passivation layer and an etching gas.
  • the spacer further includes a metal chloride which is formed by reacting a spacer substrate with an etching gas.
  • the spacer is a column spacer.
  • the spacer substrate is made of the same material as the scanning line.
  • the spacer substrate is disposed in parallel with the scanning line, or the spacer substrate is disposed to intersect the scanning line.
  • inventions of the present invention provide an array substrate.
  • the array substrate includes a substrate substrate, a scan line, a spacer substrate, a gate insulating layer, an active layer, a passivation layer, a spacer, and a via.
  • the spacer substrate is disposed in the same layer as the scan line, and is located above the substrate substrate; the gate insulating layer Located above the spacer substrate and the scan line; the active layer is located above the gate insulating layer; the passivation layer is located above the active layer; the via penetrates the gate insulating layer and is passivated a layer to expose the spacer substrate; the spacer being located inside the via and above the spacer substrate.
  • the via penetrates the gate insulating layer, the active layer, and the passivation layer to expose the spacer substrate.
  • the spacer comprises silicon chloride.
  • the spacer further comprises a metal chloride.
  • the spacer is a column spacer.
  • the spacer substrate is made of the same material as the scanning line.
  • the spacer substrate is disposed in parallel with the scanning line, or the spacer substrate is disposed to intersect the scanning line.
  • an embodiment of the present invention provides a display panel.
  • the display panel includes the above array substrate.
  • FIG. 1 is a schematic structural view of a conventional liquid crystal display panel
  • FIGS. 2 and 3 are schematic views showing the positions of the scanning lines and the spacer substrate
  • FIG. 5 is a schematic structural view of an array substrate after completion of fabrication of a pixel electrode
  • FIG. 6 is a schematic cross-sectional view of an array substrate having a spacer according to an embodiment of the present invention. detailed description
  • the embodiment of the invention provides a method for fabricating an array substrate, and the method includes: Forming a pattern including a scan line and a spacer substrate on the same substrate on the substrate; forming a gate insulating layer;
  • the passivation layer and the gate insulating layer are sequentially etched by dry etching to form vias exposing the spacer substrate, through the exposed spacer substrate in the via and the etching process
  • the electric field formed by the etching gas in the reaction chamber of the etching device is induced to deposit a substance generated in the etching process in the reaction chamber onto the surface of the spacer substrate to form a spacer.
  • the passivation layer, the active layer, and the gate insulating layer are sequentially etched to form via holes exposing the spacer substrate.
  • the active layer is etched using a first etching gas including sulfur hexafluoride and chlorine; using a second etching gas including sulphur hexafluoride, chlorine, and oxygen
  • a first etching gas including sulfur hexafluoride and chlorine
  • a second etching gas including sulphur hexafluoride, chlorine, and oxygen
  • the insulating layer and the passivation layer are etched.
  • the second etching gas further includes helium gas.
  • the spacer substrate is a metal pattern for making a spacer thereon.
  • the metal on the surface of the spacer substrate reacts with the second etching gas to form a metal chloride on the surface of the spacer substrate.
  • the temperature in the reaction chamber is 30 ° C ⁇ 50 ° C
  • the pressure is 50 ⁇ 70 Pa
  • the flow rate of sulfur hexafluoride gas in the second etching gas is 50 ⁇ 200 standard ml / minute (sccm)
  • oxygen The gas flow rate is 100 ⁇ 300sccm
  • the gas flow rate of helium gas is 50 ⁇ 100sccm
  • the gas flow rate of chlorine gas is 10 ⁇ 50sccm
  • the power applied by the plasma etching equipment is 5000 ⁇ 9000 watts
  • the growth rate of the spacer is 150. ⁇ 250 people m/s.
  • a scanning line and a spacer substrate which are parallel to each other are produced, or a scanning line and a spacer substrate which intersect each other are formed.
  • the scan lines and spacer substrates are fabricated using the same process, the same materials.
  • the spacer substrate may be fabricated first, and then the scanning line may be fabricated.
  • the scan line is formed first, and then the spacer substrate is fabricated.
  • the scanning lines and the spacer substrates may be separately formed using different metal materials.
  • the shape of the spacer substrate may be any shape such as a line shape, a square shape, a circular shape, a triangular shape or a polygonal shape, but at least the spacer substrate is required to be located at a position where a spacer is required.
  • the substrate of the village is a glass substrate.
  • the first step S1 deposits a metal layer such as molybdenum (Mo), aluminum (A1) or cadmium (Cr) on the glass substrate 31, and then forms a same layer including the scan line 32 and the spacer substrate by a patterning process.
  • the pattern of the material 33 produces mutually parallel scanning lines 32 and spacer substrates 33 as shown in Fig. 2, or intersecting scanning lines 32 and spacer substrates 33 as shown in Fig. 3. It is to be noted that the position of the resulting spacer substrate 33 corresponds to the position at which the spacer needs to be placed. Meanwhile, in order to obtain the spacer substrate 33 which intersects the scanning line 32, the intersecting position areas should be prevented from overlapping with the position area where the spacers need to be provided, so as not to adversely affect the transmission function of the scanning lines.
  • a second step S2 depositing a silicon nitride (SiN x) or silicon oxide (SiO x) layer is formed on a substrate includes a scanning line 32 and the spacers 33 of the base pad pattern, and then forming a gate patterning process using Insulation layer 34.
  • SiN x silicon nitride
  • SiO x silicon oxide
  • a semiconductor film, a doped semiconductor film, and a source/drain metal film are deposited on the substrate on which the gate insulating layer 34 is formed, using a two-tone mask (for example, a halftone mask or a gray tone mask) at the gate.
  • a two-tone mask for example, a halftone mask or a gray tone mask
  • An active layer 35 (see FIG. 4), a source (not shown) of the array substrate, and a drain (not shown) of the array substrate are formed on the insulating layer 34.
  • a silicon nitride film is deposited on the substrate on which the active layer 35, the source and the drain are formed, and a passivation layer 36 is formed (see FIG. 4); and the passivation layer 36 is patterned.
  • a first via 37 is formed (see Fig. 5).
  • an indium tin oxide (ITO) transparent conductive film is deposited on the passivation layer 36 by magnetron sputtering, and the pixel electrode 60 is formed by a patterning process (see FIG. 5), and the pixel electrode 60 is located in the blunt
  • the first via 37 of the layer 36 is directly connected to the drain of the array substrate.
  • the passivation layer 36 is etched by dry etching to form a second via 38 to expose the spacer substrate.
  • the process includes, for example, etching a passivation layer 36 at a position where a spacer is required by a second etching gas including sulfur hexafluoride, chlorine, and oxygen in a dry etching process.
  • a second etching gas including sulfur hexafluoride, chlorine, and oxygen in a dry etching process.
  • the addition of the second etching gas of 0 2 relative to the first etching gas including sulfur hexafluoride and chlorine gas without containing oxygen (0 2 ) can improve the etching rate and uniformity of SiNx.
  • the second etching gas is converted into the first etching gas, and the active layer 35 is engraved.
  • the eclipse causes the second via 38 to continue to extend downward.
  • the first etching gas is converted into the second etching gas, and the gate insulating layer 34 is etched to make the second via hole 38.
  • the depth continues to be extended until the surface of the spacer substrate 33 is exposed.
  • the second via hole 38 penetrating through the passivation layer 36, the active layer 35, and the gate insulating layer 34 is formed.
  • a ninth step S9 the metal on the surface of the spacer substrate 33 reacts with the second etching gas to form a metal chloride on the surface of the spacer substrate; meanwhile, the spacer exposed through the second via 38 is formed.
  • the substrate forms an electric field with the etching gas in the reaction chamber of the etching device used in the etching process, and induces a substance generated in the etching process in the reaction chamber to deposit on the surface of the spacer substrate, and then grows through the crystal. In a manner, a spacer 39 is produced.
  • the spacer 39 may be a columnar structure, and its constituent material is mainly SiCl 4 , and the SiCl 4 is a reaction material of a gate insulating layer and a passivation layer and an etching gas for etching the second via 38. Further, the constituent material of the spacer 39 further includes a metal chloride which is formed by reacting a metal on the surface of the spacer substrate 33 with an etching gas.
  • the height of the spacer 39 can be controlled according to its growth rate and growth time. The faster the growth rate is, the higher the height of the spacer 39 is for a certain period of time. At a certain growth rate, the longer the growth time, the higher the height of the spacer 39.
  • the growth rate of the spacer 39 is related to the growth environment thereof, and the growth rate of the spacer 39 can be controlled by controlling the temperature, the pressure, and the concentration of the etching gas in the reaction chamber, for example, when in the reaction chamber.
  • the temperature is 30 ° C ⁇ 50 ° C
  • the pressure is 50 ⁇ 70 Pa
  • the flow rate of sulfur hexafluoride gas in the second etching gas is 50 ⁇ 200 sccm
  • the gas flow rate of oxygen is 100 ⁇ 300 sccm
  • the gas flow rate is 50 to 100 sccm
  • the gas flow rate of the chlorine gas is 10 to 50 sccm
  • the power applied by the plasma etching apparatus is 5000 to 9000 watts
  • the growth rate of the spacer 39 is 150 to 250 angstroms/second (A/s) ).
  • the array substrate provided in the embodiment of the present invention has a cross-sectional structure as shown in FIG. 6.
  • the spacer substrate formed by the method has a spacer, and the spacer has the advantages of high hardness, not easy to be broken, and the like, and can effectively solve the display defect caused by the damage of the spacer.
  • the problem is to improve the display effect of the liquid crystal display device.
  • An embodiment of the present invention provides an array substrate, which includes a substrate substrate, a scan line, a spacer substrate, a gate insulating layer, an active layer, a passivation layer, a spacer, and a second via hole.
  • the spacer substrate is disposed in the same layer as the scan line, and is located above the substrate of the substrate;
  • the gate insulating layer is located above the spacer substrate and the scan line;
  • the active layer is located above the gate insulating layer
  • the passivation layer is located above the active layer
  • the second via penetrates the gate insulating layer and the passivation layer to expose the spacer substrate;
  • the spacer is located inside the second via and above the spacer substrate to which the second via is exposed.
  • the second via penetrates the gate insulating layer, the active layer, and the passivation layer to expose the spacer substrate.
  • the composition of the spacer material comprises silicon chloride (SiCl 4), the SiCl 4 reactant is a building material of the passivation layer and the gate insulating layer and the second etching gas.
  • the constituent material of the spacer further includes a metal chloride which is formed by reacting a metal on the surface of the spacer substrate with an etching gas.
  • the spacer is a column spacer, located inside the second via and above the spacer substrate, for supporting, preventing liquid crystal molecules from being deformed by pressing and failing to perform normally. Rotate.
  • the material of the spacer substrate is made of the same material as that of the scanning line.
  • the spacer substrate may be disposed in parallel with the scanning line or may be disposed across the scanning line.
  • the shape of the spacer substrate may be any shape such as a line shape, a square shape, a circular shape, a triangular shape, or a polygonal shape.
  • FIG. 6 is a cross-sectional structural view of an array substrate having a spacer substrate.
  • the array substrate includes: a substrate substrate 31, a spacer substrate 33, a gate insulating layer 34, an active layer 35, a passivation layer 36, a second via 38, and a spacer. 39.
  • the array substrate further includes structures not shown in FIG. 6, such as a scan line, a first via, a gate, a source, a drain, a pixel electrode, and the like.
  • the gate electrode, the scan line, and the spacer substrate 33 are disposed in the same layer, and both are located on the substrate of the substrate.
  • the spacer substrate 33 has a linear shape and may be disposed in parallel with the scanning line, and the two may be disposed to cross each other.
  • the gate electrode of the array substrate, the scanning line, and the spacer substrate 33 are made of the same material, and are a metal such as molybdenum (Mo), (aluminum A1), chromium (Cr), or copper (Cu).
  • the gate insulating layer 34 is located above the gate of the array substrate, the scan line and the spacer substrate 33, and is used for insulating the gate, the scan line and the spacer substrate 33 of the array substrate from other layers.
  • the material to be produced is, for example, silicon nitride (SiN x ) or silicon oxide (SiO x ).
  • the active layer 35 is located above the gate insulating layer 34.
  • the source and drain electrodes of the array substrate are disposed in the same layer, and are all located on the active layer 35 and opposed to each other.
  • the source and the drain of the array substrate are made of a conductive metal such as a single layer of molybdenum (Mo), chromium (Gr) or a double-layered aluminum-bismuth alloy molybdenum (AlNd/Mo).
  • the passivation layer 36 is located above the source and the drain of the array substrate, and is made of the same material as the gate insulating layer 34, such as silicon nitride (SiN x ) or silicon oxide (SiO x ).
  • the pixel electrode is located above the passivation layer 36 and directly connected to the drain of the array substrate through a first via hole in the passivation layer 36.
  • the pixel electrode is made of a transparent conductive material, such as indium tin oxide (ITO). )Wait.
  • the second via 38 penetrates the gate insulating layer 34, the active layer 35, and the passivation layer 36 to expose the spacer substrate 33.
  • the spacer 39 is located inside the second via 38 and above the spacer substrate 33.
  • the spacer 39 is a columnar structure, and its constituent material is mainly silicon chloride (SiCl 4 ), and further includes some metal chlorides, which are metal and surface 2 from the surface of the spacer substrate 33.
  • the etching gas is generated by a reaction.
  • the embodiment of the invention further provides a display panel, wherein the display panel comprises the above array substrate.
  • an embodiment of the present invention provides an array substrate, a method for fabricating the same, and a display panel.
  • the passivation layer, the active layer and the gate insulating layer are sequentially etched by dry etching to form via holes exposing the spacer substrate, and etching to the spacers
  • the metal on the surface of the substrate of the spacer forms an electric field with the gas in the reaction chamber, and under the action of the electric field, the substance generated during the etching is deposited on the surface of the substrate of the spacer to form a spacer.
  • the spacer Compared with the conventional spacer formed of a resin material, the spacer has the advantages of high hardness, non-breaking, and the like, and can ensure that the liquid crystal molecules around it are not subjected to extrusion deformation, so that the liquid crystal molecules can rotate normally, thereby improving the spacer.
  • the spacer is fabricated on the array substrate, and the fabrication process of the opposite substrate is completed.

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Abstract

一种阵列基板及其制作方法和显示面板。所述制作方法包括：在衬底基板（31）上同层形成包括扫描线（32）和隔垫物基材（33）的图形；形成栅绝缘层（34）；形成包括有源层（35）、数据线、源电极和漏电极的图形；形成钝化层（36）；利用干法刻蚀法依次对钝化层（36）和栅绝缘层（34）进行刻蚀以形成暴露隔垫物基材（33）的过孔（38）,通过该过孔（38）中暴露的隔垫物基材（33）与刻蚀过程中使用的刻蚀气体形成的电场，诱导反应腔内刻蚀过程中产生的物质沉积到所述隔垫物基材（33）表面，生成隔垫物（39）。

Description

阵列基板及其制作方法和显示面板 技术领域
本发明的实施例涉及一种阵列基板及其制作方法和显示面板。 背景技术
随着薄膜晶体管液晶显示器（ TFT-LCD Display )技术的发展和工业技术 的进步， 液晶显示技术已经取代了阴极射线管显示技术成为日常显示领域的 主流技术。
目前， 高级超维场转换（Advanced-Super Dimensional Switching, 筒称 ADS )液晶显示技术已成为高精尖显示领域的主流技术。 高级超维场转换技 术是平面电场宽视角核心技术， 通过同一平面内狭缝电极边缘所产生的电场 以及狭缝电极层与板状电极层间产生的电场形成多维电场， 使液晶盒内狭缝 电极间、 电极正上方所有取向液晶分子都能够产生旋转， 从而提高了液晶工 作效率并增大了透光效率。 高级超维场转换技术可以提高 TFT-LCD产品的 画面品质， 具有高分辨率、 高透过率、 低功耗、 宽视角、 高开口率、 低色差、 无挤压水波纹（push Mura )等优点。 该技术被广泛应用于高端手机屏幕， 移 动应用产品， 电视等领域。
图 1为传统液晶显示面板的结构示意图。 从图 1中可以看出， 所述显示 面板包括对向基板 11、 阵列基板 12、 以及设置在对向基板 11和阵列基板 12 之间的液晶层 13。 所述对向基板 11上设置有隔垫物 110, 所述隔垫物 110 根据实际需要，其高度一般在 2~3μιη左右。所述隔垫物 110的作用是维持盒 厚， 防止液晶受挤压变形而无法正常显示。 目前， 主要是采用光刻法制作隔 垫物， 其制作方法是将隔垫物感光材料涂布于对向基板表面， 经过曝光、 显 影工艺制作出隔垫物。 在具体的制作过程中， 通常需要经过灰度掩膜板或半 透过掩膜板曝光来实现隔垫物感光材料的图案化， 所述隔垫物感光材料的主 要成分为树脂。 由于树脂的硬度较低， 故制得的隔垫物容易碎裂， 碎裂的隔 垫物无法起到支撑作用， 使得周围的液晶受挤压变形， 变形的液晶分子无法 正常进行旋转， 最终导致液晶显示器的显示效果不良， 甚至无法正常显示。 发明内容
一方面，本发明实施例提供了一种阵列基板的制作方法，所述方法包括： 在村底基板上同层形成包括扫描线和隔垫物基材的图形； 形成栅绝缘层； 形 成包括有源层、 数据线、 源电极和漏电极的图形； 形成钝化层； 利用干法刻 蚀法依次对钝化层和栅绝缘层进行刻蚀以形成暴露隔垫物基材的过孔， 通过 该过孔中暴露的隔垫物基材与刻蚀过程中使用的刻蚀气体形成的电场， 诱导 反应腔内刻蚀过程中产生的物质沉积到所述隔垫物基材表面， 生成隔垫物。
例如， 在干法刻蚀过程中，依次对钝化层、有源层和栅绝缘层进行刻蚀， 以形成暴露隔垫物基材的过孔。
例如， 在干法刻蚀过程中， 利用包括六氟化硫与氯气的第一刻蚀气体对 有源层进行刻蚀。
例如， 在干法刻蚀过程中， 利用包括六氟化^ £、 氯气和氧气的第二刻蚀 气体对栅绝缘层和钝化层进行刻蚀。
例如， 所述第二刻蚀气体还包括氦气。
例如， 当反应腔内温度为 30°C~50°C , 压强为 50~70帕， 所述第二刻蚀 气体中六氟化硫气体流量为 50~200 毫升每分 sccm, 氧气的气体流量为 100~300sccm , 氦气的气体流量为 50~100sccm , 氯气的气体流量为 10~50sccm, 等离子刻蚀设备施加的功率为 5000~9000 瓦时， 所述隔垫物的 生长速度为 150~250埃 /秒。
例如， 所述隔垫物包括氯化硅， 所述氯化硅为栅绝缘层和钝化层的制作 材料与刻蚀气体的反应物。
例如， 所述隔垫物还包括金属氯化物， 所述金属氯化物是由隔垫物基材 与刻蚀气体发生反应生成的。
例如， 所述隔垫物为柱状隔垫物。
例如， 所述隔垫物基材与扫描线的制作材料相同。
例如， 所述隔垫物基材与扫描线平行设置， 或者所述隔垫物基材与扫描 线交叉设置。
另一方面， 本发明的实施例提供了一种阵列基板。 该阵列基板包括村底 基板、 扫描线、 隔垫物基材、 栅绝缘层、 有源层、 钝化层、 隔垫物和过孔。 所述隔垫物基材与扫描线同层设置， 位于所述村底基板上方； 所述栅绝缘层 位于所述隔垫物基材和扫描线上方； 所述有源层位于所述栅绝缘层上方； 所 述钝化层位于所述有源层上方； 所述过孔贯穿栅绝缘层和钝化层以暴露所述 隔垫物基材； 所述隔垫物位于所述过孔的内部且位于所述隔垫物基材上方。
例如，所述过孔贯穿栅绝缘层、有源层和钝化层而暴露所述隔垫物基材。 例如， 所述隔垫物包括氯化硅。
例如， 所述隔垫物还包括金属氯化物。
例如， 所述隔垫物为柱状隔垫物。
例如， 所述隔垫物基材与扫描线的制作材料相同。
例如， 所述隔垫物基材与扫描线平行设置， 或者所述隔垫物基材与扫描 线交叉设置。
另一方面， 本发明实施例提供了一种显示面板。 所述显示面板包括上述 的阵列基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为传统的液晶显示面板的结构示意图；
图 2和图 3为扫描线和隔垫物基材的位置示意图；
图 4为完成钝化层制作后的阵列基板的剖面结构示意图；
图 5为完成像素电极制作后的阵列基板的结构示意图；
图 6为本发明实施例提供的具有隔垫物的阵列基板的剖面结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例中的附图， 对本发明实施例中的技术方案进行清楚、 完整地描述， 显然， 所描述的实施例仅是本发明一部分实施例， 而不是全部的实施例。 基 于本发明中的实施例， 本领域普通技术人员在没有做出创造性劳动前提下所 获得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例提供了一种阵列基板的制作方法， 所述方法包括： 在村底基板上同层形成包括扫描线和隔垫物基材的图形； 形成栅绝缘层；
形成半导体薄膜、 掺杂半导体薄膜和源漏金属薄膜， 通过构图工艺形成 包括有源层、 数据线、 源电极和漏电极的图形；
形成钝化层；
利用干法刻蚀法， 依次对钝化层和栅绝缘层进行刻蚀， 以形成暴露隔垫 物基材的过孔， 通过过孔中暴露的隔垫物基材与刻蚀过程中使用的刻蚀设备 反应腔内的刻蚀气体形成的电场， 诱导反应腔内刻蚀过程中产生的物质沉积 到所述隔垫物基材的表面， 生成隔垫物。
例如， 在干法刻蚀过程中，依次对钝化层、有源层和栅绝缘层进行刻蚀， 以形成暴露隔垫物基材的过孔。
例如， 在干法刻蚀过程中， 利用包括六氟化硫与氯气的第一刻蚀气体对 有源层进行刻蚀； 利用包括六氟化硫、 氯气和氧气的第二刻蚀气体对栅绝缘 层和钝化层进行刻蚀。 例如， 所述第二刻蚀气体中还包括氦气。
例如， 所述隔垫物基材为金属图案以用于在其上方制作隔垫物。 刻蚀到 隔垫物基材时， 隔垫物基材表面的金属与第二刻蚀气体发生反应， 在该隔垫 物基材表面形成金属氯化物。
例如， 反应腔内温度为 30°C ~50°C , 压强为 50~70帕， 所述第二刻蚀气 体中六氟化硫气体流量为 50~200标准毫升 /分钟 ( sccm ) , 氧气的气体流量 为 100~300sccm , 氦气的气体流量为 50~100sccm , 氯气的气体流量为 10~50sccm, 等离子刻蚀设备施加的功率为 5000~9000 瓦时， 所述隔垫物的 生长速度为 150~250人 m/s。
例如， 制作相互平行的扫描线和隔垫物基材， 或者制作相互交叉的扫描 线和隔垫物基材。 例如， 采用相同的工艺、 同样的材料制作所述扫描线和隔 垫物基材。
此外， 也可以先制作所述隔垫物基材， 后制作所述扫描线。 或者， 先制 作所述扫描线， 后制作所述隔垫物基材。 此外， 也可以采用不同的金属材料 分别制作所述扫描线和隔垫物基材。
所述隔垫物基材的形状可以为线形、 方形、 圓形、 三角形或多边形等任 意形状， 但至少应保证所述隔垫物基材位于需要设置隔垫物的位置。 例如， 村底基板为玻璃基板。
下面， 将结合附图详细介绍本发明实施例提供的阵列基板的制作方法。 该方法包括以下步骤。
第一步 S1 , 参见图 2, 在玻璃基板 31上沉积钼 （Mo ) 、 铝（A1 )或镉 ( Cr )等金属层， 然后利用构图工艺， 同层形成包括扫描线 32和隔垫物基材 33的图形， 制得如图 2所示的相互平行的扫描线 32和隔垫物基材 33 , 或者 如图 3所示的相互交叉的扫描线 32和隔垫物基材 33。 值得注意的是， 制得 的隔垫物基材 33的位置对应于需要设置隔垫物的位置。 同时，若要制得与扫 描线 32相互交叉的隔垫物基材 33, 相交叉的位置区域应避免与需要设置隔 垫物的位置区域重合， 以免对扫描线的传输功能造成不良影响。
第二步 S2, 参见图 4, 在形成包括扫描线 32和隔垫物基材 33的图案的 基板上沉积氮化硅（ SiNx )或氧化硅（ SiOx )层， 然后利用构图工艺形成栅 绝缘层 34。
第三步 S3, 在形成栅绝缘层 34的基板上沉积半导体薄膜、 掺杂半导体 薄膜和源漏金属薄膜， 采用双色调掩模（例如， 半色调掩模或灰色调掩模）， 在栅极绝缘层 34上形成有源层 35 (见图 4 )、 阵列基板的源极（未图示）和 阵列基板的漏极（未图示） 。
第四步 S4, 在形成所述有源层 35、 源极和漏极的基板上沉积氮化硅薄 膜， 形成钝化层 36 (见图 4 )； 并且对该钝化层 36进行构图工艺， 形成第一 过孔 37 (见图 5 ) 。
第五步 S5, 使用磁控溅射法在钝化层 36上沉积氧化铟锡（ ITO )透明导 电薄膜， 通过构图工艺形成像素电极 60 (见图 5 ) , 且所述像素电极 60通过 位于钝化层 36的第一过孔 37直接与阵列基板的漏极连接。
第六步 S6, 参见图 6, 利用干法刻蚀法对钝化层 36进行刻蚀， 形成第 二过孔 38以暴露隔垫物基材。该过程例如包括： 在干法刻蚀过程中， 利用包 括六氟化硫、 氯气和氧气的第二刻蚀气体， 在需要设置隔垫物的位置对钝化 层 36进行刻蚀。 该过程中， 相对于包括六氟化硫和氯气而不包含氧气（02 ) 的第一刻蚀气体， 添加有 02的第二刻蚀气体能够提高对 SiNx的刻蚀速率和 均匀性。
第七步 S7, 将第二刻蚀气体转换为第一刻蚀气体， 对有源层 35进行刻 蚀， 使得第二过孔 38继续向下延深。
第八步 S8, 由于栅绝缘层 34和钝化层 36的制作材料相同， 因此将第一 刻蚀气体转换为第二刻蚀气体， 对栅绝缘层 34进行刻蚀， 使得第二过孔 38 继续向下延深， 直至使隔垫物基材 33的表面暴露出来。 至此， 形成了贯穿所 述钝化层 36、 有源层 35和栅绝缘层 34的第二过孔 38。
第九步 S9, 隔垫物基材 33表面的金属与第二刻蚀气体发生反应， 在该 隔垫物基材表面形成金属氯化物； 同时，通过第二过孔 38中暴露的隔垫物基 材与刻蚀过程中使用的刻蚀设备反应腔内的刻蚀气体形成电场， 诱导反应腔 内刻蚀过程中产生的物质沉积到所述隔垫物基材的表面， 然后通过晶体生长 的方式， 生成隔垫物 39。 所述隔垫物 39可为柱状结构， 其组成材料主要为 SiCl4, 所述 SiCl4为栅绝缘层和钝化层的制作材料与用于刻蚀第二过孔 38的 刻蚀气体的反应物，此外隔垫物 39的组成材料还包括金属氯化物，所述金属 氯化物是由隔垫物基材 33表面的金属与刻蚀气体发生反应生成的。
所述隔垫物 39 的高度可根据其生长速度和生长时间来控制。 一定时间 内， 生长速度越快， 隔垫物 39的高度越高。 一定生长速度下， 生长的时间越 长， 所述隔垫物 39的高度越高。
所述隔垫物 39的生长速度和其生长环境有关，可以通过控制反应腔内的 温度、 压强以及刻蚀气体的浓度， 来控制所述隔垫物 39的生长速度， 例如， 当反应腔内温度为为 30°C ~50°C , 压强为 50~70帕， 所述第二刻蚀气体中六 氟化硫气体流量为 50~200 sccm,氧气的气体流量为 100~300sccm, 氦气的气 体流量为 50~100sccm, 氯气的气体流量为 10~50sccm, 等离子刻蚀设备施加 的功率为 5000~9000瓦时，所述隔垫物 39的生长速度为 150~250埃 /秒（ A/s )。
需指出的是， 参见图 5, 在利用干法刻蚀法进行刻蚀的过程中， 由于除 第二过孔 38外的其它过孔（如用于连接所述像素电极 60和漏极的第一过孔 37 )处都有氧化铟锡进行保护， 因此该干法刻蚀过程中不会在除第二过孔 38 外的其它过孔中形成隔垫物，因此除第二过孔 38外的其它过孔的功能不会受 到影响。
经过上述步骤， 即可制得本发明实施例提供的剖面结构如图 6所示的阵 列基板。 利用所述方法形成的阵列基板中设置有隔垫物， 且该隔垫物具有硬 度高、 不易碎裂等优点， 可以有效的解决因隔垫物破损导致的显示不良的问 题， 提高液晶显示装置的显示效果。
本发明实施例提供了一种阵列基板， 所述阵列基板包括村底基板、 扫描 线、 隔垫物基材、 栅绝缘层、 有源层、 钝化层、 隔垫物和第二过孔， 其中 所述隔垫物基材与扫描线同层设置， 位于所述村底基板上方；
所述栅绝缘层位于所述隔垫物基材和扫描线上方；
所述有源层位于所述栅绝缘层上方；
所述钝化层位于所述有源层的上方；
所述第二过孔贯穿栅绝缘层和钝化层以暴露所述隔垫物基材；
所述隔垫物位于所述第二过孔内部且位于所述第二过孔所暴露的隔垫物 基材的上方。
例如， 所述第二过孔贯穿栅绝缘层、 有源层和钝化层而暴露所述隔垫物 基材。
例如， 所述隔垫物的组成材料包括氯化硅（SiCl4 ) , 所述 SiCl4为钝化 层和栅绝缘层的制作材料与第二刻蚀气体的反应物。 例如， 所述隔垫物的组 成材料还包括金属氯化物， 所述金属氯化物是由隔垫物基材表面的金属与刻 蚀气体发生反应生成的。
例如， 所述隔垫物为柱状隔垫物， 位于所述第二过孔的内部且位于隔垫 物基材的上方， 用于起到支撑作用， 防止液晶分子受挤压变形而无法正常进 行旋转。
例如， 隔垫物基材的制作材料与扫描线的制作材料相同。 例如， 所述隔 垫物基材既可以与扫描线平行设置， 也可以与扫描线交叉设置。
例如， 所述隔垫物基材的形状可以为线形、 方形、 圓形、 三角形或多边 形等任意形状。
下面， 将结合附图对本发明实施例提供的阵列基板进行详细说明。 所述 阵列基板的结构如图 6所示。 图 6为具有隔垫物基材的阵列基板的剖面结构 图。 从图 6中可以看出， 所述阵列基板包括： 村底基板 31、 隔垫物基材 33、 栅绝缘层 34、 有源层 35、 钝化层 36、 第二过孔 38、 隔垫物 39。 此外， 所述 阵列基板还包括在图 6中未图示结构， 如扫描线、 第一过孔、 栅极、 源极、 漏极和像素电极等。
例如， 栅极、 扫描线和隔垫物基材 33 同层设置， 均位于所述村底基板 31上方。 例如， 所述隔垫物基材 33的形状为线形， 与所述扫描线可以平行 设置， 二者也可以相互交叉设置。 进一步地， 例如所述阵列基板的栅极、 扫 描线和隔垫物基材 33的制作材料相同， 为钼 （Mo ) 、 （铝 A1 ) 、 铬（Cr ) 或铜（Cu )等金属。
所述栅绝缘层 34位于所述阵列基板的栅极、 扫描线和隔垫物基材 33上 方， 用于将所述阵列基板的栅极、扫描线和隔垫物基材 33与其它层绝缘， 其 制作材料例如为氮化硅（SiNx )或氧化硅（SiOx ) 。
所述有源层 35位于所述栅绝缘层 34上方。
所述阵列基板的源极与漏极同层设置，均位于所述有源层 35上并彼此相 对。
所述阵列基板的源极和漏极的制作材料为导电金属， 例如单层的钼 ( Mo ) 、 铬（Gr )或者双层的铝铌合金钼 （AlNd/Mo )等金属。
所述钝化层 36位于所述阵列基板的源极和漏极上方，其制作材料例如与 栅绝缘层 34的制作材料相同， 为氮化硅（SiNx )或氧化硅（SiOx ) 。
所述像素电极位于钝化层 36上方， 并通过钝化层 36中的第一过孔与阵 列基板的漏极直接连接； 所述像素电极的制作材料为透明导电材料， 例如氧 化铟锡（ITO )等。
所述第二过孔 38贯穿栅绝缘层 34、 有源层 35和钝化层 36而暴露隔垫 物基材 33。
所述隔垫物 39位于所述第二过孔 38的内部且位于隔垫物基材 33的上 方。 所述隔垫物 39为柱状结构， 其组成材料主要为氯化硅（SiCl4 ) , 此外 还包括一些金属氯化物，所述金属氯化物是由隔垫物基材 33表面的金属与第 二刻蚀气体发生反应生成的。
本发明实施例还提供了一种显示面板， 所述显示面板包括上述的阵列基 板。
综上所述， 本发明实施例一种阵列基板及其制作方法和显示面板。 所述 阵列基板的制作过程中， 利用干法刻蚀依次对钝化层、 有源层和栅绝缘层进 行刻蚀， 以形成暴露隔垫物基材的过孔， 当刻蚀到隔垫物基材的表面时， 隔 垫物基材表面的金属与反应腔内的气体形成电场， 在电场的作用下， 刻蚀过 程中产生的物质沉积到隔垫物基材的表面， 生成隔垫物， 通过所述方法生成 的隔垫物相对传统的由树脂材料形成的隔垫物具有硬度大、不易碎裂等优点， 能够保证其周围的液晶分子不会受到挤压变形， 使得液晶分子能够正常进行 旋转，从而改善了液晶显示器的显示效。 此外， 将隔垫物制作在阵列基板上， 筒化了对向基板的制作工艺。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种阵列基板的制作方法， 包括：
在村底基板上同层形成包括扫描线和隔垫物基材的图形；
形成栅绝缘层；
形成包括有源层、 数据线、 源电极和漏电极的图形；
形成钝化层；
利用干法刻蚀法依次对钝化层和栅绝缘层进行刻蚀以形成暴露隔垫物基 材的过孔， 通过该过孔中暴露的隔垫物基材与刻蚀过程中使用的刻蚀气体形 成的电场，诱导反应腔内刻蚀过程中产生的物质沉积到所述隔垫物基材表面， 生成隔垫物。
2、 如权利要求 1所述的方法， 其中在干法刻蚀过程中， 依次对钝化层、 有源层和栅绝缘层进行刻蚀， 以形成暴露隔垫物基材的过孔。
3、如权利要求 2所述的方法， 其中在干法刻蚀过程中， 利用包括六氟化 硫与氯气的第一刻蚀气体对有源层进行刻蚀。
4、 如权利要求 1-3任一项所述的方法， 其中在干法刻蚀过程中， 利用包 括六氟化硫、 氯气和氧气的第二刻蚀气体对栅绝缘层和钝化层进行刻蚀。
5、 如权利要求 4所述的方法， 其中所述第二刻蚀气体还包括氦气。
6、如权利要求 5所述方法， 其中在干法刻蚀过程中， 当反应腔内温度为 30°C ~50 °C , 压强为 50~70 帕， 所述第二刻蚀气体中六氟化硫气体流量为
50~200毫升每分 sccm,氧气的气体流量为 100~300sccm, 氦气的气体流量为 50~100sccm, 氯气的气体流量为 10~50sccm, 等离子刻蚀设备施加的功率为 5000-9000瓦时， 所述隔垫物的生长速度为 150~250埃 /秒。
7、 如权利要求 1-6任一项所述的方法， 其中所述隔垫物包括氯化硅， 所 述氯化硅为栅绝缘层和钝化层的制作材料与刻蚀气体的反应物。
8、如权利要求 7所述的方法， 其中所述隔垫物还包括金属氯化物， 所述 金属氯化物是由隔垫物基材与刻蚀气体发生反应生成的。
9、 如权利要求 1-8任一项所述的方法， 其中所述隔垫物为柱状隔垫物。
10、 如权利要求 1-9任一项所述的方法， 其中所述隔垫物基材与扫描线 的制作材料相同。
11、如权利要求 1-10任一项所述的方法， 其中所述隔垫物基材与扫描线 平行设置， 或者所述隔垫物基材与扫描线交叉设置。
12、 一种阵列基板， 包括村底基板、 扫描线、 隔垫物基材、 栅绝缘层、 有源层、 钝化层、 隔垫物和过孔， 其中，
所述隔垫物基材与扫描线同层设置， 位于所述村底基板上方；
所述栅绝缘层位于所述隔垫物基材和扫描线上方；
所述有源层位于所述栅绝缘层上方；
所述钝化层位于所述有源层上方；
所述过孔贯穿栅绝缘层和钝化层以暴露所述隔垫物基材；
所述隔垫物位于所述过孔的内部且位于所述隔垫物基材上方。
13、如权利要求 12所述的阵列基板， 其中所述过孔贯穿栅绝缘层、有源 层和钝化层而暴露所述隔垫物基材。
14、如权利要求 12或 13所述的阵列基板，其中所述隔垫物包括氯化硅。
15、如权利要求 14所述的阵列基板，其中所述隔垫物还包括金属氯化物。
16、 如权利要求 12-15任一项所述阵列基板， 其中所述隔垫物为柱状隔 垫物。
17、 如权利要求 12-16任一项所述的阵列基板， 其中所述隔垫物基材与 扫描线的制作材料相同。
18、 如权利要求 12-17任一项所述阵列基板， 其中所述隔垫物基材与扫 描线平行设置， 或者所述隔垫物基材与扫描线交叉设置。
19、 一种显示面板， 包括权利要求 12-18任一权项所述的阵列基板。
PCT/CN2013/088839 2013-07-23 2013-12-09 阵列基板及其制作方法和显示面板 Ceased WO2015010416A1 (zh)

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