WO2015010350A1 - 一种多层印刷线路板 - Google Patents

一种多层印刷线路板 Download PDF

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Publication number
WO2015010350A1
WO2015010350A1 PCT/CN2013/081615 CN2013081615W WO2015010350A1 WO 2015010350 A1 WO2015010350 A1 WO 2015010350A1 CN 2013081615 W CN2013081615 W CN 2013081615W WO 2015010350 A1 WO2015010350 A1 WO 2015010350A1
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WO
WIPO (PCT)
Prior art keywords
multilayer printed
circuit board
printed circuit
layer
trench
Prior art date
Application number
PCT/CN2013/081615
Other languages
English (en)
French (fr)
Inventor
郭东胜
符俭泳
宋丽佳
Original Assignee
深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Publication of WO2015010350A1 publication Critical patent/WO2015010350A1/zh

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits

Definitions

  • the present invention relates to a multilayer printed wiring board having two or more wiring layers. Background technique
  • multilayer printed wiring boards are widely used in products with high density of various electronic components.
  • Multilayer printed wiring boards are often formed by alternately overlapping wiring layers and isolation layers.
  • SMT surface mount technology
  • more stringent requirements are imposed on the plate bending and panel warpage of multilayer printed wiring boards.
  • the residual copper ratio of each layer of the multilayer printed wiring board is different, when the temperature is high, the problem of the plate bending «1 may occur due to the difference in the residual copper ratio of each layer.
  • An object of the present invention is to provide a multilayer printed wiring board which can prevent a multilayer printed wiring board from being bent after being subjected to a high temperature due to a residual copper ratio, and has no space limitation and noise problem.
  • the utility model is realized by the following technical solutions: a multi-layer printed circuit board, wherein the plurality of at least two wiring layers comprise a copper foil region, and at least one of the at least two wiring layers is provided on the wiring layer And a dummy trench for adjusting thermal stress, the dummy trench being disposed on the copper foil region.
  • the dummy trench is formed in such a manner as to remove the copper foil.
  • the dummy trench is provided in the middle of the copper foil region to reduce the internal stress of the copper foil due to heat.
  • the dummy trench is formed on the wiring layer having the largest residual copper ratio in the at least two wiring layers to reduce the difference between the thermal stresses of the respective wiring layers.
  • the multilayer printed wiring board comprises a top layer, a bottom layer, An intermediate wiring layer between the top layer and the bottom layer, wherein a residual copper ratio of the bottom layer is greater than a residual copper ratio of the top layer, and the dummy trench is disposed in a copper foil region of the bottom layer on.
  • the extending direction of the dummy groove corresponds to the width direction of the multilayer printed wiring board.
  • the dummy trench includes a strip groove.
  • the dummy trench includes an arcuate groove.
  • the dummy trench comprises a closed elliptical groove.
  • the dummy trench includes a curved groove.
  • the dummy trench is disposed at a height direction of the at least two wiring layers along the printed circuit board.
  • the dummy trench is provided with a plurality of segments, and the minimum distance between the dummy trenches of each segment is greater than 1 mm.
  • the utility model has the beneficial effects that: according to the multilayer printed wiring board of the present invention, at least one of the at least two wiring layers is provided with a dummy trench, and the dummy trench is disposed in the On the copper foil area, thereby, by setting the etching line trenches (ie, etching away part of the copper foil), the integrity of the large copper foil is destroyed, and the stress generated by the large-area copper foil is reduced to satisfy the multilayer printed wiring board.
  • the warpage requirements balance the stress of each layer of the wiring layer, which has no space limitation and noise problems.
  • FIG. 1 is a schematic cross-sectional view of panels of a multilayer printed line in accordance with an embodiment of the present invention.
  • 2 is a cross-sectional view of a multilayer printed wiring board for comparison with the multilayer printed wiring board of FIG. 1.
  • FIG. 2 is a top layer for displaying a multilayer printed wiring board according to another embodiment of the present invention. Plane schematic.
  • Fig. 4 is a plan view schematically showing a bottom layer of a multilayer printed wiring board according to another embodiment of the present invention before a dummy trench is provided.
  • Fig. 5 is a schematic view for explaining that a multilayer printed wiring board is bent due to a difference in residual copper ratio.
  • Fig. 6 is a view for explaining a first embodiment of a dummy groove on a wiring layer of a multilayer printed wiring board.
  • Fig. 7 is a view for explaining a second embodiment of a dummy groove on a wiring layer of a multilayer printed wiring board.
  • Fig. 8 is a view for explaining a third embodiment of a dummy groove on a wiring layer of a multilayer printed wiring board.
  • Fig. 9 is a view for explaining a fourth embodiment of a dummy groove on a wiring layer of a multilayer printed wiring board.
  • the multilayer printed wiring board of the present invention reduces the stress generated by the large copper foil by etching a part of the copper foil by providing a dummy groove for adjusting thermal stress on the large copper foil area of the wiring layer. It satisfies the warpage requirements of multilayer printed wiring boards and balances the stress of each wiring layer. This method and structure has no space limitations and noise issues.
  • a multilayer printed wiring board according to an embodiment of the present invention will be described with reference to FIG. 1 and FIG. 2, wherein no dummy trench is provided on the wiring layer of the multilayer printed wiring board in FIG.
  • the structure of the multilayer printed wiring board in 1 is compared.
  • the multilayer printed wiring board 100 includes four wiring layers 112, 114, 116, 118 and three isolation layers 122 interposed between the four wiring layers 112, 114, 116, 118. .
  • the isolating layer is a resin layer, for example, a polypropylene film (Polypropylene, abbreviated as PP).
  • PP polypropylene
  • the four wiring layers 112, 114, 116, 118 each include a copper foil region 140.
  • the wiring layer 112 at the top, the wiring layer 118 at the bottom, and the wiring layer 116 include signal traces 130.
  • a dummy trench 150 is provided on the wiring layer 118 of the four wiring layers 112, 114, 116, 118. Moreover, the dummy trench 150 is disposed on the copper foil region 140. Wherein, the dummy trench 150 is formed in a manner of removing copper foil (hollowed out). As can be seen from Fig. 1, the dummy trench 150 is disposed in the middle of the copper foil region 140 of the wiring layer 118 to reduce the internal stress of the copper foil due to heat.
  • the residual copper ratio of the wiring layer 118 is larger than the residual copper ratio of the wiring layer 112, since the residual copper ratio of the wiring layer 112 at the top is smaller than the residual copper ratio of the wiring layer 118 at the bottom.
  • the expansion force of the wiring layer 112 at the top when heated is greater than the expansion force of the wiring layer 118 at the bottom, resulting in warping of the middle of the multilayer printed wiring board upward.
  • the warped shape is difficult to recover.
  • the wiring layer 118 and the wiring layer 112 are symmetrical layers; the wiring layer 116 and the wiring layer 114 are symmetrical layers.
  • the isolation layer 122 located between the three isolation layers 122, that is, the core layer is a symmetric reference layer. If the residual copper ratio of the symmetrical layer is largely different, the symmetrical layer formed by the high-temperature wiring layer 116 and the wiring layer 114 of the multilayer printed wiring board can also utilize the dummy trench to narrow the difference in thermal stress of the symmetrical layer.
  • the dummy trench is formed on the wiring layer having the largest residual copper ratio in the at least two wiring layers to reduce a difference between thermal stresses of the respective wiring layers, thereby Balance the stress of each wiring layer.
  • a dummy trench may be provided on the wiring layer 114 and the wiring layer 118, whereby the difference in thermal stress of each symmetrical layer is reduced, and the internal stress of the four wiring layers is balanced.
  • the multilayer printed wiring board 200 includes a top layer 212, a bottom layer 218, and an intermediate wiring layer (not shown) between the top layer 212 and the bottom layer 218.
  • the bottom layer 218 has a residual copper ratio greater than the residual copper ratio of the top layer 212, and the dummy trench 150 is disposed on the copper foil region 240 of the bottom layer 218.
  • the top layer 212 and the bottom layer 218 are square.
  • the top layer 212 includes a copper foil region 240 and a wiring region 250.
  • a signal trace 230 is disposed on the wiring area 250.
  • the signal traces 230 extend along the length direction X of the multilayer printed wiring board and are provided in the width direction Y. Also, as shown in FIG. 4, the bottom layer 218 includes a copper foil region 240 and a wiring region 250. A signal trace 230 is disposed on the wiring area 250. The area of the copper foil region 240 on the bottom layer 218 is large compared to the top layer 212, and there is a large copper foil. The residual copper layer of the bottom layer 218 is greater than the copper residual rate of the top layer 212.
  • the expansion force of the top layer 212 when heated is greater than the expansion force of the bottom layer 218, and may result in a similar copper residual rate of the intermediate wiring layer.
  • the middle of the multilayer printed wiring board is warped upward in the height direction Z of the printed wiring board as shown in FIG. After the heat dissipation, since the internal stress of the copper foil of the top layer 212 is smaller than the internal stress of the copper foil of the bottom layer 218, the shape of the warpage is difficult to recover. If the electronic component is soldered while the multilayer printed wiring board is bent during the reflow process, the soldering reliability is remarkably lowered.
  • the top layer 212 and the bottom layer 218 are symmetrical layers. If the residual copper ratio of the symmetrical layer is largely different, the multilayer printed wiring board is likely to be bent after passing through a high temperature.
  • the symmetrical layer formed by the top layer 212 and the bottom layer 218 has been described above as an example, and the symmetrical layer formed by the intermediate wiring layer can also reduce the difference in thermal stress of the symmetrical layer by using the dummy trench.
  • the stress of each wiring layer is balanced, and the extending direction of the dummy trench on the copper foil corresponds to the width direction Y of the multilayer printed wiring board.
  • a specific embodiment of the dummy trench will be described below with reference to FIGS. 6 to 9.
  • Fig. 6 is a view for explaining a first embodiment of a dummy groove on a wiring layer of a multilayer printed wiring board.
  • the dummy trenches 310, 320 include strip-shaped grooves.
  • the dummy trench 310 includes a first trench 318, and a second trench 312, a third trench 314, and a fourth trench 316.
  • the second trench 312, the third trench 314, and the fourth trench 316 extend in the width direction Y.
  • the first trench 318 and the second trench 312, the third trench 314, and the fourth trench 316 are in the length direction.
  • the first trench 318, the second trench 312, the third trench 314, and the fourth trench 316 all correspond to the width direction Y (here, the same).
  • the dummy trench 320 includes a first trench 328, and a second trench 322, a third trench 324, and a fourth trench 326.
  • the dummy trench 310 is identical in structure to the dummy trench 320 and symmetrically disposed. Thereby, the original copper foil region 240 is broken by the dummy trench 310 and the dummy trench 320, and the ability of the copper foil region 240 to generate internal stress in the longitudinal direction X (longitudinal direction) is greatly impaired.
  • the second trench 322, the third trench 324, and the fourth trench 326 are uniformly disposed in the width direction Y.
  • the first trench 328, and the second trench 322, the third trench 324, and the fourth trench 326 are provided with an etched section uniformly disposed in the non-wiring region.
  • the width of the first trench 328, the second trench 322, the third trench 324, and the fourth trench 326 may be as long as the minimum etch width achievable by fabrication is satisfied.
  • the length of the first trench 328, and the second trench 322, the third trench 324, and the fourth trench 326 are adjusted according to the area of the copper foil, and should not be too long or too short. Too long will damage the integrity of the copper foil.
  • the length of the first trench 328, the second trench 322, the third trench 324, and the fourth trench 326 is too short (in theory, as long as it is greater than zero), and the effect of reducing the stress generated by the copper foil is not significant.
  • the minimum distance between each two dummy trenches ie, the minimum of the horizontal distance and the vertical distance
  • the electronic components are overheated and operate abnormally.
  • Fig. 7 is a view for explaining a second embodiment of a dummy groove on a wiring layer of a multilayer printed wiring board.
  • the dummy trenches 410, 420 include curved slots.
  • Fig. 8 is a view for explaining a third embodiment of a dummy groove on a wiring layer of a multilayer printed wiring board.
  • the dummy trenches 510, 520 include closed elliptical slots.
  • Fig. 9 is a view for explaining a fourth embodiment of a dummy groove on a wiring layer of a multilayer printed wiring board.
  • the dummy The grooves 610, 620 include curved grooves.
  • the entire trenches 410, 420, the dummy trenches 510, 520, and the dummy trenches 610, 620 have the same length direction as the width direction Y.
  • the functional dummy trenches 310, 320 are the same, both for weakening the copper foil region 240 along the length direction X (longitudinal direction) The ability of internal stress.
  • the dummy trenches 310, 320, the dummy trenches 410, 420, the dummy trenches 510, 520, and the dummy trenches 610, 620 may be of other shapes or may be used in combination.
  • the stress generated by the large copper foil is reduced by etching a portion of the (foiled) copper foil by providing dummy trenches on the large copper foil region of the wiring layer. , balance the stress of each layer of wiring layer.
  • the plate bending of the multilayer printed wiring board is reduced, the yield of the multilayer printed wiring board is improved, and the cost is saved.
  • the residual copper ratio of each wiring layer can be calculated by using commercial software such as Genesis2000 or CAM350, and the residual copper ratio of each symmetric layer can be compared.
  • the symmetry plane (the symmetry plane is the middle layer and the bottom layer, and the layer symmetrical with respect to the core layer) has a large difference in the residual copper ratio
  • the non-wiring region of the wiring layer having a large residual copper ratio The dummy groove is added to the copper foil to increase the expansion force of the copper foil.
  • the stress generated by the large copper foil reaches the purpose of balancing the expansion force and stress of the symmetrical layer.
  • the printed circuit board refers to a printed circuit board, that is, a printed circuit board (PCB); the method of quantifying the bending of the printed circuit board or the bending of the board bending plate is to measure the warpage of the printed circuit board and the pair of printed circuit boards.
  • the length of the corner line; the residual copper ratio refers to the ratio of the area of the copper foil remaining after the etching of the copper foil of the wiring layer of the printed wiring board to the total substrate area of the wiring layer of the printed wiring board.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

一种所述多层印刷线路板，其包括至少两层布线层（112，114，116，118）及夹设在所述至少两层布线层（112，114，116，118）之间的隔离层，所述至少两层布线层（112，114，116，118）包括铜箔区（140），所述至少两层布线层（112，114，116，118）中至少一层布线层上设有用于调整热应力的虚设沟槽（150），所述虚设沟槽（150）设置在所述铜箔区（140）上。该多层印刷线路板，通过设置蚀刻线沟槽（即蚀刻掉部分的铜箔）来破坏大片铜箔的完整性，减小大面积的铜箔所产生的应力，平衡各层布线层的应力，其没有空间的限制和噪音的问题。

Description

一种多层印刷线路板 技术领域
本实用新型涉及具备二层以上的布线层的多层印刷线路板。 背景技术
众所周知， 多层印刷线路板广泛用于各种电子元器件密度高的产品。 多层印 刷线路板多由布线层与隔离层交替叠合而成。 随着表面贴装技术 (SMT)的普及， 对 多层印刷线路板的板弯及板翘提出了更加严格的要求。 在多层印刷线路板的各层 的残铜率不同的情况下， 在经过高温时， 由于各层的残铜率不同可能会出现板弯 «1的问题。
目前， 为了防止回流焊等时多层印刷线路板弯曲， 一般釆用在残铜率小的布 线层上增加虚设的图形（dummy pattern ),使各布线层的残铜率尽可能一样。但是， 一般不能确保有足够的空间来增设虚设图形。 而且， 在有高频信号的情况下， 有 虚设图形的存在可能会在天线效应等的作用下而产生噪音。 实用新型内容
本实用新型的目的在于， 提供一种多层印刷线路板， 其能够防止多层印刷线 路板因残铜率而经过高温后发生弯曲， 而且没有空间的限制和噪音的问题。
本实用新型通过如下技术方案实现： 一种多层印刷线路板， 其中， 所述多层 述至少两层布线层包括铜箔区， 所述至少两层布线层中至少一层布线层上设有用 于调整热应力的虚设沟槽， 所述虚设沟槽设置在所述铜箔区上。
作为上述技术方案的进一步改进， 所述虚设沟槽以移除铜箔的方式形成。 作为上述技术方案的进一步改进， 所述虚设沟槽设置在铜箔区的中部以减小 铜箔因受热而产生的内应力。
作为上述技术方案的进一步改进， 所述虚设沟槽形成在所述至少两层布线层 中残铜率最大的布线层上以减小各布线层的热应力之间的差异。
作为上述技术方案的进一步改进， 所述多层印刷线路板包括顶部层、 底部层、 位于所述顶部层与所述底部层之间的中间布线层， 所述底部层的残铜率大于所述 顶部层的残铜率， 所述虚设沟槽设置在所述底部层的铜箔区上。
作为上述技术方案的进一步改进， 所述虚设沟槽的延伸方向与所述多层印刷 线路板的宽度方向相对应。
作为上述技术方案的进一步改进， 所述虚设沟槽包括条形槽。
作为上述技术方案的进一步改进， 所述虚设沟槽包括弧形槽。
作为上述技术方案的进一步改进， 所述虚设沟槽包括封闭的椭圓形槽。
作为上述技术方案的进一步改进， 所述虚设沟槽包括曲线槽。
作为上述技术方案的进一步改进， 所述虚设沟槽设置在所述至少两层布线层 沿印刷线路板的高度方向 Z
以平衡对称层面的热应力差异。
作为上述技术方案的进一步改进， 所述虚设沟槽设置有多段， 且各段虚设沟 槽之间的最小距离大于 1 mm。
本实用新型的有益效果是： 才艮据本实用新型的多层印刷线路板， 所述至少两 层布线层中至少一层布线层上设有虚设沟槽， 所述虚设沟槽设置在所述铜箔区上， 由此， 通过设置蚀刻线沟槽（即蚀刻掉部分的铜箔）来破坏大片铜箔的完整性， 减小大面积的铜箔所产生的应力， 满足多层印刷线路板的翘曲要求， 平衡各层布 线层的应力， 其没有空间的限制和噪音的问题。
附图说明
图 1是根据本实用新型的一个具体实施例的多层印刷线各板的截面示意图。 图 2是用于与图 1的多层印刷线路板进行比对的多层印刷线路板的截面示意 图 3是用于显示根据本实用新型的另一个具体实施例的多层印刷线路板的顶 部层的平面示意图。
图 4是用于显示根据本实用新型的另一个具体实施例的多层印刷线路板的底 部层在未设置虚设沟槽之前的平面示意图。
图 5是用于说明多层印刷线路板因残铜率不同而弯曲的示意图。
图 6是用于说明多层印刷线路板的布线层上的虚设沟槽的第一实施例的图。 图 7是用于说明多层印刷线路板的布线层上的虚设沟槽的第二实施例的图。 图 8是用于说明多层印刷线路板的布线层上的虚设沟槽的第三实施例的图。 图 9是用于说明多层印刷线路板的布线层上的虚设沟槽的第四实施例的图。 具体实施方式
以下结合附图对本实用新型的具体实施方式进行进一步的说明。
本实用新型的多层印刷线路板， 通过在布线层的大片铜箔区上设有用于调整 热应力的虚设沟槽， 通过蚀刻掉部分的铜箔来减小大块的铜箔所产生的应力， 满 足多层印刷线路板的翘曲要求， 平衡各层布线层的应力。 此方法和结构没有空间 的限制和噪音的问题。
首先结合附图 1和图 2对本实用新型的一个具体实施例的多层印刷线路板进 行说明， 其中图 2中的多层印刷线路板的布线层上未设置虚设沟槽， 其用于与图 1 中的多层印刷线路板的结构进行比对。
如图 1所示， 该多层印刷线路板 100包括四层布线层 112, 114, 116 , 118及 夹设在所述四层布线层 112 , 114, 116, 118之间的三层隔离层 122。 当然， 该多 层。 所述隔离层为树脂层， 例如为聚丙婦树脂层（Polypropylene, 简称： PP )。 图 1中共有三层隔离层 122 , 位于三层隔离层 122中间的隔离层 122为芯层（ core )。
所述四层布线层 112, 114, 116 , 118均包括铜箔区 140。 其中， 位于顶部的 布线层 112、 位于底部的布线层 118、 以及布线层 116包括信号走线 130。 所述四 层布线层 112, 114, 116, 118中的布线层 118上设有虚设沟槽 150。 而且， 所述 虚设沟槽 150设置在所述铜箔区 140上。 其中， 所述虚设沟槽 150以移除铜箔的 方式（挖空）形成。 从图 1中可以看出， 所述虚设沟槽 150设置在布线层 118的 铜箔区 140的中部以减小铜箔因受热而产生的内应力。
在四层布线层 112, 114, 116, 118中， 布线层 118的残铜率大于布线层 112 的残铜率， 由于顶部的布线层 112的残铜率小于底部的布线层 118的残铜率，受热 时顶部的布线层 112的膨胀力大于底部的布线层 118的膨胀力，导致多层印刷线路 板的中间向上翘曲。 散热后， 因为顶部的布线层 112 的铜箔的内应力小于底部的 布线层 118 的铜箔的内应力， 翘曲的形状难以恢复。 如果在回流:早工艺时， 在多 层印刷线路板弯曲的情况下 ;1：早接电子元件， ；1：早接可靠性明显降低。 在四层布线层 112, 114, 116, 118中， 布线层 118与布线层 112为对称层面； 布线层 116与布线层 114为对称层面。位于三层隔离层 122中间的隔离层 122即芯 层为对称基准层。 如果对称层面的残铜率差异较大， 则多层印刷线路板经过高温 布线层 116与布线层 114形成的对称层面也同样能够利用虚设沟槽缩小对称层面的 热应力的差异。
在本实用新型的一个具体应用例中， 所述虚设沟槽形成在所述至少两层布线 层中残铜率最大的布线层上以减小各布线层的热应力之间的差异， 由此平衡各层 布线层的应力。在图 1的实施例中， 例如可以在布线层 114上、布线层 118设置虚 设沟槽， 由此， 使各对称层面的热应力的差异缩小， 平衡四层布线层的内应力。
接着， 结合附图 3至图 9对本实用新型的另一些具体实施例的多层印刷线路 板进行说明。 该多层印刷线路板 200包括顶部层 212、 底部层 218、 位于所述顶部 层 212与所述底部层 218之间的中间布线层（未示出）。 所述底部层 218的残铜率 大于所述顶部层 212的残铜率， 所述虚设沟槽 150设置在所述底部层 218的铜箔 区 240上。 其中， 顶部层 212、 底部层 218呈方形。 如图 3所示， 顶部层 212包括 铜箔区 240、 布线区 250。 布线区 250上布设有信号走线 230。 信号走线 230沿多 层印刷线路板的长度方向 X延伸， 并在宽度方向 Y上设有多条。 同样， 如图 4所 示， 底部层 218包括铜箔区 240、 布线区 250。 布线区 250上布设有信号走线 230。 与顶部层 212相比， 底部层 218上的铜箔区 240的面积大， 存在大块的铜箔。 底 部层 218的残铜率大于顶部层 212的残铜率。 由于顶部的顶部层 212的残铜率小 于底部层 218的残铜率， 受热时顶部层 212的膨胀力大于底部层 218的膨胀力， 在中间布线层的残铜率相近的情况下， 可导致多层印刷线路板的中间沿印刷线路 板的高度方向 Z向上翘曲， 如图 5所示。 散热后， 因为顶部层 212的铜箔的内应 力小于底部层 218的铜箔的内应力， 翘曲的形状难以恢复。 如果在回流焊工艺时， 在多层印刷线路板弯曲的情况下焊接电子元件， 焊接可靠性明显降低。
顶部层 212、 底部层 218为对称层面。 如果对称层面的残铜率差异较大， 则多 层印刷线路板经过高温后容易发生弯曲。 以上对顶部层 212、底部层 218形成的对 称层面为例进行了说明， 中间布线层形成的对称层面也同样能够利用虚设沟槽缩 小对称层面的热应力的差异。 为了有效减小大块的铜箔所产生的应力， 平衡各层布线层的应力， 在铜箔上 所述虚设沟槽的延伸方向与所述多层印刷线路板的宽度方向 Y相对应。 下面结合 图 6至图 9对虚设沟槽的具体实施例进行说明。
图 6是用于说明多层印刷线路板的布线层上的虚设沟槽的第一实施例的图。 其中， 所述虚设沟槽 310, 320包括条形槽。 所述虚设沟槽 310包括第一沟槽 318、 及第二沟槽 312、 第三沟槽 314、 第四沟槽 316。 第二沟槽 312、 第三沟槽 314、 第 四沟槽 316沿宽度方向 Y对齐延伸，第一沟槽 318与第二沟槽 312、第三沟槽 314、 第四沟槽 316在长度方向 X平行间隔设置。其中，第一沟槽 318、及第二沟槽 312、 第三沟槽 314、 第四沟槽 316均与宽度方向 Y相对应 （此处为相同）。 同样地， 所 述虚设沟槽 320包括第一沟槽 328、及第二沟槽 322、第三沟槽 324、第四沟槽 326。 所述虚设沟槽 310与虚设沟槽 320结构相同且对称设置。 由此，原本的铜箔区 240 被虚设沟槽 310与虚设沟槽 320破坏， 铜箔区 240沿长度方向 X (长边方向）产 生内应力的能力被大大削弱。
其中， 第二沟槽 322、 第三沟槽 324、 第四沟槽 326沿宽度方向 Y均匀设置。 第一沟槽 328、 及第二沟槽 322、 第三沟槽 324、 第四沟槽 326为设置在非布线区 均匀设置蚀刻段。 第一沟槽 328、 及第二沟槽 322、 第三沟槽 324、 第四沟槽 326 的宽度只要满足制作可实现的最小蚀刻宽度即可。第一沟槽 328、及第二沟槽 322、 第三沟槽 324、 第四沟槽 326的长度根据铜箔的面积做调整， 不宜过长或过短， 过 长会破坏铜箔的完整性， 即最长使得虚设沟槽不能贯穿铜箔区， 影响信号的回流 路径。 第一沟槽 328、 及第二沟槽 322、 第三沟槽 324、 第四沟槽 326的长度过短 (理论上只要大于零即可）， 对减小铜箔产生的应力作用不明显。 且每两段虚设沟 槽之间的最小距离 （即水平距离和垂直距离中最小值）应至少满足印刷线路板上 最大电流通过所需的走线宽度例如 1mm, 以免造成印刷线路板过热， 导致电子元 件过热而工作异常。
图 7是用于说明多层印刷线路板的布线层上的虚设沟槽的第二实施例的图。 所述虚设沟槽 410, 420包括弧形槽。 图 8是用于说明多层印刷线路板的布线层上 的虚设沟槽的第三实施例的图。 所述虚设沟槽 510, 520包括封闭的椭圓形槽。 图 9是用于说明多层印刷线路板的布线层上的虚设沟槽的第四实施例的图。所述虚设 沟槽 610, 620包括曲线槽。 虚设沟槽 410, 420、 虚设沟槽 510, 520、 虚设沟槽 610, 620的整体的长度方向均与宽度方向 Y相同。 对于虚设沟槽 410, 420、 虚设 沟槽 510, 520、 虚设沟槽 610, 620, 其功能虚设沟槽 310, 320相同， 均用于削 弱铜箔区 240沿长度方向 X (长边方向）产生内应力的能力。 与当然， 虚设沟槽 310, 320、 虚设沟槽 410, 420、 虚设沟槽 510, 520、 虚设沟槽 610, 620可以釆 用其它的形状， 也可以组合使用。
根据本实用新型的多层印刷线路板， 通过在布线层的大片铜箔区上设有虚设 沟槽， 通过蚀刻掉部分（挖空） 的铜箔来减小大块的铜箔所产生的应力， 平衡各 层布线层的应力。 由此， 减小多层印刷线路板的板弯板翘， 提高多层印刷线路板 产品良率， 节约成本。
在应用本实用新型的多层印刷线路板时， 可以利用使用 Genesis2000 或 CAM350等商业软件对各个布线层的残铜率进行的计算， 分别比较各对称层面的 残铜率。 当对称层面 (对称层面即从最顶层与最底层往中间走， 相对于芯层相互对 称的层)的残铜率差异较大时， 在残铜率较大的布线层的非走线区域的铜箔上增加 虚设沟槽， 增加铜箔的膨月长力的同时， ^：大片铜箔产生的应力， 达到平衡对称 层面的膨胀力和应力的目的。
本文中， 印刷线路板是指印制电路板， 即 PCB ( Printed Circuit Board ); 印刷 线路板的弯曲或板弯板翘的量化方法为测量印刷线路板翘曲的高^/印刷线路板的 对角线长度； 残铜率是指印刷线路板的布线层的铜箔经蚀刻制程后残余的铜箔面 积占印刷线路板的布线层的总基板面积的比率。
以上具体实施方式对本实用新型进行了详细的说明， 但这些并非构成对本实 用新型的限制。 本实用新型的保护范围并不以上述实施方式为限， 但凡本领域普 通技术人员根据本实用新型所揭示内容所作的等效修饰或变化， 皆应纳入权利要 求书中记载的保护范围内。

Claims

权 利 要 求 书
1、 一种多层印刷线路板， 其中， 所述多层印刷线路板包括至少两层布线层 ( 112, 114, 116, 118)及夹设在所述至少两层布线层（ 112, 114, 116, 118)之 间的隔离层， 所述至少两层布线层（112, 114, 116, 118) 包括铜箔区（140), 所 述至少两层布线层（112, 114, 116, 118)中至少一层布线层上设有用于调整热应 力的虚设沟槽（150), 所述虚设沟槽（150)设置在所述铜箔区 （140)上。
2、 根据权利要求 1 所述的多层印刷线路板， 其中， 所述虚设沟槽（150) 以 移除铜箔的方式形成。
3、 根据权利要求 1 所述的多层印刷线路板， 其中， 所述虚设沟槽（150)设 置在铜箔区 （140) 的中部以减小铜箔因受热而产生的内应力。
4、 根据权利要求 1 所述的多层印刷线路板， 其中， 所述虚设沟槽（150)形 成在所述至少两层布线层（112, 114, 116, 118)中残铜率最大的布线层上以减小 各布线层的热应力之间的差异。
5、 根据权利要求 1所述的多层印刷线路板， 其中， 所述多层印刷线路板包括 顶部层（212)、 底部层（218)、 位于所述顶部层（212)与所述底部层（218)之 间的中间布线层， 所述底部层（218)的残铜率大于所述顶部层（212)的残铜率， 所述虚设沟槽设置在所述底部层（218) 的铜箔区 （240)上。
6、 根据权利要求 1所述的多层印刷线路板， 其中， 所述虚设沟槽的延伸方向 与所述多层印刷线路板的宽度方向 （Y)相对应。
7、根据权利要求 1所述的多层印刷线路板， 其中， 所述虚设沟槽（310, 320) 包括条形槽。
8、根据权利要求 1所述的多层印刷线路板，其中， 所述虚设沟槽包括弧形槽。
9、 根据权利要求 1所述的多层印刷线路板， 其中， 所述虚设沟槽包括封闭的 椭圓形槽。
10、 根据权利要求 1 所述的多层印刷线路板， 其中， 所述虚设沟槽包括曲线 槽。
11、 根据权利要求 1 所述的多层印刷线路板， 其中， 所述虚设沟槽设置在所 述至少两层布线层沿印刷线路板的高度方向为对称层面的两个布线层中的残铜率 较大的布线层上以平衡对称层面的热应力差异。
12、 根据权利要求 1 所述的多层印刷线路板， 其中， 所述虚设沟槽设置有多 段， 且各段虚设沟槽之间的最小距离大于 l mm。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007243088A (ja) * 2006-03-13 2007-09-20 Sumitomo Metal Electronics Devices Inc 多層セラミック基板及びその製造方法
US20110089138A1 (en) * 2009-10-20 2011-04-21 Young Gwan Ko Method of manufacturing printed circuit board
KR101172175B1 (ko) * 2010-08-03 2012-08-07 엘지이노텍 주식회사 인쇄회로기판 및 그의 제조 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007243088A (ja) * 2006-03-13 2007-09-20 Sumitomo Metal Electronics Devices Inc 多層セラミック基板及びその製造方法
US20110089138A1 (en) * 2009-10-20 2011-04-21 Young Gwan Ko Method of manufacturing printed circuit board
KR101172175B1 (ko) * 2010-08-03 2012-08-07 엘지이노텍 주식회사 인쇄회로기판 및 그의 제조 방법

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