WO2015008789A1 - はんだバンプ製造方法 - Google Patents
はんだバンプ製造方法 Download PDFInfo
- Publication number
- WO2015008789A1 WO2015008789A1 PCT/JP2014/068910 JP2014068910W WO2015008789A1 WO 2015008789 A1 WO2015008789 A1 WO 2015008789A1 JP 2014068910 W JP2014068910 W JP 2014068910W WO 2015008789 A1 WO2015008789 A1 WO 2015008789A1
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- WIPO (PCT)
- Prior art keywords
- solder
- bump
- forming paste
- flux
- base
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/11332—Manufacturing methods by local deposition of the material of the bump connector in solid form using a powder
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
- H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
- H01L2224/11849—Reflowing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
- H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
Definitions
- the present invention relates to a method for manufacturing a solder bump using a solder paste, and more particularly to a method for manufacturing a solder bump by printing and reflowing the solder paste.
- solder bumps are formed by forming a large number of solder bumps on a metal pad formed on a wafer or a substrate and mounting a semiconductor chip on the solder bumps, followed by heating. Flip chip mounting is performed in which a semiconductor chip is bonded to a pad by melting the substrate.
- solder bumps are formed, that is, during reflow, gas due to the flux contained in the solder paste is generated and may become voids and remain in the solder bumps. In this case, variations in bump height, a decrease in bonding strength between the solder and the electrode, and the like may result in a decrease in long-term reliability.
- solder bumps are formed by a bump forming paste that is a mixture of the above-described solder powder and flux and has a lower flux ratio than the base forming paste.
- Patent Document 1 describes that by forming a solder bump using a bump forming paste on a base layer, a solder bump without a large void can be formed and the uniformity of the bump height can be improved. .
- Patent Document 1 the amount of solder contained in the base forming paste is reduced to improve the wettability of the solder, and the generation of voids is suppressed by forming a thin base layer formed on the pad. Since solder bumps are becoming smaller in diameter due to the effects of downsizing and the like, and are becoming more susceptible to voids, further measures are desired.
- the present invention has been made in view of such circumstances, and an object of the present invention is to provide a method for producing a solder bump having a high effect of suppressing the generation of voids.
- a base forming paste formed by mixing a solder powder having an average particle diameter of 5 ⁇ m or less and a flux is applied onto a pad provided on a substrate and reflowed to form a base layer having a thickness of 20 ⁇ m or less.
- a base layer forming step and a bump forming paste formed by mixing a solder powder and a flux having an average particle size larger than that of the base forming paste are applied onto the base layer and reflowed to form solder bumps on the pad. And a bump forming process.
- solder powder in the paste is not evenly present on the pad surface, and if there are large gaps between the solder powders and local vacancies, there will be places where only the flux is present on the pad surface. It is conceivable as a cause of the generation of voids that it becomes difficult for the pad to wet and spread when it melts, and voids are easily captured at the interface with the pad.
- the average particle size of the solder powder in the underlayer forming paste is set to 5 ⁇ m or less so that the solder powder is uniformly present on the pad surface. It is possible to prevent voids from being generated at the interface between the pad and the underlying layer.
- the base layer is thinly formed to a thickness of 20 ⁇ m or less, it is easy to escape the gas generated during reflow of the base forming paste, and a void larger than the thickness of the base layer cannot be generated. The formation can be firmly attached to the pad.
- solder powder having a particle size larger than the average particle size of the solder powder of the base forming paste is used for bump formation. Even if it is used for paste, voids are not trapped at the pad interface, and voids remaining on the solder bumps can be reduced.
- the flux ratio in the base forming paste may be set to be larger than the flux ratio in the bump forming paste.
- the pad surface is improved in cleanliness by the flux, and the solder content is reduced because of the higher flux ratio. It becomes easy to spread on the surface. For this reason, a base layer is formed thinly on a pad, and generation
- the flux ratio is not increased in the bump forming paste, the viscosity of the paste can be maintained, and when the solder is melted to form a spherical solder bump with surface tension, the bump height is increased. Can be formed.
- the base forming paste has an average particle size of the solder powder of 1 ⁇ m to 5 ⁇ m, and a flux ratio of 20% by mass to 40% by mass.
- the paste may have an average particle size of the solder powder of more than 5 ⁇ m and 15 ⁇ m or less, and a flux ratio of 5% by mass to 15% by mass.
- voids generated at the interface with the pad can be reduced, and the effect of suppressing generation of voids In addition, it is possible to improve the bonding reliability.
- solder bump manufacturing method of this invention it is sectional drawing which showed typically the board
- FIGS. 2A to 2B sequentially show the process of forming solder bumps 4 on bump forming pads (hereinafter referred to simply as pads) 2 formed on the substrate 1.
- pads bump forming pads
- a base solder powder and a flux are applied at a predetermined flux ratio on the pad 2 disposed in the opening 7 of the resist layer 6.
- the mixed base formation paste 30 is applied with a predetermined thickness by printing using a stencil mask or printing and filling the openings 7 of the resist layer 6 directly without using a stencil mask (FIG. 1B). Then, reflow is performed to form the base layer 3 (FIG. 1C).
- a bump forming paste 40 obtained by mixing a solder powder of the same type as the solder powder for the base and a solder powder having an average particle size larger than the solder powder for the base and a flux on the base layer 3 is used as a stencil mask.
- a predetermined amount is supplied by printing used (FIG. 2A), and reflowed to form a substantially spherical solder bump 4 (FIG. 2B).
- a pad 2 is provided on a wiring pattern (not shown) at the bump forming position of the substrate 1 before the solder bump 4 is formed, and this pad 2 is made to face the opening 7.
- a resist layer 6 is provided in the state. These pads 2 and the resist layer 6 are formed by a known circuit board forming technique.
- solder powder constituting the base forming paste 30 and the bump forming paste 40 for example, an alloy powder of Sn—Ag—Cu type, Pb—Sn type, or the like is used.
- the flux contains a resin such as rosin, an activator, a thixotropic agent, and a solvent.
- a halogen-free type, an active (RA) type, a weakly active (RMA) type, a water-soluble type, or the like may be used. it can.
- the base forming paste 30 is a mixture of a solder powder having an average particle size of 1 ⁇ m or more and 5 ⁇ m or less and a flux, and a flux ratio of 20% by mass or more and 40% by mass or less.
- the bump forming paste 40 is a mixture of a solder powder having an average particle size of solder powder exceeding 5 ⁇ m and not more than 15 ⁇ m and a flux, and the flux ratio is not less than 5 mass% and not more than 15 mass%.
- the flux ratio of the base forming paste 30 is set larger than the flux ratio of the bump forming paste 40.
- the base layer 3 is formed on the pad 2 disposed in the opening 7 of the resist layer 6.
- the underlayer forming paste 30 is filled in the opening 7 (filling space S) and reflowed as it is to melt the solder and remove the flux.
- the base layer 3 has a thickness t of 20 ⁇ m or less and is lower than the height of the resist layer 6 formed around the pad 2. In this embodiment, the flux is removed, but the flux may remain.
- the solder powder in the base forming paste 30 By setting the average particle size of the solder powder in the base forming paste 30 to 5 ⁇ m or less, the solder powder is uniformly present on the surface of the pad 2, and voids are generated at the interface between the pad 2 and the base layer 3. Can be prevented. Further, by forming the underlayer 3 thin, it is easy to escape the gas generated during the reflow of the underlayer forming paste 30, and a large void larger than the thickness t of the underlayer 3 cannot be generated. Can be firmly attached to the pad 2.
- the average particle size of the solder powder constituting the base forming paste 30 is less than 1 ⁇ m, the surface of the powder is oxidized and the amount of reducing gas generated during reflow increases.
- the average particle size is more preferably 1 ⁇ m or more and 5 ⁇ m or less.
- the bump forming paste 40 is further supplied to the base layer 3 and the pad 2 and reflowed to form the solder bumps 4. Specifically, as shown in FIG. 2A, the filling space S is filled with the bump forming paste 40 and reflowed as it is, thereby melting the base layer 3 together with the solder powder of the bump forming paste 40, and the flux. Remove (FIG. 2B). Then, when cooled, a substantially hemispherical solder bump 4 is formed on the pad 2 of the substrate 1 by surface tension. The bump height of the solder bump 4 is formed to about 40 ⁇ m, for example.
- the bump forming paste 40 When the bump forming paste 40 is filled in the filling space S and reflowed, since the base layer 3 having almost no voids is already formed on the pad 2, the bump forming paste 40 is melted. The solder agglomerates on the pad 2 together with the molten underlayer 3. Thereby, solder bumps 4 with reduced voids are formed on the pads 2. Since the bump forming paste 40 is applied to the preformed base layer 3 to form the solder bumps 4, the particle size larger than the average particle size of the solder powder of the base forming paste 30 on the bump forming paste 40. Even if this solder powder is used, voids are not trapped at the interface of the pad 2 and voids remaining on the solder bumps 4 can be reduced.
- the flux content of the base forming paste 30 is increased, when the base layer 3 is formed, the cleanliness of the surface of the pad 2 is improved by the flux, and the solder easily spreads on the surface of the pad 2. In addition, since the solder content is reduced due to the higher flux ratio, the solder is likely to wet and spread on the surface of the pad 2. For this reason, the base layer 3 is formed thin on the pad 2, and generation of a large void can be prevented.
- the flux ratio is more preferably 20% by mass or more and 40% by mass or less because the paste is easily separated due to a change with time when the flux content of the base forming paste 30 is increased.
- the flux ratio is not increased in the bump forming paste 40, the viscosity of the paste can be maintained, and when the spherical solder bump 4 is formed by melting the solder and forming the spherical solder bump 4 with the surface tension, the bump height is increased. Can be formed. Moreover, since the solder bump 4 without a large void can be formed, the uniformity of the bump height can also be improved.
- the bump forming paste 40 preferably has an average particle size of the solder powder of more than 5 ⁇ m and 15 ⁇ m or less, and a flux ratio of 5% by mass to 15% by mass.
- the bump forming paste 40 is supplied onto the base layer 3 and reflowed. Therefore, it is possible to obtain the solder bump 4 with high bonding reliability of flip chip mounting without leaving a large void inside.
- a base forming paste was printed on a substrate provided with a resist layer patterned with an opening diameter of 110 ⁇ m and a thickness of 20 ⁇ m, and the maximum temperature was 240 in a nitrogen atmosphere.
- An underlayer was formed by reflowing at 0 ° C.
- it was cleaned using a pure water-based cleaning agent, and a bump forming paste was printed on the underlayer, and solder bumps were formed by reflowing at a maximum temperature of 240 ° C. in a nitrogen atmosphere. 2500 solder bumps were formed on each substrate.
- the size of the void was calculated as an area ratio by the ratio of the diameter of the void to the diameter of the solder bump.
- the maximum void area ratio was calculated for the largest void among them.
- each column of the number of void occurrence bumps in Table 2 the distribution range of voids having the size of each void area ratio is displayed.
- the numerical value on the left in Table 2 indicates “above” and the numerical value on the right indicates “less than”. For example, “0% to 2%” indicates 0% or more and less than 2%.
- the board having many solder bumps with large voids is defective and the maximum void area ratio is less than 6%.
- a sample having a solder bump in which a void having a size of 6% or more in the area is generated or a sample having 10 or more bumps having a void having a size of 4% or more is determined to be defective.
- “NG” is shown.
- a sample with good results a sample having a maximum void area ratio of less than 6% and an area ratio of 4% or more and less than 6% in each solder bump
- Examples 1 to 15 voids with an area ratio of 6% or more do not remain, and the distribution of generated voids is concentrated to an area ratio of less than 4%. Obtained.
- the thickness t of the underlayer is 20 ⁇ m or less
- the average particle size of the solder powder constituting the undercoat paste is 5 ⁇ m or less
- the average of the solder powder constituting the bump forming paste The particle size is larger than the average particle size of the solder powder of the base forming paste.
- the average particle size of the solder powder constituting the base forming paste is 0.5 ⁇ m, which is less than 1 ⁇ m, and the flux ratio is more than 40% by mass and 42% by mass.
- the number of void generation with an area ratio of 2% or more and less than 4% increased compared to other Examples.
- Comparative Example 1 in which the average particle size of the solder powder of the base forming paste exceeds 5 ⁇ m and Comparative Examples 1 and 2 in which the thickness t of the base layer exceeds 20 ⁇ m are both 10 or more voids with an area ratio of 4% or more.
- the maximum void area ratio exceeded 6%.
- Comparative Examples 3 and 4 in which the underlayer was not formed 10 or more voids having an area ratio of 4% or more were formed, and the maximum void area ratio exceeded 6%.
- Comparative Example 5 in Comparative Example 5 the underlying layer was not formed, and 10 or more voids having an area ratio of 4% or more were formed. However, the maximum void area ratio was less than 6%.
- voids generated at the interface with the pad can be reduced, and the effect of suppressing the generation of voids can be enhanced and bonding can be performed. Reliability can be increased.
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Abstract
Description
本願は、2013年7月18日に出願された特願2013-149560号に基づき優先権を主張し、その内容をここに援用する。
図1A~図1C及び図2A~図2Bは、基板1上に形成されたバンプ形成用パッド(Under Bump Metal,以下、単にパッドという)2に対して、はんだバンプ4を形成する工程を順に示したものである。
(下地層形成工程)
まず、レジスト層6の開口部7内に配置されたパッド2上に、下地層3形成する。具体的には、図1Bに示すように、下地形成用ペースト30を開口部7内(充填空間S)に充填し、そのままリフローすることによりはんだを溶融させるとともにフラックスを除去し、下地層3を形成する(図1C)。この下地層3の厚みtは20μm以下とされ、パッド2周辺に形成されたレジスト層6の高さよりも低く形成される。なお、本実施形態では、フラックスを除去したが、フラックスが残留していても構わない。
次いで、バンプ形成用ペースト40を、下地層3及びパッド2に対してさらに供給し、リフローしてはんだバンプ4を形成する。具体的には、図2Aに示すように、充填空間S内にバンプ形成用ペースト40を充填し、そのままリフローすることにより、バンプ形成用ペースト40のはんだ粉末とともに下地層3を溶融させ、フラックスを除去する(図2B)。その後冷却すると、表面張力により基板1のパッド2上に略半球状のはんだバンプ4が形成される。はんだバンプ4のバンプ高さは、例えば40μm程度に形成される。
表1に示すように、含有するはんだ粉末の平均粒径や成分、フラックス比率等を変更して作製した下地形成用ペースト及びバンプ形成用ペーストを用いて、基板上に複数のはんだバンプを形成した試料(実施例1~15および比較例1~5)を形成し、各試料について発生したボイドを確認した。
なお、下地用形成ペースト及びバンプ形成用ペーストのフラックスには、活性(RA)タイプのものを用いた。比較例3~5については、下地層を形成することなく、パッドに直接バンプ形成用ペーストを印刷してはんだバンプを形成した。
2 パッド
3 下地層
4 はんだバンプ
5 配線パターン
6 レジスト層
7 開口部
30 下地形成用ペースト
40 バンプ形成用ペースト
Claims (3)
- 基板上に設けられたパッド上に、平均粒径5μm以下のはんだ粉末及びフラックスを混合してなる下地形成用ペーストを塗布し、リフローして厚み20μm以下の下地層を形成する下地層形成工程と、
平均粒径が前記下地形成用ペーストより大きいはんだ粉末及びフラックスを混合してなるバンプ形成用ペーストを前記下地層上に塗布し、リフローしてはんだバンプを前記パッド上に形成するバンプ形成工程と
を備えることを特徴とするはんだバンプ製造方法。 - 前記下地形成用ペースト中の前記フラックスの比率が、前記バンプ形成用ペースト中の前記フラックスの比率よりも大きく設定されることを特徴とする請求項1記載のはんだバンプ製造方法。
- 前記下地形成用ペーストは、前記はんだ粉末の平均粒径が1μm以上5μm以下で、フラックスの比率が20質量%以上40質量%以下とされ、
前記バンプ形成用ペーストは、前記はんだ粉末の平均粒径が5μmを超えて15μm以下で、フラックスの比率が5質量%以上15質量%以下とされる
ことを特徴とする請求項1に記載のはんだバンプ製造方法。
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KR1020167000522A KR20160033098A (ko) | 2013-07-18 | 2014-07-16 | 땜납 범프 제조 방법 |
CN201480032887.0A CN105283949A (zh) | 2013-07-18 | 2014-07-16 | 焊锡凸块的制造方法 |
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JP2013149560A JP6263885B2 (ja) | 2013-07-18 | 2013-07-18 | はんだバンプ製造方法 |
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KR (1) | KR20160033098A (ja) |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02150031A (ja) * | 1988-11-30 | 1990-06-08 | Fujitsu Ltd | はんだバンプの形成方法 |
JP2006165336A (ja) * | 2004-12-08 | 2006-06-22 | Mitsubishi Materials Corp | バンプ形成用ハンダペースト |
JP2010109022A (ja) * | 2008-10-29 | 2010-05-13 | Mitsubishi Materials Corp | はんだバンプの形成方法 |
Family Cites Families (2)
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JPS5821430B2 (ja) * | 1975-03-07 | 1983-04-30 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JP2013004929A (ja) * | 2011-06-21 | 2013-01-07 | Mitsubishi Materials Corp | はんだバンプ製造方法および下地形成用ペースト |
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2013
- 2013-07-18 JP JP2013149560A patent/JP6263885B2/ja not_active Expired - Fee Related
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2014
- 2014-07-16 CN CN201480032887.0A patent/CN105283949A/zh active Pending
- 2014-07-16 WO PCT/JP2014/068910 patent/WO2015008789A1/ja active Application Filing
- 2014-07-16 KR KR1020167000522A patent/KR20160033098A/ko not_active Application Discontinuation
- 2014-07-17 TW TW103124527A patent/TWI613741B/zh not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02150031A (ja) * | 1988-11-30 | 1990-06-08 | Fujitsu Ltd | はんだバンプの形成方法 |
JP2006165336A (ja) * | 2004-12-08 | 2006-06-22 | Mitsubishi Materials Corp | バンプ形成用ハンダペースト |
JP2010109022A (ja) * | 2008-10-29 | 2010-05-13 | Mitsubishi Materials Corp | はんだバンプの形成方法 |
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JP2015023129A (ja) | 2015-02-02 |
TWI613741B (zh) | 2018-02-01 |
KR20160033098A (ko) | 2016-03-25 |
CN105283949A (zh) | 2016-01-27 |
JP6263885B2 (ja) | 2018-01-24 |
TW201513243A (zh) | 2015-04-01 |
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