WO2015000355A1 - Igbt制造方法 - Google Patents

Igbt制造方法 Download PDF

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Publication number
WO2015000355A1
WO2015000355A1 PCT/CN2014/079820 CN2014079820W WO2015000355A1 WO 2015000355 A1 WO2015000355 A1 WO 2015000355A1 CN 2014079820 W CN2014079820 W CN 2014079820W WO 2015000355 A1 WO2015000355 A1 WO 2015000355A1
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Prior art keywords
substrate
igbt
type
manufacturing
conductivity type
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PCT/CN2014/079820
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English (en)
French (fr)
Inventor
黄璇
王万礼
王根毅
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无锡华润上华半导体有限公司
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Priority to US14/902,205 priority Critical patent/US9553164B2/en
Publication of WO2015000355A1 publication Critical patent/WO2015000355A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT

Definitions

  • the present invention relates to the field of semiconductor design and manufacturing technology, and in particular to an IGBT (Insulated Gate Bipolar) Transistor, a method of manufacturing an insulated gate bipolar transistor.
  • IGBT Insulated Gate Bipolar
  • IGBT is made of BJT (Bipolar Junction Transistor) Composite fully-regulated voltage-driven power semiconductor device composed of MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor), combining high input impedance of MOSFET and low on-state voltage of BJT
  • MOSFET Metal-Oxide-Semiconductor-Field-Effect-Transistor
  • FWD Freewheeling Diode
  • parallel freewheeling diodes can be integrated in the IGBT chip, ie with built-in diodes or reverse-conducting IGBTs.
  • a common reverse-conducting IGBT requires thinning and double-sided lithography to produce an implant window for the backside P+ collector region.
  • the shortcomings of this kind of solution mainly have two aspects: First, there is a need to reduce the throughput of the wafer, especially for the common IGBTs below 1200V, the thickness of which is below 200 ⁇ m, which requires high throughput of the sheet; second, A special double exposure machine is required to expose the wafer.
  • existing reverse conducting IGBTs typically employ backside lithography.
  • a method of fabricating an IGBT comprising: providing a substrate of a first conductivity type or a second conductivity type having a first surface and a second surface; forming a groove at a first surface of the substrate; Filling a recess with a second conductivity type or a first conductivity type semiconductor material to form a channel, wherein the channel has a conductivity type different from that of the substrate; bonding is formed on the first surface of the substrate a drift region of a second conductivity type; forming a front side structure of the IGBT based on the drift region; and thinning the substrate from a second surface of the substrate until the channel is exposed, at which time the channel and The thinned substrate spaces are staggered; a back metal electrode is formed on the via and the thinned substrate, the back metal electrode being in electrical contact with the via and the thinned substrate.
  • the substrate is provided to have a thickness of 100 ⁇ m to 650 ⁇ m and a resistivity of 0.001 ⁇ *cm to 100. ⁇ *cm.
  • the drift region formed by bonding has a thickness of 10 ⁇ m to 650 ⁇ m and a resistivity of 5 ⁇ *cm to 500. ⁇ *cm.
  • the sum of the thickness of the substrate and the thickness of the drift region formed by the bonding is the normal flow silicon wafer thickness.
  • the normally flowing silicon wafer is a 6 inch silicon wafer having a thickness of 625 microns or 675 microns, or an 8 inch silicon wafer having a thickness of 725 microns.
  • spaced grooves are formed on the first surface of the substrate by photolithography, etching processes.
  • the groove has a depth of 0.5 ⁇ m ⁇ 50 ⁇ m.
  • the filled semiconductor material is changed into single crystal silicon by a high temperature step, and then the substrate is planarized by a chemical mechanical polishing process. The first surface.
  • the front structure of the IGBT includes: a selectively formed first conductivity type base region on an upper surface of the drift region; and a selectively formed portion in the base region a second conductivity type emitter region; a gate oxide layer on an upper surface of the drift region; a polysilicon gate formed on an upper surface of the gate oxide layer; covering the gate oxide layer and the polysilicon gate a dielectric layer; a front side metal electrode in electrical contact with the base region and the emitter region; and a passivation layer formed on the outside of the front metal electrode.
  • the first conductivity type is a P type and the second conductivity type is an N type.
  • the manufacturing method of the above IGBT first completes the fabrication of the collector regions and the channels which are spaced apart from each other on the back side of the IGBT, and then prepares the front structure of the IGBT on the bonding drift region, and only needs to be thinned and back metallized after the front structure is completed. In the step, there is no special requirement for the sheet flow capacity, and there is no need for a double-sided exposure machine.
  • FIG. 1 is a flow chart of a method of fabricating an IGBT in an embodiment
  • one embodiment or “an embodiment” as used herein refers to a particular feature, structure, or characteristic that can be included in at least one implementation of the invention.
  • the surface on which the emitter and the gate of the IGBT are located is generally understood to be the front side, and the surface on which the collector of the IGBT is located is generally understood to be the reverse side.
  • a method of fabricating an IGBT includes the following steps.
  • Step S110 in conjunction with FIG. 2, provides a P-type or N-type substrate 10 having a first surface 11 and a second surface 12.
  • the substrate 10 may have a thickness of 100 ⁇ m to 650 ⁇ m and a resistivity of 0.001 ⁇ *cm to 100. ⁇ *cm.
  • the thickness of the substrate 10 is related to the thickness of the bonding drift region mentioned below.
  • Step S120 as shown in FIG. 3, spaced grooves 13 are formed on the first surface 11 of the substrate 10 by photolithography and etching processes. Specifically, the depth of the groove may be 0.5 ⁇ m ⁇ 50 ⁇ m.
  • Step S130 in conjunction with FIG. 4, fills the recess 13 with an N-type or P-type semiconductor material to form an N-type or P-type via 14.
  • the substrate material 10 is P-type and the channel 14 is N-type as an example.
  • the recess 13 is filled with an N-type semiconductor material (such as single crystal silicon, polycrystalline silicon, amorphous silicon), and the filled semiconductor material is converted into single crystal silicon by a high temperature step to be activated.
  • the subsequent N-type channel 14 is then planarized by a chemical mechanical polishing (CMP) process to the first surface 11 of the substrate 10.
  • CMP chemical mechanical polishing
  • Activation of the N-type channel 14 in prior art processes typically occurs after the formation of the front side metal electrode, while the activation steps in the present invention occur prior to the formation of the metal electrode, increasing the activation of the doped region (such as the N-type channel 14). effectiveness.
  • step S140 in combination with FIG. 5, an N-type drift region (N Drift) 15 is bonded on the first surface 11 of the substrate 10.
  • the drift region 15 formed by bonding has a thickness of 10 ⁇ m to 650 ⁇ m and a resistivity of 5 ⁇ *cm to 500. ⁇ *cm.
  • the thickness of the drift region 15 is related to the thickness of the substrate 10.
  • the sum of the thickness of the substrate 10 and the thickness of the drift region formed by the bonding is the thickness of the normal circulating silicon wafer, for example, the normal thickness of the 6-inch sheet is 625.
  • the normal thickness of the ⁇ m/675 ⁇ m, 8-inch sheet is 725 ⁇ m.
  • Step S150 in combination with FIG. 6, forms a front structure of the IGBT based on the drift region 15 using a normal IGBT process flow.
  • the front structure of a planar IGBT is illustrated in FIG.
  • the front side structure of the IGBT includes a selectively formed P-type body (P-body) 16 on the upper surface of the drift region 15, and selectively forming an N-type emission in the P-type base region 16 a polar region 17, a gate oxide layer 18 on the upper surface of the drift region 15, a polysilicon gate 19 (G) formed on the gate oxide layer 18, covering the gate oxide layer 18 and the polysilicon gate A dielectric layer 20 of the pole 19, and a front side metal electrode 21 (i.e., emitter E) in electrical contact with the P-type base region 16 and the N-type emitter region 17.
  • P-body P-type body
  • G polysilicon gate 19
  • the front metal electrode 21 is only schematically shown in FIG. 6, and in fact, the front metal electrode 21 may cover the entire dielectric layer 20. Further, the front surface structure of the IGBT may further include a passivation layer (not shown) formed on the outside of the front surface metal electrode 21, such as silicon oxide and silicon nitride.
  • a trench IGBT may also be fabricated.
  • the front structure of the trench IGBT is different from the front structure of the IGBT in FIG. 6, but many trench IGBTs have been disclosed in the prior art. The description will not be repeated here. It is to be understood that, from a certain aspect of the present invention, the present invention does not particularly concern the specific front structure of the IGBT as long as it has a front side structure and can form an IGBT device that can be used.
  • the specific manufacturing process of the front structure of the IGBT is not the focus of the present invention, and it can be manufactured by using various existing manufacturing processes, so in order to highlight the focus of the present invention, the front side of the IGBT is concerned.
  • the specific manufacturing process of the structure is not described in detail herein.
  • Step S160 starting from the second surface of the substrate 10, thinning the substrate 22 until the channel 14 is exposed, and the thinned substrate 22 is spaced apart from the channel 14 in a staggered arrangement. .
  • the thinned substrate 22 forms a P-type collector region, and the N-type channel 14 forms a N-type cathode region; when the substrate 10 is N-type, The channel 14 forms a P-type collector region, and the thinned N-type substrate 22 forms an N-type cathode region.
  • the N-type cathode region, the N-type drift region 15 and the P-type base region 16 together form a PIN type (positive Intrinsic negative diode)
  • the IGBT in the present invention may also be referred to as a reverse conducting IGBT.
  • the substrate 10 may be thinned by a grinding process.
  • Step S170 in conjunction with FIG. 8, a back metal electrode (collector C) 23 is formed on the outside of the channel 14 and the thinned substrate 22 by sputtering or evaporation.
  • the back metal electrode 23 and the The channel 14 is in electrical contact with the thinned substrate 22.
  • one of ordinary skill in the art will appreciate that one of the features or objects of the present invention is to first complete the fabrication of mutually spaced P-type collector regions and N-type channels on the back side of the IGBT, followed by bonding drift regions.
  • the front structure of the IGBT is prepared on the 15th. After the front structure is completed, only the thinning and back metallization steps are required, so that there is no special requirement for the sheet flowability, and no double-sided exposure machine is needed.
  • the P type in the above embodiment may be referred to as a first conductivity type, and the N type may be referred to as a second conductivity type.
  • all of the P-type regions (such as the P-base region and the P-type collector region) involved in the above embodiments may be changed to N-type, and all N-type regions (N-type drift regions)
  • the N-type emitter region and the N-type cathode region can all be changed to P-type.
  • the first conductivity type can be considered to be N-type
  • the second conductivity type is P-type.

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • General Chemical & Material Sciences (AREA)
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Abstract

一种IGBT的制造方法，包括：提供具有第一表面和第二表面的第一或第二导电类型的衬底；在所述衬底的第一表面形成间隔的凹槽；在所述凹槽内填充第二或第一导电类型的半导体材料以形成通道，其中所述通道的导电类型与所述衬底的导电类型不同；在所述衬底的第一表面上键合形成第二导电类型的漂移区；基于所述漂移区形成所述IGBT的正面结构；自所述衬底的第二表面开始减薄所述衬底直到露出所述通道；在所述通道和减薄后的衬底上形成背面金属电极。上述方法对薄片流通能力没有特殊要求，更不需要双面曝光机设备，与现有的常规工艺兼容，工艺简单、效率高。

Description

IGBT制造方法
【技术领域】
本发明涉及半导体设计及制造技术领域，特别涉及一种IGBT（Insulated Gate Bipolar Transistor，绝缘栅双极晶体管）的制造方法。
【背景技术】
IGBT是由BJT （Bipolar Junction Transistor，双极结型晶体管） 和MOSFET（Metal-Oxide-Semiconductor-Field-Effect-Transistor，金属氧化物半导体场效应晶体管）组成的复合全控型电压驱动式功率半导体器件，兼有MOSFET的高输入阻抗和BJT的低导通压降两方面的优点，具有工作频率高，控制电路简单，电流密度高，通态压低等特点，广泛应用于功率控制领域。在实际应用中，IGBT很少作为一个独立器件使用，尤其在感性负载的条件下，IGBT需要一个快恢复二极管续流。因此，现有的绝缘栅双极晶体管产品，一般采用并联一个续流二极管（Freewheeling diode ，简称FWD）以保护IGBT。为了降低成本，并联的续流二极管可以集成在IGBT芯片内，即具有内置二极管或反向导通的IGBT。
常见的反向导通的IGBT需要减薄后双面光刻制备出背面P+集电极区的注入窗口。这种方案的缺点主要有两个方面：第一、需要有减薄晶圆流通能力，特别是对于常见的1200V以下的IGBT，其厚度在200μm以下，对薄片流通工艺要求很高；第二、需要专门的双面曝光机对晶圆曝光。此外，现有的反向导通的IGBT通常采用背面两次光刻技术。
【发明内容】
基于此，有必要提供一种对薄片流通能力没有特殊要求，更不需要双面曝光机的IGBT制备方法。
一种IGBT的制造方法，包括：提供具有第一表面和第二表面的第一导电类型或第二导电类型的衬底；在所述衬底的第一表面形成间隔的凹槽；在所述凹槽内填充第二导电类型或第一导电类型的半导体材料以形成通道，其中所述通道的导电类型与所述衬底的导电类型不同；在所述衬底的第一表面上键合形成第二导电类型的漂移区；基于所述漂移区形成所述IGBT的正面结构；和自所述衬底的第二表面开始减薄所述衬底直到露出所述通道，此时所述通道和减薄后的衬底间隔交错排布；在所述通道和减薄后的衬底上形成背面金属电极，该背面金属电极与所述通道和减薄后的衬底电性接触。
在其中的一个实施例中，提供的衬底的厚度为100 μm -650 μm，电阻率为0.001 Ω*cm ~100 Ω*cm。键合形成的漂移区的厚度为10 μm ~650 μm，电阻率为5 Ω*cm ~500 Ω*cm。所述衬底的厚度和所述键合形成的漂移区的厚度的和为正常流通硅片厚度。
在其中的一个实施例中，所述正常流通硅片是厚度为625微米或675微米的6英寸硅片，或者是厚度为725微米的8英寸硅片。
在其中的一个实施例中，通过光刻、蚀刻工艺在在所述衬底的第一表面形成间隔的凹槽。所述凹槽的深度为0.5 μm ~50 μm。
在其中的一个实施例中，在填充第二导电类型或第一导电类型的半导体材料后，通过高温步骤使填充的半导体材料变成单晶硅，随后通过化学机械抛光工艺平整所述衬底的第一表面。
在其中的一个实施例中，所述IGBT的正面结构包括：在所述漂移区的上表面上有选择的形成的第一导电类型的基区；在所述基区内有选择的形成的第二导电类型的发射极区；位于所述漂移区的上表面上的栅氧化层；在所述栅极氧化层的上表面上形成的多晶硅栅极；覆盖所述栅极氧化层和多晶硅栅极的介质层；与所述基区和所述发射极区电性接触的正面金属电极；形成于正面金属电极外侧的钝化层。
在其中的一个实施例中，所述第一导电类型为P型，所述第二导电类型为N型。
上述IGBT的制造方法，首先完成IGBT的背面的相互间隔的集电极区和通道的制作，之后在键合漂移区上制备IGBT的正面结构，在正面结构完成后仅需要做减薄和背面金属化步骤，对薄片流通能力没有特殊要求，更不需要双面曝光机设备。
【附图说明】
为了更清楚地说明本发明实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其它的附图。其中：
图1为一实施例中的IGBT制造方法的流程图；
[根据细则91更正 25.08.2014]　
图2至图8为图1中的制造方法的各个制造工序得到晶圆的纵剖面示意图。
【具体实施方式】
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本发明作进一步详细的说明。
此处所称的“一个实施例”或“实施例”是指可包含于本发明至少一个实现方式中的特定特征、结构或特性。在本说明书中不同地方出现的“在一个实施例中”并非均指同一个实施例，也不是单独的或选择性的与其他实施例互相排斥的实施例。
在介绍本发明中的IGBT的制造方法之前，需要说明的是，IGBT的发射极和栅极所在的面通常被理解为正面，而IGBT的集电极所在的面通常被理解反面。
如图1所示，在一个实施例中，一种IGBT的制造方法包括如下步骤。
步骤S110，结合图2所示，提供具有第一表面11和第二表面12的P型或N型衬底10。
具体的，所述衬底10的厚度可以为100 μm ~ 650 μm，电阻率可以为0.001 Ω*cm ~100 Ω*cm。所述衬底10的厚度与下文提到的键合漂移区的厚度相关。
步骤S120，如图3所示，通过光刻、蚀刻工艺在所述衬底10的第一表面11形成间隔的凹槽13。具体的，所述凹槽的深度可以为0.5 μm ~ 50 μm。
步骤S130，结合图4所示，在所述凹槽13内填充N型或P型半导体材料以形成N型或P型通道14。
在所述衬底为P型时，所述步骤S130中形成N型通道，在所述衬底10为N型时，所述步骤S130中形成P型通道，两者之间的导电类型相反。在图2-7所示出的实施例中，以衬底材料10为P型，通道14为N型为例进行介绍。具体的，如图3所示，在所述凹槽13内填充N型半导体材料(比如单晶硅、多晶硅、非晶硅)，通过高温步骤使填充的半导体材料变成单晶硅从而得到激活后的N型通道14，随后通过化学机械抛光(CMP)工艺平整所述衬底10的第一表面11。在图3中的光刻胶30可以在合适步骤中被去除。
在现有工艺中的N型通道14的激活通常发生在正面金属电极形成之后，而本发明中的激活步骤都发生在金属电极形成之前，提高了掺杂区域(比如N型通道14)的激活效率。
步骤S140，结合图5所示，在所述衬底10的第一表面11上键合形成N型漂移区(N Drift)15。
具体的，键合形成的漂移区15的厚度为10 μm ~ 650 μm，电阻率为5 Ω*cm ~ 500 Ω*cm。所述漂移区15的厚度与所述衬底10的厚度相关。所述衬底10的厚度和所述键合形成的漂移区的厚度的和为正常流通硅片厚度，比如对于6寸片的正常厚度为625 μm/675 μm，8寸片的正常厚度为725 μm。
步骤S150，结合图6所示，基于所述漂移区15采用正常IGBT工艺流程形成所述IGBT的正面结构。
图6中示意出了一种平面IGBT的正面结构。所述IGBT的正面结构包括：在所述漂移区15的上表面上有选择的形成的P型基区(P-body)16，在所述P型基区16内有选择的形成N型发射极区17，位于所述漂移区15的上表面上的栅氧化层18，在所述栅极氧化层18上形成的多晶硅栅极19(G)，覆盖所述栅极氧化层18和多晶硅栅极19的介质层20，以及与所述P型基区16和所述N型发射极区17电性接触的正面金属电极21(即发射极E)。
图6中只是示意性的示出了正面金属电极21，事实上，正面金属电极21可能会覆盖整个介质层20。此外，所述IGBT的正面结构还可能包括形成于正面金属电极21外侧的钝化层(未示出)，比如二氧化硅和氮化硅。
在其他实施例中，也可以制造沟槽型IGBT，所述沟槽型IGBT的正面结构与图6中的IGBT的正面结构并不相同，不过现有技术中已经公开了很多沟槽型IGBT，这里就不再重复描述了。需要知晓的是，从本发明的某个角度来说，本发明并不特别关心IGBT的具体正面结构，只要有正面结构并且能形成可以使用的IGBT器件即可。
从另一个角度来讲，有关IGBT的正面结构的具体制造工艺也不属于本发明的重点，其可以采用现有的各种制造工艺制造而成，因此为了突出本发明的重点，有关IGBT的正面结构的具体制造工艺在本文中并未被详细描述。
步骤S160，结合图7所示，自所述衬底10的第二表面开始减薄所述衬底22直到露出所述通道14，减薄后的衬底22与所述通道14间隔交错排布。
在所述衬底10为P型时，减薄后的衬底22形成P型集电极区，所述N型通道14形成型N型阴极区；在所述衬底10为N型时，所述通道14形成P型集电极区，减薄后的N型衬底22形成N型阴极区。所述N型阴极区、N型漂移区15和P型基区16共同形成一个PIN型(positive intrinsic negative diode)反向二极管，本发明中的IGBT也可以被称为反向导通的IGBT。
具体的，可以通过研磨(Grinding)工艺对所述衬底10进行减薄。
步骤S170，结合图8所示，在所述通道14和减薄后的衬底22外侧通过采用溅射或蒸发的方式制得背面金属电极(集电极C)23，该背面金属电极23与所述通道14和所述减薄后的衬底22电性接触。
所属领域内的普通技术人员应该能够理解的是，本发明的特点或目的之一在于：首先完成IGBT的背面的相互间隔的P型集电极区和N型通道的制作，之后在键合漂移区15上制备IGBT的正面结构，在正面结构完成后仅需要做减薄和背面金属化步骤，这样对薄片流通能力没有特殊要求，更不需要双面曝光机设备。
上述实施例中的P型可以被称为第一导电类型，N型可以被称为第二导电类型。在其他实施例中，上述实施例中的所涉及的所有P型的区域(比如P基区、P型集电极区)都可以更改为N型的，所有的N型的区域(N型漂移区、N型发射极区、N型阴极区)都可以更改为P型，此时可以认为第一导电类型是N型，第二导电类型为P型。
需要指出的是，熟悉该领域的技术人员对本发明的具体实施方式所做的任何改动均不脱离本发明的权利要求书的范围。相应地，本发明的权利要求的范围也并不仅仅局限于前述具体实施方式。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (12)

  1. 一种IGBT的制造方法，其特征在于，包括：
    提供具有第一表面和第二表面的衬底；
    在所述衬底的所述第一表面形成间隔的凹槽；
    在所述凹槽内填充半导体材料以形成通道，其中所述通道的导电类型与所述衬底的导电类型不同；
    在所述衬底的第一表面上键合形成漂移区；
    基于所述漂移区形成所述IGBT的正面结构；
    自所述衬底的第二表面开始减薄所述衬底直到露出所述通道，此时所述通道和减薄后的衬底间隔交错排布；及
    在所述通道和所述减薄后的衬底上形成背面金属电极，所述背面金属电极与所述通道和所述减薄后的衬底电性接触。
  2. 根据权利要求1所述的IGBT的制造方法，其特征在于，提供的衬底的厚度为100 μm -650 μm，电阻率为0.001 Ω*cm ~100 Ω*cm。
  3. 根据权利要求1所述的IGBT的制造方法，其特征在于，键合形成的漂移区的厚度为10 μm ~ 650 μm，电阻率为5 Ω*cm ~500 Ω*cm。
  4. 根据权利要求1所述的IGBT的制造方法，其特征在于，所述衬底的厚度和键合形成的漂移区的厚度的和为正常流通硅片厚度。
  5. 根据权利要求4所述的IGBT的制造方法，其特征在于，所述正常流通硅片是厚度为625微米或675微米的6英寸硅片，或者是厚度为725微米的8英寸硅片。
  6. 根据权利要求1所述的IGBT的制造方法，其特征在于，通过光刻、蚀刻工艺在在所述衬底的第一表面形成间隔的凹槽。
  7. 根据权利要求6所述的IGBT的制造方法，其特征在于，所述凹槽的深度为0.5 μm ~ 50 μm。
  8. 根据权利要求6所述的IGBT的制造方法，其特征在于，在填充第二导电类型或第一导电类型的半导体材料后，通过高温步骤使填充的半导体材料变成单晶硅，随后通过化学机械抛光工艺平整所述衬底的第一表面。
  9. 根据权利要求1所述的IGBT的制造方法，其特征在于，所述IGBT的正面结构包括：
    第一导电类型的基区，有选择的形成在所述漂移区的上表面；
    第二导电类型的发射极区，有选择的形成在所述基区内；
    栅氧化层，位于所述漂移区的上表面；
    多晶硅栅极，形成在所述栅极氧化层的上表面；
    介质层，覆盖所述栅极氧化层和多晶硅栅极；
    正面金属电极，与所述基区和所述发射极区电性接触。
  10. 根据权利要求9所述的IGBT的制造方法，其特征在于，所述IGBT的正面结构包括：
    形成于正面金属电极外侧的钝化层。
  11. 根据权利要求1-10中任一所述的IGBT的制造方法，其特征在于，所述第一导电类型为P型，所述第二导电类型为N型。
  12. 根据权利要求1所述的IGBT的制造方法，其特征在于，所述漂移区为N型。
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