WO2014206160A1 - Transistor bipolaire à grille isolée et procédé de fabrication associé - Google Patents

Transistor bipolaire à grille isolée et procédé de fabrication associé Download PDF

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Publication number
WO2014206160A1
WO2014206160A1 PCT/CN2014/078203 CN2014078203W WO2014206160A1 WO 2014206160 A1 WO2014206160 A1 WO 2014206160A1 CN 2014078203 W CN2014078203 W CN 2014078203W WO 2014206160 A1 WO2014206160 A1 WO 2014206160A1
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Prior art keywords
semiconductor substrate
insulated gate
active region
main surface
layer
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PCT/CN2014/078203
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English (en)
Chinese (zh)
Inventor
张硕
芮强
王根毅
邓小社
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无锡华润上华半导体有限公司
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Publication of WO2014206160A1 publication Critical patent/WO2014206160A1/fr

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    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
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    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
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    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions

Definitions

  • the present invention relates to the field of semiconductor design and manufacturing technology, and in particular to an insulated gate bipolar transistor (Insulated Gate) Bipolar Transistor, IGBT) and its manufacturing method.
  • IGBT Insulated Gate Bipolar Transistor
  • IGBT is made up of bipolar junction transistors (Bipolar Junction) Transistor, BJT) and Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) composite fully-regulated voltage-driven power semiconductor devices with high input impedance of MOSFET and BJT
  • BJT Bipolar Junction transistors
  • MOSFET Metal-Oxide-Semiconductor-Field-Effect-Transistor
  • FWD Freewheeling Diode
  • the parallel freewheeling diodes can be integrated in the IGBT chip, ie the reverse conducting IGBT.
  • the reverse conducting IGBT is usually subjected to a back surface two-lithography technique, which selectively implants and diffuses to form a spacer N+ region and a P+ region, and the N+ region and the P+ region are distributed throughout the back surface region of the IGBT.
  • the entire back surface region includes an active region and a termination protection region), resulting in poor recovery characteristics of the built-in diode of this type of IGBT.
  • An IGBT comprising: a first conductivity type semiconductor substrate having a first major surface and a second major surface, wherein the semiconductor substrate includes an active region and termination protection disposed outside the active region
  • An insulated gate type transistor cell formed on a first main surface side of the active region, which is formed with a channel of a first conductivity type when it is turned on; and a second main surface side of the semiconductor substrate a trench formed and a semiconductor layer of a second conductivity type, wherein the trench and the semiconductor layer are spaced apart from each other on a second main surface side of the active region, and only a semiconductor layer is formed at the terminal The second main side of the protected area.
  • the IGBT further includes: a protection terminal formed on a first main surface side of the termination protection region; on a first main surface of the first conductivity type semiconductor substrate on which the insulated gate transistor unit is formed
  • the formed IGBT uses a first main electrode; the IGBT formed on the trench and the semiconductor layer is a second main electrode, and the second main electrode is in electrical contact with the semiconductor substrate through the trench.
  • the depth of the trench is greater than the thickness of the semiconductor layer.
  • the first conductivity type is N-type and the second conductivity type is P-type.
  • the insulated gate transistor unit is an N-channel MOSFET unit
  • the first conductive type semiconductor substrate is an N-type semiconductor substrate
  • the semiconductor layer is a P+ type collector layer
  • the first main The electrode is an emitter
  • the second main electrode is a collector, wherein "+" in N-, P+ indicates a high doping concentration, and "-" indicates a low doping concentration.
  • the N-channel MOSFET cell includes: a P-well selectively formed from the first main surface of the active region in the N-type semiconductor substrate; from the P-well a surface of the P+ well having a selectively formed N+ active region; a selectively formed gate oxide layer on the first major surface of the active region, wherein the gate oxide layer is located in the P well a first main surface of the edge portion and a first main surface of the active region where the P well is not formed; a polysilicon gate electrode formed on an upper surface of the gate oxide layer; covering the gate oxide layer And the polysilicon gate electrode exposes the dielectric layer of the surface.
  • the first main electrode is formed outside the dielectric layer and is in electrical contact with the N+ active region and the P well.
  • a method of fabricating an IGBT comprising: preparing a semiconductor substrate of a first conductivity type having a first major surface and a second major surface, the semiconductor substrate including an active region and being disposed outside the active region a termination protection region; forming an insulated gate transistor unit on a first main surface side of the active region of the semiconductor substrate; and thinning the insulated gate transistor unit from a second main surface of the semiconductor substrate a semiconductor substrate; a second main surface of the self-thinned semiconductor substrate is formed in the semiconductor substrate to form a trench and a second conductivity type semiconductor layer, wherein the trench and the second conductivity type semiconductor layer are spaced apart from each other
  • the second main surface side of the active region is formed on the second main surface side of the active region, and only the second conductive type semiconductor layer is formed on the second main surface side of the terminal protection region.
  • the method of fabricating the IGBT further includes: forming a protection terminal on a first main surface side of the termination protection region; forming on a first main surface of the semiconductor substrate forming an insulated gate transistor unit
  • the IGBT uses a first main electrode; and a second main surface of the semiconductor substrate after the trench and the second conductivity type semiconductor layer are formed to be in electrical contact with the semiconductor substrate through the trench.
  • the IGBT which is also in contact with the semiconductor layer of the second conductivity type uses the second main electrode.
  • the semiconductor layer is formed first, and then the trench is formed.
  • the first conductivity type is N-type and the second conductivity type is P-type.
  • the insulated gate transistor unit is an N-channel MOSFET unit
  • the first conductive type semiconductor substrate is an N-type semiconductor substrate
  • the semiconductor layer is a P+ type collector layer
  • the first main The electrode is an emitter
  • the second main electrode is a collector, wherein "+" in N-, P+ indicates a high doping concentration, and "-" indicates a low doping concentration.
  • forming the insulated gate transistor unit on the first main surface side of the active region of the semiconductor substrate includes: generating a field oxide layer on the first main surface of the N-type semiconductor substrate, And etching a region of the active region; generating a gate oxide layer on the first main surface of the active region, and depositing a polysilicon gate on the gate oxide layer; Selectively etching the gate oxide layer and the polysilicon gate to etch the implantation window of the P well, and forming a P well into the N-type semiconductor substrate along the etched implantation window; Selectively forming an N+ active region from the P-well surface into the N-type semiconductor substrate; depositing a dielectric layer on the first main surface of the active region, and etching the shorted N+ active region And a contact hole of the P well, wherein a first main electrode is formed outside the dielectric layer and is in electrical contact with the N+ active region and the P well.
  • the IGBT and the manufacturing method thereof are formed with a Trench and a second conductivity type semiconductor layer spaced apart from each other on the second main surface side of the active region of the semiconductor substrate, and Only a semiconductor layer of the second conductivity type is formed on the second main surface side of the termination protection region of the semiconductor substrate, so that the semiconductor substrate stored under the termination protection region when the built-in diode is reversely restored can be reduced.
  • the number of carriers inside can be used to optimize the reverse recovery characteristics of the built-in diode and reduce the voltage drop at the beginning of the IGBT turn-on.
  • Figure 1 is a longitudinal cross-sectional view of a portion of an IGBT in one embodiment
  • FIG. 2 to 12 are longitudinal cross-sectional views showing respective manufacturing processes of the IGBT of FIG. 1 in one embodiment
  • FIG. 13 is a flow chart of a method of fabricating the IGBT of FIG. 1 in one embodiment.
  • FIG. 1 is a longitudinal cross-sectional view of a portion of an IGBT in one embodiment.
  • the IGBT includes: a semiconductor substrate 1 of a first conductivity type having a first main surface 1S1 and a second main surface 1S2, wherein the semiconductor substrate 1 An active region 100 and a termination protection region 200 disposed outside the active region 100; an insulated gate transistor unit formed on a first main surface 1S1 side of the active region 100, when it is turned on, a channel having a first conductivity type; a protection terminal formed on a first main surface 1S1 side of the termination protection region 200; and a trench formed on a second main surface 1S2 side of the semiconductor substrate 1 And a semiconductor layer 10 of a second conductivity type, wherein the trench 11 and the semiconductor layer 10 are spaced apart from each other on the second main surface 1S2 side of the active region 200, and only the semiconductor layer 10 is formed on The second main surface 1S2 side of the terminal protection zone 200. And the depth of the trench 11 is greater than the thickness of
  • the structure of the IGBT described above will be specifically described with reference to FIG. 1 , in which the first conductivity type is N-type and the second conductivity type is P-type.
  • the first conductivity type semiconductor substrate 1 is an N-type semiconductor substrate (also referred to as an N-layer), and the protection terminal is a field limiting ring termination structure.
  • the ring-limiting termination structure includes a P-type layer 2 formed by selectively doping P-type impurities into the N-type semiconductor substrate 1 from the first main surface 1S1 in the termination protection region 200.
  • a field oxide layer 13 is also formed on the first main surface 1S1 in the terminal protection region 200. It is easy to think that the protection terminal can also be other protection terminal structures in the prior art, for example, a field limiting ring plus field plate terminal structure.
  • the insulated gate transistor unit is a MOSFET having a channel of a first conductivity type (here, an N-type channel).
  • the N-channel MOSFET is DMOS.
  • DMOS Double-diffused Metal Oxide Semiconductor, double diffused MOS
  • a structured MOSFET comprising: a P well 5 formed from a first main surface 1S1 of the active region 100 to a selected diffused P-type impurity in the N-type semiconductor substrate 1; a surface from the P well 5
  • An N+ active region (or referred to as an N+ emitter) 6 formed by selectively diffusing a high concentration of N-type impurities into the P well 5; selectively formed on the first main surface of the active region 100 a gate oxide layer (abbreviated as gate oxide layer) 3, wherein the gate oxide layer 3 is located on a first main surface of an edge portion of the P well 5 and a first main surface of the active region where a P well is not formed a polysilicon gate electrode 4
  • the second conductive type semiconductor layer 10 is a P+ layer formed by injecting a P-type impurity into the N-type semiconductor substrate 1 from the second main surface 1S2 (or Referring to the P+ collector layer, the trench 11 is a trench selectively etched from the second main surface 1S2 into the N-type semiconductor substrate 1.
  • the P+ collector layer 10 and The trenches 11 are formed spaced apart from each other on the second main surface 1S2 side of the active region 200, and only the P+ collector layer 10 is provided on the second main surface 1S2 side of the terminal protection region 200.
  • the IGBT of FIG. 1 further includes: a first main electrode (in the present embodiment, an emitter) 8 formed on the first main surface 1S1 of the active region 100 covering the dielectric layer 7; in the trench 11 and the A second main electrode (collector in the present embodiment) 12 formed on the second conductivity type semiconductor layer 10, that is, the second main electrode 12 includes a metal filling the trench 11 and a metal covering the second main surface 1S2 a layer; a passivation layer 9 covering the first main electrode 8 and the field oxide layer 13 for protecting the surface of the chip from external ions.
  • the second main electrode 12 is in electrical contact with the first conductive type semiconductor substrate 1 portion and the second conductive type semiconductor layer 10 around the trench 11, the first main electrode 8 and the N+ active region 6 It is in electrical contact with the P well 5.
  • the channel region The inversion is an N-type region, and a channel connecting the N-layer 1 and the N+ active region 6 is electrically formed in the P well 5, through which electrons are injected from the emitter 8 to the N-type semiconductor substrate 1
  • a forward bias is formed between the P+ collector layer 10 and the N-type semiconductor substrate 1, and holes are injected from the P+ collector layer 10, and the resistance of the N-type semiconductor substrate 1 is large.
  • the current capacity of the IGBT increases, that is, the IGBT is turned on.
  • the IGBT Since the trench 11 is filled with metal, there is no PN junction barrier. Therefore, as long as there is a small collector voltage VCE, the IGBT is turned on, that is, the voltage drop at the beginning of the IGBT conduction can be reduced, and its working principle is The small current is the DMOS effect, and the large current is the IGBT characteristic.
  • the gate voltage VGE applied between the emitter 8 and the gate electrode 4 is 0 V in the on state, or the emitter 8 and the gate electrode 4 are reverse biased, the channel region is returned to In the P-type region, the injection of holes from the P+ collector layer 10 is also stopped because the injection of electrons from the emitter 8 is stopped. Thereafter, electrons and holes remaining in the N-type semiconductor substrate 1 are respectively withdrawn to the collector 12 and the emitter 8, or recombined with each other in the N-type semiconductor substrate 1 to disappear, that is, the IGBT is turned off. .
  • a diode ie, a built-in diode in the IGBT
  • a forward current ie, a guide
  • the forward current is derived from the holes injected by the P well 5 and the electrons partially injected from the N-type semiconductor substrate 1 around the trench 11.
  • the electrons and holes remaining in the substrate 1 are respectively withdrawn from the collector 12 and the emitter 8, or are recombined and disappeared in the N-type semiconductor substrate 1, and the current flowing through the built-in diode is referred to as a recovery current.
  • the direction of current flowing when the built-in diode is in the on state is opposite.
  • the recovery characteristics of the built-in diode can be improved by reducing the recovery current.
  • the trench 11 and the P+ collector layer 10 are spaced apart from each other on the second main surface 1S2 side of the active region 200, and only the P+ collector layer 10 is formed on the IGBT.
  • the second main surface 1S2 side of the terminal protection zone 200 In this way, the number of carriers stored in the semiconductor substrate 1 under the terminal protection region 200 when the built-in diode is reversely restored can be reduced, so that the reverse recovery characteristic of the built-in diode can be optimized and reduced at the same time.
  • the voltage drop at the beginning of the IGBT turn-on.
  • the insulated gate transistor is a MOSFET of a DMOS structure, and in other embodiments, it may also be a trench MOSFET or a V-shaped MOSFET.
  • the second main surface 1S2 of the bottom 1 serves to thin the semiconductor substrate 1 after the formation of the insulated gate transistor unit to meet a predetermined thickness requirement; the second main surface 1S2 of the thinned semiconductor substrate 1
  • a trench 11 and a second conductive type semiconductor layer 10 are formed in the semiconductor substrate 1, wherein the trench 11 and
  • Step 110 preparing an N-type semiconductor substrate 1 having a first major surface 1S1 and a second major surface 1S2.
  • Step 120 forms a protection terminal on the first main surface 1S1 side of the terminal protection region 200 of the N-type semiconductor substrate 1.
  • a P-type impurity is selectively implanted in the first main surface 1S1 of the N-type semiconductor substrate 1 by a photolithography process, and a P-type layer 2 is formed in the terminal protection region 200 by diffusion to obtain a field limiting ring terminal. structure.
  • Step 130 generates a field oxide layer 13 on the first main surface 1S1 of the N-type semiconductor substrate 1, and etches a region of the active region 100.
  • the field oxide layer 13 is formed on the first main surface 1S1 of the N-type semiconductor substrate 1, and the region of the active region 100 is selectively etched by photolithography and etching processes.
  • Step 140 as shown in FIG. 4, a gate oxide layer 3 is formed on the first main surface 1S1 in the active region 100, and a polysilicon gate 4 is deposited on the gate oxide layer 3.
  • a gate oxide layer 3 is formed on the first main surface 1S1 of the active region 100 by thermal oxidation, and the gate oxide layer 3 has a thickness of about 600 ⁇ to 1500.
  • a polysilicon gate 4 of a certain thickness is then deposited on the upper surface of the gate oxide layer 3.
  • Step 150 selectively etching the gate oxide layer 3 and the polysilicon gate 4 to etch the implantation window of the P-type base region or the P-well 5, and self-etching the window to the N P-type diffusion is performed in the -type semiconductor substrate 1 to form a P-type base region or a P well 5.
  • the gate oxide layer 3 and the polysilicon gate 4 are selectively etched by photolithography and etching to etch the implantation window of the P well 5, and the P-type is implanted through the self-aligned implantation process. Impurities, and a P well 5 is formed in the N-type semiconductor substrate 1 by a push well.
  • Step 160 selectively forms an N-type active region 6 from the surface of the P-well 5 into the N-type semiconductor substrate 1.
  • an N+ implantation window is selectively formed on the surface of the P well 5 by a photolithography process, and an N+ active region (or N+ emitter) 6 is formed by implanting and pushing the well.
  • Step 170 As shown in FIG. 7, a dielectric layer 7 formed with a polysilicon gate 4 is deposited on the first main surface 1S1 of the active region 100, and is etched by photolithography and etching to short-circuit N+ active. Contact holes of the region 6 and the P well 5.
  • Step 180 as shown in FIG. 8, forming a first main electrode (here, emitter) metal 8 covering the exposed surface of the dielectric layer 7 on the first main surface 1S1 of the active region 100, wherein the first main The electrode metal 8 is electrically connected to the P well 5 and the N+ active region 6.
  • the emitter metal 8 is formed by sputtering, and part of the metal is selectively etched by photolithography and etching processes.
  • the emitter metal 8 may be formed by other means, such as by depositing metal. The way.
  • Step 190 as shown in FIG. 9, a passivation layer 9 is deposited on the first main electrode metal 8 and the field oxide layer 13. Specifically, a passivation layer 9 for protecting the surface of the chip from external ions is deposited on the first main electrode metal 8 and the field oxide layer 13 by chemical vapor deposition, and is lithographically and etched. A PAD (pad) region (not shown) for extracting the gate electrode 4 and the emitter 8 is etched.
  • Step 210 thins the thickness of the N-type semiconductor substrate 1 by a backside thinning process. Specifically, the semiconductor substrate 1 is polished from the second main surface of the N-type semiconductor substrate 1 to meet a predetermined thickness requirement.
  • Step 220 as shown in FIG. 10, P-type impurity implantation is performed from the second main surface of the thinned N-type semiconductor substrate 1 toward the inside of the semiconductor substrate 1, and low-temperature annealing is performed to form a P-type semiconductor layer. (or P+ collector layer) 10.
  • Step 230 as shown in FIG. 11, etching from the second main surface 1S2 of the active region 100 through the P+ collector layer 10 to the N-type semiconductor substrate 1 by photolithography and etching processes A groove 11 of a certain depth and width is produced.
  • Step 240 forming a metal layer (such as Al-Ti-Ni-Ag) 12 of a certain thickness on the second main surface 1S2 side of the N-type semiconductor substrate 1 on which the trench 11 and the P+ collector layer 10 are formed,
  • the metal layer 12 is a second main electrode for IGBT, and the metal layer 12 is electrically connected to the N-type semiconductor substrate 1 through the trench 11.
  • Steps 140 to 180 are processes of forming an insulated gate transistor on the first main surface of the active region of the N-type semiconductor substrate 1, and therefore, if the insulated gate transistor is another type of MOSFET, the corresponding manufacturing steps are also Need the corresponding changes.
  • the first conductivity type is N-type
  • the second conductivity type is P-type.
  • the first conductivity type may be P-type.
  • the second conductivity type is N-type, in which case a P-type semiconductor substrate 1 is used, the insulated gate transistor is a P-channel MOSFET unit, and the second main electrode 12 is an emitter, and the first main electrode 8
  • the specific structure and principle are similar to those of the above IGBT, and are not described here.
  • the IGBT and the method of fabricating the same according to the present invention are formed with a trench 11 and a semiconductor layer 10 of a second conductivity type spaced apart from each other on the second main surface side of the active region 100 of the semiconductor substrate 1.
  • the semiconductor layer 10 of the second conductivity type is formed, so that the terminal protection region can be reduced when the built-in diode is reversely restored.
  • the number of carriers in the underlying semiconductor substrate can be used to optimize the reverse recovery characteristics of the built-in diode while reducing the voltage drop at the beginning of the IGBT turn-on.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

La présente invention concerne un transistor bipolaire à grille isolée, ainsi qu'un procédé de fabrication associé. Le transistor bipolaire à grille isolée comprend : un substrat semi-conducteur (1) d'un premier type conducteur, qui est pourvu d'une première face principale (1S1) et d'une seconde face principale (1S2), le substrat semi-conducteur (1) comprenant une zone active (100) et une zone de protection de borne (200) qui est agencée à l'extérieur de la zone active (100); une unité de transistor à grille isolée qui est formée au niveau du côté de la première face principale (1S1) de la zone active (100); des rainures (11) et des couches semi-conductrices (10) d'un second type conducteur, qui sont formées au niveau du côté de la seconde face principale (1S2) du substrat semi-conducteur (1), les rainures (11) et les couches semi-conductrices (10) étant formées au niveau du côté de la seconde face principale (1S2) de la zone active (100) en étant séparées les unes des autres, et seules les couches semi-conductrices (10) étant formées au niveau du côté de la seconde face principale (1S2) de la zone de protection de borne (200). Le transistor bipolaire à grille isolée et son procédé de fabrication permettent d'améliorer les caractéristiques de récupération d'une diode intégrée.
PCT/CN2014/078203 2013-06-28 2014-05-23 Transistor bipolaire à grille isolée et procédé de fabrication associé WO2014206160A1 (fr)

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CN108649072A (zh) * 2018-02-09 2018-10-12 江苏捷捷微电子股份有限公司 一种低导通电阻的沟槽mosfet器件及其制造方法
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CN113284940A (zh) * 2021-05-13 2021-08-20 乐山无线电股份有限公司 一种电力电子用半导体器件及其制作方法

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