WO2014205997A1 - 一种阵列基板及其制造方法、显示装置 - Google Patents

一种阵列基板及其制造方法、显示装置 Download PDF

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Publication number
WO2014205997A1
WO2014205997A1 PCT/CN2013/087943 CN2013087943W WO2014205997A1 WO 2014205997 A1 WO2014205997 A1 WO 2014205997A1 CN 2013087943 W CN2013087943 W CN 2013087943W WO 2014205997 A1 WO2014205997 A1 WO 2014205997A1
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Prior art keywords
tft
layer
substrate
light
array substrate
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Ceased
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PCT/CN2013/087943
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English (en)
French (fr)
Inventor
阎长江
李靖
李田生
谢振宇
陈旭
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to US14/348,359 priority Critical patent/US9664973B2/en
Publication of WO2014205997A1 publication Critical patent/WO2014205997A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a manufacturing method thereof, and a display device.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • LCD Thin Film Transistor Liquid Crystal Display
  • the manufacturing process of the TFT-LCD display panel includes: manufacturing an array (Array) substrate and a color filter substrate, and then aligning the array substrate and the color filter substrate into a cell.
  • a typical TFT array substrate includes a transparent substrate 11 and a TFT gate 120 sequentially on the surface of the transparent substrate 11, a gate insulating layer 13, an active layer 14, and TFT drains on both sides of the active layer 14.
  • 16 and a second deuterated layer 17 and a slit-shaped second transparent electrode 18 which are sequentially formed on the surface of the first transparent electrode 16.
  • a portion of the semiconductor active layer 14 and the gate insulating layer 13 are not blocked by the TFT source 122 or the drain 121 (as shown by the area A in FIG. 1), Without the reflection of the metal layer, it directly illuminates the interface between the semiconductor active layer 14 and the gate insulating layer 13, so that it is activated by the ambient light to generate a shallow level defect state in the semiconductor active layer 14 and the gate.
  • a carrier trapping effect occurs at the interface of the insulating layer 13, which causes a relatively large leakage current between the semiconductor active layer 14 and the gate insulating layer 13, thereby affecting the stability of the TFT and reducing the display effect of the display device. .
  • Embodiments of the present invention provide an array substrate, a method of fabricating the same, and a display device for reducing leakage current of a TFT, improving stability of the TFT, and improving display performance of the display device.
  • an embodiment of the present invention adopts the following technical solutions:
  • an array substrate including a transparent substrate, a TFT on the transparent substrate, and a first covering the TFT.
  • a deuterated layer a first transparent electrode on a surface of the first deuterated layer; wherein the side of the TFT away from the transparent substrate has light for preventing light transmission at a position corresponding to the TFT channel Resistance structure.
  • a display device including the array substrate as described above is provided.
  • a method for manufacturing an array substrate including:
  • a photoresist structure for preventing light transmission is formed at a position of the TFT on the substrate on which the TFT is located away from the transparent substrate.
  • An embodiment of the present invention provides an array substrate, a manufacturing method thereof, and a display device.
  • the array substrate includes a transparent substrate, a TFT on the transparent substrate, a first deuterated layer covering the TFT, and a surface on the surface of the first deuterated layer. a first transparent electrode, and a photoresist structure for preventing light transmission at a position corresponding to the TFT channel on a side of the TFT away from the transparent substrate.
  • the present invention by providing a photoresist structure at a position corresponding to the TFT channel on the side of the TFT remote from the transparent substrate, it is possible to prevent light from entering the channel blocked by the source and the drain and entering the TFT, thereby being able to reduce
  • the TFT leakage current caused by the TFT further improves the stability of the TFT and improves the display effect of the display device.
  • FIG. 1 is a schematic structural view of an array substrate in the prior art
  • FIG. 2 is a schematic view showing the structure of an array substrate according to a first embodiment of the present invention
  • 3a is a schematic structural view of an array substrate according to a second embodiment of the present invention.
  • 3b is a schematic view showing another structure of an array substrate according to a second embodiment of the present invention.
  • FIG. 4 is a schematic structural view of an array substrate according to a third embodiment of the present invention.
  • FIG. 5 is a flow chart showing a method of fabricating an array substrate according to a fourth embodiment of the present invention.
  • FIG. 6 is a flow chart showing a method of fabricating an array substrate according to a fifth embodiment of the present invention.
  • FIG. 7 is a flow chart showing a method of fabricating an array substrate according to a sixth embodiment of the present invention.
  • Figure 8 is a flow chart showing a method of fabricating an array substrate in accordance with a seventh embodiment of the present invention.
  • the technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings, and the embodiments described herein are merely illustrative embodiments of the present invention. All embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments described in the present invention without departing from the inventive scope are the scope of the invention.
  • the array substrate according to the first embodiment of the present invention may include: a transparent substrate 11, a TFT 12 on the transparent substrate 11, and a cover TFT 12. a first transparent layer 15 on the surface of the first deuterated layer 15 , wherein the TFT 12 in the array substrate according to the embodiment of the invention is away from the transparent substrate 11
  • a photoresist structure 20 for preventing light transmission is provided at the channel position.
  • the semiconductor active layer 14 and the gate insulating layer 13 in the prior art can be effectively avoided by fabricating a photoresist structure for preventing light transmission at a position corresponding to the TFT channel.
  • the light leakage phenomenon caused by the direct irradiation of the light due to the source 122 or the drain 121 of the TFT is not present at the interface.
  • leakage current of the thin film transistor due to direct irradiation of light to the interface between the semiconductor active layer 14 and the gate insulating layer 13 can be reduced, the stability of the TFT can be improved, and the display effect of the display device can be improved.
  • the photoresist structure 20 may be a microstructure having a plurality of continuous slopes or curved surfaces formed on the surface of the first deuterated layer 15.
  • micro-junction shape having a plurality of continuous slopes or curved surfaces.
  • the embodiments of the present invention are described by taking a zigzag irregular shape as an example, but the present invention is not limited thereto.
  • the photoresist structure 20 having a sawtooth surface may be formed on the surface of the first deuterated layer 15 corresponding to the channel position of the TFT 12 by a patterning process.
  • the position of the channel corresponding to the TFT 12 on the substrate on which the first deuterated layer 15 is formed is subjected to ion bombardment etching, and then the ashing photoresist is applied to correspond to the TFT 12 on the surface of the first deuterated layer 15.
  • the channel position forms a microstructure having a zigzag irregular shape; or the surface of the first deuterated layer 15 may be roughened to form a microstructure having a zigzag irregular shape.
  • the passing surface has
  • the jagged irregular shaped photoresist structure 20 scatters the incident light to reduce the light transmitted through the region A, thereby avoiding the light leakage phenomenon of the display device, reducing the leakage current of the TFT, and improving the leakage current.
  • the stability of the TFT improves the display effect of the display device.
  • the patterning process in the present invention may include a photolithography process, or may include a photolithography process and an etching process, and may also include other processes for forming a predetermined pattern, such as printing, inkjet, etc.; It refers to a process of forming a pattern using a photoresist, a mask, an exposure machine, or the like including a process of film formation, exposure, development, and the like.
  • the corresponding patterning process can be selected according to the structure formed in the present invention.
  • the surface of the first transparent electrode 16 has a second deuterated layer 17, and the surface of the second deuterated layer 17 is formed with a second transparent electrode 18.
  • the first transparent electrode 16 may be a plate-like structure
  • the second transparent electrode 18 may be a slit-like structure spaced apart from each other; or, the first transparent electrode 16 may be a slit-like structure spaced apart from each other, and the second transparent electrode 18 may be a plate-like structure; or both the first transparent electrode 16 and the second transparent electrode 18 may be slit-like structures.
  • the array substrate provided by the embodiment of the present invention can be applied to FFS (Fringe Field Switching) type or AD-SDS (Advanced-Super Dimensional Switching) type.
  • Liquid crystal display device For example, an electrode of a slit-like structure in which the first transparent electrode 16 and the second transparent electrode 18 are spaced apart is generally used for an ADS type liquid crystal display device in which the ADS technology passes through the same plane.
  • the parallel electric field generated by the edge of the inner pixel electrode and the longitudinal electric field generated between the pixel electrode layer and the common electrode layer form a multi-dimensional electric field, so that all the aligned liquid crystal molecules between the pixel electrodes in the liquid crystal cell and directly above the electrode can generate rotation conversion, and other types
  • the ADS type liquid crystal display device further improves the working efficiency of the planar orientation liquid crystal and increases the light transmission efficiency.
  • the first transparent electrode 16 may be a pixel electrode, and the second transparent electrode 18 may be a common electrode; or the first transparent electrode 16 may be a common electrode, and the second transparent electrode 18 may be Pixel electrode.
  • the photoresist structure 20 is specifically a light reflecting structure formed by the first deuterated layer 15, so that light can be realized by changing the shape of the corresponding TFT channel position in the existing hierarchical structure.
  • the design of the resistive structure eliminates the need to additionally set a new level, effectively ensuring the thickness of the display device.
  • the photoresist structure 20 may further include a light shielding layer 21.
  • the light shielding layer 21 is located between the TFT 12 and the first deuterated layer 15. It should be noted that the light shielding layer 21 may block a portion where the semiconductor active layer 14 and the gate insulating layer 13 are not covered by the source 122 or the drain 121 of the TFT 12, and thus may be formed in the channel of the corresponding TFT 12.
  • the light shielding layer 21 at the position serves as the photoresist structure 20.
  • the surface of the light shielding layer 21 may be formed into a zigzag irregular shape by a patterning process, such that the first vaporization layer 15 located on the surface of the light shielding layer corresponding to the channel position of the TFT 12 also has a zigzag irregularity.
  • the surface shape of the light shielding layer and the first deuterated layer at the channel position is not limited.
  • the light shielding layer 21 has a flat surface
  • the first deuterated layer 15 formed thereon has Jagged irregular shape.
  • the light shielding layer 21 may be located between the first deuterated layer 15 and the second deuterated layer 17.
  • the first deuterated layer 15 and the light shielding layer 21 are formed layer by layer on the surface of the substrate on which the TFT 12 is formed by a patterning process above the position of the channel corresponding to the TFT 12, and the first deuterated layer 15 at the position passes.
  • the patterning process forms a zigzag irregular shape as shown in FIG.
  • the light shielding layer 21 formed on the surface of the first deuterated layer 15 will have the same zigzag irregular shape due to the first deuterated layer 15
  • the light shielding layer 21 and the light shielding layer 21 can be made of a material having a certain refractive index of light, so that the first vaporization layer 15 and the light shielding layer 21 formed at the position corresponding to the channel of the TFT 12 can be collectively used as the photoresist structure 20.
  • a material for forming the light shielding layer 21 between the TFT and the first deuterated layer 15 as shown in FIGS. 3a and 3b includes a resin material; or as shown in FIG. 4, the first deuterated layer 15 is formed.
  • the material of the light shielding layer 21 between the second deuterated layers 17 includes a resin material or a metal material.
  • the metal material is, for example, at least one of molybdenum, titanium, and aluminum.
  • Embodiments of the present invention provide a display device including any of the array substrates described above.
  • the display device may specifically be any liquid crystal display product or component having a display function such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer.
  • Embodiments of the present invention provide a display device including an array substrate, the array substrate including a transparent substrate, a TFT on the transparent substrate, a first deuterated layer covering the TFT, and a surface on the surface of the first deuterated layer
  • the first transparent electrode and the photoresist structure for preventing light transmission at a position corresponding to the TFT channel on the side of the TFT away from the transparent substrate.
  • the photoresist structure can reduce the leakage current of the thin film transistor, improve the stability of the TFT, and improve the display effect of the display device.
  • a fourth embodiment of the present invention provides a method for fabricating an array substrate, as shown in FIG. 5, which includes:
  • a photoresist structure for preventing light transmission is formed at a position of the substrate on which the TFT is formed on a side of the TFT away from the transparent substrate corresponding to the TFT channel.
  • Embodiments of the present invention provide a method of fabricating an array substrate, the array substrate including a transparent substrate, a TFT on the transparent substrate, a first deuterated layer covering the TFT, and a first transparent electrode on a surface of the first deuterated layer. And a photoresist structure for preventing light transmission at a position of the TFT channel at a side of the TFT away from the transparent substrate. In this way, the photoresist structure can prevent the light from the front surface from being incident on the channel not blocked by the source or the drain of the TFT, thereby reducing the leakage current of the TFT, improving the stability of the TFT, and improving the display.
  • the display of the device is a transparent substrate, a TFT on the transparent substrate, a first deuterated layer covering the TFT, and a first transparent electrode on a surface of the first deuterated layer.
  • a photoresist structure for preventing light transmission at a position of the TFT channel at a side of the TFT away from the transparent substrate
  • the array substrate manufacturing method of the embodiment may include:
  • micro-junction shape having a plurality of continuous slopes or curved surfaces.
  • the embodiments of the present invention are described by taking a zigzag irregular shape as an example.
  • the first deuterated layer 15 corresponding to the channel position of the TFT 12 serves as a photoresist structure 20 having a zigzag-shaped irregular shape on its surface.
  • the photoresist structure 20 having a serrated irregular shape on the surface, thereby reducing the light transmitted through the region A, thereby avoiding the light leakage phenomenon of the display device, reducing the leakage current of the thin film transistor, and improving the TFT.
  • the stability of the display device is improved.
  • forming the photoresist structure 20 for preventing light transmission at a position corresponding to the channel of the TFT 12 may include forming the light shielding layer 21.
  • the light shielding layer 21 may be located on a substrate on which the TFT 12 is formed. It should be noted that the light shielding layer 21 may block a portion where the semiconductor active layer 14 and the gate insulating layer 13 are not covered by the source 122 or the drain 121 of the TFT, and thus may be formed at a channel position of the corresponding TFT 12. The light shielding layer 21 at the point serves as the photoresist structure 20.
  • the light shielding layer 21 may be located on the substrate on which the first deuterated layer 15 is formed. It should be noted that the first deuterated layer 15 and the light shielding layer 21 are formed layer by layer on the surface of the substrate on which the TFT 12 is formed by a patterning process above the position of the channel of the corresponding TFT 12, and the first deuterated layer 15 at the position is When the zigzag irregular shape as shown in FIG. 4 is formed by the patterning process, the light shielding layer 21 formed on the surface of the first deuterated layer 15 will have the same zigzag irregularity.
  • the first deuterated layer 15 and the light shielding layer 21 can be made of a material having a certain refractive index of light, the first deuterated layer 15 and the light shielding layer formed at the position of the channel corresponding to the TFT 12 can be formed. 21 is commonly used as the photoresist structure 20.
  • a material for forming the light shielding layer 21 between the TFT and the first deuterated layer 15 as shown in FIGS. 3a and 3b includes a resin material; or as shown in FIG. 4, the first deuterated layer 15 is formed.
  • the material of the light shielding layer 21 between the second deuterated layers 17 includes a resin material or a metal material.
  • the metal material is, for example, at least one of molybdenum, titanium, and aluminum.
  • the light shielding layer that blocks the portion of the semiconductor active layer 14 and the gate insulating layer 13 that is not covered by the source 122 or the drain 121 of the TFT can function to prevent light from being transmitted or to reflect incident light, thereby avoiding
  • the light leakage phenomenon of the display panel reduces the leakage current of the thin film transistor, improves the stability of the TFT, and improves the display effect of the display device.
  • a method for fabricating an array substrate according to a sixth embodiment of the present invention includes:
  • a pattern of the gate electrode 120 of the TFT is formed on the surface of the transparent substrate 11 by a patterning process.
  • the gate insulating layer 13 is covered on the surface of the gate 120 of the TFT.
  • a semiconductor active layer 14 by using a lift-out at a surface of the gate insulating layer 13 corresponding to the channel position of the TFT 12, the semiconductor active layer 14 being a metal oxide (IGZ0).
  • a source 122 and a drain 121 of the TFT are formed on the surface of the semiconductor active layer 14. After the step is completed, the fabrication of the TFT 12 is completed.
  • a pattern of the first deuterated layer 15 is formed on the surface of the substrate on which the TFT 12 is formed.
  • the surface of the first deuterated layer 15 at the position may be formed into a zigzag irregular shape at a channel position of the substrate 12 formed with the above pattern by using a specially designed mask or dry etching process. , or its surface is roughened.
  • the photoresist structure 20 is specifically a light reflecting structure formed by the first deuterated layer 15, so that light can be realized by changing the shape of the corresponding TFT channel position in the existing hierarchical structure.
  • the design of the resistive structure eliminates the need to additionally set a new level, effectively ensuring the thickness of the display device.
  • the array substrate manufacturing method according to the seventh embodiment of the present invention includes:
  • a pattern of the gate 120 of the TFT is formed on the surface of the transparent substrate 11 by a patterning process.
  • the gate insulating layer 13 is covered on the surface of the gate 120 of the TFT.
  • a semiconductor active layer 14 by using a lift-out at a surface of the gate insulating layer 13 corresponding to the channel position of the TFT 12, the semiconductor active layer 14 being a metal oxide (IGZO).
  • IGZO metal oxide
  • a source 122 and a drain 121 of the TFT are formed on the surface of the semiconductor active layer 14. After the step is completed, the fabrication of the TFT 12 is completed.
  • a pattern of the first deuterated layer 15 is formed on the surface of the substrate on which the TFT 12 is formed.
  • the surface of the first deuterated layer 15 at the position may be formed into a zigzag irregular shape at a channel position of the substrate 12 formed with the above pattern by using a specially designed mask or dry etching process. , or its surface is roughened.
  • the deposition of the metal material is performed on the surface of the substrate on which the above-described structure is formed corresponding to the channel of the TFT 12, whereby crystal grains having a large texture and a large individual shape are formed, and a zigzag structure is obtained, thereby completing the fabrication of the light shielding layer 21.
  • a photoresist structure 20 for preventing light transmission is formed at a channel position of the corresponding TFT 12.
  • a second transparent electrode 18 is formed on the surface of the substrate on which the second deuterated layer 17 is formed.

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  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
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Abstract

公开了一种阵列基板及其制造方法、显示装置，涉及显示技术领域，用以降低薄膜晶体管的漏电流，提高TFT的稳定性，提升显示器件的显示效果。阵列基板包括：透明基板（11）、位于透明基板（11）上的TFT（12）、覆盖TFT（12）的第一钝化层（15）、位于第一钝化层（15）的表面上的第一透明电极（16）、以及设置在TFT（12）远离透明基板（11）一侧对应的TFT沟道位置处的用于防止光线透射的光阻结构（20）。

Description

一种阵列基板及其制造方法、 显示装置
技术领域 本发明涉及显示技术领域， 尤其涉及一种阵列基板及其制 造方法、 显示装置。 背景技术 随着显示技术的飞速发展， TFT-LCD ( Thin Film Transistor Liquid Crystal Display, 薄膜晶体管液晶显示器）作为一种平板 显示装置， 因其具有体积小、 功耗低、 无辐射以及制作成本相 对较低等特点， 而越来越多地被应用于高性能显示领域当中。
TFT-LCD 显示面板的制造工艺包括： 制造阵列 （Array ) 基板和彩膜 （ Color Filter )基板， 然后再将阵列基板和彩膜基 板进行对位、 成盒（Cell ) 。 如图 1所示， 典型的 TFT阵列基 板包括透明基板 11以及依次位于透明基板 11表面上的 TFT栅 极 120,栅极绝缘层 13 ,有源层 14,位于有源层 14两侧的 TFT 漏极 121和 TFT源极 122, 位于有源层 14、 TFT漏极 121和 TFT源极 122表面上的第一飩化层 15, 位于第一飩化层 15表 面上的板状的第一透明电极 16 以及依次形成于第一透明电极 16表面上的第二飩化层 17和狭缝状的第二透明电极 18。
现有技术中， 如图 1所示， 半导体有源层 14和栅极绝缘 层 13的一部分没有被 TFT源极 122或漏极 121所遮挡 （如图 1中区域 A所示） ， 因此光线由于没有金属层的反射而直接照 射到半导体有源层 14和栅极绝缘层 13的界面， 这样一来， 会 被外界环境光激活而产生浅能级缺陷态， 在半导体有源层 14 和栅极绝缘层 13 的界面处发生载流子捕获效应， 进而造成在 半导体有源层 14 和栅极绝缘层 13 之间产生相对较大的漏电 流， 从而影响 TFT的稳定性， 降低显示器件的显示效果。 发明内容 本发明的实施例提供一种阵列基板及其制造方法、 显示装 置， 用以降低 TFT的漏电流， 提高 TFT的稳定性， 提升显示 器件的显示效果。
为达到上述目的， 本发明的实施例采用如下技术方案： 本发明实施例的一方面， 提供了一种阵列基板， 包括透明 基板、 位于所述透明基板上的 TFT、覆盖所述 TFT的第一飩化 层、 位于所述第一飩化层的表面上的第一透明电极； 其特征在 于， 在 TFT远离透明基板的一侧对应所述 TFT沟道的位置处 具有用于防止光线透射的光阻结构。
本发明实施例的另一方面， 提供一种显示装置， 包括如上 所述的阵列基板。
本发明实施例的又一方面， 提供一种阵列基板的制造方 法， 包括：
在透明基板上形成 TFT;
在形成 TFT的基板表面上在 TFT远离所述透明基板的一 侧对应所述 TFT 沟道的位置处形成用于防止光线透射的光阻 结构。
本发明实施例提供一种阵列基板及其制造方法、 显示装 置， 该阵列基板包括透明基板、 位于透明基板上的 TFT、 覆盖 TFT的第一飩化层、位于第一飩化层的表面上的第一透明电极、 以及在 TFT远离透明基板一侧对应所述 TFT沟道的位置处的 用于防止光线透射的光阻结构。 在本发明中， 通过在 TFT远离 透明基板的一侧对应 TFT沟道的位置处设置光阻结构，可以防 止光线入射到未被源极和漏极遮挡的沟道处而进入 TFT, 从而 能够降低其所引起的 TFT漏电流， 进而提高 TFT的稳定性， 提升显示器件的显示效果。 附图说明 为了更清楚地说明本发明实施例的技术方案， 下面将参照附图 对本发明进行详细地描述：
图 1为现有技术中的阵列基板结构示意图；
图 2 为根据本发明第一实施例的一种阵列基板结构示意 图；
图 3a 为根据本发明第二实施例的一种阵列基板结构示意 图；
图 3b 为根据本发明第二实施例的另一种阵列基板结构示 意图；
图 4 为根据本发明第三实施例的一种阵列基板结构示意 图；
图 5为根据本发明第四实施例的一种阵列基板制造方法的 流程图；
图 6为根据本发明第五实施例的一种阵列基板制造方法的 流程图；
图 7为根据本发明第六实施例的一种阵列基板制造方法的 流程图； 以及
图 8为根据本发明第七实施例的一种阵列基板制造方法的 流程图。 具体实施方式 下面将结合附图， 对本发明实施例中的技术方案进行清楚、 完 整地描述， 显然， 所描述的实施例仅仅是本发明示意性实施例， 而 不是穷举了能够实现本发明构思的全部实施例。基于本发明中所述 的实施例， 本领域普通技术人员在没有做出创造性劳动前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
根据本发明第一实施例的阵列基板， 如图 2所示， 可以包 括： 透明基板 11、 位于透明基板 11上的 TFT 12、 覆盖 TFT 12 的第一飩化层 15、 位于第一飩化层 15的表面的第一透明电极 16, 其中， 根据本发明实施例的阵列基板中在 TFT 12远离所 述透明基板 11的一侧对应 TFT 12的沟道位置处具有用于防止 光线透射的光阻结构 20。
在本发明实施例提供的阵列基板中， 通过在对应所述 TFT 沟道位置处制作用于防止光线透射的光阻结构， 可以有效避免 现有技术中半导体有源层 14和栅极绝缘层 13的界面处由于未 被 TFT的源极 122或漏极 121所覆盖而被光线直接照射产生的 漏光现象。 这样一来， 可以降低由于光线直接照射到半导体有 源层 14和栅极绝缘层 13的界面处而导致的薄膜晶体管的漏电 流， 提高 TFT的稳定性， 提升显示器件的显示效果。
根据本发明的第一实施例， 如图 2所示， 光阻结构 20具 体可以为在第一飩化层 15 表面上形成的具有连续的多个斜面 或者曲面的微结构。
需要说明的是， 上述具有连续的多个斜面或者曲面的微结 形状。 其中， 本发明实施例均是以锯齿状的不规则形状为例进 行的说明， 但是本发明不限于此。
需要说明的是， 可以通过构图工艺在第一飩化层 15 的表 面对应 TFT 12的沟道位置形成表面具有锯齿状的光阻结构 20。 例如， 对形成有第一飩化层 15的基板上对应 TFT 12的沟道的 位置进行离子轰击刻蚀， 再进行灰化光刻胶， 可在第一飩化层 15的表面上对应 TFT 12的沟道位置形成具有锯齿状的不规则 形状的微结构； 或可以将第一飩化层 15 的表面粗糙化形成具 有锯齿状的不规则形状的微结构。
这样一来， 当光线照射到半导体有源层 14 和栅极绝缘层 13的未被 TFT的源极 122或漏极 121所遮挡的区域 （如图 1 中区域 A所示）时， 通过表面具有锯齿状的不规则形状的光阻 结构 20将入射光线散射开， 减少了透过该区域 A的光线， 从 而避免了显示器件的漏光现象， 降低了 TFT的漏电流， 提高了 TFT的稳定性， 提升了显示器件的显示效果。
需要说明的是，本发明中的构图工艺，可以包括光刻工艺， 或者包括光刻工艺以及刻蚀工艺， 同时还可以包括打印、 喷墨 等其他用于形成预定图形的工艺； 光刻工艺， 是指包括成膜、 曝光、 显影等工艺过程的利用光刻胶、 掩模板、 曝光机等形成 图形的工艺。 可根据本发明中所形成的结构选择相应的构图工 艺
此外， 第一透明电极 16表面具有第二飩化层 17, 第二飩 化层 17的表面形成有第二透明电极 18。
具体的， 第一透明电极 16 可以为板状结构， 第二透明电 极 18可以为相互间隔的狭缝状结构； 或， 第一透明电极 16可 以为相互间隔的狭缝状结构， 第二透明电极 18 可以为板状结 构； 或第一透明电极 16和第二透明电极 18均可以为狭缝状结 构。
例如， 本发明实施例提供的阵列基板可以适用于 FFS ( Fringe Field Switching , 边缘场开关 ） 型或 AD-SDS ( Advanced- Super Dimensional Switching, 筒称为 ADS, 高级 超维场开关） 型等类型的液晶显示装置。 以第一透明电极 16 和第二透明电极 18 均为间隔设置的狭缝状结构的电极为例， 这样一种结构的阵列基板通常被用于 ADS 型液晶显示装置， 其中， ADS技术通过同一平面内像素电极边缘所产生的平行电 场以及像素电极层与公共电极层间产生的纵向电场形成多维 电场， 使液晶盒内像素电极间、 电极正上方所有取向液晶分子 都能够产生旋转转换， 与其他类型的显示装置相比， ADS型液 晶显示装置进一步提高了平面取向系液晶工作效率并增大了 透光效率。
需要说明的是， 在本发明实施例中， 第一透明电极 16 可 以为像素电极， 第二透明电极 18 可以为公共电极； 或者第一 透明电极 16可以为公共电极， 第二透明电极 18可以为像素电 极。 本发明对此并不作限制。 采用上述的这样一种阵列基板， 光阻结构 20具体是由第 一飩化层 15 形成的光反射结构， 这样一来， 通过改变现有层 级结构中对应 TFT沟道位置的形状即可实现光阻结构的设计， 从而无需额外设置新的层级， 有效保证了显示装置的厚度。
作为选择， 光阻结构 20还可以包括遮光层 21。
根据本发明的第二实施例， 如图 3a所示， 该遮光层 21位 于 TFT 12与第一飩化层 15之间。 需要说明的是， 该遮光层 21 可以遮挡半导体有源层 14和栅极绝缘层 13未被 TFT 12的源 极 122或漏极 121所覆盖的部分， 因此可以将形成于对应 TFT 12的沟道位置处的遮光层 21作为光阻结构 20。 其中， 可以将 该遮光层 21 的表面通过构图工艺形成具有锯齿状的不规则形 状， 这样位于该遮光层表面对应 TFT 12沟道位置处的第一飩 化层 15 也同样具有锯齿状的不规则形状。 这里对该沟道位置 处的遮光层和第一飩化层的表面形状不作限定， 例如， 如图 3b 所示， 遮光层 21 具有平坦表面， 而其上所形成的第一飩化层 15具有锯齿状的不规则形状。
根据本发明的第三实施例， 如图 4所示， 遮光层 21 可以 位于第一飩化层 15与第二飩化层 17之间。 需要说明的是， 在 形成有 TFT 12的基板表面通过构图工艺在对应 TFT 12沟道的 位置上方逐层形成第一飩化层 15和遮光层 21 , 当该位置的第 一飩化层 15通过构图工艺形成如图 4所示的锯齿状的不规则 形状时， 形成于该第一飩化层 15表面上的遮光层 21将具有相 同的锯齿状的不规则形状， 由于第一飩化层 15和遮光层 21可 以采用具有一定光折射率的材料制成， 因此可以将形成于对应 TFT 12沟道的位置处的第一飩化层 15和遮光层 21共同作为光 阻结构 20。
进一步地，制作位于如图 3a和图 3b所示的 TFT与第一飩 化层 15之间的遮光层 21的材料包括树脂材料； 或者如图 4所 示，制作位于第一飩化层 15与第二飩化层 17之间的遮光层 21 的材料包括树脂材料或金属材料。 金属材料例如为钼、 钛、 铝 中的至少一种。 这样一来， 用以遮挡半导体有源层 14 和栅极 绝缘层 13未被 TFT的源极 122或漏极 121所覆盖的部分的遮 光层 21 可以起到防止光线透射或将入射光线反射的作用， 从 而避免了显示面板的漏光现象， 降低了薄膜晶体管的漏电流， 提高了 TFT的稳定性， 提升了显示器件的显示效果。
本发明的实施例提供一种显示装置， 包括如上所述的任意 一种阵列基板。该显示装置具体可以为液晶显示器、液晶电视、 数码相框、 手机、 平板电脑等任何具有显示功能的液晶显示产 品或者部件。
本发明实施例提供一种显示装置， 该显示装置包括阵列基 板， 该阵列基板包括透明基板、 位于透明基板上的 TFT、 覆盖 TFT的第一飩化层、位于第一飩化层的表面上的第一透明电极、 以及设置在 TFT远离透明基板一侧对应述 TFT沟道位置处的 用于防止光线透射的光阻结构。 这样一来， 通过该光阻结构可 以降低薄膜晶体管的漏电流， 提高 TFT的稳定性， 提升显示器 件的显示效果。
本发明第四实施例提供一种阵列基板的制造方法， 如图 5 所示， 其包括：
5101、 在透明基板上形成 TFT。
5102、 在形成 TFT的基板表面在 TFT远离透明基板一侧 对应所述 TFT 沟道的位置处形成用于防止光线透射的光阻结 构。
本发明实施例提供一种阵列基板的制造方法， 该阵列基板 包括透明基板、位于透明基板上的 TFT、覆盖 TFT的第一飩化 层、 第一飩化层的表面上的第一透明电极、 以及在 TFT远离透 明基板一侧对应所述 TFT 沟道位置处的用于防止光线透射的 光阻结构。 这样一来， 通过该光阻结构可以防止来自正面的光 线入射到未被 TFT源极或漏极遮挡的沟道处，以降低由此导致 的 TFT的漏电流， 提高 TFT的稳定性， 提升显示器件的显示 效果。
进一步地， 如图 6所示并且结合图 2, 根据本发明第五实 施例的阵列基板制造方法可以包括：
5201、 在形成有 TFT的基板上形成第一飩化层 15。
5202、 在第一飩化层 15的表面上在 TFT远离透明基板一 侧对应 TFT 沟道的位置通过构图工艺形成表面具有连续的多 个斜面或者曲面的微结构。
需要说明的是， 上述具有连续的多个斜面或者曲面的微结 形状。 其中， 本发明实施例均是以锯齿状的不规则形状为例进 行的说明。
具体地， 如图 2所示， 对应 TFT 12沟道位置处的第一飩 化层 15作为表面具有锯齿状的不规则形状的光阻结构 20。 这 样一来， 当光线从正面照射到半导体有源层 14 和栅极绝缘层 13的未被 TFT的源极 122或漏极 121所遮挡的区域 （如图 1 中区域 A所示）时， 可以通过表面具有锯齿状的不规则形状的 光阻结构 20将入射光线散射开，减少了透过该区域 A的光线， 从而避免了显示器件的漏光现象， 降低了薄膜晶体管的漏电 流， 提高了 TFT的稳定性， 提升了显示器件的显示效果。
作为选择， 在对应 TFT 12沟道的位置处形成用于防止光 线透射的光阻结构 20可以包括形成遮光层 21。
例如， 如图 3a和图 3b所示， 该遮光层 21可以位于在形 成有 TFT 12的基板上。 需要说明的是， 该遮光层 21可以遮挡 半导体有源层 14和栅极绝缘层 13未被 TFT的源极 122或漏极 121所覆盖的部分， 因此可以将形成于对应 TFT 12的沟道位置 处的遮光层 21作为光阻结构 20。
作为选择， 如图 4所示， 该遮光层 21 可以位于形成有第 一飩化层 15的基板上。 需要说明的是， 在形成有 TFT 12的基 板表面通过构图工艺在对应 TFT 12的沟道的位置上方逐层形 成第一飩化层 15和遮光层 21 , 当该位置的第一飩化层 15通过 构图工艺形成如图 4所示的锯齿状的不规则形状时， 形成于该 第一飩化层 15表面上的遮光层 21将具有相同的锯齿状的不规 则形状， 由于第一飩化层 15和遮光层 21可以采用具有一定光 折射率的材料制成， 因此可以将形成于对应 TFT 12的沟道的 位置处的第一飩化层 15和遮光层 21共同作为光阻结构 20。
进一步地，制作如图 3a和图 3b所示的位于 TFT与第一飩 化层 15之间的遮光层 21的材料包括树脂材料； 或者如图 4所 示，制作位于第一飩化层 15与第二飩化层 17之间的遮光层 21 的材料包括树脂材料或金属材料。 金属材料例如为钼、 钛、 铝 中的至少一种。 这样一来， 遮挡半导体有源层 14 和栅极绝缘 层 13未被 TFT的源极 122或漏极 121所覆盖的部分的遮光层 可以起到防止光线透射或将入射光线反射的作用， 从而避免了 显示面板的漏光现象，降低了薄膜晶体管的漏电流，提高了 TFT 的稳定性， 提升了显示器件的显示效果。
具体地， 参照图 7并结合图 2, 根据本发明第六实施例的 阵列基板制造方法包括：
5301、 在透明基板 11的表面通过构图工艺形成 TFT的栅 极 120的图案。
5302、 在 TFT的栅极 120的表面覆盖栅极绝缘层 13。
5303、 在栅极绝缘层 13的表面对应 TFT 12的沟道位置处 采用隔离技术（lift-out )形成半导体有源层 14, 该半导体有源 层 14为金属氧化物 （IGZ0 ) 。
5304、 在半导体有源层 14的表面形成 TFT的源极 122和 漏极 121 , 该步骤结束后， 完成了对 TFT 12的制作。
5305、 在形成有 TFT 12的基板表面形成第一飩化层 15的 图案。
5306、 在形成有上述图案的基板表面对应 TFT 12的沟道 位置处利用特殊设计的掩模板或者干刻蚀工艺可使得该位置 处的第一飩化层 15 的表面形成锯齿状的不规则形状， 或其表 面被粗糙化。
5307、 在形成有上述图案的基板表面形成第一透明电极 16, 这样就在对应 TFT 12的沟道位置处形成用于防止光线透 射的光阻结构 20。
5308、 在形成有第一透明电极 16 的基板表面形成第二飩 化层 17。
5309、 在形成有第二飩化层 17 的基板表面形成第二透明 电极 18。
采用上述的这样一种阵列基板， 光阻结构 20具体是由第 一飩化层 15 形成的光反射结构， 这样一来， 通过改变现有层 级结构中对应 TFT沟道位置的形状即可实现光阻结构的设计， 从而无需额外设置新的层级， 有效保证了显示装置的厚度。
作为选择， 参照图 8并结合图 4, 根据本发明第七实施例 的阵列基板制造方法包括：
5401、 在透明基板 11的表面通过构图工艺形成 TFT的栅 极 120的图案。
5402、 在 TFT的栅极 120的表面覆盖栅极绝缘层 13。
5403、 在栅极绝缘层 13的表面对应 TFT 12的沟道位置处 采用隔离技术（lift-out )形成半导体有源层 14, 该半导体有源 层 14为金属氧化物 （IGZO ) 。
5404、 在半导体有源层 14的表面形成 TFT的源极 122和 漏极 121 , 该步骤结束后， 完成了对 TFT 12的制作。
5405、 在形成有 TFT 12的基板表面形成第一飩化层 15的 图案。
5406、 在形成有上述图案的基板表面对应 TFT 12的沟道 位置处利用特殊设计的掩模板或者干刻蚀工艺可使得该位置 处的第一飩化层 15 的表面形成锯齿状的不规则形状， 或其表 面被粗糙化。
5407、 在形成有上述结构的基板表面对应 TFT 12的沟道 位置处，进行金属材料的沉积，可以形成质地粗个体大的晶粒， 得到锯齿状的结构， 从而完成遮光层 21的制作。
5408、 在形成有上述图案的基板表面形成第一透明电极 16, 这样就在对应 TFT 12的沟道位置处形成用于防止光线透 射的光阻结构 20。
5409、 在形成有第一透明电极 16 的基板表面形成第二飩 化层 17。
5410、 在形成有第二飩化层 17 的基板表面形成第二透明 电极 18。
需要说明的是， 以上仅仅是对图 2和图 4所示的阵列基板 的制作过程进行举例说明， 其他具有光阻结构 20 的阵列基板 的制作过程在这里不再——赘述， 但都应当属于本发明的保护 范围。
以上所述仅为本发明的具体实施方式， 但本发明的保护范 围并不局限于此， 任何熟悉本领域的技术人员在本发明揭露的 范围内， 可轻易想到的变化或替换都应涵盖在本发明的保护范 围之内。 因此， 本发明的保护范围应以所述权利要求的保护范 围为准。

Claims

权 利 要 求 书
1、 一种阵列基板， 包括： 透明基板、 位于所述透明基板 上的 TFT、覆盖所述 TFT的第一飩化层、 以及位于所述第一飩 化层的表面上的第一透明电极； 其特征在于， 所述阵列基板还 包括设置在所述 TFT远离所述透明基板一侧对应所述 TFT的 沟道位置处的用于防止光线透射的光阻结构。
2、 根据权利要求 1 所述的阵列基板， 其特征在于， 所述 光阻结构包括在第一飩化层表面上形成的表面具有连续的多 个斜面或者曲面的微结构。
3、 根据权利要求 1或 2所述的阵列基板， 其特征在于， 所述光阻结构包括位于所述 TFT 与所述第一飩化层之间的遮 光层。
4、 根据权利要求 3所述的阵列基板， 其特征在于， 所述遮光层的材料包括树脂材料。
5、 根据权利要求 1或 2所述的阵列基板，还包括形成于第 一透明电极表面上的第二飩化层， 以及所述光阻结构包括位于 所述第一飩化层与所述第二飩化层之间的遮光层。
6、 根据权利要求 5 所述的阵列基板， 其特征在于， 所述 遮光层的材料包括树脂材料或金属材料。
7、 一种显示装置， 其特征在于， 包括如权利要求 1-6所述 的任一阵列基板。
8、 一种阵列基板的制造方法， 其特征在于， 包括步骤： 在透明基板表面形成 TFT;
在形成 TFT的基板表面上在所述 TFT远离透明基板一侧 对应所述 TFT 沟道的位置处形成用于防止光线透射的光阻结 构。
9、 根据权利要求 8 所述的制造方法， 其特征在于， 在形 成 TFT的基板表面上在所述 TFT远离透明基板一侧对应所述 TFT沟道的位置处形成用于防止光线透射的光阻结构的步骤包 括：
在形成 TFT的基板表面上形成第一飩化层； 以及
在所述第一飩化层的表面上对应所述 TFT 沟道的位置处 通过构图工艺形成表面具有连续的多个斜面或者曲面的微结 构。
10、 根据权利要求 9所述的制造方法， 还包括步骤： 在形成表面具有连续的多个斜面或曲面的微结构的表面 上形成遮光层。
11、 根据权利要求 10 所述的制造方法， 所述遮光层的材 料包括树脂材料或金属材料。
12、 根据权利要求 8所述的制造方法， 其特征在于， 在形 成 TFT的基板表面在所述 TFT远离所述透明基板一侧对应所 述 TFT 沟道的位置处形成用于防止光线透射的光阻结构的步 骤包括：
在形成 TFT的基板表面对应所述 TFT沟道的位置处形成 遮光层。
13、 根据权利要求 12 所述的制造方法， 其特征在于， 所 述遮光层的材料包括树脂材料。
14、 根据权利要求 12或 13所述的制造方法，还包括步骤： 在形成遮光层的表面上形成第一飩化层； 以及 在所述第一飩化层的表面上对应所述 TFT 沟道的位置处 通过构图工艺形成表面具有连续的多个斜面或者曲面的微结 构。
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