WO2014183523A1 - 一种延迟锁相方法和电路 - Google Patents

一种延迟锁相方法和电路 Download PDF

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Publication number
WO2014183523A1
WO2014183523A1 PCT/CN2014/075459 CN2014075459W WO2014183523A1 WO 2014183523 A1 WO2014183523 A1 WO 2014183523A1 CN 2014075459 W CN2014075459 W CN 2014075459W WO 2014183523 A1 WO2014183523 A1 WO 2014183523A1
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Prior art keywords
delay
delay line
main
reference clock
phase
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PCT/CN2014/075459
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English (en)
French (fr)
Inventor
严龙军
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中兴通讯股份有限公司
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Publication of WO2014183523A1 publication Critical patent/WO2014183523A1/zh

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    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/0805Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop

Definitions

  • the present invention relates to the field of integrated circuits, and in particular, to a delay phase locking method and circuit. Background technique
  • delay-locked circuits are widely used in the field of integrated circuits. They are mainly used to generate accurate phase shifts for key signals in some circuits, such as clock signals, and finally adjust the phase relationship between signals, for example, to be sampled. Data and sample signals to get the best sample points.
  • the existing invention patents although implemented by digital or analog circuits, have implemented the function of delay-locking, but they do not involve how to automatically lock the signals in the wide dynamic signal frequency range. Summary of the invention
  • an embodiment of the present invention provides a delay lock phase circuit, and the circuit includes:
  • the phase detecting circuit is configured to: perform phase detection on the reference clock signal delayed by the main delay line;
  • the control circuit is configured to: control the reference clock signal to delay phase lock through the main delay line or from the delay line according to the phase detection result.
  • phase detecting circuit is:
  • the delay phase-locked circuit wherein, when the number of cycles is a full cycle, the phase detection result is determined according to adjacent positive edge phases of the reference clock signal delayed by a main delay line; In the half cycle, the phase detection result is determined according to adjacent negative edge phases of the reference clock signal delayed by the main delay line.
  • control circuit comprises:
  • a calculation circuit configured to: calculate, according to the phase detection result, a target number of delay units when the delay condition is satisfied;
  • a determining circuit configured to: determine whether the number of delay units in the main delay line is lower than the target number
  • the main control circuit is configured to: when the determination result indicates that the number of delay units in the main delay line is not lower than the target number, control the reference clock signal to delay phase lock through the main delay line, and Controlling, in the main delay line, the number of delay units in an active state as the target number; the slave control circuit is configured to: when the determination result indicates that the number of delay units in the main delay line is lower than the When the number of targets is controlled, the reference clock signal is controlled to be delayed-locked from the delay line, and the number of the delay units in the working state in the slave delay line is a preset value.
  • the delay condition is a second delay condition of delaying a half period.
  • an embodiment of the present invention further provides a delay phase locking method, where the method includes:
  • the reference clock signal is controlled to be phase-locked by the main delay line or from the delay line.
  • the delay phase locking method wherein the phase detection of the delayed reference clock signal is: Determining the number of cycles of the reference clock signal delay through the main delay line, the number of cycles being a full cycle or a half cycle.
  • the phase detection result is determined according to adjacent positive edge phases of the reference clock signal delayed by the main delay line;
  • the phase detection result is determined according to adjacent negative edge phases of the reference clock signal delayed by the main delay line.
  • the determination result indicates that the number of delay units in the main delay line is lower than the target number
  • controlling the reference clock signal to delay phase-locking from a delay line, wherein the slave delay line is in operation
  • the number of delay units in the state is a preset value.
  • the delay condition is a first delay condition for delaying a single period.
  • the delay condition is a second delay condition of delaying a half period.
  • the embodiment of the invention has a phase detecting circuit for performing phase detection on the delayed reference clock signal, and the control circuit automatically controls the reference clock signal to pass through the main delay line or within a wide dynamic signal frequency range according to the phase detection result. Delayed phase lock from the delay line.
  • FIG. 1 is a schematic structural diagram of a delay lock phase circuit according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of a delay line according to an embodiment of the present invention.
  • 3 is a schematic diagram of a phase detection circuit according to an embodiment of the present invention
  • 4 is a schematic structural diagram of a delay phase locked circuit according to an embodiment of the present invention
  • FIG. 5 is a schematic flowchart of a delay phase locking method according to an embodiment of the present invention. Preferred embodiment of the invention
  • An embodiment of the present invention provides a delay lock phase circuit, as shown in FIG. 1 , the circuit includes: a main delay line;
  • phase detecting circuit configured to perform phase detection on a reference clock signal delayed by a main delay line
  • a control circuit configured to control the reference clock signal to delay phase lock through the main delay line or from the delay line according to the phase detection result.
  • the delay lock phase circuit provided by the embodiment of the invention has a phase detecting circuit for performing phase detection on the delayed reference clock signal, and further, the control circuit in the delay phase locked circuit is based on the phase detection result, and is in a wide dynamic Within the signal frequency range, the reference clock signal is automatically controlled to be phase-locked through the main delay line or from the delay line for the purpose of the present invention.
  • the main delay line and the slave delay line are composed of a plurality of delay units as shown in Fig. 2 .
  • Both the main delay line and the slave delay line are composed of a number of delay units. Generally, the number of delay units is fixed, and the delay of the input delay line after the delay line is obtained.
  • the circuitry of the delay unit can be constructed with a basic gate circuit for generating a delay in the reference clock signal.
  • the phase detecting circuit is specifically:
  • the number of cycles of the reference clock signal delay that is delayed by the main delay line is determined, the number of cycles being a full cycle or a half cycle.
  • the phase detection result is determined according to adjacent positive edge phases among the reference clock signals delayed by the main delay line;
  • the reference clock signal delayed according to the main delay line The adjacent negative edge phase in the number determines the phase detection result.
  • control circuit specifically includes:
  • a calculation circuit configured to calculate, according to the phase detection result, a target number of delay units when the delay condition is met;
  • a determining circuit configured to determine whether the number of delay units in the main delay line is lower than the target number
  • a main control circuit configured to: when the determination result indicates that the number of delay units in the main delay line is not lower than the target number;
  • a slave control circuit configured to: when the determination result indicates that the number of delay units in the main delay line is lower than the target number, control the reference clock signal to delay phase-locking from a delay line, the slave The number of delay units in the working line in the delay line is a preset value.
  • the main control circuit controls the reference clock signal to delay phase lock through the main delay line, and ensures that the number of delay units in the main delay line is at the target
  • the reference clock signal is automatically controlled to be delayed-locked from the delay line, where the preset delay value can be directly passed (can pass the register) Configure in advance) Give the slave delay line.
  • the above delay condition is specifically a first delay condition for delaying a single period.
  • the detection circuit first detects the number of delay units corresponding to half a cycle, and then detects the number of delay units in one cycle.
  • the frequency of the reference clock signal is high, and the required delay unit is small, preferably, the first delay condition that satisfies the delay single period can be acquired, but if the delay time of the single period exceeds the main delay When the line has the maximum delay capability, the main delay line no longer has the ability to lock in a single cycle. At this time, a half-cycle lock value can be used.
  • the delay condition is specifically a second delay condition delayed by half a cycle.
  • the corresponding clock signal frequency is very low, and the data window is very large.
  • the sample signal can sample the data over a wide range, and does not need to be sampled in the middle of the data. Therefore, we can directly assign the delay line by specifying a fixed delay value (which can be configured in advance through the register). . That is, when the second delay condition of delaying half a cycle is not satisfied, the main delay line is directly bypassed, and the delay from the delay line is controlled with a preset value.
  • an embodiment of the present invention further provides a delay latch circuit, as shown in the figure.
  • the reference clock signal is delayed by the main delay line, and the delayed reference clock signal is phase-detected by the phase detecting circuit, and the result of the detection is sent to the main control circuit.
  • the main control circuit controls the delay of the main delay line, and determines the result of the phase detection, finally calculates the number of delay units of a single clock cycle, and feeds back the state of the locked phase locked circuit; obtains the main delay line from the control circuit
  • the information such as the number of delay units in a single cycle, whether a bypass mode delay code or the like is required, is used to calculate the delay from the delay line.
  • the main delay line is bypassed directly when the second delay condition of the delay half cycle is not satisfied.
  • an embodiment of the present invention further provides a delay phase locking method, where the method is as shown in FIG. 5, including:
  • Step 51 Send a reference clock signal to the main delay line for delay
  • Step 52 Perform phase detection on the delayed reference clock signal.
  • Step 53 Control, according to the phase detection result, the reference clock signal to delay phase lock through the main delay line or from the delay line.
  • phase detection of the delayed reference clock signal is specifically as follows:
  • the number of cycles of the reference clock signal delay through the main delay line is determined, the number of cycles being a full cycle or a half cycle.
  • the control unit controls the parameter to calculate a target number of delay units when the delay condition is satisfied according to the phase detection result; and determine the main delay line Whether the number of delay units is lower than the target number; when the number is controlled, the reference clock signal is controlled to delay phase lock through the main delay line, and the number of delay units in the active delay line is controlled to be The number of targets;
  • the reference clock signal is controlled to be delayed-locked from the delay line, and the number of delay units in the slave delay line is a preset value.
  • the delay condition is specifically a first delay condition that delays a single period.
  • the delay condition is specifically a second delay condition of delaying half a period.
  • the embodiment of the invention has a phase detecting circuit for performing phase detection on the delayed reference clock signal, and the control circuit automatically controls the reference clock signal to pass through the main delay line or within a wide dynamic signal frequency range according to the phase detection result. Delayed phase lock from the delay line.

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  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dram (AREA)

Abstract

一种延迟锁相方法和电路,其中,所述方法包括:将参考时钟信号送到主延迟线进行延迟;对延迟后的所述参考时钟信号进行相位检测;根据相位检测结果,控制所述参考时钟信号经过主延迟线或从延迟线进行延迟锁相。所述方法和电路能够在宽动态信号频率范围内实现信号的自动锁定。

Description

一种延迟锁相方法和电路
技术领域
本发明涉及集成电路领域, 尤其涉及一种延迟锁相方法和电路。 背景技术
目前, 延迟锁相电路在集成电路领域被广泛使用, 主要用于对一些电路 中的关键信号, 例如时钟信号, 产生精确的相移, 最终使得信号间的相位关 系得到调整, 例如待釆样的数据和釆样信号, 从而获得最佳的釆样点。 已有 的发明专利,通过数字或者模拟电路的方式, 虽然都实现了延迟锁相的功能, 但是均未涉及到如何在宽动态信号频率范围内实现信号自动锁定。 发明内容
本发明的目的是提供一种延迟锁相方法和电路, 在宽动态信号频率范围 内实现信号的自动锁定。
为了实现上述目的, 本发明实施例提供了一种延迟锁相电路, 所述电路 包括:
主延迟线;
从延迟线;
相位检测电路, 设置为: 对经过主延迟线延迟后的参考时钟信号进行相 位检测;
控制电路, 设置为: 根据所述相位检测结果, 控制所述参考时钟信号经 过主延迟线或从延迟线进行延迟锁相。
上述的延迟锁相电路, 其中, 所述主延迟线和从延迟线由多个延迟单元 组成。
上述的延迟锁相电路, 其中, 所述相位检测电路为:
确定经过主延迟线进行延迟的所述参考时钟信号延迟的周期数, 所述周 期数为整周期或半周期。 上述的延迟锁相电路, 其中, 所述周期数为整周期时, 根据经过主延迟 线进行延迟的所述参考时钟信号中相邻的正沿相位确定所述相位检测结果; 所述周期数为半周期时, 根据经过主延迟线进行延迟的所述参考时钟信 号中相邻的负沿相位确定所述相位检测结果。
上述的延迟锁相电路, 其中, 所述控制电路包括:
计算电路, 设置为: 根据所述相位检测结果, 计算满足延迟条件时的延 迟单元的目标个数;
判断电路, 设置为: 判断所述主延迟线中的延迟单元个数能否低于所述 目标个数;
主控制电路, 设置为: 当所述判断结果指示所述主延迟线中的延迟单元 个数不低于所述目标个数时, 控制所述参考时钟信号经过主延迟线进行延迟 锁相,并控制所述主延迟线中处于工作状态的延迟单元个数为所述目标个数; 从控制电路, 设置为: 当所述判断结果指示所述主延迟线中的延迟单元 个数低于所述目标个数时, 控制所述参考时钟信号经过从延迟线进行延迟锁 相, 所述从延迟线中的处于工作状态的延迟单元个数为预设值。
上述的延迟锁相电路, 其中, 所述延迟条件为延迟单个周期的第一延迟 条件。
上述的延迟锁相电路, 其中, 当所述主延迟线的延迟单元个数不满足延 迟所述第一延迟条件时, 所述延迟条件为延迟半个周期的第二延迟条件。
为了实现上述目的, 本发明实施例还提供了一种延迟锁相方法, 所述方 法包括:
将参考时钟信号送到主延迟线进行延迟;
对延迟后的所述参考时钟信号进行相位检测;
根据相位检测结果, 控制所述参考时钟信号经过主延迟线或从延迟线进 行延迟锁相。
上述的延迟锁相方法, 其中, 所述主延迟线和从延迟线由多个延迟单元 组成。
上述的延迟锁相方法, 其中, 所述对延迟后的所述参考时钟信号进行相 位检测为: 确定经过主延迟线的所述参考时钟信号延迟的周期数, 所述周期数为整 周期或半周期。
上述的延迟锁相方法, 其中, 所述周期数为整周期时, 根据经过主延迟 线进行延迟的所述参考时钟信号中相邻的正沿相位确定所述相位检测结果; 所述周期数为半周期时, 根据经过主延迟线进行延迟的所述参考时钟信 号中相邻的负沿相位确定所述相位检测结果。
上述的延迟锁相方法, 其中, 所述根据所述相位检测结果, 控制所述参 考时钟信号进行主延迟线或从延迟线进行延迟锁相为:
根据所述相位检测结果, 计算满足延迟条件时的延迟单元的目标个数; 判断所述主延迟线中的延迟单元个数能否低于所述目标个数; 数时, 控制所述参考时钟信号经过主延迟线进行延迟锁相, 并控制所述主延 迟线中处于工作状态的延迟单元个数为所述目标个数;
当所述判断结果指示所述主延迟线中的延迟单元个数低于所述目标个数 时, 控制所述参考时钟信号经过从延迟线进行延迟锁相, 所述从延迟线中的 处于工作状态的延迟单元个数为预设值。
上述的延迟锁相方法, 其中, 所述延迟条件为延迟单个周期的第一延迟 条件。
上述的延迟锁相方法, 其中, 当所述主延迟线的延迟单元个数不满足延 迟所述第一延迟条件时, 所述延迟条件为延迟半个周期的第二延迟条件。
本发明实施例具有相位检测电路, 用于对延迟后的参考时钟信号进行相 位检测, 由控制电路根据相位检测结果, 在宽动态信号频率范围内, 自动控 制所述参考时钟信号经过主延迟线或从延迟线进行延迟锁相。 附图概述
图 1为本发明实施例提供的延迟锁相电路的结构示意图;
图 2为本发明实施例提供的延迟线示意图;
图 3为本发明实施例提供的相位检测电路的示意图; 图 4为本发明实施例提供的延迟锁相电路优选的结构示意图;
图 5为本发明实施例提供的延迟锁相方法的流程示意图。 本发明的较佳实施方式
下面将结合附图及具体实施例进行详细描述。
本发明实施例提供了一种延迟锁相电路, 所述电路如图 1所示, 包括: 主延迟线;
从延迟线;
相位检测电路, 用于对经过主延迟线延迟后的参考时钟信号进行相位检 测;
控制电路, 用于根据所述相位检测结果, 控制所述参考时钟信号经过主 延迟线或从延迟线进行延迟锁相。
本发明实施例提供的延迟锁相电路, 具有一相位检测电路, 用于对延迟 后的参考时钟信号进行相位检测, 进一步地, 由延迟锁相电路中的控制电路 根据相位检测结果, 在宽动态信号频率范围内, 自动控制所述参考时钟信号 经过主延迟线或从延迟线进行延迟锁相, 达到本发明的目的。
上述的延迟锁相电路中, 所述主延迟线和从延迟线如图 2所示, 由多个 延迟单元组成。
主延迟线和从延迟线均由若干个延迟单元组成, 一般来说, 延迟单元的 个数是固定的, 输入延迟线的信号经过延迟线后, 会获取到若干的延迟。 延 迟单元的电路可以用基本的门电路进行构造, 用于产生对参考时钟信号延迟 的效果。
上述的延迟锁相电路中, 所述相位检测电路具体为:
确定经过主延迟线进行延迟的所述参考时钟信号延迟的周期数, 所述周 期数为整周期或半周期。
如图 3所示, 所述周期数为整周期时, 根据经过主延迟线进行延迟的所 述参考时钟信号中相邻的正沿相位确定所述相位检测结果;
所述周期数为半周期时, 根据经过主延迟线进行延迟的所述参考时钟信 号中相邻的负沿相位确定所述相位检测结果。
上述的延迟锁相电路中, 所述控制电路具体包括:
计算电路, 用于根据所述相位检测结果, 计算满足延迟条件时的延迟单 元的目标个数;
判断电路, 用于判断所述主延迟线中的延迟单元个数能否低于所述目标 个数;
主控制电路, 用于当所述判断结果指示所述主延迟线中的延迟单元个数 不低于所述目标个数时, 控制所述;
从控制电路, 用于当所述判断结果指示所述主延迟线中的延迟单元个数 低于所述目标个数时, 控制所述参考时钟信号经过从延迟线进行延迟锁相, 所述从延迟线中的处于工作状态的延迟单元个数为预设值。
根据相位检测电路获得的相位检测结果, 计算足延迟条件时的延迟单元 的目标个数,当延迟锁相电路中的主延迟线的延迟能力能够满足延迟条件时, 即所述主延迟线中的延迟单元个数不低于所述目标个数时,通过主控制电路, 控制参考时钟信号经过主延迟线进行延迟锁相, 并且保证所述主延迟线中处 于工作状态的延迟单元个数达到目标个数; 当延迟锁相电路中的主延迟线的 延迟能力不能够满足延迟条件时, 就自动控制参考时钟信号经过从延迟线进 行延迟锁相, 这里可以直接通过预设延迟值(可以通过寄存器提前配置好) 给从延迟线。
上述延迟条件具体为延迟单个周期的第一延迟条件。
一般情况下, 检测电路会先检测到半个周期对应的延迟单元个数, 再检 测到一个周期的延迟单元个数。 在本发明实施例中, 如果参考时钟信号的频 率较高, 需要的延迟单元较少, 优选地, 可以获取到满足延迟单个周期的第 一延迟条件, 但是, 如果单个周期的延迟时间超出主延迟线最大的延迟能力 时, 主延迟线就不再具备单个周期的锁定能力, 这个时候可以使用半个周期 锁定值。
即, 当所述主延迟线的延迟单元个数不满足延迟所述第一延迟条件时, 所述延迟条件具体为延迟半个周期的第二延迟条件。
此时, 对应的情况时, 参考时钟信号频率很低,数据的釆样窗口非常大, 釆样信号可以在很宽的范围对数据进行釆样, 并不需要在数据的中间位置去 釆样, 因此, 我们可以直接通过指定固定的延迟值(可以通过寄存器提前配 置好)给从延迟线。 即, 在延迟半个周期的第二延迟条件不满足时, 直接旁 路主延迟线, 而用预先设定的值去控制从延迟线的延迟。
综合上述过程, 本发明实施例还提供了一种优选地延迟锁存电路, 如图
4所示:
一般参考时钟信号经主延迟线进行延迟, 延迟后的参考时钟信号经相位 检测电路进行相位检测, 检测的结果送主控制电路。 主控制电路对主延迟线 的延迟进行控制, 并判决相位检测的结果, 最终计算出单个时钟周期的延迟 单元个数, 并反馈延迟锁相电路锁定的状态; 从控制电路获取到主延迟线提 供的信息, 如单个周期的延迟单元数、 是否需要使用旁路模式延迟码等, 从 而计算出从延迟线的延迟。 在延迟半个周期的第二延迟条件不满足时, 直接 旁路主延迟线。
为了实现上述目的, 本发明实施例还提供了一种延迟锁相方法, 所述方 法如图 5所示, 包括:
步骤 51 , 将参考时钟信号送到主延迟线进行延迟;
步骤 52, 对延迟后的所述参考时钟信号进行相位检测;
步骤 53 , 根据相位检测结果, 控制所述参考时钟信号经过主延迟线或从 延迟线进行延迟锁相。
上述的延迟锁相方法, 其中, 所述主延迟线和从延迟线由多个延迟单元 组成。
上述的延迟锁相方法, 其中, 所述对延迟后的所述参考时钟信号进行相 位检测具体为:
确定经过主延迟线的所述参考时钟信号延迟的周期数, 所述周期数为整 周期或半周期。
上述的延迟锁相方法, 其中, 所述周期数为整周期时, 根据经过主延迟 线进行延迟的所述参考时钟信号中相邻的正沿相位确定所述相位检测结果; 所述周期数为半周期时, 根据经过主延迟线进行延迟的所述参考时钟信 号中相邻的负沿相位确定所述相位检测结果。 上述的延迟锁相方法, 其中, 所述根据所述相位检测结果, 控制所述参 根据所述相位检测结果, 计算满足延迟条件时的延迟单元的目标个数; 判断所述主延迟线中的延迟单元个数能否低于所述目标个数; 数时, 控制所述参考时钟信号经过主延迟线进行延迟锁相, 并控制所述主延 迟线中处于工作状态的延迟单元个数为所述目标个数;
否则, 控制所述参考时钟信号经过从延迟线进行延迟锁相, 所述从延迟 线中的处于工作状态的延迟单元个数为预设值。
上述的延迟锁相方法, 其中, 所述延迟条件具体为延迟单个周期的第一 延迟条件。
上述的延迟锁相方法, 其中, 当所述主延迟线的延迟单元个数不满足延 迟所述第一延迟条件时,所述延迟条件具体为延迟半个周期的第二延迟条件。
以上所述仅是本发明的优选实施方式, 应当指出, 对于本技术领域的普 通技术人员来说, 在不脱离本发明原理的前提下, 还可以做出若干改进和润 饰, 这些改进和润饰也应视为本发明的保护范围。
工业实用性
本发明实施例具有相位检测电路, 用于对延迟后的参考时钟信号进行相 位检测, 由控制电路根据相位检测结果, 在宽动态信号频率范围内, 自动控 制所述参考时钟信号经过主延迟线或从延迟线进行延迟锁相。

Claims

权 利 要 求 书
1. 一种延迟锁相电路, 所述电路包括:
主延迟线;
从延迟线;
相位检测电路, 设置为: 对经过主延迟线延迟后的参考时钟信号进行相 位检测;
控制电路, 设置为: 根据所述相位检测结果, 控制所述参考时钟信号经 过主延迟线或从延迟线进行延迟锁相。
2. 如权利要求 1所述的延迟锁相电路, 其中, 所述主延迟线和从延迟线 由多个延迟单元组成。
3.如权利要求 2所述的延迟锁相电路, 其中, 所述相位检测电路为: 确定经过主延迟线进行延迟的所述参考时钟信号延迟的周期数, 所述周 期数为整周期或半周期。
4. 如权利要求 3所述的延迟锁相电路, 其中, 所述周期数为整周期时, 根据经过主延迟线进行延迟的所述参考时钟信号中相邻的正沿相位确定所述 相位检测结果;
所述周期数为半周期时, 根据经过主延迟线进行延迟的所述参考时钟信 号中相邻的负沿相位确定所述相位检测结果。
5. 如权利要求 3所述的延迟锁相电路, 其中, 所述控制电路包括: 计算电路, 设置为: 根据所述相位检测结果, 计算满足延迟条件时的延 迟单元的目标个数;
判断电路, 设置为: 判断所述主延迟线中的延迟单元个数能否低于所述 目标个数;
主控制电路, 设置为: 当所述判断结果指示所述主延迟线中的延迟单元 个数不低于所述目标个数时, 控制所述参考时钟信号经过主延迟线进行延迟 锁相,并控制所述主延迟线中处于工作状态的延迟单元个数为所述目标个数; 从控制电路, 设置为: 当所述判断结果指示所述主延迟线中的延迟单元 个数低于所述目标个数时, 控制所述参考时钟信号经过从延迟线进行延迟锁 相, 所述从延迟线中的处于工作状态的延迟单元个数为预设值。
6.如权利要求 5所述的延迟锁相电路, 其中, 所述延迟条件为延迟单个 周期的第一延迟条件。
7.如权利要求 6所述的延迟锁相电路, 其中, 当所述主延迟线的延迟单 元个数不满足延迟所述第一延迟条件时, 所述延迟条件为延迟半个周期的第 二延迟条件。
8.—种延迟锁相方法, 所述方法包括:
将参考时钟信号送到主延迟线进行延迟;
对延迟后的所述参考时钟信号进行相位检测;
根据相位检测结果, 控制所述参考时钟信号经过主延迟线或从延迟线进 行延迟锁相。
9. 如权利要求 8所述的延迟锁相方法, 其中, 所述主延迟线和从延迟线 由多个延迟单元组成。
10.如权利要求 9所述的延迟锁相方法, 其中, 所述对延迟后的所述参考 时钟信号进行相位检测为:
确定经过主延迟线的所述参考时钟信号延迟的周期数, 所述周期数为整 周期或半周期。
11. 如权利要求 10所述的延迟锁相方法,其中,所述周期数为整周期时, 根据经过主延迟线进行延迟的所述参考时钟信号中相邻的正沿相位确定所述 相位检测结果;
所述周期数为半周期时, 根据经过主延迟线进行延迟的所述参考时钟信 号中相邻的负沿相位确定所述相位检测结果。
12. 如权利要求 10所述的延迟锁相方法, 其中, 所述根据所述相位检测 结果, 控制所述参考时钟信号进行主延迟线或从延迟线进行延迟锁相为: 根据所述相位检测结果, 计算满足延迟条件时的延迟单元的目标个数; 判断所述主延迟线中的延迟单元个数能否低于所述目标个数; 数时, 控制所述参考时钟信号经过主延迟线进行延迟锁相, 并控制所述主延 迟线中处于工作状态的延迟单元个数为所述目标个数; 当所述判断结果指示所述主延迟线中的延迟单元个数低于所述目标个数 时, 控制所述参考时钟信号经过从延迟线进行延迟锁相, 所述从延迟线中的 处于工作状态的延迟单元个数为预设值。
13.如权利要求 12所述的延迟锁相方法, 其中, 所述延迟条件为延迟单 个周期的第一延迟条件。
14.如权利要求 13所述的延迟锁相方法, 其中, 当所述主延迟线的延迟 单元个数不满足延迟所述第一延迟条件时, 所述延迟条件为延迟半个周期的 第二延迟条件。
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