WO2014183422A1 - 薄膜晶体管及其制备方法、阵列基板 - Google Patents

薄膜晶体管及其制备方法、阵列基板 Download PDF

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Publication number
WO2014183422A1
WO2014183422A1 PCT/CN2013/088543 CN2013088543W WO2014183422A1 WO 2014183422 A1 WO2014183422 A1 WO 2014183422A1 CN 2013088543 W CN2013088543 W CN 2013088543W WO 2014183422 A1 WO2014183422 A1 WO 2014183422A1
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Prior art keywords
layer
active layer
electrode
gate
drain
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English (en)
French (fr)
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张文余
田宗民
李婧
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to US14/388,634 priority Critical patent/US9620651B2/en
Publication of WO2014183422A1 publication Critical patent/WO2014183422A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6728—Vertical TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6732—Bottom-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6746—Amorphous silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • Embodiments of the present invention relate to a thin film transistor, a method of fabricating the same, and an array substrate. Background technique
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the array substrate is one of the important components of the thin film transistor liquid crystal display, and its cross-sectional structure is as shown in FIG. 1 , and mainly includes a substrate 10 , a gate electrode 20 disposed on the substrate 10 , a gate insulating layer 30 , an active layer 40 , and a source including A source/drain metal layer of 501 and drain 502, and a protective layer 60 and a pixel electrode layer 70.
  • the on-state current of the thin film transistor is; where / is equal Effective carrier mobility, t im is the thickness of the gate insulating layer, ⁇ is the capacitance value of the gate insulating layer per unit area,
  • W is the channel width
  • L is the channel length
  • V gs is the gate-source voltage
  • V ds is the drain-source voltage
  • V th is the threshold voltage.
  • the channel length of the thin film transistor is generally 3 ⁇ 4 ⁇ , which results in the on-state current of the thin film transistor not being too large.
  • Embodiments of the present invention provide a thin film transistor, a method of fabricating the same, and an array substrate, which can reduce a channel length of a thin film transistor, thereby increasing an on-state current, thereby improving characteristics of the thin film transistor.
  • an embodiment of the present invention provides a thin film transistor including a gate, a gate insulating layer, an active layer, a source, and a drain disposed on a substrate, wherein a substrate perpendicular to the substrate a direction, the source and the drain are respectively disposed on two sides of the active layer, and the source and the The drain is in contact with the active layer.
  • embodiments of the present invention provide an array substrate comprising the above-described thin film transistor.
  • an embodiment of the present invention provides a method for fabricating a thin film transistor, including: forming a gate, a gate insulating layer, an active layer, a source, and a drain on a substrate, wherein In the direction of the substrate of the substrate, the source and the drain are respectively formed on both sides of the active layer, and the source and the drain are in contact with the active layer.
  • 1 is a cross-sectional structural view of a conventional array substrate
  • FIG. 2 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of another thin film transistor according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of still another thin film transistor according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of an array substrate according to an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of another array substrate according to an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of an array substrate including a common electrode according to an embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of another array substrate including a common electrode according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a process for fabricating two thin film transistors according to an embodiment of the present invention. detailed description
  • the embodiment of the present invention provides a thin film transistor.
  • the thin film transistor includes: a gate electrode 20 disposed on the base substrate 10, a gate insulating layer 30, an active layer 40, and a source electrode 501. And a drain 502; wherein, in a direction perpendicular to the substrate, the source 501 and the drain 502 are respectively disposed on two sides of the active layer 40, and the source and the The drain is in contact with the active layer 40.
  • the gate insulating layer 30 is provided between the gate electrode 20 and the active layer 40.
  • the source 501 and the drain 502 are respectively disposed on two sides of the active layer 40, and the contact with the active layer refers to two forms, the first one being When the thin film transistor is prepared, the source electrode 501 is formed first, then the active layer 40 is formed, and then the drain electrode 502 is formed, wherein the source electrode 501 is in contact with the lower surface of the active layer 40, The drain 502 is in contact with the upper surface of the active layer 40; the second is, in the preparation of the thin film transistor, the drain 502 is formed first, then the active layer 40 is formed, and then the formation The source 501 is in contact with the lower surface of the active layer 40, and the source 501 is in contact with the upper surface of the active layer 40.
  • other pattern layers may be formed between the two, which are not limited herein.
  • the manner in which the source 501 and the drain 502 are in contact with the active layer 40 is not limited, and may be direct contact or via via contact.
  • Embodiments of the present invention provide a thin film transistor including a gate, a gate insulating layer, an active layer, a source, and a drain, wherein the source is in a direction perpendicular to the substrate a drain and the drain are respectively disposed on both sides of the active layer and in contact with the active layer; since a channel length of the thin film transistor is determined by a thickness of the active layer, The thickness of the active layer between the source and the drain is set to reduce the channel length, thereby increasing the on-state current of the thin film transistor, thereby improving the characteristics of the thin film transistor.
  • channel length determined by the thickness of the active layer described in all embodiments of the present invention corresponds to the channel length between the source and the drain of the thin film transistor in the background art.
  • one example structure of the thin film transistor provided by the embodiment of the present invention may be: the source 501 is disposed between the base substrate 10 and the active layer 40, and the drain 502 is disposed.
  • the active layer 40 is away from a side of the base substrate 10.
  • the gate insulating layer 30 may be disposed between the drain 502 and the active layer 40, and the drain 502 is disposed on the gate insulating layer.
  • the first via 301 is in contact with the active layer 40; the gate 20 is disposed in the same layer as the drain 502, and the gate insulating layer is disposed between the gate 20 and the active layer 40. 30.
  • the gate 20 is not connected to the drain 502.
  • the gate electrode 20 is disposed in the same layer as the drain electrode 502, and refers to the gate electrode 20 and the drain electrode 502 formed by the same layer of metal film processed by one patterning process. This reduces the number of patterning processes and reduces costs.
  • the active layer 40 may be a metal oxide semiconductor active layer or an amorphous silicon semiconductor layer.
  • the active layer 40 further includes the amorphous silicon semiconductor.
  • another example structure of the thin film transistor provided by the embodiment of the present invention may further be: the drain 502 is disposed between the base substrate 10 and the active layer 40, the source 501 is disposed on a side of the active layer 40 away from the base substrate 10.
  • the gate insulating layer 30 may be disposed between the source 501 and the active layer 40, and the source 501 is insulated by the gate.
  • a first via 301 in the layer is in contact with the active layer 40; the gate insulating layer 30 is disposed between the gate 20 and the active layer 40, the gate 20 and the source 501 is disposed in the same layer, and the gate 20 is not connected to the source 501.
  • the gate electrode 20 is disposed in the same layer as the source electrode 501, and refers to the gate electrode 20 and the source electrode 501 formed by the same layer of metal film processed by one patterning process. This reduces the number of patterning processes and reduces costs.
  • the active layer 40 may be a metal oxide semiconductor active layer or an amorphous silicon semiconductor layer.
  • the active layer 40 further includes the amorphous silicon semiconductor.
  • Embodiment 1 Two specific embodiments will be provided below to describe in detail the structures of the above two thin film transistors. Embodiment 1
  • the present embodiment provides a thin film transistor.
  • the thin film transistor includes: a source 501 disposed on the base substrate 10, and an active layer 40 disposed above the source. A drain 502 over the source layer, and a gate insulating layer 30 disposed between the active layer and the drain and a gate 20 disposed over the gate insulating layer.
  • the active layer 40 includes an amorphous silicon semiconductor layer 401 located in the middle, located at the non- A first ohmic contact layer 402 over the crystalline silicon semiconductor layer and a second ohmic contact layer 403 under the amorphous silicon semiconductor layer.
  • the source 501 is in contact with the second ohmic contact layer 403 of the active layer 40, the drain 502 is in the same layer but not connected to the gate 20, and the drain 502 is disposed through the gate.
  • the first via 301 in the insulating layer 30 is in contact with the first ohmic contact layer 402 of the active layer 40.
  • the active layer is not limited to include an amorphous silicon semiconductor layer, and the first and second ohmic contact layers, and the active layer may also be a metal oxide semiconductor. Source layer.
  • the present embodiment provides a thin film transistor including a source, an active layer, a gate insulating layer, and drains and gates disposed in the same layer and not connected to each other;
  • the source layer includes an amorphous silicon semiconductor layer located in the middle, and a first ohmic contact layer and a second ohmic contact layer respectively located above and below the amorphous silicon semiconductor layer, the source being in contact with the second ohmic contact layer
  • the drain is in contact with the first ohmic layer through a first via provided in the gate insulating layer; since the channel length of the thin film transistor is determined by the thickness of the active layer, By setting the thickness of the active layer, the channel length can be reduced, thereby increasing the on-state current of the thin film transistor, thereby improving the characteristics of the thin film transistor.
  • the present embodiment provides a thin film transistor.
  • the thin film transistor includes: a drain 502 disposed on the base substrate 10, and an active layer 40 disposed above the drain, disposed in the A source 501 over the active layer, and a gate insulating layer 30 disposed between the active layer and the source and a gate 20 disposed over the gate insulating layer.
  • the active layer 40 includes an amorphous silicon semiconductor layer 401 located in the middle, a first ohmic contact layer 402 over the amorphous silicon semiconductor layer, and a second ohmic contact under the amorphous silicon semiconductor layer.
  • the drain 502 is in contact with the second ohmic contact layer 403 of the active layer 40, the source
  • the source 501 is in the same layer but not connected to the gate 20, and the source 501 is in contact with the first ohmic contact layer 402 of the active layer 40 through the first via 301 disposed in the gate insulating layer 30. .
  • the active layer is not limited to include an amorphous silicon semiconductor layer, and the first and second ohmic contact layers, and the active layer may also be a metal oxide semiconductor.
  • Source layer The present embodiment provides a thin film transistor including a drain, an active layer, a gate insulating layer, and a source and a gate which are disposed in the same layer and are not connected to each other; wherein the active layer includes An amorphous silicon semiconductor layer located in the middle, and a first ohmic contact layer and a second ohmic contact layer respectively located above and below the amorphous silicon semiconductor layer, the drain being in contact with the second ohmic contact layer, The source is in contact with the first ohmic layer through a first via provided on the gate insulating layer; since a channel length of the thin film transistor is determined by a thickness of the active layer, The thickness of the active layer can reduce the channel length, thereby increasing the on-state current of the thin film transistor, thereby improving the
  • the thin film transistor provided by the embodiment of the present invention is not limited to the structure of the thin film transistor described in the above two embodiments, and may be other structures, and details are not described herein again.
  • An embodiment of the present invention further provides an array substrate, as shown in FIG. 6 and FIG. 7, the array substrate includes the thin film transistor and the pixel electrode 70, wherein the pixel electrode 70 and the drain of the thin film transistor 502 connection.
  • the array substrate may further include a protective layer 60.
  • the source 501 of the thin film transistor is disposed between the base substrate 10 and the active layer 40, and the gate insulating layer 30 is disposed at the drain.
  • a first via 301 is disposed in the gate insulating layer 30, and the drain 502 is in contact with the active layer 40 through the first via 301, and
  • the gate electrode 20 is disposed in the same layer as the drain electrode 502
  • the pixel electrode 70 passes through the second via hole 601 and the drain electrode 502 in the protective layer 60 disposed above the gate and the drain. connection.
  • the gate insulating layer 30 is disposed on the source 501 and Between the active layers 40, a first via 301 is disposed in the gate insulating layer 30, and the source 501 is in contact with the active layer 30 through the first via 301, and the gate is In the case where the pole 20 is disposed in the same layer as the source 501, the pixel electrode 70 passes through the second via 601 disposed in the protective layer 60 above the gate and the source and is disposed on the gate insulating layer 30.
  • the third via 302 is connected to the drain 502.
  • the second via 601 and the third via 302 may be formed by one etching process.
  • the array substrate includes, in order from bottom to top, a substrate substrate 10 , a source 501 disposed on the substrate substrate, and a data line connected to the source (FIG.
  • An active layer 40 disposed above the source, a gate insulating layer 30 disposed over the active layer 40, and a layer disposed above the gate insulating layer 30 but not connected a drain 502 and a gate 20, and a gate line (not shown) connected to the gate 20, wherein a first via 301 is disposed in the gate insulating layer 30, and the drain 502 passes through the first via 301.
  • the active layer 40 further comprising: a protective layer 60, and a pixel electrode 70 disposed on the protective layer, and the pixel electrode 70 passes through a second pass disposed in the protective layer 60
  • a hole 601 is connected to the drain 502.
  • the gate electrode 20 constitutes a thin film transistor.
  • the array substrate includes, in order from bottom to top, a substrate substrate 10, a drain 502 disposed on the substrate, and a drain disposed above the drain. a source layer 40, a gate insulating layer 30 disposed above the active layer 40, and a source 501 disposed on the same layer above the gate insulating layer 30, and a data line connected to the source 501 (not shown) And a gate line 20 connected to the gate electrode 20 (not shown), wherein the source electrode 501 is not connected to the gate electrode 20, and the gate insulating layer 30 is provided with a first
  • the via 301 is in contact with the active layer 40 through the first via 301, and further includes: a protective layer 60, and a pixel electrode 70 disposed on the protective layer, and the pixel electrode 70
  • the drain 502 is connected through a second via 601 disposed in the protective layer 60 and a third via 302 in the gate insulating layer 30.
  • a drain 502 an active layer 40 disposed above the drain, a gate insulating layer 30 disposed over the active layer, and a source disposed on the same layer but not connected above the gate insulating layer 501 and gate 20 constitute a thin film transistor.
  • the channel length of the thin film transistor is determined by the thickness of the active layer, by appropriately setting the thickness of the active layer, the channel length can be reduced, thereby increasing The on-state current of the thin film transistor further enhances the characteristics of the thin film transistor.
  • the array substrate provided by the embodiment of the present invention can be used as a TN type, an advanced-super-dimension switch (In-Plane Switching), and an in-plane switching (In-Plane Switching, IPS)
  • An array substrate of a liquid crystal display device and can be used as an array substrate of an organic electroluminescence display device (OLED).
  • OLED organic electroluminescence display device
  • the core of the advanced super-dimensional field-switching liquid crystal display device can be described as: forming a multi-dimensional electric field by an electric field generated by the edge of the slit electrode in the same plane and an electric field generated between the slit electrode layer and the plate-like electrode layer, so that the liquid crystal All the aligned liquid crystal molecules between the slit electrodes in the box and directly above the electrodes can rotate, thereby improving the liquid crystal working efficiency and increasing the light transmission efficiency.
  • Advanced super-dimensional field conversion technology can improve the picture quality of thin film transistor liquid crystal displays, with high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, no push spur (push Mura), etc. advantage.
  • the organic electroluminescence display device has self-luminous characteristics, and has the advantages of large viewing angle and remarkable power saving.
  • the array substrate further includes: a passivation layer 90 and a common electrode 80.
  • An embodiment of the present invention provides an array substrate including the thin film transistor, and a pixel electrode and a common electrode.
  • the channel length of the thin film transistor is determined by the thickness of the active layer, By properly setting the thickness of the active layer, the channel length can be reduced, thereby increasing the on-state current of the thin film transistor, thereby improving the characteristics of the thin film transistor; on the other hand, since the pixel electrode and the common electrode are both located on the array substrate When the array substrate is applied to a display, it has the advantages of high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, and no push mura.
  • An embodiment of the present invention further provides a method of fabricating a thin film transistor, the method comprising: forming a gate 20, a gate insulating layer 30, an active layer 40, a source 501, and a drain 502 on a substrate 10;
  • the source 501 and the drain 502 are respectively formed on both sides of the active layer 40 in a direction perpendicular to the substrate, and the source 501 and the drain 502 are The active layer 40 is in contact.
  • the gate is formed in the same patterning process as the source/drain, the gate is not connected to the drain, and the gate is disposed between the gate and the active layer Insulation.
  • Embodiments of the present invention provide a method of fabricating a thin film transistor, the method comprising: forming a gate, a gate insulating layer, an active layer on a substrate, and in a direction perpendicular to the substrate, Forming a source and a drain in contact with the active layer on both sides of the active layer; since the channel length of the thin film transistor is determined by the thickness of the active layer, it can be located at a reasonable setting The thickness of the active layer between the source and the drain to reduce the channel length, thereby increasing the thin film transistor The on-state current increases the characteristics of the thin film transistor.
  • the source 501 and the drain 502 are respectively formed on both sides of the active layer 40.
  • the source 501 is formed between the base substrate 10 and the active layer 40.
  • the drain 502 is formed on a side of the active layer 40 away from the base substrate 10.
  • the drain 502 is formed on a side of the active layer 40 away from the base substrate 10, and the gate insulating layer 30 is formed between the drain 502 and the active layer 40.
  • the drain 502 is in contact with the active layer 40 through a first via 301 formed in the gate insulating layer 30; the gate 20 is formed in the same layer as the drain 502, and the gate The pole 20 is not connected to the drain 502.
  • Embodiment 5 A specific embodiment will be provided below to describe in detail the preparation method of the above thin film transistor. Embodiment 5
  • This embodiment provides a method for preparing a thin film transistor, including the following steps:
  • a metal thin film is formed on the base substrate 10, and processed by a patterning process to form a source 501 as shown in FIG.
  • a thickness can be prepared on the base substrate 10 using a magnetron sputtering method.
  • the metal material can usually be a metal such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, or a combination of the above-mentioned materials.
  • the source electrode 501 is formed on a certain area of the substrate by a patterning process such as exposure, development, etching, and lift-off.
  • step S102 On the substrate on which step S101 is completed, an active layer film is formed, and the active layer 40 is formed by one patterning process.
  • a metal oxide semiconductor thin film can be deposited on the substrate on which the source electrode 501 is formed by chemical vapor deposition. Then, the active layer 40 as shown in Fig. 11 is formed on a certain area of the substrate by a patterning process such as exposure, development, etching, and peeling.
  • An amorphous silicon film and an n+ amorphous silicon film having a thickness of 1000 A to 6000 A may be deposited on the substrate on which the source electrode 501 is formed, and then processed by a patterning process such as exposure, development, etching, and peeling, in a certain region of the substrate. Formed as shown in Figure 12, including the amorphous silicon semiconductor layer in the middle
  • step S103 Form an insulating film on the substrate that completes step S102, and pass through a patterning process.
  • the gate insulating layer 30 including the first via hole 301 is formed.
  • the first via 301 exposes the active layer 40.
  • an insulating film having a thickness of 1000 A to 6000 A may be continuously deposited on the substrate by chemical vapor deposition.
  • the material of the insulating film is usually silicon nitride, and silicon oxide, silicon oxynitride or the like may also be used.
  • the gate insulating layer 30 having the first via hole 301 as shown in Fig. 13 or Fig. 14 is formed by exposure, development, and etching.
  • a metal thin film having a thickness of 1000 A to 7000 A can be prepared on a glass substrate using a magnetron sputtering method.
  • the metal material can usually be a metal such as molybdenum, aluminum, an aluminum-nickel alloy, a molybdenum-tungsten alloy, chromium, or copper, or a combination of the above-mentioned materials.
  • a drain electrode 502 that is in contact with the active layer 40 through the first via hole 301 is formed on a certain region of the substrate by a patterning process such as exposure, development, etching, and peeling, and the gate electrode 20 is simultaneously formed.
  • An embodiment of the present invention provides a method for fabricating a thin film transistor, the method comprising: sequentially forming a source, an active layer, a gate insulating layer, and a drain and a gate formed in the same layer and not connected on the substrate; wherein The source is in contact with a lower surface of the active layer, and the drain is in contact with an upper surface of the active layer through a first via formed in the gate insulating layer;
  • the channel length is determined by the thickness of the active layer. Therefore, by appropriately setting the thickness of the active layer, the channel length can be reduced, thereby increasing the on-state current of the thin film transistor and further improving the characteristics of the thin film transistor.
  • the method may be as follows: after the steps S101-S104 are completed, the method further includes: forming a protective layer 60 and a pixel on the substrate with reference to FIG. The electrode 70, wherein the pixel electrode 70 is electrically connected to the drain 502 through a second via 601 formed in the protective layer 60.
  • the method may further include: forming a passivation layer 90 and a common electrode 80 as shown in FIG.
  • the method for fabricating the thin film transistor provided by the embodiment of the present invention is not limited to the above embodiment.
  • the method for fabricating the thin film transistor provided by the embodiment of the present invention may further be: the drain
  • the source 201 is formed on a side of the active layer 40 away from the base substrate.
  • the source 501 is formed on a side of the active layer 40 away from the base substrate.
  • the gate insulating layer 30 is formed between the source 501 and the active layer 40.
  • the source electrode 501 is in contact with the active layer 40 through a first via 301 formed on the gate insulating layer 30; the gate electrode 20 is formed in the same layer as the source electrode 501.
  • the method includes the following steps:
  • a metal thin film is formed on the base substrate 10, and a drain 502 is formed by one patterning process.
  • the active layer film is formed on the substrate of step S201, and the active layer 40 is formed by one patterning process.
  • the active layer 40 is formed by depositing a metal oxide semiconductor film on a substrate; or, as shown in FIG. 5, the active layer 40 includes an amorphous silicon semiconductor layer 401 located in the middle. And a first ohmic contact layer 402 and a second ohmic contact layer 403 respectively located above and below the amorphous silicon semiconductor layer, that is, formed by depositing an amorphous silicon film and an n+ amorphous silicon film on the substrate.
  • step S203 forming a metal thin film on the substrate on which step S203 is completed, and performing a patterning process to form a source 501 and a gate 20 as shown in FIG. 3 or 5; wherein the source 501 passes through the gate insulating layer
  • the first via hole 301 is in contact with the active layer 40.
  • Embodiments of the present invention provide a method of fabricating a thin film transistor, the method comprising: sequentially forming a drain, an active layer, a gate insulating layer, and a source and a gate formed in the same layer on a base substrate; The drain is in contact with a lower surface of the active layer, and the source is in contact with an upper surface of the active layer through a first via formed in the gate insulating layer; due to a trench of the thin film transistor The track length is determined by the thickness of the active layer. Therefore, by appropriately setting the thickness of the active layer, the channel length can be reduced, thereby increasing the on-state current of the thin film transistor, thereby improving the characteristics of the thin film transistor. Sex.
  • the method may be: after completing the above steps S201-S204, further comprising: forming a protective layer 60 and a pixel as shown in FIG. 7 on the substrate; The electrode 70, wherein the pixel electrode 70 is electrically connected to the drain 502 through a second via 601 formed in the protective layer 60 and a third via 302 disposed in the gate insulating layer 30.
  • the method further includes forming a passivation layer 90 and a common electrode 80 as shown in FIG.
  • Embodiments of the present invention provide a thin film transistor and a method of fabricating the same, and an array substrate including a gate, a gate insulating layer, an active layer, a source, and a drain, wherein the substrate is vertical
  • the source and the drain are respectively disposed on both sides of the active layer and in contact with the active layer; since the channel length of the thin film transistor is from the active layer
  • the thickness is determined, so that the thickness of the active layer between the source and the drain can be appropriately set to reduce the channel length, thereby increasing the on-state current of the thin film transistor, thereby improving the characteristics of the thin film transistor.

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Abstract

提供一种薄膜晶体管及其制备方法、阵列基板，该薄膜晶体管包括设置在衬底基板（10）上的栅极（20）、栅绝缘层（30）、有源层（40）、源极（501）、以及漏极（502），其中沿垂直于所述衬底基板（10）的方向，所述源极（501）和漏极（502）分别设置在所述有源层（40）两侧，且所述源极（501）和所述漏极（502）与有源层（40）接触。

Description

薄膜晶体管及其制备方法、 阵列基板 技术领域
本发明的实施例涉及一种薄膜晶体管及其制备方法、 阵列基板。 背景技术
薄膜晶体管液晶显示器（TFT-LCD, Thin Film Transistor-Liquid Crystal Display )具有体积小、 功耗低、 无辐射等特点， 在当前的显示器市场中占据 主导地位。
阵列基板是薄膜晶体管液晶显示器的重要部件之一， 其剖面结构如图 1 所示， 主要包括基板 10、 设置在基板 10上的栅极 20、 栅绝缘层 30、 有源层 40、 包括源极 501和漏极 502的源漏金属层、 以及保护层 60和像素电极层 70。 薄膜晶体管的开态电流为 ; 其中， /为等 效载流子迁移率， tim为栅绝缘层厚度， ^为单位面积栅绝缘层的电容值，
W为沟道宽度， L为沟道长度， Vgs为栅极-源极电压， Vds为漏极 -源极电压， Vth为阀值电压。 显然， 由上述公式可知， 沟道长度 L越小， TFT的开态电 流越大。 这里沟道长度 L即为源极和漏极的距离， 例如图 1中双箭头所示。
然而， 在阵列基板的制备过程中， 由于现有工艺的限制， 薄膜晶体管的 沟道长度一般最小能做到 3~4μηι, 导致薄膜晶体管的开态电流不能太大。 发明内容
本发明的实施例提供一种薄膜晶体管及其制备方法、 阵列基板， 可减小 薄膜晶体管的沟道长度， 从而增大开态电流， 进而提高薄膜晶体管的特性。
一方面， 本发明的实施例提供一种薄膜晶体管， 包括设置在衬底基板上 的栅极、 栅绝缘层、 有源层、 源极、 以及漏极， 其中沿垂直于所述衬底基板 的方向， 所述源极和所述漏极分别设置在所述有源层两侧， 且所述源极和所 述漏极与所述有源层接触。
另一方面， 本发明的实施例提供了一种阵列基板， 包括上述的薄膜晶体 管。
再一方面， 本发明的实施例提供了一种薄膜晶体管的制备方法， 包括： 在村底基板上形成栅极、 栅绝缘层、 有源层、 源极、 以及漏极， 其中沿垂直 于所述村底基板的方向，所述源极和所述漏极分别形成在所述有源层的两侧， 且所述源极和所述漏极与所述有源层接触。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为一种现有的阵列基板的截面结构图；
图 2为本发明实施例提供的一种薄膜晶体管的结构示意图；
图 3为本发明实施例提供的另一种薄膜晶体管的结构示意图；
图 4为本发明实施例提供的再一种薄膜晶体管的结构示意图；
图 5为本发明实施例提供的又一种薄膜晶体管的结构示意图；
图 6为本发明实施例提供的一种阵列基板的结构示意图；
图 7为本发明实施例提供的另一种阵列基板的结构示意图；
图 8 为本发明实施例提供的一种包括公共电极的阵列基板的结构示意 图；
图 9为本发明实施例提供的另一种包括公共电极的阵列基板的结构示意 图； 以及
图 10-图 14为本发明实施例提供的两种薄膜晶体管的制备过程示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例提供了一种薄膜晶体管， 如图 2-图 5所示， 该薄膜晶体管 包括： 设置在衬底基板 10上的栅极 20、栅绝缘层 30、有源层 40、 源极 501、 以及漏极 502; 其中， 沿垂直于所述衬底基板的方向， 所述源极 501和所述 漏极 502分别设置于所述有源层 40的两侧，且所述源极和所述漏极与所述有 源层 40接触。 而且， 所述栅极 20与所述有源层 40之间具有所述栅绝缘层 30。
需要说明的是，所述源极 501和所述漏极 502分别设置在所述有源层 40 的两侧， 且与所述有源层接触是指包括两种形式， 第一种是， 在制备所述薄 膜晶体管时， 先形成所述源极 501 , 之后形成所述有源层 40, 然后形成所述 漏极 502, 其中所述源极 501与所述有源层 40的下表面接触， 所述漏极 502 与所述有源层 40的上表面接触； 第二种是， 在制备所述薄膜晶体管时， 先形 成所述漏极 502, 之后形成所述有源层 40, 然后形成所述源极 501 , 其中所 述漏极 502与所述有源层 40的下表面接触， 所述源极 501与所述有源层 40 的上表面接触。 当然在这之间还可以形成其他图案层， 在此不做限定。
这里不对所述源极 501和漏极 502与所述有源层 40的接触方式进行限 定， 可以是直接接触， 也可以是通过过孔接触。
本发明实施例提供了一种薄膜晶体管， 该薄膜晶体管包括栅极、 栅绝缘 层、 有源层、 源极、 以及漏极， 其中， 沿垂直于所述衬底基板的方向上， 所 述源极和所述漏极分别设置在所述有源层的两侧， 且与所述有源层接触； 由 于所述薄膜晶体管的沟道长度由所述有源层的厚度决定， 因此可以通过合理 设置位于所述源极和漏极之间的有源层厚度， 以减小沟道长度， 从而增加薄 膜晶体管的开态电流， 进而提高薄膜晶体管的特性。
需要说明的是本发明所有实施例中所描述的由有源层的厚度决定的沟道 长度相当于背景技术中的薄膜晶体管的源漏极之间的沟道长度。
基于上述描述， 本发明实施例提供的薄膜晶体管的其中一种示例结构可 以为： 所述源极 501设置于所述衬底基板 10与所述有源层 40之间， 所述漏 极 502设置于所述有源层 40远离所述衬底基板 10的一侧。
在此基础上， 进一步地， 如图 2所示， 所述栅绝缘层 30可以设置于所述 漏极 502与所述有源层 40之间 ,所述漏极 502通过设置于所述栅绝缘层中的 第一过孔 301与所述有源层 40接触；所述栅极 20与所述漏极 502同层设置， 所述栅极 20与所述有源层 40之间设置有所述栅绝缘层 30, 所述栅极 20与 所述漏极 502不连接。
此处需要说明的是，所述栅极 20与所述漏极 502同层设置，是指同一层 金属薄膜经一次构图工艺处理后形成的所述栅极 20与所述漏极 502。这样可 以减少构图工艺的次数， 降低成本。
其中，所述有源层 40可以为金属氧化物半导体有源层，或者为非晶硅半 导体层， 当为非晶硅半导体层时，所述有源层 40还包括位于所述非晶硅半导 体层两侧的欧姆接触层。
此夕卜，本发明实施例提供的薄膜晶体管的其中又一种示例结构还可以为： 所述漏极 502设置于所述衬底基板 10与所述有源层 40之间， 所述源极 501 设置于所述有源层 40远离所述衬底基板 10的一侧。
在此基础上， 进一步地， 如图 3所示， 所述栅绝缘层 30可以设置于所述 源极 501与所述有源层 40之间，所述源极 501通过设置于所述栅绝缘层中的 第一过孔 301与所述有源层 40接触；所述栅极 20与所述有源层 40之间设置 有所述栅绝缘层 30, 所述栅极 20与所述源极 501同层设置， 且所述栅极 20 与所述源极 501不连接。
此处需要说明的是，所述栅极 20与所述源极 501同层设置，是指同一层 金属薄膜经一次构图工艺处理后形成的所述栅极 20与所述源极 501。这样可 以减少构图工艺的次数， 降低成本。
其中，所述有源层 40可以为金属氧化物半导体有源层，或者为非晶硅半 导体层， 当为非晶硅半导体层时，所述有源层 40还包括位于所述非晶硅半导 体层两侧的欧姆接触层。
下面将提供两个具体实施例， 以详细描述上述两种薄膜晶体管的结构。 实施例一
本实施例提供一种薄膜晶体管， 如图 4所示， 该薄膜晶体管包括： 设置 在衬底基板 10上的源极 501、设置在所述源极上方的有源层 40、设置在所述 有源层上方的漏极 502、 以及设置在所述有源层和所述漏极之间的栅绝缘层 30和设置在所述栅绝缘层上方的栅极 20。
其中， 所述有源层 40包括位于中间的非晶硅半导体层 401、位于所述非 晶硅半导体层上方的第一欧姆接触层 402以及位于所述非晶硅半导体层下方 的第二欧姆接触层 403。
所述源极 501和所述有源层 40的第二欧姆接触层 403接触， 所述漏极 502与所述栅极 20同层但不连接，且所述漏极 502通过设置在所述栅绝缘层 30中的第一过孔 301与所述有源层 40的第一欧姆接触层 402接触。
需要说明的是， 在本发明实施例中并不限于所述有源层为包括非晶硅半 导体层、 以及第一、 第二欧姆接触层， 所述有源层也可以为金属氧化物半导 体有源层。
本实施例提供了一种薄膜晶体管， 包括依次设置在衬底基板上的源极、 有源层、 栅绝缘层、 以及同层设置且不连接的的漏极和栅极； 其中， 所述有 源层包括位于中间的非晶硅半导体层、 以及分别位于所述非晶硅半导体层上 下方的第一欧姆接触层和第二欧姆接触层， 所述源极与所述第二欧姆接触层 接触， 所述漏极通过设置在所述栅绝缘层中的第一过孔与所述第一欧姆层接 触； 由于所述薄膜晶体管的沟道长度由所述有源层的厚度决定， 因此通过合 理设置所述有源层的厚度， 便可以减小沟道长度， 从而增加薄膜晶体管的开 态电流， 进而提高薄膜晶体管的特性。
实施例二
本实施例提供了一种薄膜晶体管， 如图 5所示， 该薄膜晶体管包括： 设 置在衬底基板 10上的漏极 502、设置在所述漏极上方的有源层 40、设置在所 述有源层上方的源极 501、 以及设置在所述有源层和所述源极之间的栅绝缘 层 30和设置在所述栅绝缘层上方的栅极 20。
其中， 所述有源层 40包括位于中间的非晶硅半导体层 401、位于所述非 晶硅半导体层上方的第一欧姆接触层 402以及位于所述非晶硅半导体层下方 的第二欧姆接触层 403。
所述漏极 502和所述有源层 40的第二欧姆接触层 403接触， 所述源极
501与所述栅极 20同层但不连接，且所述源极 501通过设置在所述栅绝缘层 30中的第一过孔 301与所述有源层 40的第一欧姆接触层 402接触。
需要说明的是， 在本发明实施例中并不限于所述有源层为包括非晶硅半 导体层、 以及第一、 第二欧姆接触层， 所述有源层也可以为金属氧化物半导 体有源层。 本实施例提供了一种薄膜晶体管， 包括依次设置在基板上的漏极、 有源 层、 栅绝缘层、 以及同层设置且不连接的源极和栅极； 其中， 所述有源层包 括位于中间的非晶硅半导体层、 以及分别位于所述非晶硅半导体层上下方的 第一欧姆接触层和第二欧姆接触层， 所述漏极与所述第二欧姆接触层接触， 所述源极通过设置在所述栅绝缘层上的第一过孔与所述第一欧姆层接触； 由 于所述薄膜晶体管的沟道长度由所述有源层的厚度决定， 因此通过合理设置 所述有源层的厚度，便可以减小沟道长度，从而增加薄膜晶体管的开态电流， 进而提高薄膜晶体管的特性。
需要说明的是， 本发明实施例提供的薄膜晶体管并不限于上述两个实施 例描述的薄膜晶体管的结构， 也可以为其他结构， 在此不再赘述。
本发明的实施例还提供了一种阵列基板， 如图 6和图 7所示， 该阵列基 板包括上述的薄膜晶体管、 以及像素电极 70, 其中所述像素电极 70与所述 薄膜晶体管的漏极 502连接。 示例性地， 该阵列基板还可以包括保护层 60。
可选的， 参考图 6所示， 当上述薄膜晶体管的所述源极 501设置于所述 衬底基板 10与所述有源层 40之间、 所述栅绝缘层 30设置于所述漏极 502 与所述有源层 40之间， 所述栅绝缘层 30中设置有第一过孔 301 , 所述漏极 502通过所述第一过孔 301与所述有源层 40接触， 且所述栅极 20与所述漏 极 502同层设置的情况下，所述像素电极 70通过设置在栅极和漏极上方的所 述保护层 60中的第二过孔 601与所述漏极 502连接。
可选的， 参考图 7所示， 当上述薄膜晶体管的所述漏极 502设置于所述 基板 10与所述有源层 40之间、所述栅绝缘层 30设置于所述源极 501与所述 有源层 40之间， 所述栅绝缘层 30中设置有第一过孔 301 , 所述源极 501通 过所述第一过孔 301与所述有源层 30接触， 且所述栅极 20与所述源极 501 同层设置的情况下， 所述像素电极 70通过设置在栅极与源极上方的保护层 60中的第二过孔 601和设置在所述栅绝缘层 30上的第三过孔 302与所述漏 极 502连接。
这里， 所述第二过孔 601和所述第三过孔 302可以通过一次刻蚀工艺形 成。
下面将提供两个具体实施例， 以详细描述上述两种阵列基板的结构。 实施例三 本实施例提供一种阵列基板， 参考图 6所示， 该阵列基板从下到上依次 包括：衬底基板 10、设置在衬底基板上的源极 501和与源极连接的数据线（图 中未标识出） 、 设置在所述源极上方的有源层 40、 设置在所述有源层 40上 方的栅绝缘层 30、以及设置在所述栅绝缘层 30上方同层但不连接的漏极 502 和栅极 20、 与栅极 20连接的栅线（图中未标识出）， 其中， 栅绝缘层 30中 设置有第一过孔 301 , 所述漏极 502通过第一过孔 301与有源层 40接触， 此 夕卜， 还包括： 保护层 60、 以及设置在所述保护层上的像素电极 70, 且所述像 素电极 70通过设置在所述保护层 60中的第二过孔 601与所述漏极 502连接。
其中， 源极 501、 设置在源极上方的有源层 40、 设置在所述有源层上方 的栅绝缘层 30、 以及设置在所述栅绝缘层上方同层但不连接的漏极 502和栅 极 20构成薄膜晶体管。
实施例四
本实施例提供一种阵列基板， 参考图 7所示， 该阵列基板从下到上依次 包括： 衬底基板 10、 设置在衬底基板上的漏极 502、 设置在所述漏极上方的 有源层 40、 设置在所述有源层 40上方的栅绝缘层 30、 以及设置在所述栅绝 缘层 30上方同层的源极 501、与所述源极 501连接的数据线（图中未标识出） 和栅极 20、 与所述栅极 20连接的栅线（图中未标识出）， 其中所述源极 501 与所述栅极 20不连接， 栅绝缘层 30中设置有第一过孔 301 , 所述源极 501 通过第一过孔 301与有源层 40接触， 此外， 还包括： 保护层 60、 以及设置 在所述保护层上的像素电极 70, 且所述像素电极 70通过设置在所述保护层 60中的第二过孔 601和所述栅绝缘层 30中的第三过孔 302与所述漏极 502 连接。
其中， 漏极 502、 设置在所述漏极上方的有源层 40、 设置在所述有源层 上方的栅绝缘层 30、 以及设置在所述栅绝缘层上方同层但不连接的源极 501 和栅极 20构成薄膜晶体管。
本发明实施例提供的阵列基板， 由于所述薄膜晶体管的沟道长度由所述 有源层的厚度决定， 因此通过合理设置所述有源层的厚度， 便可以减小沟道 长度， 从而增加薄膜晶体管的开态电流， 进而提高薄膜晶体管的特性。
此外， 本发明实施例提供的阵列基板可以用作 TN式、 高级超维场转换 式 ( Advanced-Super Dimension Switch ) 、 面内转换式 ( In-Plane Switching, IPS )液晶显示装置的阵列基板且可以用作有机电致发光显示装置（Organic Electroluminesence Display , OLED )等的阵列基板。
示例性地， 高级超维场转换液晶显示装置的核心可以描述为： 通过同一 平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的电 场形成多维电场， 使液晶盒内狭缝电极间、 电极正上方所有取向液晶分子都 能够产生旋转， 从而提高了液晶工作效率并增大了透光效率。 高级超维场转 换技术可以提高薄膜晶体管液晶显示器的画面品质， 具有高分辨率、 高透过 率、 低功耗、 宽视角、 高开口率、 低色差、 无挤压水波纹（push Mura )等优 点。 有机电致发光显示装置具有自发光的特性， 且其具有可视角度大， 显著 节省电能等优点。
因此， 对于高级超维场转换式液晶显示装置中适用的阵列基板， 如图 8 和图 9所示， 所述阵列基板还包括： 钝化层 90和公共电极 80。
本发明实施例提供了一种阵列基板,该阵列基板包括上述的薄膜晶体管、 以及像素电极和公共电极； 一方面， 由于上述的薄膜晶体管的沟道长度由所 述有源层的厚度决定， 因此通过合理设置所述有源层的厚度， 便可以减小沟 道长度， 从而增加薄膜晶体管的开态电流， 进而提高薄膜晶体管的特性； 另 一方面， 由于像素电极和公共电极均位于阵列基板上， 当该阵列基板应用于 显示器时， 具有高分辨率、 高透过率、 低功耗、 宽视角、 高开口率、 低色差、 无挤压水波纹（ push Mura )等优点。
本发明的实施例还提供了一种薄膜晶体管的制备方法， 该方法包括： 在 衬底基板 10上形成栅极 20、 栅绝缘层 30、 有源层 40、 源极 501、 以及漏极 502; 其中， 沿垂直于所述衬底基板的方向， 所述源极 501和漏极 502分别形 成在所述有源层 40的两侧， 且所述源极 501和所述漏极 502与所述有源层 40接触。 而且所述栅极与所述源极 /漏极在同一构图工艺中形成， 所述栅极 与所述漏极不连接， 且所述栅极与所述有源层之间设置有所述栅绝缘层。
本发明实施例提供了一种薄膜晶体管的制备方法， 该方法包括在衬底基 板上形成栅极、栅绝缘层、有源层、 以及在沿垂直于所述衬底基板的方向上， 在所述有源层的两侧分别形成与所述有源层接触的源极和漏极； 由于所述薄 膜晶体管的沟道长度由所述有源层的厚度决定， 因此可以通过合理设置位于 所述源极和漏极之间的有源层厚度， 以减小沟道长度， 从而增加薄膜晶体管 的开态电流， 进而提高薄膜晶体管的特性。
可选的，所述源极 501和漏极 502分别形成在所述有源层 40的两侧包括： 所述源极 501形成在所述衬底基板 10与所述有源层 40之间， 所述漏极 502 形成在所述有源层 40远离所述衬底基板 10的一侧。
进一步地， 所述漏极 502形成在所述有源层 40远离所述衬底基板 10的 一侧包括： 所述栅绝缘层 30形成在所述漏极 502与所述有源层 40之间， 所 述漏极 502通过形成在所述栅绝缘层 30中的第一过孔 301与所述有源层 40 接触；所述栅极 20与所述漏极 502同层形成，且所述栅极 20与所述漏极 502 不连接。
下面将提供一个具体实施例，以详细描述上述的薄膜晶体管的制备方法。 实施例五
本实施例提供一种薄膜晶体管的制备方法， 包括如下步骤：
S101、 在衬底基板 10上制作金属薄膜， 通过一次构图工艺处理， 形成 如图 10所示的源极 501。
示例性地， 可以使用磁控溅射方法， 在衬底基板 10上制备一层厚度在
1000A至 7000A的金属薄膜。 金属材料通常可以采用钼、 铝、 铝镍合金、 钼 钨合金、铬、 或铜等金属， 也可以使用上述几种材料薄膜的组合结构。 然后， 通过曝光、 显影、 刻蚀、 剥离等构图工艺处理， 在基板的一定区域上形成所 述源极 501。
S102、 在完成步骤 S101 的基板上， 制作有源层薄膜， 通过一次构图工 艺处理， 形成有源层 40。
示例性地， 可以利用化学气相沉积法在形成有源极 501的基板上沉积金 属氧化物半导体薄膜。 然后， 通过曝光、 显影、 刻蚀、 剥离等构图工艺处理， 在基板的一定区域上形成如图 11所示的所述有源层 40。
也可以在形成有源极 501的基板上沉积厚度为 1000A至 6000A的非晶硅 薄膜和 n+非晶硅薄膜， 然后， 通过曝光、显影、刻蚀、 剥离等构图工艺处理， 在基板的一定区域上形成如图 12 所示的， 包括位于中间的非晶硅半导体层
401 以及分别位于所述非晶硅半导体层上下方的第一欧姆接触层 402和第二 欧姆接触层 403的所述有源层 40。
S103、 在完成步骤 S102 的基板上制作绝缘薄膜， 通过一次构图工艺处 理， 形成包括第一过孔 301的栅绝缘层 30。
其中， 所述第一过孔 301露出所述有源层 40。
示例性地，可以利用化学气相沉积法在基板上连续沉积厚度为 1000A至 6000A的绝缘薄膜， 绝缘薄膜的材料通常是氮化硅， 也可以使用氧化硅和氮 氧化硅等。 然后， 通过曝光、 显影、 刻蚀形成如图 13或图 14所示的具有第 一过孔 301的栅绝缘层 30。
S104、 在完成步骤 S103 的基板上制作金属薄膜， 通过一次构图工艺处 理， 形成参考如图 2或图 4所示的漏极 502、 以及栅极 20, 且所述漏极 502 和所述栅极 20不连接；其中所述漏极 502通过所述第一过孔 301与所述有源 层 40接触。
示例性地，可以使用磁控溅射方法，在玻璃基板上制备一层厚度在 1000A 至 7000A的金属薄膜。金属材料通常可以采用钼、铝、铝镍合金、钼钨合金、 铬、 或铜等金属， 也可以使用上述几种材料薄膜的组合结构。 然后， 通过曝 光、 显影、 刻蚀、 剥离等构图工艺处理， 在基板的一定区域上形成通过所述 第一过孔 301与所述有源层 40接触的漏极 502、 同时形成栅极 20。
本发明实施例提供了一种薄膜晶体管的制备方法， 该方法包括在基板上 依次形成源极、有源层、栅绝缘层、 以及形成在同层且不连接的漏极和栅极； 其中， 所述源极与所述有源层的下表面接触， 所述漏极通过形成在所述栅绝 缘层中的第一过孔与所述有源层的上表面接触； 由于所述薄膜晶体管的沟道 长度由所述有源层的厚度决定， 因此通过合理设置所述有源层的厚度， 便可 以减小沟道长度， 从而增加薄膜晶体管的开态电流， 进而提高薄膜晶体管的 特性。
对于包括通过上述方法制备的多晶硅薄膜晶体管的阵列基板， 其制作方 法可以为， 在完成上述步骤 S101-S104的基础上， 还包括： 在基板上形成参 考图 6所示的保护层 60、 以及像素电极 70, 其中所述像素电极 70通过形成 在所述保护层 60中的第二过孔 601与所述漏极 502电连接。
进一步地，所述方法还可以包括： 形成参考图 8所示的钝化层 90以及公 共电极 80。
需要说明的是， 本发明实施例提供的薄膜晶体管的制备方法并不限于上 述实施例。 此外， 本发明实施例提供的薄膜晶体管的制备方法还可以为： 所述漏极
502形成在所述衬底基板 10与所述有源层 40之间， 所述源极 201形成在所 述有源层 40远离所述衬底基板的一侧。
进一步地，所述源极 501形成在所述有源层 40远离所述衬底基板的一侧 包括： 所述栅绝缘层 30形成在所述源极 501与所述有源层 40之间， 所述源 极 501通过形成在所述栅绝缘层 30上的第一过孔 301与所述有源层 40接触； 所述栅极 20与所述源极 501同层形成。
下面以一个具体实施例来说明， 参考图 3或图 5所示的薄膜晶体管， 该 方法包括如下步骤：
S201、 在衬底基板 10上制作金属薄膜， 通过一次构图工艺处理， 形成 漏极 502。
5202、 在完成步骤 S201 的基板上制作有源层薄膜， 通过一次构图工艺 处理， 形成有源层 40。
其中，参考图 3所示，所述有源层 40通过在基板上沉积金属氧化物半导 体薄膜形成； 或者， 参考图 5所示， 所述有源层 40包括位于中间的非晶硅半 导体层 401 以及分别位于所述非晶硅半导体层上下方的第一欧姆接触层 402 和第二欧姆接触层 403 , 即通过在基板上沉积非晶硅薄膜和 n+非晶硅薄膜形 成。
5203、 在完成步骤 S202 的基板上制作绝缘薄膜， 通过一次构图工艺处 理， 形成参考图 3或图 5所示的包括第一过孔 301的栅绝缘层 30, 其中所述 第一过孔 301露出所述有源层 40。
5204、 在完成步骤 S203 的基板上制作金属薄膜， 通过一次构图工艺处 理， 形成参考如图 3或 5所示的源极 501、 以及栅极 20; 其中所述源极 501 通过所述栅绝缘层上的第一过孔 301与所述有源层 40接触。
本发明实施例提供了一种薄膜晶体管的制备方法， 该方法包括在衬底基 板上依次形成漏极、 有源层、 栅绝缘层、 以及形成在同层的源极和栅极； 其 中， 所述漏极与所述有源层的下表面接触， 所述源极通过形成在所述栅绝缘 层中的第一过孔与所述有源层的上表面接触； 由于所述薄膜晶体管的沟道长 度由所述有源层的厚度决定， 因此通过合理设置所述有源层的厚度， 便可以 减小沟道长度， 从而增加薄膜晶体管的开态电流， 进而提高薄膜晶体管的特 性。
对于包括通过上述方法制备的多晶硅薄膜晶体管的阵列基板， 其制作方 法可以为， 在完成上述步骤 S201-S204的基础上， 还包括： 在基板上形成参 考图 7所示的保护层 60、 以及像素电极 70, 其中所述像素电极 70通过形成 在所述保护层 60中的第二过孔 601和设置在栅绝缘层 30中的第三过孔 302 与所述漏极 502电连接。
进一步地，所述方法还包括：形成参考图 9所示的钝化层 90以及公共电 极 80。 本发明的实施例提供了一种薄膜晶体管及其制备方法、 阵列基板，该薄 膜晶体管包括栅极、 栅绝缘层、 有源层、 源极、 以及漏极， 其中， 沿垂直所 述衬底基板的方向上， 所述源极和所述漏极分别设置在所述有源层的两侧， 且与所述有源层接触；由于所述薄膜晶体管的沟道长度由所述有源层的厚度 决定， 因此可以通过合理设置位于所述源极和漏极之间的有源层厚度， 以减 小沟道长度,从而增加薄膜晶体管的开态电流，进而提高薄膜晶体管的特性。
以上所述， 仅为本发明的具体实施方式， 但本发明实施例的保护范围并 不局限于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明 的保护范围应以所述权利要求的保护范围为准。

Claims

权利要求书
1、一种薄膜晶体管， 包括设置在衬底基板上的栅极、栅绝缘层、有源层、 源极、 以及漏极， 其中沿垂直于所述衬底基板的方向， 所述源极和所述漏极 分别设置在所述有源层两侧， 且所述源极和所述漏极与所述有源层接触。
2、 根据权利要求 1所述的薄膜晶体管， 其中所述栅极与所述源极 /漏极 同层设置， 所述栅极与所述漏极不连接， 且所述栅极与所述有源层之间设置 有所述栅绝缘层。
3、根据权利要求 2所述的薄膜晶体管，其中所述源极设置于所述衬底基 板与所述有源层之间，所述漏极设置于所述有源层远离所述衬底基板的一侧。
4、根据权利要求 3所述的薄膜晶体管，其中所述栅绝缘层设置于所述漏 极与所述有源层之间， 所述漏极通过设置于所述栅绝缘层中的第一过孔与所 述有源层接触。
5、根据权利要求 2所述的薄膜晶体管，其中所述漏极设置于所述衬底基 板与所述有源层之间，所述源极设置于所述有源层远离所述衬底基板的一侧。
6、根据权利要求 5所述的薄膜晶体管，其中所述栅绝缘层设置于所述源 极与所述有源层之间， 所述源极通过设置于所述栅绝缘层中的所述第一过孔 与所述有源层接触。
7、根据权利要求 1至 6任一项所述的薄膜晶体管，其中所述有源层包括 欧姆接触层 /非晶硅半导体层 /欧姆接触层的三层结构。
8、根据权利要求 1至 6任一项所述的薄膜晶体管，其中所述有源层为金 属氧化物半导体有源层。
9、 一种阵列基板， 包括权利要求 1所述的薄膜晶体管。
10、 根据权利要求 9所述的阵列基板， 还包括保护层与像素电极； 所述薄膜晶体管的源极设置于衬底基板与有源层之间， 所述栅绝缘层设 置于所述漏极与所述有源层之间， 所述漏极通过所述栅绝缘层中的第一过孔 与所述有源层接触， 所述栅极与所述漏极同层设置且二者彼此电绝缘， 所述 栅极与所述有源层之间设置有所述栅绝缘层， 所述栅极和所述漏极上设置所 述保护层， 所述像素电极通过设置在所述保护层中的第二过孔与所述漏极连 接； 或者 所述薄膜晶体管的漏极设置于所述村底基板与所述有源层之间、 所述栅 绝缘层设置于所述源极与所述有源层之间， 所述源极通过所述栅绝缘层中的 第一过孔与所述有源层接触， 所述栅极与所述源极同层设置且二者彼此电绝 缘， 所述栅极与所述有源层之间设置有所述栅绝缘层， 所述栅极与所述源极 上设置所述保护层， 所述像素电极通过设置在所述保护层中的所述第二过孔 和所述栅绝缘层中的第三过孔与所述漏极连接。
11、 根据权利要求 9所述的阵列基板， 还包括保护层与像素电极； 所述薄膜晶体管的源极设置于村底基板与有源层之间， 所述栅绝缘层设 置于所述漏极与所述有源层之间， 所述漏极通过所述栅绝缘层中的第一过孔 与所述有源层接触， 所述栅极与所述漏极同层设置且二者彼此电绝缘， 所述 栅极与所述有源层之间设置有所述栅绝缘层， 所述栅极和所述漏极上设置所 述保护层， 所述像素电极通过设置在所述保护层中的第二过孔和所述栅绝缘 层中的第三过孔与所述源极连接； 或者
所述薄膜晶体管的漏极设置于所述村底基板与所述有源层之间、 所述栅 绝缘层设置于所述源极与所述有源层之间， 所述源极通过所述栅绝缘层中的 第一过孔与所述有源层接触， 所述栅极与所述源极同层设置且二者彼此电绝 缘， 所述栅极与所述有源层之间设置有所述栅绝缘层， 所述栅极与所述源极 上设置所述保护层， 所述像素电极通过设置在所述保护层中的所述第二过孔 与所述源极连接。
12、 根据权利要求 10或 11所述的阵列基板， 其中还包括：
钝化层， 覆盖所述像素电极； 以及
公共电极， 形成在所述钝化层上。
13、 根据权利要求 10或 11所述的阵列基板， 其中所述有源层包括欧姆 接触层 /非晶硅半导体层 /欧姆接触层的三层结构。
14、 根据权利要求 10或 11所述的阵列基板， 其中所述有源层为金属氧 化物半导体有源层。
15、 一种薄膜晶体管的制备方法， 包括： 在村底基板上形成栅极、 栅绝 缘层、 有源层、 源极、 以及漏极，
其中沿垂直于所述村底基板的方向， 所述源极和所述漏极分别形成在所 述有源层的两侧， 且所述源极和所述漏极与所述有源层接触。
16、 根据权利要求 15所述的制备方法， 其中所述栅极与所述源极 /漏极 在同一构图工艺中形成， 所述栅极与所述漏极不连接， 且所述栅极与所述有 源层之间设置有所述栅绝缘层。
17、 根据权利要求 15或 16所述的制备方法， 其中所述源极和所述漏极 分别形成在所述有源层的两侧包括：
所述源极形成在所述衬底基板与所述有源层之间， 所述漏极形成在所述 有源层远离所述衬底基板的一侧； 或者
所述漏极形成在所述衬底基板与所述有源层之间， 所述源极形成在所述 有源层远离所述衬底基板的一侧。
18、根据权利要求 17所述的制备方法，其中所述漏极形成在所述有源层 远离所述衬底基板的一侧包括： 所述栅绝缘层形成在所述漏极与所述有源层 之间， 所述漏极通过形成在所述栅绝缘层中的过孔与所述有源层接触。
19、根据权利要求 17所述的制备方法， 其特征在于， 所述源极形成在所 述有源层远离所述衬底基板的一侧包括： 所述栅绝缘层形成在所述源极与所 述有源层之间， 所述源极通过形成在所述栅绝缘层中的过孔与所述有源层接 触。
PCT/CN2013/088543 2013-05-13 2013-12-04 薄膜晶体管及其制备方法、阵列基板 Ceased WO2014183422A1 (zh)

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