CN103700667B - 一种像素阵列结构及其制作方法、阵列基板和显示装置 - Google Patents
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Abstract
本发明公开了一种像素阵列结构及其制作方法、阵列基板和显示装置,所述像素阵列结构的制作方法包括:在有源层上方形成掺杂有源层,且上述掺杂有源层不完全覆盖所述有源层;在所述掺杂有源层和有源层上方形成源漏金属层,且所述源漏金属层部分覆盖所述掺杂有源层;对所述源漏金属层进行刻蚀,形成源极和漏极;沿着所述源漏金属层的边缘对所述掺杂有源层和所述有源层进行刻蚀,形成优化沟道。该制作方法通过改变现有技术的沟道制作工艺,在有源层上继续形成不完全覆盖的掺杂有源层,并对掺杂有源层和有源层同时进行刻蚀,由于掺杂有源层可以将其视为导体,可以等同于将漏极边长,从而形成沟道长度变短的效果,进一步达到提高开态电流的目的。
Description
技术领域
本发明涉及显示技术领域,特别涉及一种像素阵列结构及其制作方法、阵列基板和显示装置。
背景技术
目前TFT-LCD(Thin Film Transistor Liquid Crystal Display,薄膜晶体管液晶显示器)一个重要的发展方向就是低能耗高质量,这也是目前显示领域研究的重点。实现上述目的就需要提高TFT的充电能力,如果能够在一定时间内实现TFT快速充电,解决这个问题的关键就在于提高开态电流。
由于TFT沟道的开态电流Ion=W/L,其中W为沟道的宽度,L为沟道的长度,所以开态电流的大小取决于沟道的宽长比,为了提高开态电流,可以通过增加沟道的宽度或者降低沟道长度来实现。对于目前常用的显示产品,特别是近年来使用非常广泛的小尺寸显示产品而言,同时受设备精度的限制,沟道的长度不能做到很小,只能增加沟道的宽度,但是小尺寸高PPI(Pixels Per Inch,每英寸上的像素数目)的产品由于面板布局受到限制,也不可能无限的增加沟道宽度。现有技术对于TFT-LCD中像素阵列结构的示意图如图1所示,在玻璃基板1上形成栅电极层,经过刻蚀形成栅电极2,在栅电极2上方逐层形成栅绝缘层3(Gate Insulator,简称GI层),继续在栅绝缘层3上方形成有源层4并进行刻蚀,只保留位于栅电极2上方的部分,之后在部分有源层4和栅绝缘层3上方继续形成第一像素电极7,在栅电极2上方的有源层4和第一像素电极7上形成源漏极金属层,并通过刻蚀形成源极5和漏极6。另外,还在上述图形基础上形成钝化层8以及第二像素电极9。
因此,现有技术对于提高TFT沟道的开态电流仍然存在瓶颈,无法提高TFT的充电能力。
发明内容
(一)要解决的技术问题
本发明要解决的技术问题是如何提高TFT沟道的开态电流,以提高TFT的充电能力。
(二)技术方案
为解决上述技术问题,本发明提供了一种像素阵列结构的制作方法,包括:
S1、在有源层上方形成掺杂有源层,且上述掺杂有源层不完全覆盖所述有源层;
S2、在所述掺杂有源层和有源层上方形成源漏金属层,且所述源漏金属层部分覆盖所述掺杂有源层;
S3、对所述源漏金属层进行刻蚀,形成源极和漏极;
S4、沿着源极和漏极的边缘对所述掺杂有源层和所述有源层进行刻蚀,形成优化沟道。
进一步地,所述掺杂有源层的厚度是所述厚度的4~7倍。
进一步地,所述有源层上不完全覆盖的掺杂有源层位于所述源极或所述漏极所在的一侧。
进一步地,步骤S1之前还包括:
S01、在玻璃基板上制作栅电极和栅绝缘层;
S02、在所述栅绝缘层上形成所述有源层,并对所述有源层进行刻蚀,只保留所述栅电极所在位置对应的有源层。
进一步地,所述源极一侧在形成上述有源层之后,形成源漏金属层之前还包括:形成第一像素电极层,且所述第一像素电极层不完全覆盖所述有源层,同时覆盖所述有源层未覆盖的栅绝缘层。
进一步地,所述掺杂有源层的相对宽度为1~3微米。
进一步地,步骤S4中刻蚀所述掺杂有源层和刻蚀所述有源层进行刻蚀同时进行。
为解决上述技术问题,本发明还提供了一种像素阵列结构,所述像素阵列结构是由以上所述的像素阵列结构的制作方法得到的。
为解决上述技术问题,本发明还提供了一种阵列基板,包括玻璃基板以及在所述玻璃基板上按照以上所述的像素阵列结构的制作方法形成像素阵列结构,在玻璃基板上形成同层形成栅电极和存储电容,栅电极上方依次形成栅绝缘层、有源层和掺杂有源层,掺杂有源层不完全覆盖有源层,掺杂有源层上方沉积源漏金属层并形成源极和漏极,最后沿着源极和漏极的边缘对掺杂有源层和有源层进行不完全刻蚀,形成优化沟道。
为解决上述技术问题,本发明还提供了一种显示装置,包括阵列基板和彩膜基板,其中所述阵列基板为以上所述的阵列基板。
(三)有益效果
本发明实施例提供了一种像素阵列结构及其制作方法、阵列基板和显示装置,所述像素阵列结构的制作方法包括:在有源层上方形成掺杂有源层,且上述掺杂有源层不完全覆盖所述有源层;在所述掺杂有源层和有源层上方形成源漏金属层,且所述源漏金属层部分覆盖所述掺杂有源层;对所述源漏金属层进行刻蚀,形成源极和漏极;沿着所述源漏金属层的边缘对所述掺杂有源层和所述有源层进行刻蚀,形成优化沟道。该制作方法通过改变现有技术的沟道制作工艺,在有源层上继续形成不完全覆盖的掺杂有源层,并对掺杂有源层和有源层同时进行刻蚀,由于掺杂有源层可以将其视为导体,可以等同于将漏极边长,从而形成沟道长度变短的效果,进一步达到提高开态电流的目的。
附图说明
图1为现有技术的像素阵列结构截面示意图;
图2为本发明实施例一提供的一种阵列结构的制作方法的步骤流程图;
图3是发明实施例一形成栅电极的示意图;
图4是发明实施例一形成有源层和掺杂有源层的示意图;
图5为发明实施例一对掺杂有源层进行刻蚀之后的示意图;
图6为发明实施例一形成第一像素电极层的示意图;
图7为发明实施例一栅绝缘层刻蚀形成过孔的示意图;
图8为发明实施例一刻蚀形成源极和漏极的示意图;
图9为发明实施例一形成最优化沟道的示意图;
图10为发明实施例一中得到的阵列基板的示意图。
具体实施方式
下面结合附图和实施例,对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明,但不用来限制本发明的范围。
实施例一
本发明实施例一提供了一种阵列结构的制作方法,步骤流程如图2所示,具体包括以下步骤:
步骤S1、在有源层上方形成掺杂有源层,且上述掺杂有源层不完全覆盖有源层。
步骤S2、在掺杂有源层和有源层上方形成源漏金属层,且源漏金属层部分覆盖掺杂有源层。
步骤S3、对源漏金属层进行刻蚀,形成源极和漏极。
步骤S4、沿着源极和漏极的边缘对掺杂有源层和有源层进行刻蚀,形成优化沟道。
经过上述步骤,在传统TFT制备过程沉积有源层之后增加掺杂有源层,不完全覆盖已有的有源层,沉积有源金属层之后刻蚀形成源极和漏极,之后沿着源极和漏极的边缘对裸露的有源层和掺杂有源层进行刻蚀,剩余的掺杂有源层作为导体,能够等效为漏极的长度,形成长度变短的沟道,进一步达到提高开态电流的目的。
优选的,本实施例在步骤S1之前还进一步包括:
步骤S01、在玻璃基板上制作栅电极和栅绝缘层。
步骤S02、在栅绝缘层上形成有源层,并对有源层进行刻蚀,只保留栅电极所在位置对应的有源层。
其中步骤S01中制作栅电极的方法为在玻璃基板1上沉积栅电极金属层,在显示区域经过刻蚀形成栅电极2,在显示区域之外的非显示区上方的栅电极金属层保留形成存储电容14,示意图如图3所示。之后在栅电极2以及裸露的玻璃基板1上沉积栅绝缘层3,进一步在栅绝缘层3上沉积有源层4和掺杂有源层13,并在涂胶刻胶PR之后对A区之外的有源层4和掺杂有源层13进行刻蚀,得到的结果如图4所示,其中PR为光刻胶,PR是Photoresist的简称,一种由感光树脂、增感剂(见光谱增感染料)和溶剂三种主要成分组成的对光敏感的混合液体。
进一步地再对光刻胶PR进行刻蚀,只保留B区部分的光刻胶PR,并对掺杂有源层13进行刻蚀,需要说明的是,在进行掺杂有源层13刻蚀的过程中采用HT技术(HyperTransport,一种为主板上的集成电路互连而设计的端到端总线技术)形成如图5所示只保留PR下方的掺杂有源层13。优选地,本实施例中的掺杂有源层13的厚度是有源层4厚度的4~7倍,优选为5倍。需要说明的是,本实施例中的掺杂有源层13覆盖在有源层4上,并是不完全覆盖,图5中掺杂有源层13位于漏极所在的一侧。其实在实际操作中剩余的掺杂有源层13位于源极或漏极所在的一侧,需要根据需要具体设定。
优选地,源极一侧在形成上述有源层4之后,形成源漏金属层之前还包括:形成第一像素电极层7,且第一像素电极层7不完全覆盖有源层4,同时覆盖有源层4未覆盖的栅绝缘层3。进行第一像素电极层7的沉积为具体:在有源层4和栅绝缘层3上经过掩膜板遮挡进行刻蚀,得到如图6所示的第一像素电极层7。需要说明的是,掺杂有源层13的相对宽度为1~3微米。
完成优化沟道制作之后,继续对图6中存储电容14上方的栅绝缘层3刻蚀形成过孔11,如图7所示。在图7结构基础上继续沉积源漏金属层,随后进行刻蚀操作,将B区中的B2部分和C区所在的位置的源漏极金属层刻蚀掉,只保留B1区的金属层作为漏极6,另一侧作为源极5,至此得到源极5和漏极6,且源极5和漏极6示意图如图8所示。需要说明的是,在栅电极2上形成源极5和漏极6的同时,在存储电容14上方具有过孔11的栅绝缘层3上方也沉积源漏极金属层,在过孔11上方和周边形成信号接入端子10。
最后,再将B2区裸露的掺杂有缘层13以及C区的有源层4进行刻蚀,并在C区形成优化沟道。由于掺杂有源层13和有源层4具有1~3微米的相对宽度,能够保证在步骤S4中刻蚀掺杂有源层13和刻蚀有源层4进行刻蚀同时进行,最终形成优化沟道,如图9所示,其中12表示所述优化沟道。
得到优化沟道之后,在已经得到的结构上形成一层钝化层8(PVX,Passivationlayer),并在钝化层8上形成间隔分布的第二像素电极层9,最终得到的阵列基板示意图如图10所示。
综上,通过本实施例提供的像素阵列结构的制作方法,通过改变现有技术的沟道制作工艺,在有源层上继续形成不完全覆盖的掺杂有源层,并对掺杂有源层和有源层同时进行刻蚀,由于掺杂有源层可以将其视为导体,可以等同于将漏极边长,从而形成沟道长度变短的效果,进一步达到提高开态电流的目的。该方法能够突破现有技术手段以及设备限制,提升开态电流,更加有利于量产,提高生产效率。
实施例二
本发明实施例二还提供了一种阵列结构,该像素阵列结构就是由实施例一所述的像素阵列结构的制作方法得到的,进一步地,本实施例中还提供了一种阵列基板,该阵列基板包括玻璃基板以及在所述玻璃基板上按照实施例一所述的像素阵列结构的制作方法形成像素阵列结构。
该阵列基板的示意图如图10所示,在玻璃基板1上形成同层形成栅电极2和存储电容14,栅电极2上方依次形成栅绝缘层3、有源层4和掺杂有源层13,掺杂有源层13不完全覆盖有源层4,掺杂有源层13上方沉积源漏金属层并形成源极5和漏极6,最后沿着源极5和漏极6的边缘对掺杂有源层13和有源层4进行不完全刻蚀,形成优化沟道12。
进一步地,源极5还形成有第一像素电极层7,且第一像素电极层7不完全覆盖有源层4,同时覆盖有源层4未覆盖的栅绝缘层3。需要说明的是,掺杂有源层13的相对宽度为1~3微米。
另外,存储电容14上方的栅绝缘层3刻蚀形成过孔11,在栅电极2上形成源极5和漏极6的同时,在存储电容14上方具有过孔11的栅绝缘层3上方也沉积源漏极金属层,在过孔11上方和周边形成信号接入端子10。
得到优化沟道之后,在已经得到的结构上形成一层钝化(PVX)层8和第二像素电极层9,并且第二像素电极层9是间隔分布的。
基于上述阵列基板,本实施例中还提供了一种显示装置,包括阵列基板和彩膜基板,其中所述阵列基板就是上述阵列基板。
以上实施方式仅用于说明本发明,而并非对本发明的限制,有关技术领域的普通技术人员,在不脱离本发明的精神和范围的情况下,还可以做出各种变化和变型,因此所有等同的技术方案也属于本发明的范畴,本发明的专利保护范围应由权利要求限定。
Claims (6)
1.一种像素阵列结构的制作方法,其特征在于,包括:
S1、在有源层上方形成掺杂有源层,且上述掺杂有源层不完全覆盖所述有源层;
S2、在所述掺杂有源层和有源层上方形成源漏金属层,且所述源漏金属层部分覆盖所述掺杂有源层;
S3、对所述源漏金属层进行刻蚀,形成源极和漏极;
S4、沿着源极和漏极的边缘对所述掺杂有源层和所述有源层进行刻蚀,形成优化沟道,其中,沿着源极和漏极的边缘对掺杂有源层和有源层进行不完全刻蚀,形成优化沟道;
步骤S4中刻蚀所述掺杂有源层和刻蚀所述有源层同时进行。
2.如权利要求1所述的像素阵列结构的制作方法,其特征在于,所述掺杂有源层的厚度是所述有源层厚度的4~7倍。
3.如权利要求1所述的像素阵列结构的制作方法,其特征在于,所述有源层上不完全覆盖的掺杂有源层位于所述源极或所述漏极所在的一侧。
4.如权利要求1所述的像素阵列结构的制作方法,其特征在于,步骤S1之前还包括:
S01、在玻璃基板上制作栅电极和栅绝缘层;
S02、在所述栅绝缘层上形成所述有源层,并对所述有源层进行刻蚀,只保留所述栅电极所在位置对应的有源层。
5.如权利要求4所述的像素阵列结构的制作方法,其特征在于,所述源极一侧在形成上述有源层之后,形成源漏金属层之前还包括:形成第一像素电极层,且所述第一像素电极层不完全覆盖所述有源层,同时覆盖所述有源层未覆盖的栅绝缘层。
6.如权利要求1所述的像素阵列结构的制作方法,其特征在于,所述掺杂有源层的相对宽度为1~3微米。
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