WO2014178179A1 - 固体撮像素子および撮像装置 - Google Patents

固体撮像素子および撮像装置 Download PDF

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Publication number
WO2014178179A1
WO2014178179A1 PCT/JP2014/002335 JP2014002335W WO2014178179A1 WO 2014178179 A1 WO2014178179 A1 WO 2014178179A1 JP 2014002335 W JP2014002335 W JP 2014002335W WO 2014178179 A1 WO2014178179 A1 WO 2014178179A1
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Prior art keywords
discharge
row
solid
signal
imaging device
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English (en)
French (fr)
Japanese (ja)
Inventor
崇 後藤
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Fujifilm Corp
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Fujifilm Corp
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Priority to KR1020157032272A priority Critical patent/KR101732301B1/ko
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/65—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response

Definitions

  • the present invention relates to a solid-state imaging device including a photoelectric conversion unit that generates electric charge upon irradiation with light, and an imaging device including the solid-state imaging device.
  • a photoelectric conversion unit including a pair of electrodes and a photoelectric conversion layer sandwiched between these electrodes is provided above the silicon substrate, and generated in this photoelectric conversion layer
  • a photoelectric conversion layer stacked type solid-state imaging device is drawing attention, in which a stored charge is transferred from one of the pair of electrodes to a silicon substrate and accumulated, and a signal corresponding to the accumulated charge is read by a signal readout circuit formed on the silicon substrate. ing.
  • a solid-state imaging device for example, in Patent Document 1, as shown in FIG. 11, a photoelectric conversion unit 201 and a floating diffusion FD (hereinafter simply referred to as FD) that accumulates charges generated in the photoelectric conversion unit 201.
  • the output transistor 202 that outputs a voltage corresponding to the charge accumulated in the FD
  • the reset transistor 203 that resets the charge accumulated in the FD
  • the signal output from the output transistor 202 are selectively output to the signal line.
  • a solid-state imaging device has been proposed in which a large number of pixel portions 200 each including a selection transistor 204 are two-dimensionally arranged.
  • This solid-state imaging device is a circuit having a so-called three-transistor structure in which no transistor is provided between the FD and the photoelectric conversion unit 201, and the FD and the photoelectric conversion unit 201 are electrically connected directly. is there.
  • FIG. 12 shows the timing of the discharge operation and the charge signal readout operation of the pixel portion 200 in the nth to n + 2th rows.
  • FIG. 13 shows changes in drive and FD potential over time when the solid-state imaging device shown in FIG. 11 performs imaging under conditions where uniform light is incident on all pixels.
  • the solid line represents an ideal FD potential when there is no capacitive coupling, and the broken line represents a change in the potential of the FD when affected by capacitive coupling.
  • the change in the FD potential of the pixel of interest with the change in the FD potential of the adjacent pixel is a feature when there is an influence of capacitive coupling.
  • Each line discharges the charge accumulated in the FD until the time of discharge in the figure, and reads out the signal charge accumulated in the FD during the accumulation period from the discharge to the read at the time of reading.
  • the signal reading is completed at the time t1, and the potential of the FD becomes the reference potential.
  • discharging is performed at time t2, accumulation is started after the potential of FD is set to the reference potential.
  • reading is performed at time t5, and a signal corresponding to the signal charge accumulated in the FD between time t2 and time t5 is output.
  • the FD potential of the n-th row also changes with a large change in the FD potential of the n + 1-th row at time t2.
  • the FD potential changes monotonously from time t3 to time t4
  • the FD potential changes monotonically from time t3 to time t2, and then at time t2.
  • the potential decreases once, and the FD potential increases from the potential by accumulation of signal charges until time t4. For this reason, when the signal in the n-th row is read at time t4, the signal level is lower than the original signal level as indicated by the dotted line, compared to the original signal level indicated by the solid line.
  • red filters (R) and green filters (G) are alternately arranged in the column direction of the pixel unit 200.
  • the pixel unit 200 provided with the green filter is arranged in the same column as the pixel unit 200 provided with the red filter.
  • the discharge of the pixel unit 200 provided with the red filter reduces the potential of the FD of the pixel unit 200 provided with the green filter, and the magnitude of the charge signal G1. Will be smaller.
  • the coupling rate is the degree of influence of a potential change between FDs of adjacent pixel portions 200.
  • the coupling rate is determined by the ratio between the parasitic capacitance and the storage capacitance of the FD. The smaller the size of the pixel portion 200, the lower the degree of freedom of layout and the higher the coupling rate.
  • preliminary discharge which is preliminary charge discharge
  • discharge operation of each row Can be considered.
  • an operation when this preliminary discharge is performed will be described.
  • FIG. 16 shows the operation timing in the case of performing preliminary discharge on the (n + 1) th row before discharging on the nth row.
  • the FD potential change at the time of the n + 1th row discharge is performed by performing the n + 1th row preliminary discharge. Since the size can be reduced, the influence of the discharge of the (n + 1) th row on the accumulated signal of the nth row can be reduced.
  • this effect will be described quantitatively with reference to FIG.
  • the present invention includes a solid-state imaging device capable of sufficiently suppressing the influence even when a capacitive coupling formed between adjacent pixel rows is relatively large, and the solid-state imaging device.
  • An object is to provide an imaging device.
  • the solid-state imaging device of the present invention includes a photoelectric conversion unit that generates a signal charge corresponding to the amount of incident light, a storage unit that stores the signal charge generated in the photoelectric conversion unit, and a signal charge stored in the storage unit.
  • a signal charge that is stored in the storage unit and includes a plurality of pixel units that are electrically connected to the photoelectric conversion unit, the power storage unit, and the input node of the output circuit.
  • Preliminary discharge is performed at least twice, and the first preliminary discharge of the (n + 1) th row is performed before the discharge of the nth (n is a natural number) row, and the discharge is performed immediately before the discharge of the nth row. N before the first preliminary discharge in the nth row And characterized in that performing the second preliminary discharge in the first row.
  • a feedback control circuit that performs feedback control so that the power storage unit becomes a reference potential can be provided for each column of the pixel units.
  • the feedback control circuit can perform feedback control at the time of discharging, reading of signal charges, first preliminary discharging, and second preliminary discharging.
  • At least one of the discharge, the reading of signal charges, the first preliminary discharge, and the second preliminary discharge and an operation other than the at least one operation are performed in different rows within one scanning period. Can be done at different times.
  • a timing generator that outputs a pulse signal for controlling the timing of discharge, signal charge readout, first preliminary discharge, and second preliminary discharge is provided, and the timing generator is arranged within the scanning period of one row.
  • a pulse signal for controlling the timing of at least one operation and a pulse signal for controlling the timing of an operation other than the at least one operation can be output at different timings.
  • a shift register for controlling the timing of discharge, signal charge reading, first preliminary discharge, and second preliminary discharge can be provided for each operation.
  • the time for the first preliminary discharge or the second preliminary discharge can be made shorter than the discharge time.
  • the pixel portion includes a first electrode partitioned in units of pixels and a second electrode provided to face the pixel electrode with the photoelectric conversion portion interposed therebetween.
  • These pixel portions can be a common electrode.
  • the photoelectric conversion part can include an organic photoelectric conversion film.
  • the organic photoelectric conversion film can be common to all the pixel portions.
  • the signal charge from the photoelectric conversion part can be made a hole.
  • the signal charge from the photoelectric conversion unit can be converted to electrons.
  • a protection circuit can be provided in the power storage unit.
  • An image pickup apparatus includes the solid-state image sensor according to the present invention.
  • preliminary discharge which is preliminary charge discharge from the power storage unit, is performed at least twice before discharging in each row, and the nth (n is a natural number) row
  • the first preliminary discharge of the (n + 1) th row is performed
  • the second preliminary discharge of the (n + 1) th row is performed before the first preliminary discharge of the nth row performed immediately before the discharge of the nth row. Since this is performed, a change in voltage of the FD in discharging the pixel portion of each row can be reduced.
  • FIG. 1 shows the figure which shows the pixel part which comprises one Embodiment of the solid-state image sensor of this invention.
  • FIG. 1 shows the whole structure containing the peripheral circuit of the solid-state image sensor shown in FIG.
  • FIG. 1 shows an example of the timing of the 2nd preliminary
  • the figure which shows the electric potential change of FD of the pixel part of each line of nth line-n + 3th line The figure which shows an example of the relationship between the pulse signal output from a timing generator, and the operation
  • the figure which shows the positional relationship of the electrical storage part FD at the time of laying out the readout circuit of a pixel part by mirror image relation The figure which shows the electrical potential change of the electrical storage part FD at the time of only discharging, without performing preliminary discharge in the case of the positional relationship of the electrical storage part FD shown in FIG.
  • the figure which shows the structure and capacitive coupling of the pixel part of the conventional solid-state image sensor Timing chart for explaining discharge of conventional solid-state imaging device and reading of charge signal The figure for demonstrating the influence of the capacitive coupling in the conventional solid-state image sensor The figure for demonstrating the influence of the false signal by the capacitive coupling in the conventional solid-state image sensor The figure for demonstrating the influence of the afterimage by the capacitive coupling in the conventional solid-state image sensor
  • capacitance coupling at the time of performing preliminary discharge of the (n + 1) th row before discharge of the nth row The figure for demonstrating the influence of the afterimage by capacity
  • FIG. 1 is a diagram illustrating a pixel unit constituting the solid-state imaging device of the present embodiment.
  • the solid-state imaging device of the present embodiment has a large number of pixel portions 10 shown in FIG.
  • the pixel unit 10 includes a photoelectric conversion unit 11, a floating diffusion FD (corresponding to an accumulation unit) (hereinafter simply referred to as FD), an output transistor 12, a reset transistor 13, and a selection transistor 14. And.
  • the output transistor 12, the reset transistor 13, and the selection transistor 14 are each composed of an n-channel MOS transistor. Note that the size of the pixel portion 10 is desirably 5 ⁇ m or less.
  • the photoelectric conversion unit 11 includes a pixel electrode 104 (corresponding to the first electrode), a counter electrode 108 (corresponding to the second electrode) provided to face the pixel electrode 104, the pixel electrode 104, and the counter electrode. And a photoelectric conversion layer 107 provided between them.
  • the pixel electrode 104 is a thin film electrode divided for each pixel portion 10 and is formed of a transparent or opaque conductive material such as ITO, aluminum, titanium nitride, copper, tungsten, or the like.
  • the pixel electrode 104 collects charges generated in the photoelectric conversion layer 107 for each pixel unit 10.
  • the counter electrode 108 is an electrode for applying a voltage to the photoelectric conversion layer 107 between the pixel electrode 104 and generating an electric field in the photoelectric conversion layer 107. Since the counter electrode 108 is provided on the light incident surface side of the photoelectric conversion layer 107 and needs to be transmitted through the counter electrode 108 and incident on the photoelectric conversion layer 107, the counter electrode 108 is transparent to the incident light. It is formed from a conductive material such as ITO. Note that the counter electrode 108 in the present embodiment is configured by one electrode common to all the pixel units 10, but may be configured to be divided for each pixel unit 10.
  • the photoelectric conversion layer 107 includes an organic photoelectric conversion film or an inorganic photoelectric conversion film that absorbs incident light and generates charges according to the absorbed light quantity. Note that a function of a charge blocking layer or the like that suppresses charge injection from the electrode to the photoelectric conversion layer 107 between the photoelectric conversion layer 107 and the counter electrode 108 or between the photoelectric conversion layer 107 and the pixel electrode 104. A layer may be provided.
  • a bias voltage is applied to the counter electrode 108 so that holes out of the charges generated in the photoelectric conversion layer 107 move to the pixel electrode 104 and electrons move to the counter electrode 108.
  • a bias voltage a voltage higher than the power supply voltage Vdd (a voltage supplied to the drain of the output transistor 12 in FIG. 1, for example, 3 V) is used as a bias voltage so that the photoelectric conversion layer 107 exhibits sufficiently high sensitivity. It is desirable to use about 5 to 20 V, for example 10 V).
  • FD is composed of an n-type impurity region electrically connected to the pixel electrode 104. Since the potential of the FD changes according to the amount of holes collected by the pixel electrode 104, the FD functions as a charge storage portion.
  • the output transistor 12 converts the charge signal accumulated in the FD into a voltage signal and outputs it to the signal line SL.
  • the gate terminal of the output transistor 12 is electrically connected to the FD, and the drain terminal is connected to the power supply voltage Vdd of the solid-state imaging device.
  • the source terminal of the output transistor 12 is connected to the drain terminal of the selection transistor 14.
  • the pixel unit 10 in the present embodiment is a so-called three-transistor circuit in which the FD, the pixel electrode 104 of the photoelectric conversion unit 11, and the gate terminal of the output transistor 12 are directly connected.
  • the reset transistor 13 resets the potential of the FD to a reference potential.
  • the FD is electrically connected to the drain terminal of the reset transistor 13 and the feedback control circuit 16 is connected to the source terminal.
  • the feedback control circuit 16 includes an inverting amplifier 16a and a voltage source 16b that supplies a reference voltage RD.
  • the signal line SL is connected to the inverting input terminal ( ⁇ ) of the inverting amplifier 16a, the voltage source 16b is connected to the non-inverting input terminal (+), and the feedback line FL is connected to the output terminal.
  • the feedback line FL is connected to the source terminal of the reset transistor 13.
  • the reset transistor 13 When the reset pulse RS applied to the gate terminal of the reset transistor 13 becomes high level, the reset transistor 13 is turned on, and electrons are injected from the source to the drain of the reset transistor 13. Then, due to the injection of electrons, the potential of the FD drops and the potential of the FD is reset to the reference potential. At this time, the potential of the FD is changed via the output transistor 12, the selection transistor 14, and the signal line SL. Input to the feedback control circuit 16.
  • the feedback control circuit 16 feedback-controls the potential of the FD, whereby the potential of the FD is maintained at a constant reference potential. .
  • reset kTC noise of the reset transistor 13 can be reduced.
  • the feedback control circuit 16 is provided for each column of the pixel units 10 and is shared by the plurality of pixel units 10 belonging to each column.
  • the selection transistor 14 has a source terminal connected to the signal line SL, and selectively outputs a signal output from the output transistor 12 of each pixel unit 10 to the signal line SL provided for each column. belongs to.
  • the selection pulse RW applied to the gate terminal of the selection transistor 14 becomes a high level, the selection transistor 14 is turned on, whereby a signal output from the output transistor 12 of each pixel unit 10 is output to the signal line SL.
  • FIG. 2 is a schematic cross-sectional view of a solid-state imaging device 100 in which a large number of pixel portions 10 shown in FIG. 1 are two-dimensionally arranged.
  • the same name and reference numeral are assigned to the same configuration as the pixel unit 10 shown in FIG.
  • the solid-state imaging device 100 includes a substrate 101, an insulating layer 102, a connection electrode 103, a pixel electrode 104, a connection portion 105, a connection portion 106, a photoelectric conversion layer 107, and a counter electrode. 108, a sealing layer 110, a color filter 111, a light shielding layer 113, a protective layer 114, a counter electrode voltage supply unit 115, and a readout circuit 116.
  • the substrate 101 is a glass substrate or a semiconductor substrate such as Si.
  • An insulating layer 102 is formed on the substrate 101.
  • a plurality of pixel electrodes 104 and one or more connection electrodes 103 are formed on the surface of the insulating layer 102.
  • the photoelectric conversion layer 107 generates an electric charge according to the received light as described above.
  • the photoelectric conversion layer 107 is provided so as to cover the plurality of pixel electrodes 104.
  • the photoelectric conversion layer 107 has a constant film thickness on the pixel electrode 104, but there is no problem even if the film thickness changes outside the pixel portion (outside the effective pixel area).
  • the counter electrode 108 is an electrode facing the pixel electrode 104, and is provided so as to cover the photoelectric conversion layer 107.
  • the counter electrode 108 is formed up to the connection electrode 103 arranged outside the photoelectric conversion layer 107 and is electrically connected to the connection electrode 103.
  • connection unit 106 is embedded in the insulating layer 102 and is a plug or the like for electrically connecting the connection electrode 103 and the counter electrode voltage supply unit 115.
  • the counter electrode voltage supply unit 115 is formed on the substrate 101 and applies a predetermined voltage to the counter electrode 108 via the connection unit 106 and the connection electrode 103. Note that the counter voltage supply unit 115 may be configured not directly on the substrate 101 but directly connected to an external power source.
  • the readout circuit 116 includes the FD, the output transistor 12, the reset transistor 13, and the selection transistor 14 shown in FIG. 1, and is wired by a metal wiring (not shown) in the insulating layer 102.
  • the readout circuit 116 is provided on the substrate 101 corresponding to each of the plurality of pixel electrodes 104, and reads out a signal corresponding to the charge collected by the corresponding pixel electrode 104. Note that the reading circuit 116 is shielded from light by a light shielding layer (not shown) disposed in the insulating layer 102.
  • the sealing layer 110 is provided so as to cover the counter electrode 108.
  • the color filter 111 is formed at a position facing each pixel electrode 104 on the sealing layer 110.
  • the light shielding layer 113 is formed in a region other than the region where the color filter 111 is provided on the sealing layer 110, and prevents light from entering the photoelectric conversion layer 107 formed outside the effective pixel region.
  • a Bayer color filter can be used as the color filter 111.
  • the color filter is not limited to this, and a complementary color filter or other known color filters can be used.
  • the protective layer 114 is formed on the color filter 111 and the light shielding layer 113, and protects the entire solid-state imaging device.
  • FIG. 3 is a diagram showing an overall configuration including peripheral circuits of the solid-state imaging device 100 shown in FIG.
  • the solid-state imaging device 100 includes a vertical driver 121, a control unit 122, a signal processing circuit 123, a horizontal driver 124, an LVDS 125, a serial conversion unit 126, and a pad 127. It has.
  • the pixel area shown in FIG. 3 represents an area where the pixel portions 10 of the solid-state imaging device 100 shown in FIG. 2 are arranged.
  • a signal line SL for outputting a signal from the output transistor 12 of each pixel unit 10 and the feedback line FL described above are provided for each column of the pixel unit 10, and a switching pulse signal is output from the vertical driver 121.
  • a scanning line GL is provided for each row.
  • the feedback control circuit 16 is provided for each column of the pixel unit 10.
  • the control unit 122 includes a timing generator (hereinafter referred to as TG) 128 and the like, outputs a frame synchronization signal VD and a row synchronization signal HD, and controls operations of the vertical driver 121 and the horizontal driver 124. It controls the readout of charge signals in the pixel unit 10.
  • TG timing generator
  • the vertical driver 121 outputs a reset pulse RS and a selection pulse RW to the reading circuit 116 via the scanning line GL based on the timing pulse signal output from the TG 128 of the control unit 122, and performs the operation of the reading circuit 116. It is something to control.
  • the vertical driver 121 of the present embodiment performs a preliminary discharge, which is a preliminary charge discharge from the FD, twice before discharging the accumulated charge in the so-called conventional FD. Is to control.
  • the vertical driver 121 Based on the timing pulse signal output from the TG 128, the vertical driver 121 outputs a selection shift register 130 that outputs a selection pulse RW and a reset pulse RS for reading a charge signal, and a selection pulse RW and a reset for discharge.
  • the discharge shift register 131 that outputs the pulse RS
  • the first preliminary discharge shift register 132 that outputs the selection pulse RW and the reset pulse RS during the first preliminary discharge, and the selection during the second preliminary discharge
  • a second preliminary discharge shift register 133 that outputs a pulse RW and a reset pulse RS. The timing of the selection pulse RW and the reset pulse RS output from these shift registers 130 to 133 will be described in detail later.
  • the signal processing circuit 123 is provided corresponding to each column of the readout circuit 116.
  • the signal processing circuit 123 includes an ADC circuit that performs correlated double sampling (CDS) processing on the signals output from the corresponding columns and converts the processed signals into digital signals.
  • CDS correlated double sampling
  • the signal processed by the signal processing circuit 123 is stored in a memory provided for each column.
  • the horizontal driver 124 performs control to sequentially read out signals for one row of the pixel unit 10 stored in the memory of the signal processing circuit 123 and output the signals to the LVDS 125.
  • the LVDS 125 transmits a digital signal in accordance with LVDS (low voltage differential).
  • the serial conversion unit 126 converts an input parallel digital signal into a serial signal and outputs it.
  • the pad 127 is an interface used for input / output with the outside.
  • the second preliminary discharge, the first preliminary discharge, the discharge, and the charge signal reading operation are sequentially performed for each row of the pixel unit 10.
  • the second preliminary discharge, the first preliminary discharge, the discharge, and the charge signal reading operation for each row of the pixel unit 10 are sequentially scanned in the column direction of the pixel unit 10.
  • FIG. 4 shows an example of the timings of second preliminary discharge, first preliminary discharge, discharge, and charge signal readout in the nth row (n is a natural number) to the n + 3th row of the solid-state imaging device 100 of the present embodiment.
  • the second preliminary discharge, the first preliminary discharge, the discharge, and the readout of the charge signal are sequentially performed for each of the nth to n + 3th rows. .
  • the reset pulse RS and the selection pulse RW for the second preliminary discharge are output from the second preliminary discharge shift register 133 of the vertical driver 121 to each row. Then, the reset transistor 13 of the pixel unit 10 is turned on by the reset pulse RS, and the selection transistor 14 of the pixel unit 10 is turned on by the selection pulse RW. As a result, the FD is connected to the feedback control circuit 16 via the selection transistor 14, and the potential of the FD is feedback-controlled by the feedback control circuit 16 and reset to the reference potential.
  • the reset pulse RS and the selection pulse RW for the first preliminary discharge are output from the first preliminary discharge shift register 132 of the vertical driver 121 to each row.
  • the reset transistor 13 of the pixel unit 10 is turned on by the reset pulse RS
  • the selection transistor 14 of the pixel unit 10 is turned on by the selection pulse RW
  • the potential of the FD is feedback controlled again. And reset to the reference potential.
  • a reset pulse RS and a selection pulse RW for discharge are output from the discharge shift register 131 of the vertical driver 121 to each row.
  • the reset transistor 13 of the pixel unit 10 is turned on by the reset pulse RS
  • the selection transistor 14 of the pixel unit 10 is turned on by the selection pulse RW.
  • the potential is feedback controlled and reset to the reference potential.
  • a selection pulse RW is output from the read shift register 130 of the vertical driver 121 to each row. Then, the selection transistor 14 is turned on by this selection pulse RW, whereby the charge signal stored in the FD is converted into a voltage signal by the output transistor 12 and output as a storage signal to the signal line SL.
  • a reset pulse RS is output from the readout shift register 130 to each row, and the reset transistor 13 of the pixel portion 10 is turned on by this reset pulse RS, and the potential of the FD is again feedback controlled to be reset to the reference potential. . Then, a signal immediately after the reset transistor 13 is turned off and the reset is completed is output to the signal line SL as a reset signal.
  • the signal processing circuit 123 calculates the difference between the accumulated signal and the reset signal, and using this difference as an image signal makes it possible to acquire an image with less fixed pattern noise and reset kTC noise.
  • the feedback control time for the second preliminary discharge or the first preliminary discharge may be set shorter than the time for the feedback control for discharge.
  • the discharge time and the read time can be set longer, and the S / N of the image signal can be improved.
  • the feedback control time can be controlled by adjusting the ON time of the reset pulse RS and the selection pulse RW.
  • the first preliminary discharge of the (n + 1) th row is performed before the discharge of the nth row and the first preliminary discharge of the nth row is performed. And the second preliminary discharge in the (n + 1) th row is controlled. Similarly, the first preliminary discharge of the (n + 2) th row is performed before the discharge of the (n + 1) th row, and the second preliminary discharge of the (n + 2) th row is performed before the first preliminary discharge of the (n + 1) th row.
  • the first preliminary discharge of the next row is performed, and the first preliminary discharge and the second preliminary discharge of the predetermined row are Control is performed so that the second preliminary discharge of the next row is performed during the interval.
  • FIG. 5 shows the potential change of the FD of the pixel portion 10 in each row when the timing of each operation in each row is controlled as described above.
  • uniform light is irradiated to the solid-state imaging device 100 by the LED at time t0, and 10000 electrons are accumulated in the FD before the preliminary discharge of each row, and the coupling rate of adjacent rows is The case of 5% will be described.
  • the potential of the FD in the n-th row is changed from a potential corresponding to ⁇ 500 electrons to a potential corresponding to 0 electrons, that is, a reference potential.
  • the FD of the nth row is affected by the capacitive coupling, and the potential of the FD of the (n + 1) th row corresponds to ⁇ 500 electrons.
  • the potential corresponds to ⁇ 5% of the ⁇ 500 electrons. That is, the FD in the nth row has a potential corresponding to 25 electrons.
  • the potential of the FD of the nth row is changed from the potential corresponding to 25 electrons to the reference potential.
  • accumulation of signal charges is started from the start of the discharge.
  • the n + 1-th row FD is discharged, and the n-th row FD is affected by the capacitive coupling, so that the potential of the n + 1-th row FD changes from the potential corresponding to 25 electrons to the reference potential.
  • a potential fluctuation corresponding to ⁇ 5% of the 25 electrons occurs. That is, an offset potential corresponding to ⁇ 1.25 electrons is added to the charge signal accumulated after the nth row is discharged.
  • the offset potential corresponding to ⁇ 1.25 electrons can be suppressed for 10,000 stored signals.
  • the first preliminary discharge in the (n + 1) th row is performed before the discharge in the nth row
  • the second preliminary discharge is performed before the first preliminary discharge in the nth row.
  • the potential can be made sufficiently small.
  • the preliminary discharge is performed twice before the discharge of each row.
  • the preliminary discharge is not limited to two times, and may be performed three times or more.
  • the influence of capacitive coupling of optical signal charges in a predetermined frame can be set to ( ⁇ coupling ratio) (j + 1) .
  • the optical signal charge of the frame is as large as 100,000 electrons and the coupling rate is 10%
  • the effect of the present invention increases as the coupling rate increases.
  • the size of the pixel portion 10 is 5 ⁇ m or less, the coupling rate increases to a degree that cannot be ignored. It is remarkable.
  • the TG 128 periodically outputs a pulse signal in accordance with the timing of the second preliminary discharge, the first preliminary discharge, the discharge and the reading of each row.
  • the pulse signal output from the TG 128 is input to the read shift register 130, the discharge shift register 131, the first preliminary discharge shift register 132, and the second preliminary discharge shift register 133.
  • Each shift register outputs a reset pulse RS and a selection pulse RW to each row at a preset timing based on the input pulse signal.
  • FIG. 6 shows the relationship between the pulse signal output from the TG 128 and the operation timing in each of the n ⁇ 1 to n + 1 rows. In FIG. 6, it is assumed that time elapses from left to right in the upper stage and then elapses from left to right in the lower stage.
  • the TG 128 performs, for example, the second preliminary ejection pulse signal PR2, the first preliminary ejection pulse signal PR1, the ejection pulse signal R, and the readout pulse signal S in this order. Output.
  • These four types of pulse signals are output during each scanning period and input to each shift register, and each shift register is input to each row at the logical product timing of the input pulse signal and a preset timing.
  • a reset pulse RS and a selection pulse RW are output.
  • the second preliminary ejection pulse signal PR2, the first preliminary ejection pulse signal PR1, the ejection pulse signal R, and the readout pulse signal S are output from the TG 128 in this order. It is not necessarily limited to this order.
  • FIG. 7 shows an example in which four types of pulse signals are output from the TG 128 in the other order.
  • the TG 128 outputs the read pulse signal S, the discharge pulse signal R, the first preliminary discharge pulse signal PR1, and the second preliminary discharge pulse signal PR2. That is, FIG. 7 shows an example in which four types of pulse signals are output from the TG 128 in the reverse order to the example shown in FIG. Also in the example shown in FIG.
  • each shift register outputs the reset pulse RS and the selection pulse RW to each row at the logical product timing of the input pulse signal and a preset timing. Also in this case, the operation of each row is always performed in the order of the second preliminary discharge, the first preliminary discharge, the discharge, and the reading. Further, the first preliminary discharge of the (n + 1) th row is performed before the discharge of the nth row, and the second preliminary discharge of the (n + 1) th row is performed before the first preliminary discharge of the nth row. As described above, the timing is set in each shift register.
  • the output order of the four types of pulse signals output from the TG 128 is not limited to the order shown in FIGS. 6 and 7, but may be other orders.
  • the TG 128 outputs all four types of pulse signals at different timings.
  • the present invention is not limited to this, and at least one of the four types of pulse signals is output. May be output at a timing different from the timing of other pulse signals.
  • each row is performed in the order of the second preliminary discharge, the first preliminary discharge, the discharge, and the reading, and further, the first spare of the (n + 1) th row before the discharge of the nth row.
  • the timing is set in each shift register so that the discharge is performed and the second preliminary discharge of the (n + 1) th row is performed before the first preliminary discharge of the nth row.
  • the readout circuit of each pixel unit 10 may be laid out in a pattern having periodicity in the pixel unit column direction.
  • the readout circuit of the pixel unit 10 when the readout circuit of the pixel unit 10 is laid out in a mirror image relationship, the readout circuit is laid out in a pattern of 2 rows in the column direction, and the coupling capacitance between adjacent pixels is also 2 rows.
  • the capacitive coupling between the pixel units 10 in the nth row (odd row) and the n + 1th row (even row) is relatively large, and the n + 1th row (even row).
  • the (n + 2) -th row (odd-numbered row) pixel portions 10 are relatively small in capacitive coupling.
  • the capacitive coupling between the pixel portions 10 of the (n + 2) th row (odd row) and the (n + 3) th row (even row) becomes relatively large.
  • FIG. 9 shows a change in the potential of the FD when only discharging is performed as in the prior art without performing the preliminary discharging described above in such a configuration.
  • the figure shows the time variation of the drive and FD potential when imaging is performed under conditions where uniform light is incident on all pixels.
  • a solid line in FIG. 9 shows an ideal potential change when there is no capacitive coupling, and a dotted line shows an actual potential change.
  • the influence of the discharge of the (n + 1) th row on the potential of the FD of the pixel portion 10 of the nth row and the discharge of the (n + 3) th row are the discharges of the (n + 2) th row.
  • the even-numbered lines n + 1 and n + 3 can obtain an output almost equal to the case without capacitive coupling, while the odd-numbered lines n and n + 2 have no capacitive coupling.
  • the output will be very different. That is, even when uniform light is incident on the pixel units 10 from the nth row to the n + 3th row, the magnitudes of the charge signals read out by the odd-numbered pixel units 10 and the even-numbered pixel units 10 are different.
  • the horizontal stripes appear every other line on the read image.
  • the readout circuit of the pixel unit 10 is not limited to the 2-row cycle, and may be laid out with a pattern of a 3-row cycle or a 4-row cycle, for example.
  • the capacitive coupling formed between adjacent pixels in the column direction is a pattern that periodically changes in the column direction, it may be laid out in any periodic structure. The effect of the present invention becomes remarkable.
  • the reset transistor 13, the output transistor 12, and the selection transistor 14 are configured by n-channel MOS transistors, and holes are collected by the pixel electrode 104.
  • the reset transistor 13, the output transistor 12, and the selection transistor 14 are configured by p-channel MOS transistors, the electrons are collected by the pixel electrode 104, and a charge signal corresponding to the amount of the electrons is supplied to the p-channel MOS transistor. Reading may be performed by the signal reading circuit 116 configured as described above.
  • holes are collected by the pixel electrode 104 and read out by the signal readout circuit 116 constituted by an n-channel MOS transistor, or electrons are collected by the pixel electrode 104 as described above.
  • the signal readout circuit 116 configured by a p-channel MOS transistor
  • electrons are collected by the pixel electrode and read by a signal readout circuit configured by an n-channel MOS transistor.
  • the voltage amplitude of FD is large. For this reason, since the potential change of the FD at the time of discharge when the first and second preliminary discharges are not performed is large, the influence of the capacitive coupling on the signal charge of the FD of the adjacent pixel is large. The effect of the second preliminary discharge can be obtained more remarkably.
  • a configuration in which a protective circuit 17 is provided in the FD may be used. Since the number of components of the readout circuit 116 increases, the coupling rate increases. However, according to the present embodiment, there is no problem because it is possible to suppress deterioration in image quality due to the coupling rate.
  • the solid-state imaging device of the above-described embodiment can be used for various imaging devices.
  • the imaging device include a digital camera, a digital video camera, an electronic endoscope, and a camera-equipped mobile phone.

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
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JP6646824B2 (ja) 2016-01-22 2020-02-14 パナソニックＩｐマネジメント株式会社 撮像装置
KR102609647B1 (ko) 2018-02-07 2023-12-05 소니 세미컨덕터 솔루션즈 가부시키가이샤 고체 촬상 소자 및 촬상 장치

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