Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
  • H03M1/12—Analogue/digital converters
  • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
• • G—PHYSICS
  • G04—HOROLOGY
  • G04F—TIME-INTERVAL MEASURING
  • G04F10/00—Apparatus for measuring unknown time intervals by electric means
  • G04F10/005—Time-to-digital converters [TDC]
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L7/00—Automatic control of frequency or phase; Synchronisation
  • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
  • H03L7/08—Details of the phase-locked loop
  • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
  • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
  • H03L2207/50—All digital phase-locked loop

Definitions

• the present disclosure relates to electronic circuits, and more particualry to a time-to-digital converter.
• a time-to-digital converter is an electronic circuit that converts the difference between transition times of two signals to a digital signal whose value is proportional to such timing difference.
• a time-to-digital converter may be used in a phase-locked loop to convert the difference between the transition times of a reference clock signal and an oscillating signal to a digital signal in order to lock the phase of the oscillating signal to the phase of the clock signal.
• a time-to-digital converter converts the difference between transition times of a reference clock signal and an oscillating signal to a digital signal whose value is proportional to the transitions timing difference.
• the time-to-digital converter in accordance with one embodiment of the present invention, includes an edge detector, a time-to-voltage converter, and an analog-to-digital converter.
• the edge detector is adapted to detect, during each period of the reference clock signal, the edge (transition) of the oscillating signal that is closest to the edge of the reference clock signal.
• the time-to-voltage converter is adapted to generate an analog signal having a value proportional to the difference between the occurrences of the detected edge of the oscillating signal and the edge of the reference clock signal.
• the analog-to-digital converter is adapted to convert the analog signal to a digital signal.
• the time-to-digital converter has first and second differential outputs that are charged to a predefined voltage level in response to a reset signal. Thereafter, depending on the relative arrival times of the detected edge of the oscillating signal and the reference clock signals, one of the differential outputs is enable to charge to a higher voltage (or discharge to a lower voltage) while the other QUALCOMM Ref. No.: 121395U2WO 2 differential output remains at the same predefined voltage level. The longer the period between the arrival times of the two edges, the greater is the amount of voltage increase (or decrease).
• a conductive path is formed between the first differential output and a first supply voltage via first and second transistors if the edge of the reference clock signal leads the detected edge of the oscillating signal. Conversely, a conductive path is formed between the second differential output and the first supply voltage via third and fourth transistors if the edge of the reference clock signal lags the detected edge of the oscillating signal.
• the first differential output of the time-to-digital converter is charged to the predefined voltage level via a fifth transistor, and the second differential output of the time-to-digital converter is charged to the predefined voltage level via a sixth transistor.
• the predefined voltage level may be a second supply voltage.
• the fifth and sixth transistors are NMOS transistors and the second supply voltage is smaller than the first supply voltage.
• the time-to-digital converter further includes, in part, first and second multitudes of capacitors. Each of the first multitude of capacitors is adapted to be coupled between the first differential output and the second supply voltage in response to a different one of a first multitude of control signals. Similarly, each of the second multitude of capacitors is adapted to be coupled between the second differential output and the second supply voltage in response to a different one of a second multitude of control signals.
• the analog-to-digital converter further includes a comparator adapted to compare voltages of the first and second differential outputs of the time-to-voltage converter and supply a comparison signal to the control logic.
• the QUALCOMM Ref. No.: 121395U2WO 3 control logic generates the output signal of the time-to-voltage converter.
• Figure 1 is a block diagram of a time-to-digital converter, in accordance with one exemplary embodiment of the present invention.
• Figure 2 A is a schematic diagram of a time-to-digital converter, in accordance with one exemplary embodiment of the present invention.
• Figure 7A is a block diagram of a logic circuit disposed in the edge detector of Figure 1 , in accordance with one exemplary embodiment of the present invention.
• Edge detector 100 is adapted to receive an oscillating signal DCO 10, and a reference clock signal FREF 12 that has a longer time period than signal DCO 10. Accordingly, during each period of signal FREF 12, a number of transitions (edges) occur on signal DCO 10. In one embodiment, during each period of signal FREF 12, edge detector 100 filters out all DCO 10 signal edges except the rising (or falling) DCO 10 edge that is closest in time to the rising (or falling) edge of signal FREF 12 in that period. The DCO 10 signal edge detected as being closest in time to the rising (or falling) edge of signal FREF 12 is supplied as output signal CKV 14. The corresponding edge of signal FREF 12 is supplied as output signal REF 16 by edge detector 100.
• the drop in voltage level of node OUT 18 from VDD to V2 is dependent on the period (T5-T4). In other words, the longer is the delay between arrival times of the corresponding edges (i.e., transition times) of signals REF 16 and CKV 14, the greater is the drop in the voltage level of node OUT 18.
• the differential voltage across nodes OUT 18 and OUT B 20 is converted to a digital signal by an analog-to-digital converter whose output voltage represents the output of the TDC.
• Capacitor bank 280 includes N capacitors 282; and N switches 284;, where i is an integer varying from 1 to N.
• a first terminal of each capacitor 282 is coupled to node OUT 18.
• a second terminal of each capacitor 282 is coupled to supply voltage Vref via an associated switch 284; which opens or closes in response to one of the N bits of signal PhiP.
• the second terminal of capacitor 282 receives voltage Vref when bit i of N-bit signal PhiP is asserted in order to close an associated switch 284;.
• capacitor bank 290 includes N capacitors 292; and N switches 294;.
• a first terminal of each capacitor 292; is coupled to node OUT B 20.
• a second terminal of each capacitor 292; is coupled to supply voltage Vref via an associated switch 294; which opens or closes in response to one of the N bits of signal PhiN.
• the second terminal of capacitor 292 receives Vref when bit i of N-bit signal PhiN is asserted in order to close an associated switch 294;.
• the differential voltage across output nodes OUT 18, OUT B 20 of capacitor banks 280, 290 is converted to a digital signal using an ADC.
• Phase detecotor 604 is adapted to detect the difference between the signal value supplied by adder 610, namely ADD OUT 66, and the signal value supplied by delat- sigma modulator 602, namely signal FCW F to generate a phase error signal P Error 74.
• Loop filter 606 is a low-pass filter adapted to filter out the high frequency components of the noise from signal P Error and supply the filtered signal FIL OUT 76 to DCO 608.
• the phase of the osciallting signal DCO 10 generated by digitally- controlled oscillator 608 is varied in accordance with the filtered signal it receives from loop-filter 606 so as to lock the phase of signal DCO 10 to the phase of signal FREF 12.
• a TDC in accordance with embodiments of the present invention, may be used in any other controlled-loop circuitry, such as frequency-locked loop, phase/frequency locked loop, and the like.
• CMOS complementary metal-oxide-semiconductor
• Bipolar complementary metal-oxide-semiconductor
• BICMOS complementary metal-oxide-semiconductor

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• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Analogue/Digital Conversion (AREA)
• Manipulation Of Pulses (AREA)
• Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

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• 2013
  • 2013-03-15 US US13/842,481 patent/US8957712B2/en active Active
• 2014
  • 2014-03-12 CN CN201480014340.8A patent/CN105191141B/zh not_active Expired - Fee Related
  • 2014-03-12 KR KR1020157028038A patent/KR20150129794A/ko not_active Ceased
  • 2014-03-12 EP EP14714891.0A patent/EP2972598B1/en not_active Not-in-force
  • 2014-03-12 JP JP2016501405A patent/JP6382292B2/ja not_active Expired - Fee Related
  • 2014-03-12 WO PCT/US2014/024035 patent/WO2014150707A2/en not_active Ceased

Non-Patent Citations (1)

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