WO2014146362A1 - 阵列基板及其制备方法和显示面板 - Google Patents

阵列基板及其制备方法和显示面板 Download PDF

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Publication number
WO2014146362A1
WO2014146362A1 PCT/CN2013/077519 CN2013077519W WO2014146362A1 WO 2014146362 A1 WO2014146362 A1 WO 2014146362A1 CN 2013077519 W CN2013077519 W CN 2013077519W WO 2014146362 A1 WO2014146362 A1 WO 2014146362A1
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Prior art keywords
pixel electrode
ohmic contact
electrode
array substrate
conductive channel
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English (en)
French (fr)
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张文余
谢振宇
李婧
田宗民
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Beijing BOE Optoelectronics Technology Co Ltd
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Beijing BOE Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display panel. Background technique
  • the structure of the array substrate is as shown in FIG. 1 , including the horizontally arranged gate lines 10 and the vertically arranged data lines 20 and the pixel units formed by the intersection of the gate lines 10 and the data lines 20 .
  • Each of the pixel units includes a thin film transistor (TFT) and a pixel electrode 3'.
  • TFT thin film transistor
  • FIG. 2 the cross-sectional structure of the array substrate along the broken line A-A' in FIG. 1 is as shown in FIG. 2.
  • a gate electrode 21, a gate insulating layer 22, a pixel electrode 3', and an active source are sequentially formed.
  • a conductive channel 27' is formed between the source 25 and the drain 26.
  • the aspect ratio of the conductive channel determines the functional characteristics of the TFT device. Under the condition that the width of the channel is constant, reducing the length of the channel is beneficial to increase the on-state current of the TFT device, thereby improving the performance of the device. Therefore, shortening the length of the channel is very necessary for high-resolution products; and shortening the length of the channel can reduce the design size of the TFT, increasing the pixel aperture ratio and reducing the design size of the peripheral circuit (for example, Narrow borders are important. Summary of the invention
  • An embodiment of the present invention provides an array substrate including a matrix of pixel units, the pixel unit including a thin film transistor and a pixel electrode, the thin film transistor including a gate, a gate insulating layer, an active layer, and an ohmic contact layer a source, a drain, and a conductive channel, wherein the pixel electrode extends to the thin film transistor region, and the pixel electrode portion extending to the thin film transistor region covers the ohmic contact layer under the drain, and is partially formed on the gate insulating layer; The length of the conductive channel is less than the distance between the source and the drain.
  • Another embodiment of the present invention provides a display panel including the above array substrate.
  • Another embodiment of the present invention provides a method of fabricating an array substrate, comprising: forming a pattern including a gate on a substrate; forming a gate insulating layer on the substrate on which the pattern is formed; and forming a substrate on the gate insulating layer Forming an active layer and an ohmic contact layer thereon; forming an active layer and an ohmic contact layer Forming a pixel electrode on the substrate, wherein the pixel electrode extends to the TFT region, and the pixel electrode portion extending to the TFT region covers the ohmic contact layer under the drain, partially formed on the gate insulating layer; and the pixel electrode is formed Forming a pattern including a source and a drain on the substrate; forming a conductive channel by etching the ohmic contact layer on the substrate on which the source and the drain are formed, the length of the conductive channel being smaller than between the source and the drain a distance; and forming a passivation layer on the substrate on which the conductive channel is formed.
  • FIG. 1 is a top plan view of an array substrate in the prior art
  • FIG. 2 is a schematic view showing the detailed structure of a TFT in the array substrate shown in FIG. 1;
  • FIG. 3 is a schematic structural view of a TFT in an array substrate according to an embodiment of the present invention
  • FIG. 4 is a schematic plan view showing a planar structure of an array substrate according to an embodiment of the present invention
  • FIG. 5 is a process of preparing the TFT shown in FIG.
  • FIG. 6 is a structural schematic view showing the formation of a pixel electrode on the substrate of the structure shown in FIG. 5
  • FIG. 7 is a schematic view of forming a metal layer on the substrate of the structure shown in FIG. Rear structural diagram;
  • FIG. 8 is a schematic view showing a structure in which a drain and a source are formed on a substrate of the structure shown in FIG. 7.
  • FIG. 9 is a schematic view showing a conductive channel formed on a substrate of the structure shown in FIG. 8; and
  • FIG. 10 is in FIG. A schematic view of the structure after forming a passivation layer on the substrate of the structure shown. detailed description
  • the embodiment of the invention provides an array substrate, a preparation method thereof and a display panel, which are used for reducing the length of the conductive channel of the TFT, improving the on-current and TFT characteristics of the TFT, and further improving the display. Effect.
  • FIG. 3 is a structural cross-sectional view of the array substrate
  • FIG. 4 is a plan top view of the array substrate
  • FIG. 3 is a cross-sectional view taken along a line A-A' of FIG. Figure.
  • the array substrate may include matrix elements arranged in a matrix, the pixel unit including a common electrode, a thin film transistor (TFT), and a pixel electrode. As shown in FIG.
  • the array substrate includes a glass substrate 1, a TFT 2 and a pixel electrode 3 formed on the glass substrate 1, and a passivation layer 4 formed on the TFT 2 and the pixel electrode 3,
  • the TFT 2 includes a gate electrode 21, a gate insulating layer 22, an active layer 23, an ohmic contact layer 24, a source electrode 25, and a drain electrode 26.
  • the pixel electrode 3 extends to the TFT region, and the pixel electrode 3 extending to the TFT region partially covers the ohmic contact layer 24 under the drain electrode 26, and is partially formed on the gate insulating layer 22.
  • the array substrate further includes a conductive channel 27 formed between the source 25 and the drain 26, the conductive channel 27 being formed by etching the ohmic contact layer 24, the length of which is equal to the pixel electrode 3 and the source 25 The distance between the length and the length is less than the large separation between the source and the drain.
  • the length of the conductive channel 27 is less than 4 ⁇ m.
  • the length of the conductive channel in the prior art is generally the distance between the source and the drain, and is generally greater than 4 ⁇ m. .
  • the length of the conductive channel 27 is 2.5 ⁇ m.
  • a part of the ohmic contact layer is covered by the pixel electrode, so that the pixel electrode protects a part of the ohmic contact layer from being etched during the subsequent etching, thereby obtaining a length shorter than the distance between the drain and the source.
  • Conductive channel In the embodiment of the present invention, a conductive channel having a length of less than 4 ⁇ m is generally obtained, but in consideration of the lamination effect of the alignment accuracy, the length of the conductive channel may not be too short, for example, a conductive channel having a length of 2.5 ⁇ m may be formed. .
  • the array substrate further includes data lines and gate lines disposed at intersections, wherein the data lines and the gate lines surround the pixel units arranged in a matrix.
  • the gate lines 10 are arranged in the first direction
  • the data lines 20 are arranged in the second direction
  • each of the two gate lines 10 and each of the two data lines 20 intersect to form a pixel unit.
  • the pixel electrode 3 in the figure extends to an ohmic contact layer (not shown) of the TFT, and the edge of the pixel electrode 3 shown in the figure is the boundary of the conductive channel 27.
  • the ohmic contact layer and the drain are electrically connected through the pixel electrode.
  • sexual connection the resulting change in resistance and capacitance does not affect the characteristics of the TFT;
  • the thickness of the pixel electrode can be the same as in the prior art, in which case, since the thickness of the pixel electrode is small relative to the TFT, Therefore, the influence of the uniformity of the source and drain heights of the TFT does not impair the characteristics of the TFT, and the protection of the passivation layer on the TFT does not affect the uniformity of the panel.
  • the embodiment of the invention provides a method for preparing an array substrate, which comprises:
  • a pixel electrode layer on the substrate on which the active layer and the ohmic contact layer are formed, wherein the pixel electrode extends to the TFT region, and the pixel electrode portion extending to the TFT region covers the ohmic contact layer under the drain, and the portion is formed at On the gate insulating layer;
  • Forming a conductive channel by etching an ohmic contact layer on a substrate forming a source and a drain, the length of the conductive channel being less than a distance between the source and the drain;
  • a passivation layer is formed on the substrate on which the conductive channel is formed.
  • the structure of the array substrate shown in FIG. 3 is taken as an example, and the preparation process includes the following steps.
  • a pattern including the gate electrode 21 is formed on the glass substrate 1.
  • the process includes deposition, gluing, mask exposure, etching, and lift-off. The steps in the process may be the same as in the prior art, and will not be described herein.
  • a gate insulating layer 22 is deposited on the substrate on which the above pattern is formed.
  • An active layer 23 (amorphous silicon) and an ohmic contact layer 24 are deposited on the substrate on which the gate insulating layer 22 is formed, and the process includes plasma enhanced chemical vapor deposition (PECVD), etc., followed by coating, mask exposure, Etching, peeling, etc. to form a pattern of the active layer and the ohmic contact layer, as shown in FIG. 5, is a schematic cross-sectional structure after completion of this step.
  • PECVD plasma enhanced chemical vapor deposition
  • a pattern including a source and a drain is formed on the substrate on which the pixel electrode 3 is formed, in which a metal layer 5 of a source and a drain and a data line (not shown) is first deposited, and a photoresist 6 is used for coating and After the mask is exposed, a structure as shown in FIG. 7 is formed, and then a pattern of data lines (not shown), a source 25 and a drain 26 are formed by etching, as shown in FIG. It can be dry etching or wet etching, and the method is not limited.
  • the conductive channel 27 is formed by etching the ohmic contact layer 24, as shown in FIG. 9, wherein the length of the conductive channel 27 is smaller than the source 25 and the drain.
  • the length of the conductive channel formed by the pole is the length of the conductive channel formed by the pole.
  • the pixel electrode can be used as an etch barrier during the etching process, so that the ohmic contact layer covering the pixel electrode and the pixel electrode cannot be engraved.
  • the ohmic contact layer which is not covered by the pixel electrode and is not protected by the photoresist, is etched, thus forming a conductive channel smaller than the distance between the source and the drain.
  • a passivation layer 4 is deposited on the substrate on which the conductive channel 27 is formed, as shown in FIG.
  • Embodiments of the present invention provide a display panel including the above array substrate.
  • the present invention provides an array substrate, a method for fabricating the same, and a display panel.
  • the ohmic contact covered by the pixel electrode is covered during the preparation process by covering the pixel electrode portion with the ohmic contact layer under the drain.
  • the layer will not be etched, so the length of the formed conductive channel will be smaller than the conductive channel formed by the source and the drain in the prior art, thereby shortening the length of the conductive channel and improving the on-current of the TFT and The characteristics of the TFT.

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  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板及其制备方法和显示面板。该阵列基板，包括矩阵排列的像素单元，所述像素单元包括薄膜晶体管（2）和像素电极（3），所述薄膜晶体管（2）包括栅极（21）、栅绝缘层（22）、有源层（23）、欧姆接触层（24）、导电沟道（27）、源极（25）和漏极（26），其中，所述像素电极（3）延伸至薄膜晶体管（2）区域，并且延伸至薄膜晶体管（2）区域的像素电极（3）部分覆盖漏极（26）下方的欧姆接触层（24），部分形成在栅绝缘层（22）上；所述导电沟道（27）的长度小于源极（25）和漏极（26）之间的距离。通过使导电沟道（27）长度小于源极（25）和漏极（26）之间的距离，缩短了导电沟道的长度，从而提高了薄膜晶体管（2）的导通电流和特性。

Description

阵列基板及其制备方法和显示面板 技术领域
本发明的实施例涉及一种阵列基板及其制备方法和显示面板。 背景技术
目前， 在边缘场模式的液晶显示面板中， 阵列基板的结构如图 1所示， 包括横向排列的栅线 10和纵向排列的数据线 20以及由栅线 10和数据线 20 交叉形成的像素单元， 其中每一像素单元包括薄膜晶体管 （TFT )和像素电 极 3'。 具体的， 沿图 1中虚线 A-A'的阵列基板的剖面结构如图 2所示， 在玻 璃基板 1之上， 依次形成有栅极 21、 栅绝缘层 22、 像素电极 3'、 有源层 23、 欧姆接触层 24、 源极 25和漏极 26以及钝化层 4。 在源极 25与漏极 26之间 形成导电沟道 27'。 导电沟道的长宽比决定了 TFT器件的功能特性， 在沟道 的宽度一定的条件下， 减小沟道的长度有利于提高 TFT器件的开态电流， 从 而提高器件的性能。 因此， 缩短沟道的长度对于高分辨率的产品来说是非常 必要的； 且缩短沟道的长度可以减小 TFT的设计尺寸， 对于提高像素开口率 以及降低外围电路的设计尺寸 （例如， 利于窄边框）都有重要意义。 发明内容
本发明的一个实施例提供一种阵列基板， 其包括矩阵排列的像素单元， 所述像素单元包括薄膜晶体管和像素电极， 所述薄膜晶体管包括栅极、 栅绝 缘层、 有源层、 欧姆接触层、 源极、 漏极和导电沟道， 其中， 所述像素电极 延伸至薄膜晶体管区域， 并且延伸至薄膜晶体管区域的像素电极部分覆盖漏 极下方的欧姆接触层， 部分形成在栅绝缘层上； 所述导电沟道的长度小于源 极和漏极之间的距离。
本发明的另一实施例提供一种显示面板， 其包括上述阵列基板。
本发明的另一实施例提供一种阵列基板的制造方法， 其包括： 在基板上 形成包括栅极的图案； 在形成有上述图案的基板上形成栅绝缘层； 在形成有 栅绝缘层的基板上形成有源层和欧姆接触层； 在形成有有源层和欧姆接触层 的基板上形成像素电极， 其中， 所述像素电极延伸至 TFT区域， 并且延伸至 TFT区域的像素电极部分覆盖漏极下方的欧姆接触层， 部分形成在栅绝缘层 上； 在形成有像素电极的基板上形成包括源极和漏极的图案； 在形成有源极 和漏极的基板上通过刻蚀欧姆接触层形成导电沟道， 所述导电沟道的长度小 于源极和漏极之间的距离； 以及在形成有导电沟道的基板上形成钝化层。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 筒单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术中阵列基板的俯视平面示意图；
图 2为图 1所示的阵列基板中 TFT的细节结构示意图；
图 3为本发明实施例提供的一种阵列基板中 TFT的结构示意图； 图 4为本发明实施例提供的一种阵列基板的俯视平面结构示意图； 图 5为制备图 3所示的 TFT的过程中形成有源层后的结构示意图； 图 6为在图 5所示结构的基板上形成像素电极后的结构示意图； 图 7为在图 6所示结构的基板上形成金属层并且进行掩膜曝光后的结构 示意图；
图 8为在图 7所示结构的基板上形成漏极和源极后的结构示意图； 图 9为在图 8所示结构的基板上形成导电沟道后的示意图； 以及 图 10为在图 9所示结构的基板上形成钝化层后的结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例提供了一种阵列基板及其制备方法和显示面板， 用以减小 TFT的导电沟道的长度， 提高 TFT的导通电流和 TFT特性， 进而提高显示 效果。
下面结合附图和示例性实施例对本发明进行详细说明。
本发明实施例提供了一种阵列基板，图 3为所述阵列基板的结构剖面图， 图 4为所述阵列基板的平面俯视图，且图 3为沿图 4中虚线 A-A'方向的剖面 图。 所述阵列基板可以包括矩阵排列的像素单元， 所述像素单元包括公共电 极、 薄膜晶体管 （TFT )和像素电极。 如图 3所示， 所述阵列基板包括玻璃 基板 1、形成在玻璃基板 1之上的 TFT 2和像素电极 3以及形成在所述 TFT 2 和像素电极 3之上的钝化层 4, 所述 TFT 2包括栅极 21、 栅绝缘层 22、 有源 层 23、 欧姆接触层 24、 源极 25和漏极 26。 所述像素电极 3延伸至 TFT区 域， 并且延伸至 TFT区域的像素电极 3部分覆盖漏极 26下方的欧姆接触层 24, 部分形成在栅绝缘层上 22。 所述阵列基板还包括形成于源极 25与漏极 26之间的导电沟道 27 , 所述导电沟道 27是通过刻蚀欧姆接触层 24形成的， 其长度等于像素电极 3和源极 25之间的距离，且该长度小于源极和漏极之间 的 巨离。
在本发明实施例中， 所述导电沟道 27的长度小于 4μηι。 现有技术中， 一般的， 当漏极和源极形成之后， 导电沟道即形成， 因此现有技术中导电沟 道的长度一般即为源极和漏极之间的距离， 且一般大于 4μηι。
在本发明实施例中， 例如， 所述导电沟道 27的长度为 2.5μηι。 本发明实 施例通过像素电极将部分欧姆接触层覆盖， 从而在后续刻蚀的过程中像素电 极保护了部分欧姆接触层不被刻蚀， 进而可以获得长度小于漏极和源极之间 的距离的导电沟道。在本发明实施例中， 通常可以获得长度小于 4μηι的导电 沟道， 但考虑到对位精度的叠层效果， 导电沟道的长度不可过短， 例如， 可 以形成长度为 2.5μηι的导电沟道。
在本发明实施例中， 所述阵列基板还包括交叉设置的数据线和栅线， 其 中数据线和栅线围设形成矩阵排列的像素单元。 例如， 如图 4所示的平面结 构示意图， 栅线 10沿第一方向排列， 数据线 20沿第二方向排列， 每两栅线 10和每两数据线 20交叉形成一像素单元。 图中的像素电极 3延伸至 TFT的 欧姆接触层（图中未示出） ， 图中所示像素电极 3 的边缘即为导电沟道 27 的边界。
需要说明的是， 在本发明实施例中， 欧姆接触层与漏极通过像素电极电 性连接， 由此引起的电阻及电容的改变并不会影响 TFT的特性； 同时， 像素 电极的厚度可以与现有技术中相同， 在此情况下， 由于像素电极的厚度相对 于 TFT较小，因此对 TFT的源极和漏极高度的一致性的影响并不会减弱 TFT 的特性， 并且， 由于 TFT之上钝化层的保护， 也不会对面板的均匀性造成影 响。
下面结合附图详细说明本发明实施例提供的阵列基板的制备方法， 同时 进一步说明本发明实施例提供的阵列基板的结构。
本发明实施例提供了一种阵列基板的制备方法， 其包括：
在基板上形成包括栅极的图案；
在形成有上述图案的基板上形成栅绝缘层；
在形成有栅绝缘层的基板上形成有源层和欧姆接触层；
在形成有有源层和欧姆接触层的基板上形成像素电极层， 其中， 所述像 素电极延伸至 TFT区域， 并且延伸至 TFT区域的像素电极部分覆盖漏极下 方的欧姆接触层， 部分形成在栅绝缘层上；
在形成有像素电极层的基板上形成包括源极和漏极的图案；
在形成有源极和漏极的基板上通过刻蚀欧姆接触层形成导电沟道， 所述 导电沟道的长度小于源极和漏极之间的距离； 以及
在形成有导电沟道的基板上形成钝化层。
在本发明实施例中， 以图 3所示的阵列基板的结构为例， 其制备过程包 括如下步骤。
在玻璃基板 1上形成包括栅极 21的图案， 其工艺包括沉积、涂胶、掩膜 曝光、刻蚀和剥离， 该过程中的步骤可以与现有技术中相同， 在此不再赘述。
在形成有上述图案的基板上沉积形成栅绝缘层 22。
在形成有栅绝缘层 22的基板上沉积形成有源层 23 (非晶硅）和欧姆接 触层 24, 其工艺包括等离子体增强化学气相沉积（PECVD )等， 再经过涂 胶、 掩膜曝光、 刻蚀和剥离等来形成有源层和欧姆接触层的图案， 如图 5所 示， 为完成此步骤后的剖面结构示意图。
在形成有有源层 23和欧姆接触层 24的基板上形成像素电极 3的图案， 其工艺同样包括沉积、 涂胶、 掩膜曝光、 刻蚀和剥离， 其中像素电极的材料 为氧化铟锡或氧化铟辞等透明导电材料， 所述像素电极 3延伸至 TFT区域， 并且延伸至 TFT区域的像素电极部分覆盖漏极 26下方的欧姆接触层 24 , 部 分形成在栅绝缘层上 22, 如图 6所示。
在形成有像素电极 3的基板上形成包括源极和漏极的图案， 其中首先沉 积源极和漏极以及数据线（图中未示出） 的金属层 5 , 采用光阻剂 6涂胶和 掩膜曝光后， 形成如图 7所示的结构， 然后通过刻蚀形成数据线（图中未示 出） 、 源极 25和漏极 26的图案， 如图 8所示， 其中刻蚀的方法可以为干法 刻蚀或湿法刻蚀， 方法不做限定。
在形成有源极 25和漏极 26的图案的基板上， 通过刻蚀欧姆接触层 24 而形成导电沟道 27, 如图 9所示， 其中导电沟道 27的长度小于源极 25和漏 极 26之间的距离， 即图 9中所示， 像素电极 3的边缘相对于漏极 25的边缘 凸出至导电沟道， 因此形成的导电沟道的长度小于现有技术中由源极和漏极 形成的导电沟道的长度。 在此步骤中， 由于像素电极的材料与欧姆接触层的 材料不同， 因此在刻蚀的过程中， 像素电极可以用作刻蚀阻挡层， 使得不能 将像素电极以及像素电极覆盖的欧姆接触层刻蚀， 而没有被像素电极覆盖并 且没有被光阻剂保护的欧姆接触层被刻蚀， 因此形成了小于源极和漏极的距 离的导电沟道。
将光阻剂剥离后，在形成有导电沟道 27的基板上沉积钝化层 4,如图 10 所示。
本发明实施例提供了一种显示面板， 其包括上述的阵列基板。
综上所述,本发明实施例提供的一种阵列基板及其制备方法和显示面板， 通过将像素电极部分覆盖漏极下方的欧姆接触层， 在制备的过程中， 由像素 电极覆盖的欧姆接触层将不能被刻蚀， 因此形成的导电沟道的长度将小于现 有技术中由源极和漏极形成的导电沟道， 从而缩短了导电沟道的长度， 提高 了 TFT的导通电流和 TFT的特性。
以上实施例仅用以说明本发明的技术方案， 而非对其限制； 尽管参照前 述实施例对本发明进行了详细的说明， 本领域的普通技术人员应当理解： 其 依然可以对前述各实施例所记载的技术方案进行修改， 或者对其中部分技术 特征进行等同替换； 而这些修改或者替换， 并不使相应技术方案的本质脱离 本发明各实施例技术方案的精神和范围。

Claims

权利要求书
1、一种阵列基板， 包括矩阵排列的像素单元， 所述像素单元包括薄膜晶 体管和像素电极， 所述薄膜晶体管包括栅极、 栅绝缘层、 有源层、 欧姆接触 层、 源极、 漏极和导电沟道， 其中， 所述像素电极延伸至薄膜晶体管区域， 并且延伸至薄膜晶体管区域的像素电极部分覆盖漏极下方的欧姆接触层， 部 分形成在栅绝缘层上； 所述导电沟道的长度小于源极和漏极之间的距离。
2、 根据权利要求 1 所述的阵列基板， 其中， 所述导电沟道的长度小于 4μηι。
3、根据权利要求 1所述的阵列基板,其中，所述导电沟道的长度为 2.5μηι。
4、 根据权利要求 1~3 中任一权利要求所述的阵列基板， 还包括交叉设 置的数据线和栅线， 其中数据线和栅线围设形成矩阵排列的像素单元。
5、 一种显示面板， 包括权利要求 1~4中任一权利要求所述的阵列基板。
6、 一种阵列基板的制备方法， 包括：
在基板上形成包括栅极的图案；
在形成有上述图案的基板上形成栅绝缘层；
在形成有栅绝缘层的基板上形成有源层和欧姆接触层；
在形成有有源层和欧姆接触层的基板上形成像素电极， 其中， 所述像素 电极延伸至 TFT区域， 并且延伸至 TFT区域的像素电极部分覆盖漏极下方 的欧姆接触层， 部分形成在栅绝缘层上；
在形成有像素电极的基板上形成包括源极和漏极的图案；
在形成有源极和漏极的基板上通过刻蚀欧姆接触层形成导电沟道， 所述 导电沟道的长度小于源极和漏极之间的距离； 以及
在形成有导电沟道的基板上形成钝化层。
7、根据权利要求 6所述的阵列基板的制备方法， 其中，在通过刻蚀欧姆 接触层形成导电沟道期间， 所述像素电极用作蚀刻阻挡层， 使得被像素电极 覆盖的部分欧姆接触层没有被刻蚀。
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