WO2014125894A1 - 積層回路基板 - Google Patents
積層回路基板 Download PDFInfo
- Publication number
- WO2014125894A1 WO2014125894A1 PCT/JP2014/051455 JP2014051455W WO2014125894A1 WO 2014125894 A1 WO2014125894 A1 WO 2014125894A1 JP 2014051455 W JP2014051455 W JP 2014051455W WO 2014125894 A1 WO2014125894 A1 WO 2014125894A1
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- main surface
- circuit board
- conductor patterns
- conductor pattern
- conductor
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- 239000000758 substrate Substances 0.000 title abstract 3
- 239000003990 capacitor Substances 0.000 claims abstract description 44
- 229920005992 thermoplastic resin Polymers 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 13
- 238000007788 roughening Methods 0.000 claims abstract description 13
- 239000004020 conductor Substances 0.000 claims description 252
- 230000003746 surface roughness Effects 0.000 claims description 66
- 239000002184 metal Substances 0.000 claims description 30
- 229910052751 metal Inorganic materials 0.000 claims description 30
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- 229920000106 Liquid crystal polymer Polymers 0.000 description 2
- 239000004977 Liquid-crystal polymers (LCPs) Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
- H01G2/02—Mountings
- H01G2/06—Mountings specially adapted for mounting on a printed-circuit support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/40—Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
- H05K3/4617—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0104—Properties and characteristics in general
- H05K2201/0129—Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0355—Metal foils
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09509—Blind vias, i.e. vias having one side closed
- H05K2201/09527—Inverse blind vias, i.e. bottoms outwards in multilayer PCB; Blind vias in centre of PCB having opposed bottoms
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/09672—Superposed layout, i.e. in different planes
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/097—Alternating conductors, e.g. alternating different shaped pads, twisted pairs; Alternating components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0278—Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0307—Providing micro- or nanometer scale roughness on a metal surface, e.g. by plating of nodules or dendrites
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
- H05K3/383—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by microetching
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4632—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating thermoplastic or uncured resin sheets comprising printed circuits without added adhesive materials between the sheets
Definitions
- the present invention relates to a laminated circuit board configured by laminating a plurality of thermoplastic resin layers.
- Patent Document 1 discloses a laminated circuit board mounted on a communication device such as a smartphone or a mobile phone.
- the laminated circuit board of Patent Document 1 is manufactured as follows. First, the metal film is etched on a sheet having a metal film attached to one side. Thereby, the conductor pattern of the capacitor and the conductor pattern of the coil are formed.
- the sheet is made of a thermoplastic resin. And a some sheet
- the multilayer circuit board which equips an inside with a capacitor
- thermoplastic resin softens and flows due to heat and pressure during thermocompression bonding. Therefore, in the laminated circuit board of Patent Document 1, the thermoplastic resin between the conductor patterns constituting the capacitor and coil flows in a large amount to the outside between the conductor patterns during thermocompression bonding, and the conductors facing each other with the thermoplastic resin layer interposed therebetween. The distance between patterns may be displaced.
- an object of the present invention is to provide a laminated circuit board capable of suppressing changes in element values even when a laminated circuit board is manufactured by laminating a thermoplastic resin layer and thermocompression bonding.
- the laminated circuit board of the present invention has the following configuration in order to solve the above problems.
- the first and second conductor patterns constitute capacitors and coils, for example.
- the resin flow between the first and second conductor patterns is the first main surface and the second main surface. Blocked by the main face. Therefore, at the time of this thermocompression bonding, the resin between the first and second conductor patterns does not flow so much to the outside between the first and second conductor patterns.
- the capacitance between the first and second conductor patterns does not easily change.
- the stray capacitance or the line-to-line capacitance between the conductor patterns does not easily change.
- the surface roughness of the first main surface is larger than the surface roughness of the third main surface on the side opposite to the second conductor pattern in the first conductor pattern.
- the flow amount of the resin near the first main surface is smaller than the flow amount of the resin near the third main surface. Therefore, at the time of thermocompression bonding, the flow amount of the resin in the vicinity of the first main surface is further reduced, and the first conductor pattern can be further suppressed from approaching the second conductor pattern. That is, it can be further suppressed that the distance between the first and second conductor patterns changes and the element value changes.
- the surface roughness of the second main surface is larger than the surface roughness of the fourth main surface on the opposite side to the first conductor pattern in the second conductor pattern.
- the flow amount of the resin near the second main surface is smaller than the flow amount of the resin near the fourth main surface. Therefore, at the time of thermocompression bonding, the flow amount of the resin near the second main surface is further reduced, and the second conductor pattern can be further suppressed from approaching the first conductor pattern. That is, it can be further suppressed that the distance between the first and second conductor patterns changes and the element value changes.
- each of the first and second conductor patterns is obtained by patterning a metal film provided on the surface of the thermoplastic resin layer.
- the surface roughness of the first main surface is substantially the same as the surface roughness of the second main surface.
- the flow amount of the resin near the first main surface and the flow amount of the resin near the second main surface are the same. Therefore, at the time of thermocompression bonding, it can be suppressed that one of the first and second conductor patterns approaches the other. That is, it can be further suppressed that the distance between the first and second conductor patterns changes and the element value changes.
- the area of the first main surface is substantially the same as the area of the second main surface.
- thermocompression bonding since the areas of the first and second main surfaces are the same, the non-opposing regions cannot be formed. Therefore, at the time of thermocompression bonding, it can suppress that the said area
- the first and second conductor patterns constitute capacitors, for example.
- a via-hole conductor is formed around the first and second conductor patterns in the thermoplastic resin layer.
- thermocompression bonding when a thermoplastic resin layer is laminated and thermocompression bonded, the resin flow between the first and second conductor patterns is hindered by the via-hole conductor. Therefore, at the time of thermocompression bonding, it can be suppressed that one of the first and second conductor patterns approaches the other. That is, it can be further suppressed that the distance between the first and second conductor patterns changes and the element value changes.
- the first and second conductor patterns constitute a capacitor.
- the first and second conductor patterns constitute an inductor.
- the first conductor pattern constitutes an inductor
- the second conductor pattern constitutes a ground
- FIG. 1 is an external view of a multilayer circuit board 101 according to a first embodiment of the present invention.
- FIG. 2 is a cross-sectional view taken along the line PP in FIG. 1. It is sectional drawing which shows the manufacturing method of the laminated circuit board 101 shown in FIG. It is sectional drawing which shows the manufacturing method of the laminated circuit board 101 shown in FIG.
- FIG. 5A is an enlarged cross-sectional view of a portion that becomes the capacitor C1 shown in FIG.
- FIG. 5B is an enlarged cross-sectional view showing a state in which a portion to be the capacitor C1 is thermocompression bonded. It is sectional drawing which shows the manufacturing method of the laminated circuit board 201 which concerns on 2nd Embodiment of this invention.
- FIG. 1 is an external view of a multilayer circuit board 101 according to a first embodiment of the present invention.
- FIG. 2 is a cross-sectional view taken along the line PP in FIG. 1. It is sectional drawing which shows the manufacturing method of the laminated circuit
- FIG. 7A is an enlarged cross-sectional view of a portion that becomes the capacitor C2 shown in FIG.
- FIG. 7B is an enlarged cross-sectional view showing a state in which a portion to be the capacitor C2 is thermocompression bonded.
- FIG. 8A is an enlarged cross-sectional view of a portion that becomes a capacitor C3 according to a modification of the capacitor C2 shown in FIG.
- FIG. 8B is an enlarged cross-sectional view showing a state in which a portion to be the capacitor C3 is thermocompression bonded.
- It is sectional drawing which shows the manufacturing method of the multilayer circuit board 301 which concerns on 3rd Embodiment of this invention. It is a front view of the principal part of the sheet
- FIG. 12A is an enlarged cross-sectional view of a portion that becomes the capacitor C1 shown in FIG.
- FIG. 12B is an enlarged cross-sectional view showing a state where a portion to be the capacitor C1 shown in FIG. 9 is thermocompression bonded.
- FIG. 14A is an enlarged cross-sectional view of a portion that becomes the coil L2 shown in FIG.
- FIG. 14B is an enlarged cross-sectional view showing a state in which a portion to be the coil L2 is thermocompression bonded.
- FIG. 16A is an enlarged cross-sectional view of a portion that becomes the coil L3 shown in FIG.
- FIG. 16B is an enlarged cross-sectional view showing a state in which a portion to be the coil L3 is thermocompression bonded.
- FIG. 18A is an enlarged cross-sectional view of a portion that becomes the coil L4 shown in FIG.
- FIG. 18B is an enlarged cross-sectional view showing a state where the portion to be the coil L4 is thermocompression bonded.
- FIG. 1 is an external view of the multilayer circuit board 101 according to the first embodiment of the present invention.
- 2 is a cross-sectional view taken along the line PP in FIG.
- the surface mounted on the multilayer circuit board 101 is referred to as a main surface Z1.
- the surface opposite to the main surface Z1 of the multilayer circuit board 101 is referred to as a main surface Z2.
- the laminated circuit board 101 includes a capacitor C1, a coil L1, mounting lands 121, 122, 131, 132, and 133, and external connection terminals 31A and 31B.
- the laminated circuit board 101 has a surface mount type configuration.
- the laminated circuit board 101 is a laminated body formed by laminating a plurality of thermoplastic resin sheets 11 to 15 on which conductor patterns are formed. Each of the sheets 11 to 15 has a predetermined dielectric constant.
- the capacitor C1 includes a planar first conductor pattern 32A and a planar second conductor pattern 33A.
- the coil L1 includes linear conductor patterns 33B, 33C, 33D, 33E, 34A, 34B, 34C, 34D and a via-hole conductor 44.
- the conductor patterns 33B, 33C, 33D, 33E, 34A, 34B, 34C, and 34D are provided so as to overlap in a loop shape when viewed from the stacking direction of the stacked circuit board 101.
- the conductor pattern 33C of the coil L1 is connected to the conductor pattern 32B via the via-hole conductors 43 and 42.
- External connection terminals 31A and 31B are formed on the main surface Z1 of the laminated circuit board 101.
- the external connection terminals 31A and 31B are connected to electrodes such as a printed wiring board (not shown).
- the mounting lands 121, 122, 131, 132, 133 are formed on the main surface Z2 of the laminated circuit board 101.
- the mounting component 120 is mounted on the mounting lands 121 and 122.
- the mounting component 130 is mounted on the mounting lands 131, 132, and 133.
- mounting lands 131, 132, and 133 are illustrated as mounting lands, a larger number of mounting lands may be arranged on the main surface Z2.
- FIG. 3 and 4 are cross-sectional views showing a method for manufacturing the laminated circuit board 101 shown in FIG.
- FIG. 5A is an enlarged cross-sectional view of a portion that becomes the capacitor C1 shown in FIG.
- FIG. 5B is an enlarged cross-sectional view illustrating a state in which a portion to be the capacitor C1 illustrated in FIG.
- the multilayer circuit board 101 is manufactured by providing a portion to be a large number of multilayer circuit boards 101 on the sheet, forming a plurality of multilayer circuit boards 101 at a time, and then cutting out each of the multilayer circuit boards 101.
- sheets 11 to 15 are prepared.
- the outer shape of each of the sheets 11 to 15 when viewed from the front in the stacking direction is rectangular.
- the sheet 11 includes a thermoplastic resin layer 21 and a metal film 31.
- the metal film 31 is affixed to the main surface of the thermoplastic resin layer 21 on the main surface Z1 side.
- the sheet 12 includes a thermoplastic resin layer 22 and a metal film 32.
- the metal film 32 is affixed to the main surface of the thermoplastic resin layer 22 on the main surface Z1 side.
- the sheet 13 includes a thermoplastic resin layer 23 and a metal film 33.
- the metal film 33 is attached to the main surface of the thermoplastic resin layer 23 on the main surface Z2 side.
- the sheet 14 includes a thermoplastic resin layer 24 and a metal film 34.
- the metal film 34 is affixed to the main surface of the thermoplastic resin layer 24 on the main surface Z2 side.
- the sheet 15 includes a thermoplastic resin layer 25 and a metal film 35.
- the metal film 35 is affixed to the main surface of the thermoplastic resin layer 25 on the main surface Z2 side.
- the metal film is fixed by the anchor effect. That is, of the two main surfaces of the metal film, the surface fixed to the sheet is a roughened surface (mat surface), and the opposite surface is a glossy surface (shiny surface).
- the material of the thermoplastic resin layers 21 to 25 is, for example, a liquid crystal polymer.
- the material of the metal films 31 to 35 is, for example, copper which is a metal foil.
- a heat-resistant and flexible thermoplastic resin such as thermoplastic polyimide can be used.
- metal films 31 to 35 metal foil such as silver can be used in addition to copper.
- the sheet 12 is a sheet in which the main surface on the main surface Z2 side of the metal film 32 is subjected to a roughening process in advance.
- the main surface on the main surface Z2 side in the metal film 32 is a surface including a first main surface 91 described later.
- the sheet 13 is a sheet in which the main surface on the main surface Z1 side of the metal film 33 is subjected to a roughening process in advance.
- the main surface on the main surface Z1 side in the metal film 33 is a surface including a second main surface 92 described later.
- the metal films 31 to 35 of the sheets 11 to 15 are patterned by etching or the like.
- 33C, 33D, 33E, 34A, 34B, 34C, and 34D are formed.
- wiring conductors for connecting these conductor patterns 32A, 33A, 33B, 33C, 33D, 33E, 34A, 34B, 34C, and 34D are formed at the same time.
- the area of the first main surface 91 facing the second conductor pattern 33A in the first conductor pattern 32A is the same as the area of the second main surface 92 facing the first conductor pattern 32A in the second conductor pattern 33A or It is substantially the same.
- the metal films 32 to 34 do not penetrate the thermoplastic resin layers 22 to 24 of the sheets 12 to 14 by laser or the like, but the thermoplastic resin layers 22 to 24 have through holes that penetrate.
- the through hole is filled with a conductive material such as a conductive paste mainly composed of silver and tin.
- the sheets 11 to 15 are laminated, and are pressure-bonded while being heated at a temperature of, for example, 300 ° C. using a jig 90 such as a press plate from the vertical direction of the lamination direction.
- a jig 90 such as a press plate from the vertical direction of the lamination direction.
- the sheets 11 to 15 are softened and flown and integrated, and the conductive paste filled in the through holes is metalized (sintered).
- the laminated circuit board 101 including the capacitor C1 and the coil L1 therein is manufactured.
- the capacitor C1 includes a first conductor pattern 32A and a second conductor pattern 33A that are opposed to each other with the thermoplastic resin layers 22 and 23 therebetween.
- the mounting components 120 and 130 are mounted on the mounting lands 121, 122, 131, 132, and 133 of the multilayer circuit board 101 (see FIGS. 1 and 2).
- the laminated circuit board 101 is mounted on a printed wiring board (not shown), and the external connection terminals 31A and 31B are connected to the electrodes of the printed wiring board.
- thermoplastic resins of the sheets 11 to 15 are softened and flowed by heat and pressure during thermocompression bonding, and are integrated without using an adhesive layer such as a bonding sheet or prepreg. Therefore, also in the laminated circuit board 101, the thermoplastic resin between the first conductor pattern 32A and the second conductor pattern 33A constituting the capacitor C1 is moved outside between the first conductor pattern 32A and the second conductor pattern 33A during thermocompression bonding. To flow.
- the first main surface 91 facing the second conductor pattern 33A in the first conductor pattern 32A is roughened (see FIG. 5A).
- the roughening process is also performed on the second main surface 92 of the second conductor pattern 33A facing the first conductor pattern 32A (see FIG. 5A).
- the roughening process is, for example, etching.
- the surface roughness of the first main surface 91 is larger than the surface roughness of the third main surface 93 opposite to the second conductor pattern 33A in the first conductor pattern 32A. Further, the surface roughness of the second main surface 92 is also larger than the surface roughness of the fourth main surface 94 on the opposite side of the first conductor pattern 32A in the second conductor pattern 33A.
- the surface roughness of the first main surface 91 is, for example, about 1.3 to 15 ⁇ m, and is 2.7 ⁇ m in this embodiment.
- the surface roughness of the first major surface 91 is the same as or substantially the same as the surface roughness of the second major surface 92.
- the maximum height roughness [Rz] defined by [JIS B 0601-2001] is adopted.
- the surface roughness of the third main surface 93 and the fourth main surface 94 is, for example, about 0.1 to 3 ⁇ m, and in the present embodiment is 1.5 ⁇ m.
- the flow amount of resin near the 1st main surface 91 is smaller than the flow amount of resin near the 3rd main surface 93.
- the surface roughness of the second main surface 92 is also larger than the surface roughness of the fourth main surface 94, the flow amount of the resin near the second main surface 92 is smaller than the flow amount of the resin near the fourth main surface 94.
- the size of the arrow shown in FIG. 5B represents the amount of resin flow.
- the flow rate of the resin near the third main surface 93 and the resin near the fourth main surface 94 is larger than the flow rate of the resin near the first main surface 91 and the resin near the second main surface 92, the first main surface The resin near 91 and the resin near the second main surface 92 are less likely to flow to the outside between the first and second conductor patterns 32A and 33A.
- the capacitance between the first and second conductor patterns 32A and 33A does not easily change. That is, when manufacturing the laminated circuit board 101 by thermocompression bonding, the designed distance G and capacitance between the first and second conductor patterns 32A and 33A can be realized almost accurately.
- the element value (capacitance in this embodiment) of the capacitor C1 does not easily change even if the temperature and pressure applied between the first and second conductor patterns 32A and 33A change slightly during thermocompression bonding.
- the laminated circuit board 101 even if the laminated circuit board 101 is manufactured by laminating the sheets 11 to 15 and thermocompression bonding, the change in the element value can be suppressed. Therefore, according to the laminated circuit board 101, it is possible to easily form the capacitor C1 having a highly accurate element value (capacitance in this embodiment) with little individual difference between element values.
- the surface roughness of the first main surface 91 is the same as the surface roughness of the second main surface 92. Therefore, the flow amount of the resin near the first main surface 91 and the flow amount of the resin near the second main surface 92 are the same. Therefore, at the time of thermocompression bonding, it is possible to suppress the end portion of one of the first and second conductor patterns 32A and 33A from approaching the other conductor pattern from the central portion located inside the end portion. That is, it can be further suppressed that the distance between the first and second conductor patterns 32A and 33A changes and the element value changes.
- the second main surface 92 when the area of the second main surface 92 is larger than the area of the first main surface 91, a region that does not face the first conductor pattern 32A is formed in the second conductor pattern.
- the area of the first main surface 91 is larger than the area of the second main surface 92, a region that does not face the second conductor pattern 33A is formed in the first conductor pattern 32A.
- the non-opposing region of any one of the first and second conductor patterns 32A and 33A is caused by the flow of the resin depending on the temperature and pressure applied between the first and second conductor patterns 32A and 33A during thermocompression bonding. It is also possible to displace to.
- the laminated circuit board 101 since the areas of the first and second main surfaces 91 and 92 are the same as described above, the non-opposing regions cannot be formed. Therefore, at the time of thermocompression bonding, it is possible to suppress displacement of one of the first and second conductor patterns 32A and 33A to the other side due to the flow of resin. That is, it can be further suppressed that the distance G between the first and second conductor patterns 32A and 33A changes and the element value changes.
- FIG. 6 is a cross-sectional view showing a method for manufacturing the laminated circuit board 201 according to the second embodiment of the present invention.
- FIG. 7A is an enlarged cross-sectional view of a portion that becomes the capacitor C2 shown in FIG.
- FIG. 7B is an enlarged cross-sectional view showing a state in which a portion to be the capacitor C2 is thermocompression bonded.
- the multilayer circuit board 201 according to the second embodiment is different from the multilayer circuit board 101 according to the first embodiment in that a capacitor C2 and sheets 211, 212, and 214 are provided instead of the capacitor C1 and sheets 11 to 14. is there.
- the sheet 212 is provided with a via-hole conductor 242 instead of the via-hole conductors 42 and 43 of the sheets 12 and 13. Since the configuration of the other laminated circuit board 201 is the same as that of the laminated circuit board 101, description thereof is omitted. Since the manufacturing method of the laminated circuit board 201 is also the same as the manufacturing method of the laminated circuit board 101, description thereof is omitted.
- the first main surface 91 facing the second conductor pattern 233A in the first conductor pattern 232A is roughened (see FIG. 7A).
- the second main surface 92 facing the first conductor pattern 232A in the second conductor pattern 233A is also subjected to a roughening process (see FIG. 7A).
- the third main surface 293 of the first conductor pattern 232A opposite to the second conductor pattern 233A is subjected to a roughening process (see FIG. 7A).
- the fourth conductor surface 294 of the second conductor pattern 233A opposite to the first conductor pattern 232A is roughened (see FIG. 7A).
- the surface roughness of the first main surface 91 is larger than the surface roughness of the third main surface 293 on the side opposite to the second conductor pattern 233A in the first conductor pattern 232A. Further, the surface roughness of the second main surface 92 is also larger than the surface roughness of the fourth main surface 294 on the opposite side of the first conductor pattern 232A in the second conductor pattern 233A.
- the surface roughness of the first main surface 91 and the second main surface 92 is, for example, about 1.3 to 15 ⁇ m.
- the surface roughness of the third main surface 293 and the fourth main surface 294 is a surface of about 0.1 to 3 ⁇ m, for example.
- first main surface 91 and the second main surface 92 are also rough in the multilayer circuit board 201, when the sheets 211, 212, 214, and 15 are stacked and thermocompression bonded, the first and second conductor patterns 232A, The flow of the resin between 233A is blocked by the first main surface 91 and the second main surface 92. Therefore, at the time of this thermocompression bonding, the resin between the first and second conductor patterns 232A and 233A does not flow so much to the outside between the first and second conductor patterns 232A and 233A (see the arrow in FIG. 7B).
- the flow amount of resin near the 1st main surface 91 is smaller than the flow amount of resin near the 3rd main surface 293.
- the surface roughness of the second main surface 92 is also larger than the surface roughness of the fourth main surface 294, the flow amount of the resin near the second main surface 92 is smaller than the flow amount of the resin near the fourth main surface 294.
- the size of the arrow shown in FIG. 7B represents the amount of resin flow.
- the flow rate of the resin near the third main surface 293 is the resin near the third main surface 93. Is less than the flow rate.
- the surface roughness of the fourth main surface 294 is also larger than the surface roughness of the fourth main surface 94 shown in FIG. 5, the flow rate of the resin near the fourth main surface 294 is that of the resin near the fourth main surface 94. Smaller than flow rate.
- the first main surface The resin in the vicinity of 291 and the resin in the vicinity of the second main surface 292 are less likely to flow to the outside between the first and second conductor patterns 232A and 233A.
- the distance G between the first and second conductor patterns 232A and 233A constituting the capacitor C2 can be suppressed, the distance between the first and second conductor patterns 232A and 233A is suppressed.
- the capacity does not change easily. That is, when the laminated circuit board 201 is manufactured by thermocompression bonding, the designed distance G and capacitance between the first and second conductor patterns 232A and 233A can be realized almost accurately.
- the laminated circuit board 201 the same effects as the laminated circuit board 101 can be obtained.
- the area of the first main surface 91 is the same as the area of the second main surface 92, but is not limited thereto.
- a conductor pattern 282 ⁇ / b> A having an area of the first main surface 91 smaller than that of the second main surface 92 may be formed on the sheet 211.
- FIG. 9 is a cross-sectional view showing a method of manufacturing the multilayer circuit board 301 according to the third embodiment of the present invention.
- FIG. 10 is a front view of the sheet 13 in which only the main part of the sheet 13 shown in FIG. 9 is viewed from the main surface Z2 side.
- FIG. 11 is a front view of the sheet 12 when only the main part of the sheet 12 shown in FIG. 9 is viewed from the main surface Z1 side.
- FIG. 12A is an enlarged cross-sectional view of a portion that becomes the capacitor C1 shown in FIG.
- FIG. 12B is an enlarged cross-sectional view showing a state where a portion to be the capacitor C1 shown in FIG. 9 is thermocompression bonded.
- the multilayer circuit board 301 according to the third embodiment is different from the multilayer circuit board 101 according to the first embodiment in that via-hole conductors 342A to 342J, 343A to 343J and a conductor pattern 332A are disposed around the capacitor C1 in the sheets 12 and 13. 332J, 333A to 333J. Since the other configuration of the multilayer circuit board 301 is the same as that of the multilayer circuit board 101, the description thereof is omitted. Further, the manufacturing method of the laminated circuit board 301 is also the same as the manufacturing method of the laminated circuit board 101, and thus the description thereof is omitted.
- the resin flow between the first and second conductor patterns 32A and 33B is hindered by the via-hole conductors 342A to 342J and 343A to 343J. Therefore, at the time of thermocompression bonding, it can be suppressed that one of the first and second conductor patterns 32A and 33B approaches the other. That is, it can be further suppressed that the distance between the first and second conductor patterns 32A and 33B changes and the element value changes.
- FIG. 13 is a cross-sectional view showing a method for manufacturing a laminated circuit board 401 according to the fourth embodiment of the present invention.
- FIG. 14A is an enlarged cross-sectional view of a portion that becomes the coil L2 shown in FIG.
- FIG. 14B is an enlarged cross-sectional view showing a state in which a portion to be the coil L2 is thermocompression bonded.
- the laminated circuit board 401 according to the fourth embodiment is different from the laminated circuit board 101 according to the first embodiment in that a coil L2 and sheets 412 to 414 are provided instead of the coil L1 and sheets 12 to 14.
- the sheet 412 is provided with a via-hole conductor 442 instead of the via-hole conductors 42 and 43 of the sheets 12 and 13. Since the other configuration of the laminated circuit board 401 is the same as that of the laminated circuit board 101, the description thereof is omitted. Further, the manufacturing method of the laminated circuit board 401 is also the same as the manufacturing method of the laminated circuit board 101, and thus the description thereof is omitted.
- the coil L2 includes conductor patterns 34A, 34B, 33B, and 33C, via-hole conductors 442 to 444, and first and second conductor patterns 433D, 433E, 434C, and 434D.
- the first main surfaces 491A and 491B facing the second conductor patterns 434C and 434D in the first conductor patterns 433D and 433E are roughened (see FIG. 14A). ).
- the second conductor surfaces 492A and 492B facing the first conductor patterns 433D and 433E in the second conductor patterns 434C and 434D are also roughened (FIG. 14A). reference).
- the surface roughness of the first main surfaces 491A and 491B is greater than the surface roughness of the third main surfaces 493A and 493B on the opposite side of the second conductor patterns 434C and 434D in the first conductor patterns 433D and 433E. It is getting bigger. Further, the surface roughness of the second main surfaces 492A and 492B is also larger than the surface roughness of the fourth main surfaces 494A and 494B on the opposite side of the first conductor patterns 433D and 433E in the second conductor patterns 434C and 434D.
- first main surface 491A and the second main surface 492A are also rough in the laminated circuit board 401, when the sheets 11, 412 to 414, 15 are laminated and thermocompression bonded, the first and second conductor patterns 433D, The flow of resin between 434C is hindered by the first main surface 491A and the second main surface 492A.
- first main surface 491B and the second main surface 492B are rough, the resin flow between the first and second conductor patterns 433E and 434D when the sheets 11, 412 to 414 and 15 are laminated and thermocompression bonded. Is blocked by the first main surface 491B and the second main surface 492B.
- the flow volume of resin of 1st main surface 491A, 491B vicinity is 3rd main surface 493A, 493B. Smaller than the flow rate of nearby resin.
- the surface roughness of the second main surfaces 492A and 492B is also larger than the surface roughness of the fourth main surfaces 494A and 494B, the amount of resin flow around the second main surfaces 492A and 492B is around the fourth main surfaces 494A and 494B. Less than the amount of resin flow.
- the size of the arrow shown in FIG. 14B represents the amount of resin flow.
- the flow rates of the resin near the third main surfaces 493A and 493B and the resin near the fourth main surfaces 494A and 494B are the flow rates of the resin near the first main surfaces 491A and 491B and the resins near the second main surfaces 492A and 492B. Therefore, the resin in the vicinity of the first main surfaces 491A and 491B and the resin in the vicinity of the second main surfaces 492A and 492B are less likely to flow to the outside between the first and second conductor patterns 433D, 433E, 434C, and 434D.
- the laminated circuit board 401 it is possible to suppress a change in the distance G between the first and second conductor patterns 433D, 433E, 434C, and 434D constituting the coil L2, and thus the first and second conductor patterns 433D,
- the line capacitance between 433E, 434C, and 434D does not change easily. That is, when the laminated circuit board 401 is manufactured by thermocompression bonding, the designed distance G and line capacitance between the first and second conductor patterns 433D, 433E, 434C, and 434D can be realized almost accurately.
- the element value (inductance in this embodiment) of the coil L2 does not easily change.
- the laminated circuit board 401 the same effects as the laminated circuit board 101 can be obtained.
- FIG. 15 is an external perspective view of the first conductor pattern 32B and the coil L3 included in the multilayer circuit board 501 according to the fifth embodiment of the present invention.
- FIG. 16A is an enlarged cross-sectional view of a portion that becomes the coil L3 shown in FIG.
- FIG. 16B is an enlarged cross-sectional view showing a state in which a portion to be the coil L3 is thermocompression bonded.
- 16A and 16B are cross-sectional views taken along line TT shown in FIG.
- the laminated circuit board 501 according to the fifth embodiment is different from the laminated circuit board 101 according to the first embodiment in that a coil L3 and a sheet 514 are provided instead of the coil L1 and the sheets 13 and 14. Since the other configuration of the multilayer circuit board 501 is the same as that of the multilayer circuit board 101, the description thereof is omitted. Further, the manufacturing method of the laminated circuit board 501 is the same as the manufacturing method of the laminated circuit board 101, and thus the description thereof is omitted.
- the coil L3 is composed of second conductor patterns 533A to 533D.
- the first main surface 591 of the first conductor pattern 32B facing the second conductor patterns 533A to 533D is roughened (see FIG. 16A).
- the second main surfaces 592A to 592D facing the first conductor pattern 32B in the second conductor patterns 533A to 533D are also roughened (see FIG. 16A). .
- the surface roughness of the first main surface 591 is larger than the surface roughness of the third main surface 593 on the opposite side of the first conductor pattern 32B from the second conductor patterns 533A to 533D. Further, the surface roughness of the second main surfaces 592A to 592D is larger than the surface roughness of the fourth main surfaces 594A to 594D on the opposite side of the first conductor pattern 32B in the second conductor patterns 533A to 533D.
- first main surface 591 and the second main surfaces 592A to 592D are also rough in the laminated circuit board 501, when the sheets 11 to 13 and 514 are stacked and thermocompression bonded, the first and second conductor patterns 32B, The flow of the resin between 533A to 533D is hindered by the first main surface 591 and the second main surfaces 592A to 592D.
- the resin between the first and second conductor patterns 32B, 533A to 533D does not flow so much to the outside between the first and second conductor patterns 32B, 533A to 533D (see FIG. 16B). See arrow).
- the flow amount of the resin near the first main surface 591 is smaller than the flow amount of the resin near the third main surface 593.
- the surface roughness of the second main surfaces 592A to 592D is also larger than the surface roughness of the fourth main surfaces 594A to 594D, the amount of resin flow around the second main surfaces 592A to 592D is around the fourth main surfaces 594A to 594D. Less than the amount of resin flow.
- the size of the arrow shown in FIG. 16B represents the amount of resin flow.
- the stray capacitance between the first and second conductor patterns 32B and 533A does not easily change.
- the distance G2 between 2nd conductor patterns 533A and 533B changes, the line capacity between 2nd conductor patterns 533A and 533B does not change easily.
- the second conductor patterns 533B to 533D constituting the coil L3 are the same as the second conductor pattern 533A. That is, when the laminated circuit board 501 is manufactured by thermocompression bonding, the designed distances G1 and G2, the stray capacitance, and the line capacitance can be realized almost accurately.
- the laminated circuit board 501 substantially the same effect as the laminated circuit board 101 is obtained. Therefore, according to the laminated circuit board 501, it is possible to easily form the coil L3 having a highly accurate element value (inductance in this embodiment) with little individual difference in element values.
- FIG. 17 is an external perspective view of the first conductor pattern 32B and the coil L4 included in the multilayer circuit board 601 according to the sixth embodiment of the present invention.
- FIG. 18A is an enlarged cross-sectional view of a portion that becomes the coil L4 shown in FIG.
- FIG. 18B is an enlarged cross-sectional view showing a state where the portion to be the coil L4 is thermocompression bonded.
- 18A and 18B are cross-sectional views taken along line SS shown in FIG.
- the difference between the multilayer circuit board 601 according to the sixth embodiment and the multilayer circuit board 101 according to the first embodiment is that a coil L4 is provided instead of the coil L1. Since the configuration of the other laminated circuit board 601 is the same as that of the laminated circuit board 101, the description thereof is omitted. Further, the manufacturing method of the laminated circuit board 601 is also the same as the manufacturing method of the laminated circuit board 101, and thus the description thereof is omitted.
- the coil L4 includes conductor patterns 635A to 635G and second conductor patterns 633A to 633G.
- the conductor patterns 635A to 635G are formed on the sheet 15.
- the second conductor patterns 633A to 633G are formed on the sheet 13.
- the first conductor pattern 32B forms a ground, for example.
- the first conductor pattern 32B is a conductor pattern having a larger area than the total area of the second conductor patterns 633A to 633G.
- the first main surface 591 of the first conductor pattern 32B facing the second conductor patterns 633A to 633G is roughened (see FIG. 18A).
- the second main surfaces 692A to 692G facing the first conductor pattern 32B in the second conductor patterns 633A to 633G are also roughened (see FIG. 18A). .
- the capacitance of the second conductor patterns 633A to 633G and the first conductor pattern 32B is greater than the capacitance of the second conductor patterns 633A to 633G and the conductor patterns 635A to 635G.
- the influence on the value (inductance in this embodiment) is large.
- the first main surface 591 that faces the second conductor patterns 633A to 633G in the first conductor pattern 32B, and the second main surface that faces the first conductor pattern 32B in the second conductor patterns 633A to 633G. 692A to 692G are roughened.
- the surface roughness of the first main surface 591 is larger than the surface roughness of the third main surface 593 on the opposite side of the first conductor pattern 32B from the second conductor patterns 633A to 633G. Further, the surface roughness of the second main surfaces 692A to 692G is larger than the surface roughness of the fourth main surfaces 694A to 694G on the opposite side of the first conductor pattern 32B in the second conductor patterns 633A to 633G.
- first main surface 591 and the second main surfaces 692A to 692G are also rough in the laminated circuit board 601, when the sheets 11 to 15 are stacked and thermocompression bonded, the first and second conductor patterns 32B and 633A to The flow of the resin between 633G is hindered by the first main surface 591 and the second main surfaces 692A to 692G.
- the resin between the first and second conductor patterns 32B and 633A to 633G does not flow so much to the outside between the first and second conductor patterns 32B and 633A to 633G (see FIG. 18B). See arrow).
- the flow amount of the resin near the first main surface 591 is smaller than the flow amount of the resin near the third main surface 593.
- the surface roughness of the second main surfaces 692A to 692G is also larger than the surface roughness of the fourth main surfaces 694A to 694G, the flow rate of the resin near the second main surfaces 692A to 692G is around the fourth main surfaces 694A to 694G. Less than the amount of resin flow.
- the size of the arrow shown in FIG. 18B represents the amount of resin flow.
- the stray capacitance between the first and second conductor patterns 32B and 633A does not easily change.
- the change in the distance G2 between the second conductor patterns 633A and 633B can be suppressed, the line capacitance between the second conductor patterns 633A and 633B does not easily change.
- the other second conductor patterns 633B to 633G constituting the coil L4 are the same as the second conductor pattern 633A. That is, when the laminated circuit board 601 is manufactured by thermocompression bonding, the designed distances G1 and G2, the stray capacitance, and the line-to-line capacitance can be realized almost accurately.
- the element value (inductance in this embodiment) of the coil L4 does not easily change even if the temperature and pressure applied between the first and second conductor patterns 32B and 633A to 633G slightly change during thermocompression bonding. Further, since the surface roughness of the inner side surface of the coil L4 (that is, the second conductor patterns facing each other through the sheet 14) is relatively small, a coil having a large Q value can be formed.
- the laminated circuit board 601 there are almost the same effects as the laminated circuit board 101. Therefore, according to the laminated circuit board 601, it is possible to easily form the coil L4 having a highly accurate element value (inductance in this embodiment) with little individual difference in element values.
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Abstract
Description
前記積層回路基板の内部には、前記複数の熱可塑性樹脂層のうち少なくとも一層の熱可塑性樹脂層を挟んで互いに対向する第1、第2導体パターンが形成されており、
前記第1導体パターンにおいて前記第2導体パターンに対向する第1主面、及び前記第2導体パターンにおいて前記第1導体パターンに対向する第2主面には、粗化処理が施されている。
以下、本発明の第1実施形態に係る積層回路基板101について説明する。
以下、本発明の第2実施形態に係る積層回路基板201について説明する。
以下、本発明の第3実施形態に係る積層回路基板301について説明する。
以下、本発明の第4実施形態に係る積層回路基板401について説明する。
以下、本発明の第5実施形態に係る積層回路基板501について説明する。
以下、本発明の第6実施形態に係る積層回路基板601について説明する。
Z2…主面
11、12、13、14、15…シート
21、22、23、24、25…熱可塑性樹脂層
31…金属膜
31A、31B…外部接続端子
32…金属膜
32A、32B…第1導体パターン
33…金属膜
33A…第2導体パターン
33B~33E、34A~34D…導体パターン
34、35…金属膜
42、43、44…ビアホール導体
90…治具
91…第1主面
92…第2主面
93…第3主面
94…第4主面
101…積層回路基板
120…実装部品
121、122…実装用ランド
130…実装部品
131、132、133…実装用ランド
201…積層回路基板
211、212、214…シート
232A…第1導体パターン
233A…第2導体パターン
242…ビアホール導体
282A…導体パターン
293…第3主面
294…第4主面
301…積層回路基板
332A~332J、333A~332J…導体パターン
342A~342J、343A~343J…ビアホール導体
401…積層回路基板
412、414、413…シート
433D、433E…第1導体パターン
434C、434D…第2導体パターン
442…ビアホール導体
491A、491B…第1主面
492A、492B…第2主面
493A、493B…第3主面
494A、494B…第4主面
501…積層回路基板
514…シート
533A~533D…第2導体パターン
591…第1主面
592A~592D…第2主面
593…第3主面
594A~594D…第4主面
601…積層回路基板
633A~633G…第2導体パターン
692A~692G…第2主面
694A~694G…第4主面
Claims (10)
- 複数の熱可塑性樹脂層を積層した積層回路基板であって、
前記積層回路基板の内部には、前記複数の熱可塑性樹脂層のうち少なくとも一層の熱可塑性樹脂層を挟んで互いに対向する第1、第2導体パターンが形成されており、
前記第1導体パターンにおいて前記第2導体パターンに対向する第1主面、及び前記第2導体パターンにおいて前記第1導体パターンに対向する第2主面には、粗化処理が施されている、積層回路基板。 - 前記第1主面の表面粗さは、前記第1導体パターンにおいて前記第2導体パターンとは逆側の第3主面の表面粗さより大きい、請求項1に記載の積層回路基板。
- 前記第2主面の表面粗さは、前記第2導体パターンにおいて前記第1導体パターンとは逆側の第4主面の表面粗さより大きい、請求項1又は2に記載の積層回路基板。
- 前記第1、第2導体パターンのそれぞれは、前記熱可塑性樹脂層の表面に設けられた金属膜をパターニングしたものである、請求項1から3のいずれか1項に記載の積層回路基板。
- 前記第1主面の表面粗さは、前記第2主面の表面粗さと実質的に同じである、請求項1から4のいずれか1項に記載の積層回路基板。
- 前記第1主面の面積は、前記第2主面の面積と実質的に同じである、請求項1から5のいずれか1項に記載の積層回路基板。
- 前記熱可塑性樹脂層における前記第1、第2導体パターン間の周囲には、ビアホール導体が形成されている、請求項1から6のいずれか1項に記載の積層回路基板。
- 前記第1、第2導体パターンはコンデンサを構成する、請求項1から7のいずれか1項に記載の積層回路基板。
- 前記第1、第2導体パターンはインダクタを構成する、請求項1から7のいずれか1項に記載の積層回路基板。
- 前記第1導体パターンはインダクタを構成し、前記第2導体パターンはグランドを構成する、請求項1から7のいずれか1項に記載の積層回路基板。
Priority Applications (3)
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---|---|---|---|
CN201490000434.5U CN204994111U (zh) | 2013-02-15 | 2014-01-24 | 层叠电路基板 |
JP2015500170A JP6004078B2 (ja) | 2013-02-15 | 2014-01-24 | 積層回路基板、積層回路基板の製造方法 |
US14/748,623 US9980383B2 (en) | 2013-02-15 | 2015-06-24 | Laminated circuit substrate |
Applications Claiming Priority (2)
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JP2013027581 | 2013-02-15 | ||
JP2013-027581 | 2013-02-15 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US14/748,623 Continuation US9980383B2 (en) | 2013-02-15 | 2015-06-24 | Laminated circuit substrate |
Publications (1)
Publication Number | Publication Date |
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WO2014125894A1 true WO2014125894A1 (ja) | 2014-08-21 |
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PCT/JP2014/051455 WO2014125894A1 (ja) | 2013-02-15 | 2014-01-24 | 積層回路基板 |
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US (1) | US9980383B2 (ja) |
JP (1) | JP6004078B2 (ja) |
CN (1) | CN204994111U (ja) |
WO (1) | WO2014125894A1 (ja) |
Cited By (2)
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---|---|---|---|---|
WO2018066324A1 (ja) * | 2016-10-07 | 2018-04-12 | 株式会社村田製作所 | 多層基板 |
WO2021261416A1 (ja) * | 2020-06-24 | 2021-12-30 | 株式会社村田製作所 | 樹脂多層基板及びその製造方法 |
Families Citing this family (2)
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KR20180007874A (ko) * | 2016-07-14 | 2018-01-24 | 삼성전기주식회사 | 코일 부품 및 이의 제조 방법 |
KR102214641B1 (ko) * | 2018-07-16 | 2021-02-10 | 삼성전기주식회사 | 인쇄회로기판 |
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JP7315102B2 (ja) | 2020-06-24 | 2023-07-26 | 株式会社村田製作所 | 樹脂多層基板 |
Also Published As
Publication number | Publication date |
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US20150296621A1 (en) | 2015-10-15 |
US9980383B2 (en) | 2018-05-22 |
CN204994111U (zh) | 2016-01-20 |
JP6004078B2 (ja) | 2016-10-05 |
JPWO2014125894A1 (ja) | 2017-02-02 |
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