WO2014083771A1 - Élément semi-conducteur et procédé de fabrication de l'élément semi-conducteur - Google Patents

Élément semi-conducteur et procédé de fabrication de l'élément semi-conducteur Download PDF

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WO2014083771A1
WO2014083771A1 PCT/JP2013/006471 JP2013006471W WO2014083771A1 WO 2014083771 A1 WO2014083771 A1 WO 2014083771A1 JP 2013006471 W JP2013006471 W JP 2013006471W WO 2014083771 A1 WO2014083771 A1 WO 2014083771A1
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region
body region
silicon carbide
semiconductor layer
conductivity type
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English (en)
Japanese (ja)
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恒一郎 佐野
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パナソニック株式会社
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0843—Source or drain regions of field-effect devices
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    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
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    • H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
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    • H01L29/1025—Channel region of field-effect devices
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    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
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Definitions

  • the present invention relates to a semiconductor element and a manufacturing method thereof, and more particularly, to a silicon carbide semiconductor element used for high withstand voltage or large current and a manufacturing method thereof.
  • Silicon carbide (silicon carbide: SiC) is a high-hardness semiconductor material having a larger band gap than silicon (Si), and is applied to various semiconductor elements such as power elements, environment-resistant elements, high-temperature operating elements, and high-frequency elements. Has been. Especially, application to power elements, such as a semiconductor element and a rectifier, attracts attention.
  • a power element using SiC has advantages such as a significant reduction in power loss compared to a Si power element. Further, the SiC power element can realize a smaller semiconductor element as compared with the Si power element by utilizing such characteristics.
  • a typical semiconductor element is a metal-insulator-semiconductor field-effect transistor (MISFET) (see, for example, Patent Document 1). .
  • MISFET metal-insulator-semiconductor field-effect transistor
  • MOSFET Metal-oxide-semiconductor field-effect transistor
  • MOSFET Metal-Oxide-Semiconductor-Field-Effect-Transistor
  • the semiconductor element described in Patent Document 1 includes a body region divided into a first body region and a second body region. According to the semiconductor element described in Patent Document 1, electrical characteristics such as threshold voltage and on-resistance can be controlled by controlling the impurity concentrations of the first body region and the second body region.
  • the technology disclosed in this specification aims to realize a semiconductor element capable of reducing on-resistance.
  • one embodiment of a semiconductor element disclosed in this specification includes a first conductivity type semiconductor substrate, and a first conductivity type first silicon carbide provided on a main surface of the semiconductor substrate.
  • a semiconductor layer, a second conductivity type body region provided on the first silicon carbide semiconductor layer, a first conductivity type impurity region provided on the body region, and the first silicon carbide semiconductor layer A second silicon carbide semiconductor layer of a first conductivity type provided in contact with at least a part of the body region and at least a part of the impurity region, and a gate provided on the second silicon carbide semiconductor layer
  • the body region includes a first body region in contact with a surface of the first silicon carbide semiconductor layer, and a second body in contact with a bottom surface of the first body region.
  • the impurity concentration of the region is higher than the impurity concentration of the second body region, and the second body region is located inside the first body region in plan view in a direction perpendicular to the main surface of the semiconductor substrate. At least a part of the two body regions is located below the impurity region.
  • the on-resistance can be reduced.
  • FIG. 1A is a cross-sectional view showing the semiconductor element according to the first embodiment.
  • FIG. 1B and FIG. 1C are schematic plan views showing the arrangement of a plurality of unit cells constituting the semiconductor element according to the first embodiment.
  • FIG. 2A to FIG. 2D are cross-sectional views in order of steps showing the main part of the method of manufacturing a semiconductor device according to the first embodiment.
  • FIG. 3A to FIG. 3D are cross-sectional views in order of steps showing the main part of the method of manufacturing a semiconductor device according to the first embodiment.
  • FIG. 4A to FIG. 4C are cross-sectional views in order of steps showing the main part of the method of manufacturing a semiconductor device according to the first embodiment.
  • FIG. 5A is a cross-sectional view showing a semiconductor element according to the second embodiment.
  • FIGS. 5B and 5C are schematic plan views showing the arrangement of a plurality of unit cells constituting the semiconductor element according to the second embodiment.
  • FIG. 6A to FIG. 6D are cross-sectional views in order of steps showing the main part of the method for manufacturing a semiconductor device according to the second embodiment.
  • FIG. 7A to FIG. 7D are cross-sectional views in order of steps showing the main part of the method for manufacturing a semiconductor device according to the second embodiment.
  • FIG. 8A to FIG. 8C are cross-sectional views in order of steps showing the main part of the method of manufacturing a semiconductor device according to the second embodiment.
  • FIG. 9 is a cross-sectional view showing a main part of a method for manufacturing a semiconductor device according to the second embodiment.
  • FIG. 10A to FIG. 10D are cross-sectional views in order of steps showing a main part of a modified example of the method for manufacturing a semiconductor device according to the second embodiment.
  • FIG. 11 is a graph showing an example of the impurity profile of the body region in the semiconductor element according to the first and second embodiments.
  • FIG. 12 is a graph showing the relationship between the concentration of the JFET region and the depletion layer width at the time of breakdown between the JFET region and the body region in the semiconductor device according to the first and second embodiments, and the concentration of the JFET region And a maximum sidewall width.
  • FIG. 10A to FIG. 10D are cross-sectional views in order of steps showing a main part of a modified example of the method for manufacturing a semiconductor device according to the second embodiment.
  • FIG. 11 is a graph showing an example of the impurity profile of the body region
  • FIG. 13 is a graph showing the relationship between the amount of overlap between the JFET region and the body region and the threshold voltage in a conventional semiconductor device.
  • FIG. 14 is a graph showing the relationship between the on-resistance and the amount of overlap between the JFET region and the body region in the conventional semiconductor device.
  • FIG. 15A is a cross-sectional view showing a conventional semiconductor device.
  • FIG. 15B is a schematic plan view showing the arrangement of a plurality of unit cells constituting the semiconductor element according to the conventional example.
  • FIG. 16A is a cross-sectional view showing a semiconductor element according to a modification of the first embodiment.
  • FIGS. 16B and 16C are schematic plan views showing the arrangement of a plurality of unit cells constituting a semiconductor element according to a modification of the first embodiment.
  • the semiconductor element disclosed in this specification includes a first body region in contact with the surface of the first silicon carbide semiconductor layer, and a second body region in contact with the bottom surface of the first body region, and the impurity concentration of the first body region Is higher than the impurity concentration of the second body region, and the second body region is located inside the first body region in plan view in a direction perpendicular to the main surface of the semiconductor substrate, and the second body region At least some of them are located below the impurity regions.
  • a region through which current flows is widened, so that the resistance of a JFET (junction field-effect transistor) region can be reduced.
  • a semiconductor element includes a first conductivity type semiconductor substrate, a first conductivity type first silicon carbide semiconductor layer provided on a main surface of the semiconductor substrate, and a first silicon carbide semiconductor layer.
  • a second conductivity type body region provided in the upper portion; a first conductivity type impurity region provided in the upper portion of the body region; and at least a part of the body region on the first silicon carbide semiconductor layer;
  • a first conductivity type second silicon carbide semiconductor layer provided in contact with at least a part of the impurity region, a gate insulating film provided on the second silicon carbide semiconductor layer, and provided on the gate insulating film
  • the body region includes a first body region in contact with the surface of the first silicon carbide semiconductor layer, and a second body region in contact with the bottom surface of the first body region, and the impurity in the first body region Concentration is the second body region
  • the second body region is higher than the impurity concentration and is located inside the first body region in a plan view in a direction perpendicular to the main
  • the semiconductor device of one embodiment further includes a first conductivity type injection region disposed in a region of the first silicon carbide semiconductor layer at a side of the body region, and a lower portion of the injection region is formed shallower than the body region.
  • the body region may be formed by doping a second conductivity type impurity so as to reverse the conductivity type of the implantation region.
  • the semiconductor element of one embodiment further includes a first conductivity type injection region disposed in a region of the first silicon carbide semiconductor layer on a side of the body region, and the injection region is formed deeper than the body region. It may be.
  • the impurity concentration of the first body region is 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 20 cm ⁇ 3 or less
  • the impurity concentration of the second body region is 1 ⁇ 10 17. cm -3 or more and is 1 ⁇ 10 19 cm -3 or less
  • the impurity concentration of the implanted region, 5 ⁇ 10 16 cm -3 or more and 5 ⁇ 10 17 cm -3 may be less.
  • the second silicon carbide semiconductor layer includes an upper layer in contact with the gate insulating film and a lower layer in contact with the first silicon carbide semiconductor layer, and the impurity concentration of the upper layer is lower than the impurity concentration of the lower layer. May be.
  • the semiconductor device of one embodiment further includes a first ohmic electrode electrically connected to the impurity region, and a second ohmic electrode provided on a surface of the semiconductor substrate opposite to the first silicon carbide semiconductor layer. It may be.
  • the second body region may be located on the same side as the impurity region or outside the impurity region in a plan view in a direction perpendicular to the main surface of the semiconductor substrate.
  • a method of manufacturing a semiconductor device includes a step of forming a first conductivity type first silicon carbide semiconductor layer on a main surface of a first conductivity type semiconductor substrate, and a step of forming the first silicon carbide semiconductor layer.
  • a step of forming a first conductivity type implantation region on the upper portion; a step of selectively forming a second conductivity type first body region on the implantation region; and a lower side of the first body region in the implantation region A step of selectively forming a second body region of the second conductivity type, and a step of selectively forming an impurity region of the first conductivity type on the upper portion of the first body region.
  • the second body region is formed deeper than the implantation region, and the impurity concentration of the second body region is lower than the impurity concentration of the first body region, and with respect to the main surface of the semiconductor substrate.
  • the first body region in plan view in a vertical direction Located inside, at least a portion of the second body region is formed to be located below the impurity regions.
  • At least a part of the first body region and at least a part of the impurity region are respectively formed on the first silicon carbide semiconductor layer after the step of forming the impurity region.
  • a method of manufacturing a semiconductor device includes a step of forming a first conductivity type first silicon carbide semiconductor layer on a main surface of a first conductivity type semiconductor substrate, and a first silicon carbide semiconductor layer. And selectively forming one of the second conductivity type first body region and the first conductivity type implantation region on the side of the one region in the first silicon carbide semiconductor layer. And forming the other of the first body region and the implantation region in a self-aligned manner with respect to the one region, and forming a second conductive layer under the first body region in the first silicon carbide semiconductor layer.
  • the region is formed deeper than the second body region, and the second body
  • the impurity concentration of the second body region is lower than the impurity concentration of the first body region and in a plan view in a direction perpendicular to the main surface of the semiconductor substrate,
  • the second body region is formed on the inner side so that at least part of the second body region is located below the impurity region.
  • At least a part of the first body region and at least a part of the impurity region are respectively formed on the first silicon carbide semiconductor layer after the step of forming the implantation region.
  • FIG. 1A schematically shows a cross-sectional configuration of a semiconductor element 100 according to this embodiment.
  • FIG. 1A shows a cross section of two semiconductor elements 100 positioned on the right and left sides of the alternate long and short dash line. These constitute a unit cell 100u, and the semiconductor element 100 according to the present embodiment includes a plurality of unit cells 100u.
  • the present disclosure is not limited to the following embodiments and the like.
  • the numerical values, shapes, materials, constituent elements, arrangement positions and connection forms of the constituent elements, process steps, the order of the steps, and the like shown in the following embodiments are all examples.
  • constituent elements that are not described in the independent claims showing the highest concept of the present invention are described as optional constituent elements that constitute a preferred embodiment. .
  • Each figure is a schematic diagram and is not necessarily illustrated strictly. The same applies to the semiconductor elements according to other embodiments.
  • a semiconductor element 100 includes a first conductivity type semiconductor substrate 101 and a first conductivity type first silicon carbide semiconductor layer (silicon carbide epitaxial layer) located on the main surface of the semiconductor substrate 101. Layer) 102.
  • the first conductivity type is n-type
  • the second conductivity type is p-type.
  • the first conductivity type may be p-type
  • the second conductivity type may be n-type.
  • the semiconductor substrate 101 has n + type conductivity and is made of silicon carbide (SiC).
  • First silicon carbide semiconductor layer 102 is n ⁇ type. The “+” or “ ⁇ ” on the right shoulder of the n or p conductivity type represents the relative concentration of impurities.
  • n + means that the n-type impurity concentration is higher than “n”
  • n ⁇ means that the n-type impurity concentration is lower than “n”.
  • a plurality of second conductivity type body regions 103 are formed per unit cell on the first silicon carbide semiconductor layer 102, and between the body regions 103 included in the adjacent unit cells 100u, A one-conductivity type JFET region 102j is formed.
  • the JFET region 102j refers to a first conductivity type region adjacent to the body region 103, that is, a first conductivity type region sandwiched between the body regions 103 of two adjacent unit cells 100u.
  • the second conductivity type body region 103 is formed by introducing a second conductivity type impurity into the first conductivity type implantation region 102 i formed above the first silicon carbide semiconductor layer 102. Is done.
  • the body region 103 includes both the first conductivity type impurity and the second conductivity type impurity, and the second conductivity type impurity concentration is higher than the first conductivity type impurity concentration in the implantation region 102i. Defined as an area that is high. On the bottom surface of body region 103, the first conductivity type impurity concentration in the region in contact with body region 103 in first silicon carbide semiconductor layer 102 is equal to the second conductivity type impurity concentration in body region 103.
  • the body region 103 includes a second conductivity type first body region 103a and a second conductivity type second body region 103b.
  • First body region 103a is in contact with the surface of first silicon carbide semiconductor layer 102, and the upper surface of second body region 103b is in contact with the bottom surface of first body region 103a.
  • the thickness of the first body region 103a is, for example, at least 15 nm, and the thickness of the second body region 103b is, for example, at least 100 nm.
  • the thickness of each of the regions 103a and 103b is a thickness in a direction perpendicular to the main surface of the semiconductor substrate 101.
  • the first body region 103a is p + type
  • the second body region 103b is p type.
  • the average impurity concentration of the first body region 103a can be set to be twice or more the average impurity concentration of the second body region 103b.
  • the second body region 103b is located inside the first body region 103a in a so-called planar view as seen from a direction perpendicular to the main surface of the semiconductor substrate 101. That is, the second body region 103b is provided such that the width of the second body region 103b is smaller than the width of the first body region 103a.
  • a first conductivity type impurity region 104 is provided on the first body region 103a.
  • the conductivity type of the impurity region 104 is n + type.
  • the second body region 103 b is provided so as to be located at the same position as the impurity region 104 or outside the impurity region 104 in a plan view with respect to the main surface of the semiconductor substrate 101. Accordingly, at least a part of the second body region 103 b is located below the impurity region 104. Thus, in the present embodiment, at least a part of the second body region 103b is provided below the impurity region 104 that is the source region. For this reason, generation
  • a second conductivity type contact region 105 can be provided in the first body region 103a.
  • the conductivity type of contact region 105 may be p + type.
  • Contact region 105 is in contact with second body region 103b.
  • a source electrode (first ohmic electrode) 109 is provided on the impurity region 104.
  • the source electrode 109 is formed on the surfaces of the impurity region 104 and the contact region 105 and is in electrical contact with both the impurity region 104 and the contact region 105.
  • the contact region 105 may not be provided.
  • a contact trench exposing the first body region 103a is provided in the impurity region 104, and the source electrode 109 is formed at the bottom of the provided contact trench, whereby the first body region 103a and the source electrode 109 are directly connected. You may make it contact.
  • the portion where the contact region 105 is formed may be non-implanted so that the first body region 103a is exposed and the first body region 103a and the source electrode 109 are in direct contact with each other. .
  • the JFET region 102j which is the first conductivity type region sandwiched between the body regions 103 in the two unit cells 100u adjacent to each other is formed in the implantation region 102i. Therefore, the impurity concentration in the JFET region 102j is the same as that in the implantation region 102i.
  • the depth of the implantation region 102i is set to a depth at least up to the lower side of the first body region 103a. The reason is that the on-resistance of the semiconductor element 100 is increased by reducing the on-resistance of a region sandwiched between two adjacent first body regions 103a, that is, a region serving as a current path that flows when the semiconductor element 100 is on. Because. In the present embodiment, as shown in FIG. 1A, the depth of the implantation region 102i can be set shallower than the depth of the second body region 103b.
  • a second conductivity type second silicon carbide semiconductor layer 106 is provided in contact with at least part of the body region 103 and at least part of the impurity region 104, respectively.
  • Second silicon carbide semiconductor layer 106 is electrically connected to JFET region 102j adjacent to first body region 103a in impurity region 104 and first silicon carbide semiconductor layer 102, and on top of first body region 103a. Can be formed.
  • the second silicon carbide semiconductor layer 106 is formed by epitaxial growth.
  • Second silicon carbide semiconductor layer 106 includes a channel region 106c in a region in contact with first body region 103a.
  • the length of the channel region 106c corresponds to the length indicated by the two bidirectional arrows shown in FIG. That is, the “channel length” of the MISFET is determined by the length of the upper surface of the first body region 103 a, that is, the length of the interface with the first body region 103 a in the second silicon carbide semiconductor layer 106.
  • the second silicon carbide semiconductor layer (channel layer) 106 has a dopant concentration distribution in a direction perpendicular to the semiconductor substrate 101.
  • the second silicon carbide semiconductor layer 106 is expressed by a two-layered structure, the side in contact with the impurity region 104 is the lower layer 106b, and the layer located above the lower layer 106b is the upper layer 106a.
  • Lower layer 106b of second silicon carbide semiconductor layer 106 has an n-type dopant.
  • the upper layer 106a of the second silicon carbide semiconductor layer 106 is in an undoped state, for example, having a very low dopant concentration.
  • a gate insulating film 107 is provided on the second silicon carbide semiconductor layer 106.
  • a gate electrode 108 is provided on the gate insulating film 107. The gate electrode 108 is located at least above the channel region 106c.
  • An interlayer insulating film 111 is provided on the gate electrode 108 so as to cover the gate electrode 108.
  • An upper wiring 112 is provided on the interlayer insulating film 111.
  • the upper wiring 112 is connected to the source electrode 109 through a contact hole 111 a provided in the interlayer insulating film 111.
  • a drain electrode (second ohmic electrode) 110 is provided on the back surface of the semiconductor substrate 101 opposite to the first silicon carbide semiconductor layer 102.
  • the drain electrode 110 is further provided with a back surface wiring 113.
  • Each unit cell 100u constituting the semiconductor element 100 has, for example, a square shape when the semiconductor element 100 is viewed from the upper wiring 112 side.
  • Each unit cell 100u is not limited to a square shape, and may be a rectangular shape or may have a polygonal shape other than a square shape.
  • FIG. 1B shows an arrangement of a plurality of unit cells 100u. As shown in FIG. 1B, the unit cells 100u are, for example, two-dimensionally arranged in the x direction and the y direction, and the arrangement in the y direction is alternately shifted by half in the x direction. ing. When the unit cells 100u have a rectangular shape extending in one direction, the unit cells 100u may be arranged in parallel as shown in FIG.
  • the semiconductor element 100 is configured by the plurality of unit cells 100u arranged in this way.
  • second silicon carbide semiconductor layer 106 In semiconductor element 100, second silicon carbide semiconductor layer 106, gate electrode 108 that controls current flowing through second silicon carbide semiconductor layer 106, gate insulating film 107, and second silicon carbide semiconductor layer 106 are electrically connected.
  • the source electrode 109 and the drain electrode 110 thus formed constitute a MISFET.
  • the drain electrode 110 potential with reference to the source electrode 109 potential is Vds
  • the gate electrode 108 potential with reference to the source electrode 109 potential is Vgs
  • the threshold voltage of the MISFET (threshold voltage of the forward current) is Vth.
  • the MISFET is turned on when Vgs ⁇ Vth, and when Vds> 0 V, the semiconductor substrate 101, the first silicon carbide semiconductor layer (drift layer) 102, the JFET region 102j, the second carbonization are formed from the drain electrode 110.
  • a current flows to the source electrode 109 through the silicon semiconductor layer (channel layer) 106 and the impurity region 104 which is a source region.
  • the on-resistance in this region is the mobility in the JFET region 102j is ⁇ j, and the interval between two adjacent first body regions 103a is the same.
  • the distance between two adjacent second body regions 103b is a2
  • the dopant concentration of the JFET region 102j is Nj
  • the surface of the first silicon carbide semiconductor layer 102 in the body region 103 corresponds to the channel width as the JFET region 102j
  • the depth of the first body region 103a from the surface of the first silicon carbide semiconductor layer 102 is Lp1
  • the depth of the second body region 103b from the bottom of the first body region 103a is Lp2.
  • the mobility in the JFET region 2j according to the conventional example is ⁇ j
  • the interval between two adjacent body regions 3 is a
  • the dopant concentration in the JFET region 2j is Nj
  • the JFET region 2j The length of the boundary line on the surface of the first silicon carbide semiconductor layer 2 in the body region 3 corresponding to the channel width of W is W
  • the depth of the body region 3 from the surface of the first silicon carbide semiconductor layer 2 is Lp. .
  • the width of the second body region 103b is smaller than the width of the first body region 103a in plan view in the direction perpendicular to the main surface of the semiconductor substrate 101, and The two body regions 103b are located inside the first body region 103a. Therefore, as shown in FIG. 1 (a), since the interval a2 between the second body regions 103b and the interval a1 between the first body regions 103a satisfy a2> a1, [value of expression (1)] ⁇ [Value of Expression (2)] is realized. That is, the on-resistance of the semiconductor element 100 according to the present embodiment can be reduced as compared with the conventional semiconductor element 50.
  • the JFET region 102j is formed in a self-aligned manner, fluctuations in the current path are reduced. As a result, a current can be flowed stably, and variations in on-resistance and threshold voltage can be suppressed.
  • the semiconductor substrate 101 is prepared.
  • the semiconductor substrate 101 is, for example, a low resistance n-type 4H—SiC offcut substrate having a resistivity of 0.02 ⁇ cm.
  • a high-resistance first silicon carbide semiconductor is formed on the main surface of the semiconductor substrate 101 by a deposition method capable of epitaxial growth such as a chemical vapor deposition (CVD) method.
  • Layer 102 is grown epitaxially.
  • a buffer layer made of SiC having a high impurity concentration may be deposited on the semiconductor substrate 101.
  • the impurity concentration of the buffer layer is, for example, 1 ⁇ 10 18 cm ⁇ 3 and the thickness thereof is, for example, 1 ⁇ m.
  • the first silicon carbide semiconductor layer 102 is made of, for example, n-type 4H—SiC, the impurity concentration is, for example, 1 ⁇ 10 16 cm ⁇ 3 , and the thickness is, for example, 10 ⁇ m. Subsequently, nitrogen (N) ions are implanted into the first silicon carbide semiconductor layer 102 to form an n-type implanted region 102i.
  • the impurity concentration of the implantation region 102i is, for example, 1 ⁇ 10 17 cm ⁇ 3 and the depth is, for example, 0.5 ⁇ m.
  • a mask film 201 made of, for example, silicon oxide (SiO 2 ) and having the formation pattern of the first body region 103a in the opening on the implantation region 102i is used as a mask.
  • silicon oxide (SiO 2 ) For example, aluminum (Al) ions are implanted into the implantation region 102i to form the p + -type first body region 103a.
  • the JFET region 102j is formed from the implantation region 102i in a self-aligned manner with respect to the first body region 103a.
  • a sidewall formation film 202 made of SiO 2 is formed on the first body region 103a including the mask film 201 by, eg, CVD.
  • Al ions are implanted into the implantation region 102 and the first silicon carbide semiconductor layer 102 thereunder through the sidewall formation film 202 to form the p-type second body region 103b.
  • the implanted Al ions are masked by the mask film 201 and the portion of the sidewall formation film 202 formed on the side surface of the opening of the mask film 201.
  • the second body region 103b It is formed so as to be located on the inner side from the periphery or the side of the region 103a.
  • the ion implantation profile shown in FIG. 11 is obtained by implanting Al ions in four portions with the following implantation energy and dose.
  • An ion implantation profile in the first body region 103a is formed in the first two times, and an ion implantation profile in the second body region 103b is formed in the latter two times.
  • a resist pattern (not shown) having the formation pattern of the impurity region 104 in the opening is formed on the mask film 201 and the sidewall formation film 202 by lithography. Thereafter, as shown in FIG. 2D, the sidewall formation film 202 is dry-etched using the resist pattern as a mask to form a sidewall 202a and a mask film 202b from the sidewall formation film 202. Thereafter, the resist pattern is removed and, for example, N ions are implanted into the first body region 103a, thereby forming the impurity region 104 on the first body region 103a.
  • width of the sidewall 202a can be set as follows.
  • FIG. 12 shows that the sidewall width that can deplete the JFET region 102j before the avalanche breakdown occurs is the maximum sidewall width when the width of the JFET region 102j is 1 ⁇ m and 0.5 ⁇ m. Show.
  • the horizontal axis in FIG. 12 represents the impurity concentration of the first conductivity type in the JFET region 102j.
  • the solid line indicates the maximum sidewall width when the width of the JFET region 102j is 0.5 ⁇ m
  • the alternate long and short dash line indicates the maximum sidewall width when the width of the JFET region 102j is 1 ⁇ m.
  • the thick line indicates the width of the depletion layer at the time of avalanche breakdown.
  • the width of the sidewall 202a can be set so as to be a value equal to or smaller than the maximum sidewall width shown in FIG.
  • the thickness of the sidewall 202a is selected so as to have a sidewall width that can deplete the JFET region 102j, and, for example, Al ions are implanted to form the second body region 103b. Form.
  • the sidewall formation film 202 may be further enlarged by deposition so as to have a film thickness that determines the channel length, and the sidewall 202a may be formed.
  • a mask film 205 made of SiO 2 having an opening at a portion of the first body region 103a where the contact region is formed is formed.
  • Al ions are implanted to form a p-type contact region 105 at substantially the center of the impurity region 104 and the first body region.
  • the contact region 105 may be formed so as to reach the second body implantation region 103b.
  • the mask film 205 is removed, and high-temperature heat treatment (activation annealing) is performed to activate the impurities implanted into the first silicon carbide semiconductor layer 102.
  • high-temperature heat treatment activation annealing
  • the first body region 103a, the second body region 103b, the impurity region 104, the contact region 105, and the JFET region 102j are formed.
  • the ion implantation profile is determined so that the depth of the first body region 103a is, for example, 300 nm and the average impurity concentration is about 1.6 ⁇ 10 19 cm ⁇ 3 .
  • the total depth of the body region 103 including the first body region 103a and the second body region 103b is, for example, 550 nm, and the average impurity concentration of the second body region 103b is about 2 ⁇ 10 18 cm ⁇ 3 .
  • the ion implantation profile is adjusted so that The depth of the impurity region 104 is, for example, 250 nm, and the ion implantation profile is adjusted so that the average impurity concentration is about 5 ⁇ 10 19 cm ⁇ 3 .
  • the depth of the first body region 103a is determined by the boundary shown in FIG. 11, and the depth of the second body region 103b is set to a depth at which, for example, an impurity concentration of 5 ⁇ 10 17 cm ⁇ 3 is obtained.
  • the depth of the impurity region 104 is set to a depth at which an impurity concentration of 5 ⁇ 10 17 cm ⁇ 3 is obtained, for example.
  • the impurity concentration is calculated as follows, for example. As shown in FIG. 11, the relationship between the depth direction and the impurity concentration in a certain cross section is clarified using, for example, SIMS (secondary ion mass spectrometry), and then the region in the depth direction is defined. Since the depth of the first body region 103a is defined as the depth determined by the boundary shown in FIG. 11, the depth is 0.28 ⁇ m.
  • the impurity concentration is integrated in the depth direction and converted into a sheet dose (unit dimension is cm ⁇ 2 ). The impurity concentration is calculated by dividing the sheet dose calculated here by the depth of the region (here, 0.28 ⁇ m).
  • the depth of the contact region 105 is, for example, 400 nm, the average impurity concentration is about 1 ⁇ 10 20 cm ⁇ 3 , and the depth is, for example, a depth at which an impurity concentration of 5 ⁇ 10 17 cm ⁇ 3 is obtained.
  • the surface layer of the first silicon carbide semiconductor layer 102 may be removed in order to clean the surface of the first silicon carbide semiconductor layer 102 after the activation annealing.
  • the depths of the first body region 103a, the impurity region 104, and the contact region 105 are all reduced by about 50 nm and become 250 nm, 200 nm, and 350 nm, respectively.
  • the second silicon carbide semiconductor layer is formed on the entire surface of the first silicon carbide semiconductor layer 102 including the JFET region 102j, the first body region 103a, the impurity region 104, and the contact region 105.
  • 106 is epitaxially grown.
  • second silicon carbide semiconductor layer 106 includes upper layer 106a and lower layer 106b.
  • the upper layer 106a is continuously formed on the lower layer 106b.
  • the dopant concentration of the lower layer 106b is, for example, about 2 ⁇ 10 18 cm ⁇ 3 and the film thickness is, for example, 24 nm.
  • the lower layer 106b is formed by doping nitrogen (N)
  • the introduction of the doping gas is stopped and the upper layer 106a is continuously formed so as to have a film thickness of about 26 nm.
  • the gate insulating film 107 is formed on the surface of the second silicon carbide semiconductor layer upper layer 106a by, eg, thermal oxidation.
  • a polycrystalline silicon film doped with phosphorus (P) at a concentration of about 7 ⁇ 10 20 cm ⁇ 3 is deposited on the gate insulating film 107.
  • the thickness of the polycrystalline silicon film is, for example, about 500 nm.
  • a resist pattern (not shown) having a gate electrode formation pattern is formed on the polycrystalline silicon film by lithography, and the polycrystalline silicon film is dry-etched using the formed resist pattern.
  • a plurality of gate electrodes 108 made of polycrystalline silicon are formed in a predetermined region.
  • an interlayer insulating film 111 containing, for example, SiO 2 is deposited by the CVD method so as to cover the surface of the gate electrode 108 and the surface of the first silicon carbide semiconductor layer 102.
  • the thickness of the interlayer insulating film 111 is, for example, 1.5 ⁇ m.
  • the upper part of the contact region 105 and the upper part of the impurity region 104 in the interlayer insulating film 111 are removed by dry etching using a mask (not shown). As a result, a contact hole 111 a is formed in the interlayer insulating film 111.
  • a nickel (Ni) film having a thickness of, for example, about 50 nm is formed on the interlayer insulating film 111 by vacuum deposition or sputtering. Subsequently, as shown in FIG. 4B, the nickel film is reacted with the exposed portion of the silicon carbide from the interlayer insulating film 111 by performing a heat treatment in an inert atmosphere, for example, at a temperature of 950 ° C. for 5 minutes. Then, the source electrode 109 made of nickel silicide (NiSi) is formed.
  • the unreacted nickel film on the interlayer insulating film 111 is removed by etching. Thereafter, as shown in FIG. 4C, a nickel film, for example, is deposited on the entire back surface of the semiconductor substrate 101 and reacted with silicon carbide by the same heat treatment to form the drain electrode 110.
  • an upper wiring 112 is formed by depositing an aluminum (Al) film having a thickness of about 4 ⁇ m on the interlayer insulating film 111 and inside the contact hole 111a, and etching it into a desired pattern.
  • Al aluminum
  • a gate wiring or a gate pad that contacts the gate electrode 108 is formed at the end of the chip.
  • titanium (Ti) / nickel (Ni) / silver (Ag) is deposited on the back surface of the drain electrode 110 as the back surface wiring 113 for die bonding from the drain electrode 110 side. In this way, the semiconductor element 100 shown in FIG. 1 is obtained.
  • the width of the second body region 103b is smaller than the width of the first body region 103a in plan view in a direction perpendicular to the main surface of the semiconductor substrate 101.
  • the second body region 103b is disposed inside the first body region 103a in plan view.
  • the JFET region 102j is formed in a self-aligning manner. For this reason, there is no variation in the overlapping dimension of the body region 103 and the implantation region 102i. As a result, the variation in the current path is reduced, and the current can flow stably, so that variations in the on-resistance and the threshold voltage can be suppressed.
  • FIG. 15 shows a cross-sectional view of a semiconductor element having a conventional structure.
  • a semiconductor element 50 according to a conventional example includes an n-type semiconductor substrate 1 and an n-type first silicon carbide semiconductor layer 2 formed on the main surface of the semiconductor substrate 1.
  • a plurality of p-type body regions 3 are formed on top of first silicon carbide semiconductor layer 2, and n-type JFET region 2j is formed between body regions 3 included in adjacent unit cells 50u. Yes.
  • the body region 3 includes a first body region 3a and a second body region 3b below the first body region 3a.
  • the width of the first body region 3a and the width of the second body region 3b are formed to be equal, and the JFET region 2j is formed so as to overlap the body region 3.
  • An n-type impurity region 4 is formed above the first body region 3a, and a source electrode 9 is formed above the impurity region 4.
  • a source electrode 9 is formed above the impurity region 4.
  • a gate electrode 8 is formed on second silicon carbide semiconductor layer 6 with gate insulating film 7 interposed.
  • FIG. 13 shows the relationship between the amount of overlap between the JFET region 2j and the body region 3 and the threshold voltage in the conventional structure.
  • 3.2 V is obtained as a simulation value.
  • FIG. 14 shows the relationship between the ON resistance and the amount of overlap between the JFET region 2j and the body region 3 in the conventional structure.
  • 6.0 m ⁇ ⁇ cm 2 is obtained as a simulation value.
  • the conventional structure is formed by aligning the JFET region and the body region, the amount of overlap between the JFET region and the body region varies. Accordingly, since the amount of overlap between the JFET region and the body region varies, the threshold voltage and the on-resistance vary as shown in FIGS.
  • the semiconductor element 100 according to the present embodiment by forming the JFET region 102j in a self-aligning manner, it is possible to suppress fluctuations in threshold voltage and fluctuations in on-resistance while reducing on-resistance.
  • FIG. 5A schematically shows a cross-sectional configuration of the semiconductor element 300 according to the present embodiment.
  • FIG. 5A shows a cross section of two semiconductor elements 300 positioned on the right and left sides of the alternate long and short dash line. These constitute a unit cell 300u, and the semiconductor element 300 according to the present embodiment includes a plurality of unit cells 300u.
  • the same components as those in the first embodiment are denoted by the same reference numerals. Therefore, the description regarding the same content and the same component as 1st Embodiment may be abbreviate
  • Semiconductor element 300 includes a first conductivity type semiconductor substrate 101 and a first conductivity type first silicon carbide semiconductor layer (silicon carbide epitaxial layer) 102 located on the main surface of semiconductor substrate 101. Also in this embodiment, the first conductivity type is n-type, and the second conductivity type is p-type. The first conductivity type may be p-type and the second conductivity type may be n-type.
  • the semiconductor substrate 101 has n + type conductivity and is made of silicon carbide (SiC).
  • First silicon carbide semiconductor layer 102 is n ⁇ type.
  • a plurality of second conductivity type body regions 103 are formed per unit cell on the first silicon carbide semiconductor layer 102, and between the body regions 103 included in the adjacent unit cells 300u, A one-conductivity type JFET region 102j is formed.
  • the impurity concentration is the same as that of the implantation layer 102i.
  • the depth of the implantation region 102i can be set to be deeper than at least the first body region 103a. Further, in the present embodiment, as shown in FIG. 5A, the depth of the implantation region 102i can be set to be deeper than the second body region 103b. In this embodiment, since the implantation region 102i is formed only in a region sandwiched between adjacent body regions 103, the depth of the implantation region 102i is set to be deeper than the second body region 103b. However, the JFET region 102j is not formed under the second body region 103b.
  • the on-resistance of the region sandwiched between the two adjacent first body regions 103a that is, the region serving as a current path that flows when the semiconductor element 300 is turned on, is further reduced while maintaining the withstand voltage.
  • the on-current can be further increased.
  • Each unit cell 300u constituting the semiconductor element 300 has, for example, a square shape when the semiconductor element 300 is viewed from the upper wiring 112 side.
  • Each unit cell 300u is not limited to a square shape but may be a rectangle or may have a polygonal shape other than a quadrangle.
  • FIG. 5B shows an arrangement of a plurality of unit cells 300u. As shown in FIG. 5B, the unit cells 300u are, for example, arranged two-dimensionally in the x and y directions, and the arrangement in the y direction is alternately shifted by a half in the x direction. Yes. When the unit cells 300u have a rectangular shape extending in one direction, the unit cells 300u may be arranged in parallel as shown in FIG.
  • the semiconductor element 300 is constituted by the plurality of unit cells 300u arranged in this way.
  • the interval a2 between the second body regions 103b and the interval a1 between the first body regions 103a have a relationship of a2> a1, and therefore, the semiconductor element 300 according to the present embodiment.
  • the on-resistance can be reduced as compared with the conventional semiconductor element 50.
  • the JFET region 102j is formed in a self-aligned manner, fluctuations in the current path are reduced. As a result, a current can be flowed stably, and variations in on-resistance and threshold voltage can be suppressed.
  • the semiconductor substrate 101 is prepared.
  • the semiconductor substrate 101 is, for example, a low-resistance n-type 4H—SiC offcut substrate having a resistivity of about 0.02 ⁇ cm.
  • the high-resistance first silicon carbide semiconductor layer 102 is epitaxially grown on the main surface of the semiconductor substrate 101 by a deposition method capable of epitaxial growth such as CVD.
  • a buffer layer made of SiC having a high impurity concentration may be deposited on the semiconductor substrate 101.
  • the impurity concentration of the buffer layer is, for example, 1 ⁇ 10 18 cm ⁇ 3 and the thickness thereof is, for example, 1 ⁇ m.
  • the first silicon carbide semiconductor layer 102 is made of, for example, n-type 4H—SiC, the impurity concentration is, for example, 1 ⁇ 10 16 cm ⁇ 3 , and the thickness is, for example, 10 ⁇ m.
  • a mask film 211 made of, for example, polysilicon and having a formation pattern of the first body region 103a in the opening on the first silicon carbide semiconductor layer 102 is used as a mask.
  • Al ions are implanted into the first silicon carbide semiconductor layer 102 to form the p + -type first body region 103a.
  • FIG. 6C a sidewall formation film 202 made of SiO 2 is formed on the first body region 103a including the mask film 211 by, eg, CVD. Thereafter, for example, Al ions are implanted through the sidewall formation film 202 of the first silicon carbide semiconductor layer 102 to form the second body region 103b.
  • FIG. 11 shows an example of the ion implantation profile in the AB section of FIG.
  • the ion implantation profile shown in FIG. 11 is obtained by implanting Al ions in four portions with the following implantation energy and dose.
  • An ion implantation profile in the first body region 103a is formed in the first two times, and an ion implantation profile in the second body region 103b is formed in the latter two times.
  • a resist pattern (not shown) having the formation pattern of the impurity region 104 in the opening is formed on the mask film 211 and the sidewall formation film 202 by lithography. Thereafter, as shown in FIG. 6D, the sidewall formation film 202 is dry-etched using the resist pattern as a mask to form the sidewall 202a and the mask film 202b from the sidewall formation film 202. Thereafter, the resist pattern is removed and, for example, N ions are implanted into the first body region 103a, thereby forming an impurity region 104 on the first body region 103a.
  • the width of the sidewall 202a can be set to be a value equal to or smaller than the width of the sidewall described in FIG. 12, for example.
  • the thickness of the sidewall is selected so as to have a sidewall width that can deplete a JFET region formed in a later process, and Al ions are implanted, for example, to form the second body region. 103b is formed. Thereafter, the sidewall formation film 202 may be further enlarged by deposition so as to have a film thickness that determines the channel length, and the sidewall 202a may be formed.
  • a mask formation film (not shown) made of SiO 2 is deposited so as to cover the impurity region 104 including the mask films 211 and 202b and the sidewalls 202a.
  • the upper surface of the deposited mask forming film is planarized by a chemical mechanical polishing (CMP) method or the like.
  • CMP chemical mechanical polishing
  • the mask film 211 is selectively removed from the mask formation film by etching or the like, and a mask film 206 having a formation pattern of the JFET region 102j in the opening is formed.
  • N ions are implanted into the first silicon carbide semiconductor layer 102 using the mask film 206 as a mask to form a JFET region 102j.
  • the impurity concentration of the JFET region 102j is, for example, 1 ⁇ 10 17 cm ⁇ 3 and the depth thereof is, for example, 0.5 ⁇ m.
  • the JFET region 102j is formed in a self-aligned manner with respect to the first body region 103a.
  • the high-density plasma non-doped silica glass (HDP-NSG) method or SOG (Spin On Glass) method and the CMP method are combined with the formation of the mask formation film and the mask film 206. Can do.
  • the mask film 206 is removed. Thereafter, the steps shown in FIGS. 7B to 9 are performed to obtain the semiconductor element 300 shown in FIG. Since the steps shown in FIGS. 7B to 9 are the same as the steps shown in FIGS. 3A to 4C in the first embodiment, description thereof will be omitted.
  • the width of the second body region 103b is smaller than the width of the first body region 103a in plan view in a direction perpendicular to the main surface of the semiconductor substrate 101.
  • the second body region 103b is disposed inside the first body region 103a in plan view.
  • the JFET region 102j is formed in a self-aligning manner. For this reason, there is no variation in the overlap dimension between the body region 103 and the JFET region 102j. As a result, the variation in the current path is reduced, and the current can flow stably, so that variations in the on-resistance and the threshold voltage can be suppressed.
  • the semiconductor substrate 101 is prepared.
  • the semiconductor substrate 101 is, for example, a low resistance n-type 4H—SiC offcut substrate having a resistivity of 0.02 ⁇ cm.
  • the high-resistance first silicon carbide semiconductor layer 102 is epitaxially grown on the main surface of the semiconductor substrate 101 by, for example, a deposition method capable of epitaxial growth such as a CVD method.
  • a buffer layer made of SiC having a high impurity concentration may be deposited on the semiconductor substrate 101.
  • the impurity concentration of the buffer layer is, for example, 1 ⁇ 10 18 cm ⁇ 3 and the thickness thereof is, for example, 1 ⁇ m.
  • the first silicon carbide semiconductor layer 102 is made of, for example, n-type 4H—SiC, the impurity concentration is, for example, 1 ⁇ 10 16 cm ⁇ 3 , and the thickness is, for example, 10 ⁇ m.
  • the first silicon carbide semiconductor layer 102 is made of, for example, n-type 4H—SiC, the impurity concentration is, for example, 1 ⁇ 10 16 cm ⁇ 3 , and the thickness is, for example, 10 ⁇ m.
  • a polysilicon film 216 and a silicon nitride film 207 are sequentially deposited on the first silicon carbide semiconductor layer 102. Thereafter, the deposited polysilicon film 216 and silicon nitride film 207 are selectively etched to form a mask film 206A having a formation pattern of the JFET region 102j in the opening. Thereafter, N ions are implanted into first silicon carbide semiconductor layer 102 using mask film 206A as a mask to form JFET region 102j.
  • the impurity concentration of the JFET region 102j is, for example, 1 ⁇ 10 17 cm ⁇ 3 and the depth thereof is, for example, 0.5 ⁇ m.
  • a mask formation film (not shown) made of SiO 2 is deposited on the JFET region 102j including the mask film 206A by, for example, the CVD method. Thereafter, the surfaces of the mask formation film and the mask film 206A are planarized by a CMP method or the like. Subsequently, the mask film 206A is selectively removed to form a mask film 208 that is an inverted region of the mask film 206A from the mask formation film and has an opening in the formation pattern of the first body region. Thereafter, as shown in FIG. 10B, using the mask film 208 as a mask, for example, Al ions are implanted into the first silicon carbide semiconductor layer 102 to form the first body region 103a. As a result, the JFET region 102j is formed in a self-aligned manner with respect to the first body region 103a.
  • the polysilicon film 216 is thermally oxidized using the silicon nitride film 207 as a mask to form the mask film 208 in a self-aligning manner.
  • a silicon oxide film grows laterally from the side surface of the polysilicon film 216 to cover the JFET region 102j.
  • a mask film 208 is formed by selectively removing the mask film 206A so as to leave the grown silicon oxide film.
  • the silicon nitride film 207 is not necessarily provided in the case where a deposited film by a CVD method is used for the mask film 208.
  • a sidewall formation film 202 made of SiO 2 is formed on the first body region 103a including the mask film 208 by, eg, CVD.
  • Al ions are implanted through the sidewall formation film 202 of the first silicon carbide semiconductor layer 102 to form the second body region 103b.
  • An example of the ion implantation profile in the cross section AB in FIG. 10C is shown in FIG.
  • the ion implantation profile shown in FIG. 11 is obtained by implanting Al ions in four portions with the following implantation energy and dose.
  • An ion implantation profile in the first body region 103a is formed in the first two times, and an ion implantation profile in the second body region 103b is formed in the latter two times.
  • a resist pattern (not shown) having the formation pattern of the impurity region 104 in the opening is formed on the mask film 208 and the sidewall formation film 202 by lithography.
  • the sidewall formation film 202 is dry-etched using the resist pattern as a mask to form a sidewall 202a and a mask film 202b from the sidewall formation film 202.
  • the resist pattern is removed and, for example, N ions are implanted into the first body region 103a, thereby forming an impurity region 104 on the first body region 103a.
  • the width of the second body region 103b is smaller than the width of the first body region 103a in plan view in a direction perpendicular to the main surface of the semiconductor substrate 101. That is, the second body region 103b is disposed inside the first body region 103a in plan view. With this configuration, the dimension corresponding to the distance a2 between the adjacent second body regions 103b can be increased, so that the on-resistance can be reduced.
  • the JFET region 102j is formed in a self-aligned manner, fluctuations in the current path are reduced and current can be flowed stably, so that fluctuations in on-resistance and threshold voltage can be suppressed.
  • a JFET region 102j having a first conductivity type impurity having a concentration higher than that of the first silicon carbide semiconductor layer 102 is formed by ion implantation into the first silicon carbide semiconductor layer 102.
  • the present invention is not limited to this. That is, in the JFET region 102j in the semiconductor elements 100 and 300, ion implantation into the first silicon carbide semiconductor layer 102 is not performed, and the impurity concentration of the first conductivity type in the JFET region 102j is equal to that of the first silicon carbide semiconductor layer 102. It may be the same as the impurity concentration of one conductivity type.
  • FIG. 16 shows a modification of the semiconductor element in the case where the first conductivity type impurity concentration of the JFET region 102 j is the same as the first conductivity type impurity concentration of the first silicon carbide semiconductor layer 102.
  • the n-type MISFET has been described as the semiconductor elements 100 and 300.
  • a p-type MISFET can also be used.
  • the conductivity type of the semiconductor substrate, the first silicon carbide semiconductor layer (drift layer), and the source region may be p-type, and the conductivity type of the body region may be n-type.
  • the present invention is not limited to the MISFET, and various semiconductor elements in which electrodes are arranged on the semiconductor layer via an insulating film can be formed in the same manner.
  • an insulated gate bipolar transistor IGBT
  • the source electrode, drain electrode, and source region described in each embodiment are referred to as an emitter electrode, a collector electrode, and an emitter region, respectively.
  • an n-type IGBT can be obtained.
  • an n-type buffer layer may be disposed between the p-type semiconductor substrate and the n-type drift layer.
  • a p-type IGBT can be obtained.
  • a p-type buffer layer may be disposed between the n-type semiconductor substrate and the p-type drift layer.
  • the present invention can also be applied to semiconductor elements using other wide band gap semiconductors such as gallium nitride (GaN) or diamond (C).
  • GaN gallium nitride
  • C diamond
  • the configuration of the present disclosure can also be applied to a semiconductor element using silicon.
  • the semiconductor element and the manufacturing method thereof according to the present disclosure are useful as various semiconductor elements including a power device and the manufacturing method thereof.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

La présente invention concerne un élément semi-conducteur qui possède : une zone de corps à second type de conductivité dans une partie supérieure d'une première couche de semi-conducteur au carbure de silicium ; une zone d'impureté à premier type de conductivité dans une partie supérieure de ladite zone de corps ; et une seconde couche de semi-conducteur au carbure de silicium à premier type de conductivité prévue sur ladite première couche de semi-conducteur au carbure de silicium, ladite seconde couche de semi-conducteur au carbure de silicium étant en contact avec au moins une partie de ladite zone de corps et une partie de ladite zone d'impureté. Ladite zone de corps comprend une première zone de corps en contact avec la surface avant de ladite première couche de semi-conducteur au carbure de silicium, et une seconde zone de corps en contact avec la surface inférieure de ladite première zone de corps. Une concentration en impuretés de ladite première zone de corps est supérieure à celle de ladite seconde zone de corps. Ladite seconde zone de corps est positionnée sur le côté intérieur de ladite première zone de corps sur une vue en plan dans la direction perpendiculaire à la surface principale d'un substrat semi-conducteur, et au moins une partie de ladite seconde zone de corps est positionnée sous ladite zone d'impureté.
PCT/JP2013/006471 2012-11-28 2013-10-31 Élément semi-conducteur et procédé de fabrication de l'élément semi-conducteur WO2014083771A1 (fr)

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WO2016013182A1 (fr) * 2014-07-24 2016-01-28 パナソニックＩｐマネジメント株式会社 Élément semi-conducteur au carbure de silicium et procédé de fabrication
WO2016143099A1 (fr) * 2015-03-11 2016-09-15 株式会社日立製作所 Dispositif à semi-conducteur, son procédé de fabrication, et dispositif de conversion de puissance
WO2017081935A1 (fr) * 2015-11-12 2017-05-18 三菱電機株式会社 Dispositif à semi-conducteur au carbure de silicium et procédé de fabrication de dispositif à semi-conducteur au carbure de silicium
CN111430449A (zh) * 2020-04-01 2020-07-17 张清纯 一种mosfet器件及其制备工艺
JP2021061286A (ja) * 2019-10-03 2021-04-15 富士電機株式会社 窒化物半導体装置及び窒化物半導体装置の製造方法
CN113594041A (zh) * 2021-07-27 2021-11-02 厦门市三安集成电路有限公司 Mosfet器件的制备方法
US20220285503A1 (en) * 2021-03-08 2022-09-08 Fuji Electric Co., Ltd. Method for manufacturing nitride semiconductor device and nitride semiconductor device
EP4325579A4 (fr) * 2022-11-14 2024-10-02 Yuezhou Semiconductor Mfg Electronics Shaoxing Corp Dispositif mosfet et procédé de fabrication associé

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WO2016143099A1 (fr) * 2015-03-11 2016-09-15 株式会社日立製作所 Dispositif à semi-conducteur, son procédé de fabrication, et dispositif de conversion de puissance
JPWO2016143099A1 (ja) * 2015-03-11 2017-07-13 株式会社日立製作所 半導体装置およびその製造方法、並びに電力変換装置
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CN108352407A (zh) * 2015-11-12 2018-07-31 三菱电机株式会社 碳化硅半导体装置及碳化硅半导体装置的制造方法
WO2017081935A1 (fr) * 2015-11-12 2017-05-18 三菱電機株式会社 Dispositif à semi-conducteur au carbure de silicium et procédé de fabrication de dispositif à semi-conducteur au carbure de silicium
JP2021061286A (ja) * 2019-10-03 2021-04-15 富士電機株式会社 窒化物半導体装置及び窒化物半導体装置の製造方法
US11862687B2 (en) 2019-10-03 2024-01-02 Fuji Electric Co., Ltd. Nitride semiconductor device and method for fabricating nitride semiconductor device
JP7413701B2 (ja) 2019-10-03 2024-01-16 富士電機株式会社 窒化物半導体装置及び窒化物半導体装置の製造方法
CN111430449A (zh) * 2020-04-01 2020-07-17 张清纯 一种mosfet器件及其制备工艺
CN111430449B (zh) * 2020-04-01 2023-06-02 清纯半导体(宁波)有限公司 一种mosfet器件及其制备工艺
US20220285503A1 (en) * 2021-03-08 2022-09-08 Fuji Electric Co., Ltd. Method for manufacturing nitride semiconductor device and nitride semiconductor device
CN113594041A (zh) * 2021-07-27 2021-11-02 厦门市三安集成电路有限公司 Mosfet器件的制备方法
EP4325579A4 (fr) * 2022-11-14 2024-10-02 Yuezhou Semiconductor Mfg Electronics Shaoxing Corp Dispositif mosfet et procédé de fabrication associé

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