JPWO2017081935A1 - 炭化珪素半導体装置および炭化珪素半導体装置の製造方法 - Google Patents
炭化珪素半導体装置および炭化珪素半導体装置の製造方法 Download PDFInfo
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 296
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 296
- 239000004065 semiconductor Substances 0.000 title claims abstract description 190
- 238000000034 method Methods 0.000 title claims description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 29
- 239000012535 impurity Substances 0.000 claims abstract description 142
- 239000010410 layer Substances 0.000 claims abstract description 100
- 239000002344 surface layer Substances 0.000 claims abstract description 16
- 238000002513 implantation Methods 0.000 claims description 59
- 239000000758 substrate Substances 0.000 claims description 31
- 150000002500 ions Chemical class 0.000 claims description 16
- 230000005684 electric field Effects 0.000 description 72
- 238000000926 separation method Methods 0.000 description 33
- 238000004364 calculation method Methods 0.000 description 17
- 238000005468 ion implantation Methods 0.000 description 15
- 230000015556 catabolic process Effects 0.000 description 14
- 230000000694 effects Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 12
- 238000004088 simulation Methods 0.000 description 11
- 238000005259 measurement Methods 0.000 description 9
- 239000002184 metal Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 229910001423 beryllium ion Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 238000003763 carbonization Methods 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- IYLGZMTXKJYONK-ACLXAEORSA-N (12s,15r)-15-hydroxy-11,16-dioxo-15,20-dihydrosenecionan-12-yl acetate Chemical group O1C(=O)[C@](CC)(O)C[C@@H](C)[C@](C)(OC(C)=O)C(=O)OCC2=CCN3[C@H]2[C@H]1CC3 IYLGZMTXKJYONK-ACLXAEORSA-N 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- IYLGZMTXKJYONK-UHFFFAOYSA-N ruwenine Natural products O1C(=O)C(CC)(O)CC(C)C(C)(OC(C)=O)C(=O)OCC2=CCN3C2C1CC3 IYLGZMTXKJYONK-UHFFFAOYSA-N 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
Description
まず、本発明の実施の形態1における炭化珪素半導体装置の構成を説明する。なお、本発明においては、第1導電型をn型、第2導電型をp型として説明する。図1は、本発明の実施の形態1における炭化珪素半導体装置の構造を示す模式断面図である。本実施の形態1では炭化珪素半導体装置がMOSFETである場合について説明する。なお、図1は炭化珪素半導体装置のユニットセルの構成であり、炭化珪素半導体装置は図1のユニットセルが横方向に複数並んで構成される。
図17は、本発明の実施の形態2における炭化珪素半導体装置の構造を示す模式断面図である。図17において、図1と同じ符号を付けたものは、同一または対応する構成を示しており、その説明を省略する。本発明の実施の形態1とは、p型の第3ウェル領域をさらに備えた構成が相違している。
図18は、本発明の実施の形態3における炭化珪素半導体装置の構造を示す模式断面図である。図18において、図1と同じ符号を付けたものは、同一または対応する構成を示しており、その説明を省略する。本発明の実施の形態1とは、製造方法が異なり、第2ウェル領域を形成した後に第1ウェル領域を形成し、第2ウェル領域と同時に素子終端部の耐圧保持領域を形成する点が相違している。
図19は、本発明の実施の形態4における炭化珪素半導体装置の構造を示す模式断面図である。また、図20は、本実施の形態4における炭化珪素半導体装置の製造方法を示す図である。図19および図20において、図1および図2と同じ符号を付けたものは、同一または対応する構成を示しており、その説明を省略する。本発明の実施の形態1とは、製造方法が異なり、第2ウェル領域31を形成するための注入マスクを用いてソース領域を形成する点が相違している。
図21は本実施の形態5の炭化珪素半導体装置の製造方法を示す図である。本実施の形態5で説明する炭化珪素半導体装置は、実施の形態1で示した炭化珪素半導体装置と同様の構成である。本発明の実施の形態1とは、製造方法が異なり、第2ウェル領域を第1ウェル領域よりも先に形成し、第1ウェル領域30の形成には第2ウェル領域31の形成に用いた注入マスクを加工して利用する点が相違している。
20 炭化珪素ドリフト層、21 JFET領域、22 高濃度JFET領域
30 第1ウェル領域、31 第2ウェル領域、35 コンタクト領域
40 ソース領域
50 ゲート絶縁膜、55 層間絶縁膜
60 ゲート電極
70 表面側オーミック電極、71 裏面側オーミック電極
80 ソース電極、81 ドレイン電極
Claims (9)
- 炭化珪素半導体基板と、
前記炭化珪素基板上に設けられた第1導電型の炭化珪素ドリフト層と、
前記炭化珪素ドリフト層の表層部に距離W1離れて設けられ、第2電型の不純物濃度p1が、前記炭化珪素ドリフト層の第1導電型の不純物濃度n1に対してp1>n1の関係を有する第2導電型の一対の第1ウェル領域と、
前記第1ウェル領域の底部に隣接して、前記距離W1より0.8μm以上大きな距離W2離れて設けられ、第2導電型の不純物濃度p2が、前記炭化珪素ドリフト層の第1導電型の不純物濃度n1に対してp2>n1の関係を有し、前記p1に対して1.1×p2≦p1≦4.2×p2の関係を有する第2導電型の一対の第2ウェル領域と、
前記一対の第1ウェル領域のそれぞれの表層部に設けられた一対の第1導電型のソース領域と、
前記一対の第1ウェル領域間および前記一対の第2ウェル領域間に設けられ、第1導電型の不純物濃度n2が、前記n1に対してn2>n1の関係を有し、前記p2に対してn2<p2の関係を有し、前記第2ウェル領域よりも深く形成された第1導電型の高濃度JFET領域と、
を備えた炭化珪素半導体装置。 - 前記p2が、前記p1に対して1.8×p2≦p1≦3.6×p2の関係を有する請求項1に記載の炭化珪素半導体装置。
- 素子終端部に第2導電型の耐圧保持領域をさらに備え、前記耐圧保持領域の第2導電型の不純物濃度p5は、前記p2と等しい請求項1または2に記載の炭化珪素半導体装置。
- 平面視で、前記ソース領域の幅が、前記第2ウェル領域の幅の0.9倍以上1.1倍以下である請求項1から3のいずれか1項に記載の炭化珪素半導体装置。
- 前記第2ウェル領域の底部に隣接して、前記距離W2より大きな距離W3離れて設けられ、第2導電型の不純物濃度p4が、前記n1に対してp4>n1の関係を有し、前記p2に対してp4>p2の関係を有する第2導電型の一対の第3ウェル領域をさらに備えた請求項1から4のいずれか1項に記載の炭化珪素半導体装置。
- 炭化珪素基板上に第1導電型の炭化珪素ドリフト層を結晶成長させる第1工程と、
前記炭化珪素ドリフト層上に第1の注入マスクを形成し、前記炭化珪素ドリフト層内に第2導電型の不純物イオンを注入して、前記炭化珪素ドリフト層の表層部に第2導電型の第1ウェル領域を形成する第2工程と、
前記炭化珪素ドリフト層上に前記第1の注入マスクより幅が大きい第2の注入マスクを形成し、前記炭化珪素ドリフト層内に第2導電型の不純物イオンを注入して、前記第1ウェル領域の底部に隣接する領域に第2導電型の第2ウェル領域を形成する第3工程と、
前記第1ウェル領域の表層部に、第1導電型の不純物イオンを注入して第1導電型のソース領域を形成する第4工程と、
前記炭化珪素ドリフト層の表面から前記第1ウェル領域の深さを超える領域に第1導電型の不純物イオンを注入して第1導電型の高濃度JFET領域を形成する第5工程と、
を備える炭化珪素半導体装置の製造方法。 - 前記ソース領域は前記炭化珪素ドリフト層上に前記第2の注入マスクが形成された状態で前記第1導電型の不純物イオンを注入して形成される請求項6に記載の炭化珪素半導体装置の製造方法。
- 前記第1の注入マスクは前記第2の注入マスクの幅を小さく加工して形成される請求項6または7に記載の炭化珪素半導体装置の製造方法。
- 前記第3工程は、素子終端部にも第2導電型の不純物イオンを注入して、前記第2ウェル領域とともに前記素子終端部に第2導電型の耐圧保持領域を形成する請求項6から8のいずれか1項に記載の炭化珪素半導体装置の製造方法。
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