WO2014079101A1 - 液晶显示面板及液晶显示装置 - Google Patents

液晶显示面板及液晶显示装置 Download PDF

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Publication number
WO2014079101A1
WO2014079101A1 PCT/CN2012/085737 CN2012085737W WO2014079101A1 WO 2014079101 A1 WO2014079101 A1 WO 2014079101A1 CN 2012085737 W CN2012085737 W CN 2012085737W WO 2014079101 A1 WO2014079101 A1 WO 2014079101A1
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WIPO (PCT)
Prior art keywords
scan
shift register
liquid crystal
crystal display
scan line
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PCT/CN2012/085737
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English (en)
French (fr)
Inventor
张鑫
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/805,661 priority Critical patent/US20140139414A1/en
Publication of WO2014079101A1 publication Critical patent/WO2014079101A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a liquid crystal display panel and a liquid crystal display device.
  • FIG. 1 is a schematic structural diagram of a liquid crystal display panel of the prior art.
  • the prior art liquid crystal display panel 10 includes a scan driving chip 11, a plurality of rows of pixel units 12, and a plurality of scanning lines 13. .
  • the pixel unit 12 of each row is connected to the scan driving chip 11 through one scanning line 13. Therefore, the number of rows of the pixel unit 12 and the number of the scanning lines 13 are equal.
  • the scan driving chip 11 is generally designed to be relatively narrow, generally having a width of about 42 mm, and the display area of the liquid crystal display panel 10 is generally several hundred millimeters or more, so the scanning line 13 drawn from the scan driving chip 11 needs to pass.
  • the sector 14 (shown in Figure 1) is spaced apart.
  • the height of the sector 14 is typically 5 mm to 10 mm, and the height of the sector 14 is generally determined by the number of scan lines 13 and the spacing of the scan lines 13 in the sector 14. Therefore, when the number of the scan lines 13 is large, the pitch of the scan lines 13 in the sector area 14 needs to be designed to be small, which makes the fabrication difficult, and the signals between the scan lines 13 of the smaller pitch are easily disturbed. Affects display quality.
  • the technical problem to be solved by the present invention is to provide a liquid crystal display panel and a liquid crystal display device, which can reduce the scanning lines outputted on the scan driving chip, thereby reducing the number of scanning lines in the sector area and reducing the number of scanning driving chips, thereby reducing the number of scanning driving chips. Production difficulty and cost.
  • a technical solution adopted by the present invention is to provide a liquid crystal display panel including a scan driving chip for generating a scan signal, a plurality of shift registers for delaying a scan signal, and scanning a line for transmitting a scan signal, wherein the scan line includes a plurality of first scan lines and a plurality of second scan lines, and the first scan line is connected to the scan drive chip; a plurality of pixel unit groups, each of the pixel unit groups includes M rows of pixel units, each pixel unit group electrically connecting one first scan line and M-1 second scan lines, wherein, in each pixel unit group: the first row of pixel units are connected to the first scan line, m The row pixel unit is connected to the m-1th second scan line, wherein the M-1 second scan lines are respectively connected to the first scan line through M-1 shift registers; when the value of M is greater than 2, M-1 In the shift register: the scan signal input end of the first shift register is connected to the first scan line, and the scan
  • the value of t ranges from 10 to 20 ⁇ s.
  • a liquid crystal display panel including a scan driving chip for generating a scan signal, and a plurality of shift registers for delaying the scan signal; a scan line for transmitting a scan signal, wherein the scan line includes a plurality of first scan lines and a plurality of second scan lines, and the first scan line is connected to the scan drive chip; a plurality of pixel unit groups, each pixel unit group Including M rows of pixel units, each pixel unit group is electrically connected to a first scan line and M-1 second scan lines, wherein, in each pixel unit group, the first row of pixel units are connected to the first scan line, The m rows of pixel units are connected to the m-1th second scan line, wherein the M-1 second scan lines are respectively connected to the first scan line through M-1 shift registers, wherein M, m is an integer greater than 1. And m is less than or equal to M.
  • the shift register includes a scan signal input end and an output end.
  • the scan signal input end of the shift register is connected to the first scan line, and the output end of the shift register is connected to the second scan line.
  • the shift register further includes a feedback end, and the feedback end of the shift register is connected to the first scan line of the next-level pixel unit group.
  • the shift register comprises a scan signal input end and an output end.
  • the M-1 shift registers are: the scan signal input end of the first shift register is connected to the first scan line, the mth The scan signal input end of the shift register is connected to the output end of the m-1th shift register, and the output end of the mth shift register is connected to the mth second scan line and the input of the m+1th shift register end.
  • the shift register further includes a feedback end, and the output end of the mth shift register is further connected to the feedback end of the m-1th shift register.
  • the shift register includes a clock signal input end, and the clock signal input end of the shift register inputs a clock signal of time t.
  • the value of t ranges from 10 to 20 ⁇ s.
  • a liquid crystal display device including a liquid crystal display panel, the liquid crystal display panel including a scan driving chip for generating a scan signal, and a plurality of shifts a register for delaying the scan signal; a scan line for transmitting the scan signal, wherein the scan line includes a plurality of first scan lines and a plurality of second scan lines, and the first scan line is connected to the scan drive chip; a unit group, each pixel unit group includes M rows of pixel units, each pixel unit group electrically connecting one first scan line and M-1 second scan lines, wherein, in each pixel unit group: the first line of pixels The unit is connected to the first scan line, and the m-th pixel unit is connected to the m-1th second scan line, wherein the M-1 second scan lines are respectively connected to the first scan line through M-1 shift registers, wherein M, m is an integer greater than 1, and m is less than or equal to M.
  • the shift register includes a scan signal input end and an output end.
  • the scan signal input end of the shift register is connected to the first scan line, and the output end of the shift register is connected to the second scan line.
  • the shift register further includes a feedback end, and the feedback end of the shift register is connected to the first scan line of the next-level pixel unit group.
  • the shift register comprises a scan signal input end and an output end.
  • the M-1 shift registers are: the scan signal input end of the first shift register is connected to the first scan line, the mth The scan signal input end of the shift register is connected to the output end of the m-1th shift register, and the output end of the mth shift register is connected to the mth second scan line and the input of the m+1th shift register end.
  • the shift register further includes a feedback end, and the output end of the mth shift register is further connected to the feedback end of the m-1th shift register.
  • the shift register includes a clock signal input end, and the clock signal input end of the shift register inputs a clock signal of time t.
  • the value of t ranges from 10 to 20 ⁇ s.
  • the present invention connects the first scan line by setting the first row of pixel units in each pixel unit group, wherein the first scan line is connected to the scan driver chip, the mth The row pixel unit is connected to the m-1th second scan line, and the M-1 second scan lines are respectively connected to the first scan line through M-1 shift registers, wherein M, m is an integer greater than 1, and m is less than or equal to M. Therefore, each pixel unit group only needs one first scan line to provide a scan signal, and then is delayed by M-1 shift registers and then respectively sent to M-1 second scan lines to drive more Row pixel unit. Therefore, the number of first scanning lines and the number of scanning driving chips are reduced, thereby reducing the cost.
  • FIG. 1 is a schematic structural view of a liquid crystal display panel of the prior art
  • FIG. 2 is a schematic structural view of a liquid crystal display panel according to a first embodiment of the present invention
  • FIG. 3 is a schematic diagram showing a connection relationship between a pixel unit group and a shift register of a liquid crystal display panel according to a second embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of a shift register in the liquid crystal display panel shown in FIG. 3;
  • FIG. 5 is a transmission waveform diagram of a scan signal of the liquid crystal display panel shown in FIG. 3;
  • FIG. 6 is a schematic structural view of a liquid crystal display panel according to a third embodiment of the present invention.
  • FIG. 7 is a schematic diagram showing a connection relationship between a shift register and a pixel unit group of the liquid crystal display panel shown in FIG. 6;
  • FIG. 8 is a transmission waveform diagram of a scan signal of the liquid crystal display panel shown in FIG. 6;
  • Fig. 9 is a view showing the configuration of a liquid crystal display device of a fourth embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a liquid crystal display panel according to a first embodiment of the present invention.
  • the liquid crystal display panel 20 of the present embodiment includes a scan driving chip 21, a plurality of shift registers 22, scan lines 23, and a plurality of pixel unit groups 24.
  • the scan driving chip 21 is configured to generate a scan signal, wherein the scan driving chip 21 is disposed on the liquid crystal display panel 20 by a COF (chip on film) technology, and the waveform of the scan signal is preferably a width. It is a pulse of 10 ⁇ 20 ⁇ s.
  • the shift register 22 is for delaying the scanning signal, and the scanning line 23 is for transmitting the scanning signal.
  • the scan line 23 includes a plurality of first scan lines 231 and a plurality of second scan lines 232, and the first scan lines 231 are connected to the scan driving chip 21 through the sector area 25, specifically, the sector area 25 In this case, the pitch of each of the first scanning lines 231 drawn from the scan driving chip 21 becomes large.
  • Each pixel unit group 24 includes M rows of pixel units 241, each of which is electrically connected to a first scan line 231 and M-1 second scan lines 232. Specifically, in each pixel group 24 in the cell: a first row of the pixel unit 241 1 is connected to a first scan line 231, the m-th row of the pixel unit 241 is connected m 1-m of second scan lines 232 m-1, wherein The M-1 second scan lines 232 are respectively connected to the first scan line 231 through M-1 shift registers 22, wherein M, m is an integer greater than 1, and m is less than or equal to M.
  • the first row of pixel units of each pixel unit group 24 of the present embodiment is connected to the first scan line, and the pixel units of the remaining rows are respectively connected to the first scan line by a plurality of shift registers. Therefore, each pixel unit group only needs to connect the first scan line of the scan driving chip to drive the plurality of pixel units. Therefore, the number of first scan lines is reduced to reduce the number of first scan lines and the number of scan drive chips in the sector area, thereby reducing the difficulty and cost of fabrication.
  • FIG. 3 is a schematic diagram showing a connection relationship between a pixel unit group and a shift register of a liquid crystal display panel according to a second embodiment of the present invention.
  • the shift register 22 of this embodiment includes a scan signal input terminal ST, an output terminal OUT, a clock signal input terminal CLK, and a feedback terminal FB.
  • the value of M is greater than 2
  • the connection manner of the M-1 shift registers 22 corresponding to each pixel unit group 24 is: the scan signal input terminal ST of the first shift register 22 1 is connected to the first scan line 231, scan signal input terminal ST 22 m of the m-th shift registers m-1 connecting the first shift register 22 is the output terminal OUT of the m-1, m-m of the shift register 22 is connected to the first output terminal OUT m second scan lines 232 m and input terminals ST of the m+ 1th shift register 22 m+1 .
  • the m-th shift register 22 is connected to the output terminal OUT of the m feedback terminal FB of the m-1 th shift register 22 is m-1, and therefore, for the m-th shift register 22 is m, which is connected to the feedback terminal FB The output terminal OUT of the m+1th shift register 22 m+1 .
  • the clock signal input terminal CLK of the shift register 22 inputs a clock signal of time t, and the value range of t is preferably 10-20 ⁇ s.
  • FIG. 4 is a schematic structural diagram of a shift register in the liquid crystal display panel shown in FIG.
  • the scan signal input terminal ST is triggered.
  • the scan signal input terminal ST is at a high level, and the transistor T2 is turned on, so that the Q point is The potential rises, thereby turning on the transistor T1, so that the output terminal OUT outputs a clock signal, and at this time, the clock signal input terminal CLK is at a low level.
  • the scan signal stops inputting the scan signal input terminal ST
  • the scan signal input terminal ST is at a low level, so that the transistor T2 is turned off, but the potential of the Q point remains high, and the clock signal input terminal CLK is at a high level.
  • the output terminal OUT then outputs a high level, that is, outputs a scan signal to the second scan line 232.
  • the feedback terminal FB receives the high level signal of the second scan line 232, the transistors T3 and T4 are turned on, the potentials of the output terminals OUT and Q are pulled low, and the output of the output terminal OUT is turned off, thereby completing the shift.
  • One duty cycle of register 22 One duty cycle of register 22.
  • the waveform of the scan signal is preferably a pulse having a width of 10 to 20 ⁇ s
  • the time t of the clock signal input to the clock signal input terminal CLK of the shift register 22 preferably ranges from 10 to 20 ⁇ s. Therefore, the shift register 22 delays the scan signal transmitted from the scan line 23 of the previous stage by 10-20 ⁇ s. After the scan line 23 of the previous stage completes the transfer of the scan signal, the scan line 23 of the subsequent stage starts to transmit the scan signal.
  • FIG. 5 is a transmission waveform diagram of the scanning signal of the liquid crystal display panel shown in FIG. As shown in FIG.
  • the first scan line 231 transmits the scan signal output by the scan driving chip 21, and the first second scan line 232 1 transmits the first shift register 22.
  • a scanning signal output, 232 m of the m-th transmission of the second m-th scanning line is a scanning signal output from the shift register 22 is m.
  • FIG. 6 is a schematic structural view of a liquid crystal display panel according to a third embodiment of the present invention.
  • each pixel unit group 24 includes two rows of pixel units 241, and each pixel unit group 24 corresponds to one shift register 22.
  • FIG. 7 Please refer to FIG. 7 for the connection relationship between the specific shift register 22 and the pixel unit group 24.
  • the shift register 22 includes a scan signal input terminal ST, an output terminal OUT, a clock signal input terminal CLK, and a feedback terminal FB.
  • the scan signal input terminal ST of the shift register 22 is connected to the first scan line 231, and the output terminal OUT of the shift register 22 is connected to the second scan line 232.
  • the feedback terminal FB of the shift register 22 is connected to the first scan line 231 of the next-stage pixel unit group 24.
  • the clock signal input terminal CLK of the shift register 22 inputs a clock signal of time t, and the value range of t is preferably 10-20 ⁇ s.
  • the time t of the clock signal input to the clock signal input terminal CLK of the shift register 22 preferably ranges from 10 to 20 ⁇ s. Therefore, the shift register 22 delays the scan signal transmitted by the first scan line 231 by 10-20 ⁇ s. After the first scan line 231 completes the transfer of the scan signal, the second scan line 232 starts transmitting the scan signal.
  • FIG. 8 is a transmission waveform diagram of the scanning signal of the liquid crystal display panel shown in FIG. 6. As shown in FIG. 8, in one pixel unit group 24, the first scan line 231 transmits the scan signal output from the scan driving chip 21, and the second scan line 232 transmits the scan signal output from the shift register 22.
  • FIG. 9 is a schematic structural diagram of a liquid crystal display device according to a fourth embodiment of the present invention.
  • the liquid crystal display device 90 of the present embodiment includes a liquid crystal display panel 91 and a backlight module 92 that supplies a light source to the liquid crystal display panel 91.
  • the liquid crystal display panel 91 is the liquid crystal display panel 20 shown in the foregoing, and the structure thereof will not be described herein.
  • the first row of pixel cells of each pixel cell group of the present invention is connected to the first scan line, and the pixel cells of the remaining rows are respectively connected to the first scan line by a plurality of shift registers. Therefore, each pixel unit group only needs to connect the first scan line of the scan driving chip to drive the plurality of pixel units. Therefore, the number of first scan lines is reduced to reduce the number of first scan lines and the number of scan drive chips in the sector area, thereby reducing the difficulty and cost of fabrication.

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

提供了一种液晶显示面板（20）及液晶显示装置（90）。该液晶显示面板（20）包括多个移位寄存器（22）；扫描线（23），包括多条第一扫描线（231）和多条第二扫描线（232）；多个像素单元组（24），在每个像素单元组（24）中：第一行像素单元（241）连接第一扫描线（231），第m行像素单元（241m）连接第m-1条第二扫描线（232m-1），其中，M-1条第二扫描线（232）分别通过M-1个移位寄存器（22）连接第一扫描线（231），其中，M，m为大于1的整数，且m小于或等于M。通过上述方式，能够减少第一扫描线（231）的数量和扫描驱动芯片（21）的数量，进而降低成本。

Description

液晶显示面板及液晶显示装置
【技术领域】
本发明涉及显示技术领域，特别是涉及一种液晶显示面板及液晶显示装置。
【背景技术】
请参阅图1，图1是现有技术的液晶显示面板的结构示意图，如图1所示，现有技术的液晶显示面板10包括扫描驱动芯片11、多行像素单元12和多条扫描线13。其中，每行像素单元12通过一条扫描线13连接扫描驱动芯片11。因此，像素单元12的行数和扫描线13的条数是相等的。
为了节省成本，扫描驱动芯片11通常设计得比较窄，一般宽度约42毫米，而液晶显示面板10的显示区一般宽度都在几百毫米以上，所以从扫描驱动芯片11引出的扫描线13需要经过扇形区域14（如图1所示）以变大间距。扇形区域14的高度通常为5毫米~10毫米，并且扇形区域14的高度通常由扫描线13的数量和扇形区域14中扫描线13的间距决定。因此，当扫描线13的数量较多时，扫描线13在扇形区域14中的间距就需要设计得很小，提高了制作的难度，并且较小间距的扫描线13之间的信号容易受到干扰，影响显示品质。
【发明内容】
本发明主要解决的技术问题是提供一种液晶显示面板及液晶显示装置，能够减少扫描驱动芯片上输出的扫描线，从而减少扇形区域中扫描线的数量以及减少扫描驱动芯片的数量，因此可以降低制作难度和成本。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种液晶显示面板，该液晶显示面板包括扫描驱动芯片，用于产生扫描信号；多个移位寄存器，用于延迟扫描信号；扫描线，用于传输扫描信号，其中，扫描线包括多条第一扫描线和多条第二扫描线，并且第一扫描线与扫描驱动芯片连接；多个像素单元组，每个像素单元组包括M行像素单元，每个像素单元组电连接一条第一扫描线和M-1条第二扫描线，其中，在每个像素单元组中：第一行像素单元连接第一扫描线，第m行像素单元连接第m-1条第二扫描线，其中，M-1条第二扫描线分别通过M-1个移位寄存器连接第一扫描线；当M的值大于2时，M-1个移位寄存器中：第一个移位寄存器的扫描信号输入端连接第一扫描线，第m个移位寄存器的扫描信号输入端连接第m-1个移位寄存器的输出端，第m个移位寄存器的输出端连接第m条第二扫描线以及第m+1个移位寄存器的输入端，移位寄存器的时钟信号输入端输入时间为t的时钟信号，其中，M，m为大于1的整数，且m小于或等于M。
其中，t的取值范围为10-20μs。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示面板，该液晶显示面板包括扫描驱动芯片，用于产生扫描信号；多个移位寄存器，用于延迟扫描信号；扫描线，用于传输扫描信号，其中，扫描线包括多条第一扫描线和多条第二扫描线，并且第一扫描线与扫描驱动芯片连接；多个像素单元组，每个像素单元组包括M行像素单元，每个像素单元组电连接一条第一扫描线和M-1条第二扫描线，其中，在每个像素单元组中：第一行像素单元连接第一扫描线，第m行像素单元连接第m-1条第二扫描线，其中，M-1条第二扫描线分别通过M-1个移位寄存器连接第一扫描线，其中，M，m为大于1的整数，且m小于或等于M。
其中，移位寄存器包括扫描信号输入端和输出端，当M的值等于2时，移位寄存器的扫描信号输入端连接第一扫描线，移位寄存器的输出端连接第二扫描线。
其中，移位寄存器进一步包括反馈端，移位寄存器的反馈端连接下一级像素单元组的所述第一扫描线。
其中，移位寄存器包括扫描信号输入端和输出端，当M的值大于2时，M-1个移位寄存器中：第一个移位寄存器的扫描信号输入端连接第一扫描线，第m个移位寄存器的扫描信号输入端连接第m-1个移位寄存器的输出端，第m个移位寄存器的输出端连接第m条第二扫描线以及第m+1个移位寄存器的输入端。
其中，移位寄存器进一步包括反馈端，第m个移位寄存器的输出端进一步连接第m-1个移位寄存器的反馈端。
其中，移位寄存器包括时钟信号输入端，移位寄存器的时钟信号输入端输入时间为t的时钟信号。
其中，t的取值范围为10-20μs。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示装置，该液晶显示装置包括液晶显示面板，液晶显示面板包括扫描驱动芯片，用于产生扫描信号；多个移位寄存器，用于延迟扫描信号；扫描线，用于传输扫描信号，其中，扫描线包括多条第一扫描线和多条第二扫描线，并且第一扫描线与扫描驱动芯片连接；多个像素单元组，每个像素单元组包括M行像素单元，每个像素单元组电连接一条第一扫描线和M-1条第二扫描线，其中，在每个像素单元组中：第一行像素单元连接第一扫描线，第m行像素单元连接第m-1条第二扫描线，其中，M-1条第二扫描线分别通过M-1个移位寄存器连接第一扫描线，其中，M，m为大于1的整数，且m小于或等于M。
其中，移位寄存器包括扫描信号输入端和输出端，当M的值等于2时，移位寄存器的扫描信号输入端连接第一扫描线，移位寄存器的输出端连接第二扫描线。
其中，移位寄存器进一步包括反馈端，移位寄存器的反馈端连接下一级像素单元组的所述第一扫描线。
其中，移位寄存器包括扫描信号输入端和输出端，当M的值大于2时，M-1个移位寄存器中：第一个移位寄存器的扫描信号输入端连接第一扫描线，第m个移位寄存器的扫描信号输入端连接第m-1个移位寄存器的输出端，第m个移位寄存器的输出端连接第m条第二扫描线以及第m+1个移位寄存器的输入端。
其中，移位寄存器进一步包括反馈端，第m个移位寄存器的输出端进一步连接第m-1个移位寄存器的反馈端。
其中，移位寄存器包括时钟信号输入端，移位寄存器的时钟信号输入端输入时间为t的时钟信号。
其中，t的取值范围为10-20μs。
本发明的有益效果是：区别于现有技术的情况，本发明通过设置每个像素单元组中的第一行像素单元连接第一扫描线，其中，第一扫描线连接扫描驱动芯片，第m行像素单元连接第m-1条第二扫描线，并且M-1条第二扫描线分别通过M-1个移位寄存器连接第一扫描线，其中，M，m为大于1的整数，且m小于或等于M，因此，每个像素单元组只需一条第一扫描线提供扫描信号，然后通过M-1个移位寄存器延迟后分别输送到M-1条第二扫描线，以驱动多行像素单元。因此减少了第一扫描线的数量和扫描驱动芯片的数量，进而降低了成本。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是现有技术的液晶显示面板的结构示意图；
图2是本发明第一实施例的液晶显示面板的结构示意图；
图3是本发明第二实施例的液晶显示面板的像素单元组与移位寄存器的连接关系示意图；
图4是图3所示的液晶显示面板中的移位寄存器的结构示意图；
图5是图3所示的液晶显示面板的扫描信号的传输波形图；
图6是本发明第三实施例的液晶显示面板的结构示意图；
图7是图6所示的液晶显示面板的移位寄存器与像素单元组的连接关系示意图；
图8是图6所示的液晶显示面板的扫描信号的传输波形图；
图9是本发明第四实施例的液晶显示装置的结构示意图。
【具体实施方式】
请参阅图2，图2是本发明第一实施的液晶显示面板的结构示意图。如图2所示，本实施例的液晶显示面板20包括扫描驱动芯片21、多个移位寄存器22、扫描线23以及多个像素单元组24。
本实施例中，扫描驱动芯片21用于产生扫描信号，其中，扫描驱动芯片21是通过COF（chip on film，覆晶薄膜）技术设置在液晶显示面板20上，扫描信号的波形优选为一个宽度为10~20μs的脉冲。移位寄存器22用于延迟扫描信号，扫描线23用于传输扫描信号。本实施例中，扫描线23包括多条第一扫描线231和多条第二扫描线232，并且第一扫描线231通过扇形区域25后与扫描驱动芯片21连接，具体而言，扇形区域25中，每条从扫描驱动芯片21引出的第一扫描线231的间距变大。每个像素单元组24包括M行像素单元241，每个像素单元组24电连接一条第一扫描线231和M-1条第二扫描线232。具体而言，在每个像素单元组24中：第一行像素单元241 1 连接第一扫描线231，第m行像素单元241 m 连接第m-1条第二扫描线232 m-1 ，其中，M-1条第二扫描线232分别通过M-1个移位寄存器22连接第一扫描线231，其中，M，m为大于1的整数，且m小于或等于M。
区别与现有技术的情况，本实施例的每个像素单元组24的第一行像素单元连接第一扫描线，其余行的像素单元分别通过多个移位寄存器连接到第一扫描线。因此，每个像素单元组只需要一条连接扫描驱动芯片的第一扫描线即可实现对多个像素单元的驱动。因此减少了第一扫描线的数量从而减少了扇形区域的第一扫描线的数量和扫描驱动芯片的数量，进而降低了制作的难度和成本。
本发明进一步提供第二实施例，其在第一实施例的基础上进行详述。如图3所示，图3是本发明第二实施例的液晶显示面板的像素单元组与移位寄存器的连接关系示意图。
本实施例的移位寄存器22包括扫描信号输入端ST、输出端OUT、时钟信号输入端CLK以及反馈端FB。本实施例中，M的值大于2，则每个像素单元组24对应的M-1个移位寄存器22的连接方式为：第一个移位寄存器22 1 的扫描信号输入端ST连接第一扫描线231，第m个移位寄存器22 m 的扫描信号输入端ST连接第m-1个移位寄存器22 m-1 的输出端OUT，第m个移位寄存器22 m 的输出端OUT连接第m条第二扫描线232 m 以及第m+1个移位寄存器22 m+1 的输入端ST。进一步的，第m个移位寄存器22 m 的输出端OUT连接第m-1个移位寄存器22 m-1 的反馈端FB，因此，对于第m个移位寄存器22 m ，其反馈端FB连接的是第m+1个移位寄存器22 m+1 的输出端OUT。其中，移位寄存器22的时钟信号输入端CLK输入时间为t的时钟信号，并且t的取值范围优选为10-20μs。
以下说明移位寄存器的具体工作原理。
请参阅图4，图4是图3所示的液晶显示面板中的移位寄存器的结构示意图。如图4所示，当扫描信号输入移位寄存器22的扫描信号输入端ST时，扫描信号输入端ST被触发，此时扫描信号输入端ST为高电平，晶体管T2打开，使得Q点的电位升高，进而打开晶体管T1，使得输出端OUT输出时钟信号，此时时钟信号输入端CLK为低电平。当扫描信号停止输入扫描信号输入端ST时，扫描信号输入端ST为低电平，使得晶体管T2关闭，但是Q点的电位依然保持高电平，此时时钟信号输入端CLK为高电平，于是输出端OUT输出高电平，即输出扫描信号到第二扫描线232。同时，反馈端FB接收到第二扫描线232的高电平信号，则开启晶体管T3和T4，将输出端OUT和Q点的电位拉低，进而关闭输出端OUT的输出，从而完成了移位寄存器22的一个工作周期。
由于扫描信号的波形优选为一个宽度为10~20μs的脉冲，而移位寄存器22的时钟信号输入端CLK输入的时钟信号的时间t的取值范围优选为10-20μs。因此，移位寄存器22对前一级的扫描线23传输的扫描信号延迟10-20μs，待前一级的扫描线23完成扫描信号的传输后，后一级的扫描线23开始传输扫描信号。对应的扫描信号的传输波形请参阅图5，图5是图3所示液晶显示面板的扫描信号的传输波形图。如图5所示，在一个像素单元组24中：第一扫描线231传输的是扫描驱动芯片21输出的扫描信号，第一条第二扫描线232 1 传输的是第一个移位寄存器22 1 输出的扫描信号，第m条第二扫描线232 m 传输的是第m个移位寄存器22 m 输出的扫描信号。
本发明进一步提供第三实施例，其在第一实施例的基础上进行详述。如图6所示，图6是本发明第三实施例的液晶显示面板的结构示意图。
本实施例中，M的值等于2，即每个像素单元组24包括两行像素单元241，则每个像素单元组24对应一个移位寄存器22。具体的移位寄存器22与像素单元组24的连接关系请参考图7。
如图7所示，移位寄存器22包括扫描信号输入端ST、输出端OUT、时钟信号输入端CLK以及反馈端FB。其中，移位寄存器22的扫描信号输入端ST连接第一扫描线231，移位寄存器22的输出端OUT连接第二扫描线232。进一步地，移位寄存器22的反馈端FB连接下一级像素单元组24的第一扫描线231。其中，移位寄存器22的时钟信号输入端CLK输入时间为t的时钟信号，并且t的取值范围优选为10-20μs。
由于扫描信号的波形优选为一个宽度为10~20μs的脉冲，而移位寄存器22的时钟信号输入端CLK输入的时钟信号的时间t的取值范围优选为10-20μs。因此，移位寄存器22对第一扫描线231传输的扫描信号延迟10-20μs，待第一扫描线231完成扫描信号的传输后，第二扫描线232开始传输扫描信号。对应的扫描信号的传输波形请参阅图8，图8是图6所示的液晶显示面板的扫描信号的传输波形图。如图8所示，在一个像素单元组24中：第一扫描线231传输的是扫描驱动芯片21输出的扫描信号，第二扫描线232传输的是移位寄存器22输出的扫描信号。
请参阅图9，图9是本发明第四实施例的液晶显示装置的结构示意图。如图9所示，本实施例的液晶显示装置90包括液晶显示面板91以及为液晶显示面板91提供光源的背光模组92。其中液晶显示面板91为前文所示的液晶显示面板20，其结构在此不再赘述。
综上所述，本发明的每个像素单元组的第一行像素单元连接第一扫描线，其余行的像素单元分别通过多个移位寄存器连接到第一扫描线。因此，每个像素单元组只需要一条连接扫描驱动芯片的第一扫描线即可实现对多个像素单元的驱动。因此减少了第一扫描线的数量从而减少了扇形区域的第一扫描线的数量和扫描驱动芯片的数量，进而降低了制作的难度和成本。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (16)

  1. 一种液晶显示面板，其中，所述液晶显示面板包括：
    扫描驱动芯片，用于产生扫描信号；
    多个移位寄存器，用于延迟所述扫描信号；
    扫描线，用于传输所述扫描信号，其中，所述扫描线包括多条第一扫描线和多条第二扫描线，并且所述第一扫描线与所述扫描驱动芯片连接；
    多个像素单元组，每个所述像素单元组包括M行像素单元，每个所述像素单元组电连接一条所述第一扫描线和M-1条所述第二扫描线，其中，在每个所述像素单元组中：第一行所述像素单元连接所述第一扫描线，第m行所述像素单元连接第m-1条所述第二扫描线，其中，M-1条所述第二扫描线分别通过M-1个所述移位寄存器连接所述第一扫描线；
    当所述M的值大于2时，所述M-1个所述移位寄存器中：第一个所述移位寄存器的扫描信号输入端连接所述第一扫描线，第m个所述移位寄存器的扫描信号输入端连接第m-1个所述移位寄存器的输出端，第m个所述移位寄存器的输出端连接第m条所述第二扫描线以及第m+1个所述移位寄存器的输入端，所述移位寄存器的时钟信号输入端输入时间为t的时钟信号，其中，M，m为大于1的整数，且m小于或等于M。
  2. 根据权利要求1所述的液晶显示面板，其中，所述t的取值范围为10-20μs。
  3. 一种液晶显示面板，其中，所述液晶显示面板包括：
    扫描驱动芯片，用于产生扫描信号；
    多个移位寄存器，用于延迟所述扫描信号；
    扫描线，用于传输所述扫描信号，其中，所述扫描线包括多条第一扫描线和多条第二扫描线，并且所述第一扫描线与所述扫描驱动芯片连接；
    多个像素单元组，每个所述像素单元组包括M行像素单元，每个所述像素单元组电连接一条所述第一扫描线和M-1条所述第二扫描线，其中，在每个所述像素单元组中：第一行所述像素单元连接所述第一扫描线，第m行所述像素单元连接第m-1条所述第二扫描线，其中，M-1条所述第二扫描线分别通过M-1个所述移位寄存器连接所述第一扫描线，其中，M，m为大于1的整数，且m小于或等于M。
  4. 根据权利要求3所述的液晶显示面板，其中，所述移位寄存器包括扫描信号输入端和输出端，当所述M的值等于2时，所述移位寄存器的扫描信号输入端连接所述第一扫描线，所述移位寄存器的输出端连接所述第二扫描线。
  5. 根据权利要求4所述的液晶显示面板，其中，所述移位寄存器进一步包括反馈端，所述移位寄存器的反馈端连接下一级所述像素单元组的所述第一扫描线。
  6. 根据权利要求3所述的液晶显示面板，其中，所述移位寄存器包括扫描信号输入端和输出端，当所述M的值大于2时，所述M-1个所述移位寄存器中：第一个所述移位寄存器的扫描信号输入端连接所述第一扫描线，第m个所述移位寄存器的扫描信号输入端连接第m-1个所述移位寄存器的输出端，第m个所述移位寄存器的输出端连接第m条所述第二扫描线以及第m+1个所述移位寄存器的输入端。
  7. 根据权利要求6所述的液晶显示面板，其中，所述移位寄存器进一步包括反馈端，第m个所述移位寄存器的输出端进一步连接第m-1个所述移位寄存器的反馈端。
  8. 根据权利要求3所述的液晶显示面板，其中，所述移位寄存器包括时钟信号输入端，所述移位寄存器的时钟信号输入端输入时间为t的时钟信号。
  9. 根据权利要求8所述的液晶显示面板，其中，所述t的取值范围为10-20μs。
  10. 一种液晶显示装置，其中，所述液晶显示装置包括液晶显示面板，所述液晶显示面板包括：
    扫描驱动芯片，用于产生扫描信号；
    多个移位寄存器，用于延迟所述扫描信号；
    扫描线，用于传输所述扫描信号，其中，所述扫描线包括多条第一扫描线和多条第二扫描线，并且所述第一扫描线与所述扫描驱动芯片连接；
    多个像素单元组，每个所述像素单元组包括M行像素单元，每个所述像素单元组电连接一条所述第一扫描线和M-1条所述第二扫描线，其中，在每个所述像素单元组中：第一行所述像素单元连接所述第一扫描线，第m行所述像素单元连接第m-1条所述第二扫描线，其中，M-1条所述第二扫描线分别通过M-1个所述移位寄存器连接所述第一扫描线，其中，M，m为大于1的整数，且m小于或等于M。
  11. 根据权利要求10所述的液晶显示装置，其中，所述移位寄存器包括扫描信号输入端和输出端，当所述M的值等于2时，所述移位寄存器的扫描信号输入端连接所述第一扫描线，所述移位寄存器的输出端连接所述第二扫描线。
  12. 根据权利要求11所述的液晶显示装置，其中，所述移位寄存器进一步包括反馈端，所述移位寄存器的反馈端连接下一级所述像素单元组的所述第一扫描线。
  13. 根据权利要求10所述的液晶显示装置，其中，所述移位寄存器包括扫描信号输入端和输出端，当所述M的值大于2时，所述M-1个所述移位寄存器中：第一个所述移位寄存器的扫描信号输入端连接所述第一扫描线，第m个所述移位寄存器的扫描信号输入端连接第m-1个所述移位寄存器的输出端，第m个所述移位寄存器的输出端连接第m条所述第二扫描线以及第m+1个所述移位寄存器的输入端。
  14. 根据权利要求13所述的液晶显示装置，其中，所述移位寄存器进一步包括反馈端，第m个所述移位寄存器的输出端进一步连接第m-1个所述移位寄存器的反馈端。
  15. 根据权利要求10所述的液晶显示装置，其中，所述移位寄存器包括时钟信号输入端，所述移位寄存器的时钟信号输入端输入时间为t的时钟信号。
  16. 根据权利要求15所述的液晶显示装置，其中，所述t的取值范围为10-20μs。
PCT/CN2012/085737 2012-11-22 2012-12-03 液晶显示面板及液晶显示装置 Ceased WO2014079101A1 (zh)

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