WO2014059688A1 - 像素单元及主动矩阵式平面显示装置 - Google Patents

像素单元及主动矩阵式平面显示装置 Download PDF

Info

Publication number
WO2014059688A1
WO2014059688A1 PCT/CN2012/083485 CN2012083485W WO2014059688A1 WO 2014059688 A1 WO2014059688 A1 WO 2014059688A1 CN 2012083485 W CN2012083485 W CN 2012083485W WO 2014059688 A1 WO2014059688 A1 WO 2014059688A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
scan line
line
pixel unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2012/083485
Other languages
English (en)
French (fr)
Inventor
王金杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US13/701,871 priority Critical patent/US9182636B2/en
Publication of WO2014059688A1 publication Critical patent/WO2014059688A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel unit and an active matrix flat display device.
  • FIG. 1 is a schematic structural diagram of a prior art active matrix flat display device.
  • the active matrix type flat display device 10 includes a plurality of pixel units, each of which includes a thin film transistor.
  • the pixel unit P1 includes a thin film transistor T1
  • the pixel unit P2 includes a thin film transistor T2.
  • FIG. 2 is an enlarged view of the thin film crystal T1 and the thin film transistor T2, as shown in FIG. 2, the gate and the drain of the thin film transistor T1.
  • the parasitic capacitance formed by the overlap area is C gd 1
  • the parasitic capacitance formed by the overlapping area of the gate and the drain of the thin film transistor T2 is C gd 2 due to the overlapping area of the gate and the drain of the thin film transistors T1 and T2
  • the area shown by the broken line in the figure is inconsistent, resulting in C gd 1 ⁇ C gd 2 , thus causing uneven display of gray scale between pixel units P1 and P2, resulting in display of unevenness (Mura), flicker, etc. defect.
  • the technical problem to be solved by the present invention is to provide a pixel unit and an active matrix type flat display device capable of maintaining the parasitic capacitance of a thin film transistor group in each pixel unit in an active matrix type flat display device, thereby avoiding display defects. .
  • a technical solution adopted by the present invention is to provide a pixel unit including: a first scan line and a second scan line disposed in parallel intervals; a data line, and a first scan line and a The two scan lines are intersected; the pixel electrodes are electrically connected to the first scan line, the second scan line, and the data line, respectively; the thin film transistor group is electrically connected to the first scan line, the second scan line, the data line, and the pixel electrode, respectively;
  • the thin film transistor group includes a first thin film transistor and a second thin film transistor.
  • the gate of the first thin film transistor is connected to the first scan line, the source of the first thin film transistor is connected to the data line, and the drain and the pixel electrode of the first thin film transistor pass The first via hole is electrically connected; the gate of the second thin film transistor is connected to the second scan line, the source of the second thin film transistor is connected to the data line, and the drain of the second thin film transistor and the pixel electrode are electrically connected through the second via hole
  • the first via hole and the second via hole are respectively disposed at diagonal positions of the
  • the first scan line and the second scan line are connected to each other end to end and transmit the same scan driving signal.
  • a pixel unit including: a first scan line and a second scan line disposed in parallel intervals; a data line, and a first scan line and The second scan lines are arranged to intersect; the pixel electrodes are electrically connected to the first scan line, the second scan line and the data line respectively; and the thin film transistor group is electrically connected to the first scan line, the second scan line, the data line and the pixel electrode respectively
  • the gate of the first thin film transistor is connected to the first scan line, the source of the first thin film transistor is connected to the data line, and the drain of the first thin film transistor and the pixel electrode are electrically connected through the first via hole;
  • the second thin film transistor is The gate is connected to the second scan line, the source of the second thin film transistor is connected to the data line, and the drain of the second thin film transistor and the pixel electrode are electrically connected through the second via.
  • the first scan line and the second scan line are connected to each other end to end and transmit the same scan driving signal.
  • the first via hole and the second via hole are respectively disposed at diagonal positions of the pixel electrode.
  • the pixel unit includes a center line, and the center line is parallel to the data line and divides the area of the pixel unit.
  • the first via hole and the second via hole are respectively disposed on two sides of the center line, and the first via hole is perpendicular to the center line. The distance is equal to the vertical distance from the second via to the centerline.
  • an active matrix type flat display device including a display area and a non-display area, the display area being provided with a plurality of pixel units
  • the pixel unit includes: a first scan line and a second scan line disposed in parallel; the data line is disposed to intersect the first scan line and the second scan line; and the pixel electrode is respectively connected to the first scan line and the second scan line Electrically connected to the data line; the thin film transistor group is electrically connected to the first scan line, the second scan line, the data line and the pixel electrode respectively; wherein the thin film transistor group comprises a first thin film transistor and a second thin film transistor, and the thin film transistor group
  • the gate of the first thin film transistor is connected to the first scan line, the source of the first thin film transistor is connected to the data line, and the drain of the first thin film transistor and the pixel electrode are electrically connected through the first via hole;
  • the second thin film transistor is The gate is connected to the second scan line, the source of the second thin film transistor is connected to the data line, and the drain of the second thin film transistor and the pixel electrode are electrically connected through the second via.
  • the first scan line and the second scan line are connected to each other at the beginning and the end of the non-display area, and transmit the same scan driving signal.
  • the first via hole and the second via hole are respectively disposed at diagonal positions of the pixel electrode.
  • the pixel unit includes a center line, and the center line is parallel to the data line and divides the area of the pixel unit.
  • the first via hole and the second via hole are respectively disposed on two sides of the center line, and the first via hole is perpendicular to the center line. The distance is equal to the vertical distance from the second via to the centerline.
  • the sizes of the first thin film transistor and the second thin film transistor are correspondingly increased or decreased according to the size of the active matrix type flat display device.
  • the present invention provides a first scan line and a second scan line for providing two branches of the same scan driving signal in parallel in one pixel region, and when one of the branches is broken, the scan driving signal can be bypassed. Automatic repair is achieved, thus overcoming display defects due to scan line defects.
  • FIG. 1 is a schematic structural view of a prior art active matrix type flat display device
  • FIG. 2 is an enlarged schematic structural view of a thin film transistor at two different positions of the active matrix type flat display device of FIG. 1;
  • FIG. 3 is a schematic structural view of an active matrix type flat display device of the present invention.
  • FIG. 4 is a schematic structural view of a pixel unit in the active matrix type display device shown in FIG. 3 in an ideal exposure state
  • FIG. 5 is a schematic structural view of a pixel unit in the active matrix type flat display device shown in FIG. 3 in an exposure state in which a cover offset occurs.
  • FIG. 3 is a schematic structural diagram of an active matrix type flat display device according to the present invention.
  • the active matrix type flat display device 300 of the present invention includes a display area 301 and a non-display area 302.
  • a plurality of pixel units 30 are provided in the display area 301.
  • FIG. 4 is a schematic structural diagram of a pixel unit in the active matrix type flat display device shown in FIG.
  • the pixel unit 30 of the present invention includes a first scan line 31, a second scan line 32, a data line 33, a pixel electrode 35, and a thin film transistor group 36.
  • the first scan line 31 and the second scan line 32 are arranged in parallel in the display area 301, and the data lines 33 are perpendicularly intersected with the first scan line 31 and the second scan line 32, respectively.
  • the pixel electrode 35 is electrically connected to the first scan line 31, the second scan line 32, and the data line 33, respectively.
  • the thin film transistor group 36 is electrically connected to the first scan line 31, the second scan line 32, the data line 33, and the pixel electrode 35, specifically:
  • the thin film transistor group 36 includes a first thin film transistor 37 and a second thin film transistor 38.
  • the gate 371 of the first thin film transistor 37 is connected to the first scan line 31, and the gate 381 of the second thin film transistor 38 is connected to the second scan line 32.
  • the source 372 of the first thin film transistor 37 and the source 382 of the second thin film transistor 38 are connected to the data line 33.
  • the drain electrode 373 of the first thin film transistor 37 is electrically connected to the pixel electrode 35 through the first via hole 351, and the drain electrode 383 of the second thin film transistor 38 is electrically connected to the pixel electrode 35 through the second via hole 352.
  • the pixel unit 35 includes a center line 353.
  • the center line 353 is parallel to the data line 33 and divides the area of the pixel unit 30.
  • the first via hole 351 and the second via hole 352 are respectively disposed on the center line 353.
  • the side, and the vertical distance D1 of the first via 351 to the center line 353 is equal to the vertical distance D2 of the second via 352 to the center line 353.
  • the first via hole 351 and the second via hole 352 are preferably disposed at diagonal positions of the pixel electrode 35, respectively.
  • different lengths and widths of the thin film transistors are correspondingly arranged according to different sizes of the active matrix type flat display device 300.
  • the size of the first thin film transistor 37 and the second thin film transistor 38 in the pixel unit 30 is smaller than that of the thin film transistor in the prior art.
  • the size is, for example, designed to be half the size of the thin film transistor in the prior art; on the other hand, when the active matrix type flat display device 300 is a large-sized flat display device, the corresponding increase in the pixel unit 30
  • the size of a thin film transistor 37 and a second thin film transistor 38 is a large-sized flat display device.
  • the present invention can maintain the parasitic capacitance value of each pixel unit by providing two thin film transistors in one pixel unit.
  • FIG. 4 shows a schematic structural view of the pixel unit 30 in an ideal exposure state
  • FIG. 5 shows a schematic structural view of the pixel unit 30 in an exposure state in which a cover offset occurs.
  • the exposure machine does not generate a cover offset when exposing the pixel unit 30.
  • the overlapping area of the gate 371 and the drain 373 of the first thin film transistor 37 is generated.
  • the capacitance is C1
  • the capacitance generated by the overlapping area of the gate 381 and the drain 383 of the second thin film transistor 38 is C2
  • the sum of C1 and C2 is the parasitic capacitance C gd of the thin film transistor group 36, that is, C gd satisfies the following relationship formula:
  • FIG. 5 shows a case where the exposure machine generates a cover offset when the pixel unit 30 is exposed.
  • the overlapping area of the gate 371 and the drain 373 of the first thin film transistor 37 of the pixel unit 30 is reduced by X, on the contrary.
  • the overlapping area of the gate 381 and the drain 383 of the second thin film transistor 38 is increased by X correspondingly.
  • the capacitance generated by the overlap area X is C x
  • the capacitance C1 ' C1 - C x generated by the overlapping area of the gate 371 and the drain 373 of the first thin film transistor 37 at this time
  • the value of the parasitic capacitance C gd ' of the thin film transistor group 36 in the presence of the overlay offset is equal to the value of the parasitic capacitance C gd in the ideal exposure state. It can be seen that when the overlay offset occurs, for each pixel unit 30, since the amount of change of C1 and C2 is the same (both Cx ), and the change trend is reversed, when C1 decreases or increases Cx , C2 increases accordingly. Or reduce C x , thus keeping the value of C gd unchanged. Therefore, display defects caused by the difference in the parasitic capacitance values of the pixel units 30 at different positions due to the overlay offset of the exposure are overcome.
  • the design of two thin film transistors in one pixel unit is compared with the prior art in which only one thin film transistor is disposed in one pixel unit, and the pixel unit of the present invention can overcome the fact that one of the thin film transistors cannot be broken after the pixel unit is broken. The problem shown.
  • two branch scan lines are arranged in parallel in one pixel unit, and when one branch is broken, the scan driving signal can be automatically repaired by means of bypass, thereby overcoming display defects caused by scan line defects.
  • the first scan line 31 and the second scan line 32 of the pixel unit 30 of the present invention are connected to each other at the beginning and the end of the non-display area 302, and transmit the same scan driving signal.
  • the scan driving signal is bypassed by another scan line to the thin film transistor electrically connected to the open scan line, thereby securing the first film.
  • Both the transistor 37 and the second thin film transistor 38 can operate normally.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种像素单元（30）及主动矩阵式平面显示装置（300），像素单元（30）包括第一扫描线（31）、第二扫描线（32）和薄膜晶体管组（36），其中，薄膜晶体管组（36）包括第一薄膜晶体管（37）和第二薄膜晶体管（38），薄膜晶体管组（36）的寄生电容Cgd满足以下关系式：Cgd=C1+C2；其中，C1和C2的变化趋势相反，变化量相同，使得Cgd值保持不变。通过以上方式，克服了由于曝光的覆盖偏移导致各像素单元（30）的寄生电容值不同而产生的显示缺陷。

Description

像素单元及主动矩阵式平面显示装置
【技术领域】
本发明涉及显示技术领域，特别是涉及一种像素单元及主动矩阵式平面显示装置。
【背景技术】
请参阅图1，图1为现有技术的主动矩阵式平面显示装置的结构示意图。如图1所示，主动矩阵式平面显示装置10包括多个像素单元，每个像素单元包括一个薄膜晶体管，例如，像素单元P1包括薄膜晶体管T1，像素单元P2包括薄膜晶体管T2。
在主动矩阵式平面显示装置10的制作过程中，由于曝光机精度原因，容易在不同的曝光位置出现薄膜晶体管的漏极相对于其栅极的覆盖偏移（overlay shift），使得在主动矩阵式平面显示装置10不同位置处的薄膜晶体管具有不同的寄生电容。
以图1中所示的像素单元P1和P2为例，请参阅图2，图2为薄膜晶体T1和薄膜晶体管T2的放大图，如图2所示，薄膜晶体管T1的栅极和漏极的重叠面积所形成的寄生电容为 Cgd1 ，薄膜晶体管T2的栅极和漏极的重叠面积所形成的寄生电容为 Cgd 2 ，由于薄膜晶体管T1和T2的栅极和漏极的重叠面积（如图中虚线所示的面积）不一致，导致 Cgd1 ≠ Cgd2 ，因此导致像素单元P1和P2之间的灰度显示不均匀，从而产生不均匀（Mura）、闪烁（Flicker）等显示缺陷。
【发明内容】
本发明主要解决的技术问题是提供一种像素单元及主动矩阵式平面显示装置，能够维持主动矩阵式平面显示装置中每个像素单元内的薄膜晶体管组的寄生电容不变，从而避免产生显示缺陷。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种像素单元，该像素单元包括：平行间隔设置的第一扫描线和第二扫描线；数据线，与第一扫描线和第二扫描线相交设置；像素电极，分别与第一扫描线、第二扫描线和数据线电连接；薄膜晶体管组，分别与第一扫描线、第二扫描线、数据线和像素电极电连接；其中，薄膜晶体管组包括第一薄膜晶体管和第二薄膜晶体管，薄膜晶体管组的寄生电容 Cgd 满足以下关系式： Cgd=C1+C2 ；其中，C1为第一薄膜晶体管的栅极与漏极的重叠面积所产生的电容，C2为第二薄膜晶体管的栅极与漏极的重叠面积所产生的电容，且C1和C2的变化趋势相反，变化量相同，使得 Cgd 的值保持不变；其中，第一薄膜晶体管的栅极连接第一扫描线，第一薄膜晶体管的源极连接数据线，第一薄膜晶体管的漏极和像素电极通过第一导通孔电连接；第二薄膜晶体管的栅极连接第二扫描线，第二薄膜晶体管的源极连接数据线，第二薄膜晶体管的漏极和像素电极通过第二导通孔电连接，其中，第一导通孔和第二导通孔分别设置在像素电极的对角位置处；像素单元包括一中线，中线与数据线平行并把像素单元的面积平分，第一导通孔和第二导通孔分别设置在中线的两侧，并且第一导通孔到中线的垂直距离等于第二导通孔到中线的垂直距离。
其中，第一扫描线和第二扫描线首尾互相连接，并传输相同的扫描驱动信号。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种像素单元，该像素单元包括：平行间隔设置的第一扫描线和第二扫描线；数据线，与第一扫描线和第二扫描线相交设置；像素电极，分别与第一扫描线、第二扫描线和数据线电连接；薄膜晶体管组，分别与第一扫描线、第二扫描线、数据线和像素电极电连接；其中，薄膜晶体管组包括第一薄膜晶体管和第二薄膜晶体管，薄膜晶体管组的寄生电容 Cgd 满足以下关系式： Cgd=C1+C2 ；其中，C1为第一薄膜晶体管的栅极与漏极的重叠面积所产生的电容，C2为第二薄膜晶体管的栅极与漏极的重叠面积所产生的电容，且C1和C2的变化趋势相反，变化量相同，使得 Cgd 的值保持不变。
其中，第一薄膜晶体管的栅极连接第一扫描线，第一薄膜晶体管的源极连接数据线，第一薄膜晶体管的漏极和像素电极通过第一导通孔电连接；第二薄膜晶体管的栅极连接第二扫描线，第二薄膜晶体管的源极连接数据线，第二薄膜晶体管的漏极和像素电极通过第二导通孔电连接。
其中，第一扫描线和第二扫描线首尾互相连接，并传输相同的扫描驱动信号。
其中，第一导通孔和第二导通孔分别设置在像素电极的对角位置处。
其中，像素单元包括一中线，中线与数据线平行并把像素单元的面积平分，第一导通孔和第二导通孔分别设置在中线的两侧，并且第一导通孔到中线的垂直距离等于第二导通孔到中线的垂直距离。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种主动矩阵式平面显示装置，该主动矩阵式平面显示装置包括显示区域和非显示区域，该显示区域设置有多个像素单元，该像素单元包括：平行间隔设置的第一扫描线和第二扫描线；数据线，与第一扫描线和第二扫描线相交设置；像素电极，分别与第一扫描线、第二扫描线和数据线电连接；薄膜晶体管组，分别与第一扫描线、第二扫描线、数据线和像素电极电连接；其中，薄膜晶体管组包括第一薄膜晶体管和第二薄膜晶体管，薄膜晶体管组的寄生电容 Cgd 满足以下关系式： Cgd=C1+C2 ；其中，C1为第一薄膜晶体管的栅极与漏极的重叠面积所产生的电容，C2为第二薄膜晶体管的栅极与漏极的重叠面积所产生的电容，且C1和C2的变化趋势相反，变化量相同，使得 Cgd 的值保持不变。
其中，第一薄膜晶体管的栅极连接第一扫描线，第一薄膜晶体管的源极连接数据线，第一薄膜晶体管的漏极和像素电极通过第一导通孔电连接；第二薄膜晶体管的栅极连接第二扫描线，第二薄膜晶体管的源极连接数据线，第二薄膜晶体管的漏极和像素电极通过第二导通孔电连接。
其中，第一扫描线和第二扫描线在非显示区域首尾互相连接，并传输相同的扫描驱动信号。
其中，第一导通孔和第二导通孔分别设置在像素电极的对角位置处。
其中，像素单元包括一中线，中线与数据线平行并把像素单元的面积平分，第一导通孔和第二导通孔分别设置在中线的两侧，并且第一导通孔到中线的垂直距离等于第二导通孔到中线的垂直距离。
其中，第一薄膜晶体管和第二薄膜晶体管设置的尺寸随着主动矩阵式平面显示装置的尺寸的大小而相应增大或减小。
本发明的有益效果是：区别于现有技术的情况，本发明在一个像素单元中设置由第一薄膜晶体管以及第二薄膜晶体管组成的薄膜晶体管组，该薄膜晶体管组的寄生电容 Cgd 满足以下关系式： Cgd=C1+C2 ；其中，C1为第一薄膜晶体管的栅极与漏极的重叠面积所产生的电容，C2为第二薄膜晶体管的栅极与漏极的重叠面积所产生的电容，并且C1和C2变化趋势相反，变化量相同，使得 Cgd 的值保持不变。因此克服了由于曝光的覆盖偏移导致各像素单元的寄生电容值不同而产生的显示缺陷。
进一步的，本发明在一个像素区域中平行间隔设置用于提供相同扫描驱动信号的两个分支的第一扫描线和第二扫描线，当其中一条分支断路时，扫描驱动信号可以通过绕道的方式实现自动修复，因此克服了因扫描线缺陷而产生的显示缺陷。
【附图说明】
图1是现有技术的主动矩阵式平面显示装置的结构示意图；
图2是图1中的主动矩阵式平面显示装置的两个不同位置处的薄膜晶体管的放大结构示意图；
图3是本发明的一种主动矩阵式平面显示装置的结构示意图；
图4是图3所示的主动矩阵式平面显示装置中的一像素单元在理想曝光状态下的结构示意图；
图5是图3所示的主动矩阵式平面显示装置中的一像素单元在出现覆盖偏移的曝光状态下的结构示意图。
【具体实施方式】
下面结合附图和实施例对本发明进行详细说明。
请参阅图3，图3是本发明的一种主动矩阵式平面显示装置的结构示意图，本发明的主动矩阵式平面显示装置300包括显示区域301和非显示区域302。
本实施例中，在显示区域301中设置有多个像素单元30。
请一并参阅图3和图4，图4是图3所示的主动矩阵式平面显示装置中的一像素单元的结构示意图。如图4所示，本发明的像素单元30包括第一扫描线31、第二扫描线32、数据线33、像素电极35以及薄膜晶体管组36。
其中，第一扫描线31和第二扫描线32在显示区域301中平行间隔设置，数据线33分别与第一扫描线31和第二扫描线32垂直相交设置。像素电极35分别与第一扫描线31、第二扫描线32和数据线33电连接。薄膜晶体管组36分别与第一扫描线31、第二扫描线32、数据线33以及像素电极35电连接，具体地：
薄膜晶体管组36包括第一薄膜晶体管37和第二薄膜晶体管38。其中，第一薄膜晶体管37的栅极371连接第一扫描线31，第二薄膜晶体管38的栅极381连接第二扫描线32。
第一薄膜晶体管37的源极372与第二薄膜晶体管38的源极382连接数据线33。
第一薄膜晶体管37的漏极373通过第一导通孔351电连接像素电极35，第二薄膜晶体管38的漏极383通过第二导通孔352电连接像素电极35。本发明实施例中，像素单元35包括一中线353，中线353与数据线33平行并把像素单元30的面积平分，第一导通孔351和第二导通孔352分别设置在中线353的两侧，并且第一导通孔351到中线353的垂直距离D1等于第二导通孔352到中线353的垂直距离D2。其中，第一导通孔351和第二导通孔352优选为分别设置在像素电极35的对角位置处。
本发明实施例中，根据主动矩阵式平面显示装置300的不同尺寸，对应设置薄膜晶体管不同的长和宽。具体而言，当主动矩阵式平面显示装置300为中小尺寸的平面显示装置时，则设计像素单元30中的第一薄膜晶体管37和第二薄膜晶体管38的尺寸小于现有技术中的薄膜晶体管的尺寸，例如，设计为现有技术中的薄膜晶体管的尺寸的一半；另一方面，当主动矩阵式平面显示装置300为大尺寸的平面显示装置时，则相应的增大像素单元30中的第一薄膜晶体管37和第二薄膜晶体管38的尺寸。
本发明通过在一个像素单元中设置两个薄膜晶体管，能维持各个像素单元的寄生电容值不变。具体而言，请一并参阅图4和图5，图4显示在理想曝光状态下像素单元30的结构示意图，图5显示在出现覆盖偏移的曝光状态下像素单元30的结构示意图。
首先请参阅图4，在理想曝光状态下，曝光机在对像素单元30进行曝光时没有产生覆盖偏移，此时，第一薄膜晶体管37的栅极371与漏极373的重叠面积所产生的电容为C1，第二薄膜晶体管38的栅极381与漏极383的重叠面积所产生的电容为C2，并且C1和C2的和为薄膜晶体管组36的寄生电容 Cgd ，即 Cgd 满足以下关系式：
Cgd=C1+C2 。
请再参阅图5，图5显示曝光机在对像素单元30进行曝光时产生覆盖偏移的情形。具体而言，相对于图4所示的像素单元30，如图5所示，此时像素单元30的第一薄膜晶体管37的栅极371与漏极373的重叠面积减少了X，与此相反，第二薄膜晶体管38的栅极381与漏极383的重叠面积相应增加了X。假设重叠面积X所产生的电容为 Cx ，则此时第一薄膜晶体管37的栅极371与漏极373的重叠面积所产生的电容 C1 ＇ = C1- Cx ，第二薄膜晶体管38的栅极381与漏极383的重叠面积所产生的电容 C2 ＇ = C2 + Cx 。因此，薄膜晶体管组36的寄生电容 Cgd ＇ 为：
Cgd ＇ = C1 ＇ + C2 ＇ = （ C1-Cx ） + （ C2+Cx ） =C1+C2 。
即薄膜晶体管组36在存在覆盖偏移时的寄生电容 Cgd ＇ 的值等于理想曝光状态下的寄生电容 Cgd 的值。可见，当出现覆盖偏移时，对于每个像素单元30而言，由于C1和C2的变化量相同(均为 Cx )，而变化趋势相反，在C1减少或增加 Cx 时，C2相应增加或减少 Cx ，由此使得 Cgd 的值保持不变。因此，克服了由于曝光的覆盖偏移导致不同位置处的像素单元30的寄生电容值不同而引起的显示缺陷。
并且，本发明在一个像素单元中设置两个薄膜晶体管的设计与一个像素单元中仅设置一个薄膜晶体管的现有结构相比，本发明的像素单元可以克服其中一个薄膜晶体管坏掉后像素单元无法显示的问题。
进一步的，本发明在一个像素单元中平行间隔设置了两条分支的扫描线，其中一条分支断路时，扫描驱动信号可以通过绕道的方式实现自动修复，克服了因扫描线缺陷所产生的显示缺陷。具体而言，请再一并参阅图3所示，本发明像素单元30的第一扫描线31和第二扫描线32在非显示区域302首尾互相连接，并传输相同的扫描驱动信号，由此使得第一扫描线31或者第二扫描线32的其中一条断路时，扫描驱动信号会通过另一条扫描线以绕道的方式传送到与断路扫描线电连接的薄膜晶体管中，由此保证第一薄膜晶体管37和第二薄膜晶体管38均能正常工作。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (13)

  1. 一种像素单元，其中，所述像素单元包括：
    平行间隔设置的第一扫描线和第二扫描线；
    数据线，与所述第一扫描线和所述第二扫描线相交设置；
    像素电极，分别与所述第一扫描线、所述第二扫描线和所述数据线电连接；
    薄膜晶体管组，分别与所述第一扫描线、所述第二扫描线、所述数据线和所述像素电极电连接；
    其中，所述薄膜晶体管组包括第一薄膜晶体管和第二薄膜晶体管，所述薄膜晶体管组的寄生电容
    Cgd
    满足以下关系式：
    Cgd=C1+C2
    ；
    其中，C1为所述第一薄膜晶体管的栅极与漏极的重叠面积所产生的电容，C2为所述第二薄膜晶体管的栅极与漏极的重叠面积所产生的电容，且所述C1和C2的变化趋势相反，变化量相同，使得所述
    Cgd
    的值保持不变；
    其中，所述第一薄膜晶体管的栅极连接所述第一扫描线，所述第一薄膜晶体管的源极连接所述数据线，所述第一薄膜晶体管的漏极和所述像素电极通过第一导通孔电连接；所述第二薄膜晶体管的栅极连接所述第二扫描线，所述第二薄膜晶体管的源极连接所述数据线，所述第二薄膜晶体管的漏极和所述像素电极通过第二导通孔电连接，其中，所述第一导通孔和所述第二导通孔分别设置在所述像素电极的对角位置处；
    所述像素单元包括一中线，所述中线与所述数据线平行并把所述像素单元的面积平分，所述第一导通孔和所述第二导通孔分别设置在所述中线的两侧，并且所述第一导通孔到所述中线的垂直距离等于所述第二导通孔到所述中线的垂直距离。
  2. 根据权利要求1所述的像素单元，其中，所述第一扫描线和所述第二扫描线首尾互相连接，并传输相同的扫描驱动信号。
  3. 一种像素单元，其中，所述像素单元包括：
    平行间隔设置的第一扫描线和第二扫描线；
    数据线，与所述第一扫描线和所述第二扫描线相交设置；
    像素电极，分别与所述第一扫描线、所述第二扫描线和所述数据线电连接；
    薄膜晶体管组，分别与所述第一扫描线、所述第二扫描线、所述数据线和所述像素电极电连接；
    其中，所述薄膜晶体管组包括第一薄膜晶体管和第二薄膜晶体管，所述薄膜晶体管组的寄生电容
    Cgd
    满足以下关系式：
    Cgd=C1+C2
    ；
    其中，C1为所述第一薄膜晶体管的栅极与漏极的重叠面积所产生的电容，C2为所述第二薄膜晶体管的栅极与漏极的重叠面积所产生的电容，且所述C1和C2的变化趋势相反，变化量相同，使得所述
    Cgd
    的值保持不变。
  4. 根据权利要求3所述的像素单元，其中，所述第一薄膜晶体管的栅极连接所述第一扫描线，所述第一薄膜晶体管的源极连接所述数据线，所述第一薄膜晶体管的漏极和所述像素电极通过第一导通孔电连接；所述第二薄膜晶体管的栅极连接所述第二扫描线，所述第二薄膜晶体管的源极连接所述数据线，所述第二薄膜晶体管的漏极和所述像素电极通过第二导通孔电连接。
  5. 根据权利要求4所述的像素单元，其中，所述第一扫描线和所述第二扫描线首尾互相连接，并传输相同的扫描驱动信号。
  6. 根据权利要求4所述的像素单元，其中，所述第一导通孔和所述第二导通孔分别设置在所述像素电极的对角位置处。
  7. 根据权利要求4所述的像素单元，其中，所述像素单元包括一中线，所述中线与所述数据线平行并把所述像素单元的面积平分，所述第一导通孔和所述第二导通孔分别设置在所述中线的两侧，并且所述第一导通孔到所述中线的垂直距离等于所述第二导通孔到所述中线的垂直距离。
  8. 一种主动矩阵式平面显示装置，所述主动矩阵式平面显示装置包括显示区域和非显示区域，所述显示区域设置有多个像素单元，其中，所述像素单元包括：
    平行间隔设置的第一扫描线和第二扫描线；
    数据线，与所述第一扫描线和所述第二扫描线相交设置；
    像素电极，分别与所述第一扫描线、所述第二扫描线和所述数据线电连接；
    薄膜晶体管组，分别与所述第一扫描线、所述第二扫描线、所述数据线和所述像素电极电连接；
    其中，所述薄膜晶体管组包括第一薄膜晶体管和第二薄膜晶体管，所述薄膜晶体管组的寄生电容
    Cgd
    满足以下关系式：
    Cgd=C1+C2
    ；
    其中，C1为所述第一薄膜晶体管的栅极与漏极的重叠面积所产生的电容，C2为所述第二薄膜晶体管的栅极与漏极的重叠面积所产生的电容，且所述C1和C2的变化趋势相反，变化量相同，使得所述
    Cgd
    的值保持不变。
  9. 根据权利要求8所述的主动矩阵式平面显示装置，其中，所述第一薄膜晶体管的栅极连接所述第一扫描线，所述第一薄膜晶体管的源极连接所述数据线，所述第一薄膜晶体管的漏极和所述像素电极通过第一导通孔电连接；所述第二薄膜晶体管的栅极连接所述第二扫描线，所述第二薄膜晶体管的源极连接所述数据线，所述第二薄膜晶体管的漏极和所述像素电极通过第二导通孔电连接。
  10. 根据权利要求9所述的主动矩阵式平面显示装置，其中，所述第一扫描线和所述第二扫描线在非显示区域首尾互相连接，并传输相同的扫描驱动信号。
  11. 根据权利要求9所述的主动矩阵式平面显示装置，其中，所述第一导通孔和所述第二导通孔分别设置在所述像素电极的对角位置处。
  12. 根据权利要求9所述的主动矩阵式平面显示装置，其中，所述像素单元包括一中线，所述中线与所述数据线平行并把所述像素单元的面积平分，所述第一导通孔和所述第二导通孔分别设置在所述中线的两侧，并且所述第一导通孔到所述中线的垂直距离等于所述第二导通孔到所述中线的垂直距离。
  13. 根据权利要求8所述的主动矩阵式平面显示装置，其中，所述第一薄膜晶体管和所述第二薄膜晶体管设置的尺寸随着所述主动矩阵式平面显示装置的尺寸的大小而相应增大或减小。
PCT/CN2012/083485 2012-10-18 2012-10-25 像素单元及主动矩阵式平面显示装置 Ceased WO2014059688A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/701,871 US9182636B2 (en) 2012-10-18 2012-10-25 Pixel cell and active matrix liquid crystal display

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201210397891.X 2012-10-18
CN201210397891XA CN102881249A (zh) 2012-10-18 2012-10-18 像素单元及主动矩阵式平面显示装置

Publications (1)

Publication Number Publication Date
WO2014059688A1 true WO2014059688A1 (zh) 2014-04-24

Family

ID=47482552

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/083485 Ceased WO2014059688A1 (zh) 2012-10-18 2012-10-25 像素单元及主动矩阵式平面显示装置

Country Status (3)

Country Link
US (1) US9182636B2 (zh)
CN (1) CN102881249A (zh)
WO (1) WO2014059688A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106920529B (zh) * 2017-05-09 2019-03-05 深圳市华星光电技术有限公司 像素单元及包含其的阵列基板
CN114815415A (zh) * 2022-04-11 2022-07-29 Tcl华星光电技术有限公司 显示面板及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005300780A (ja) * 2004-04-08 2005-10-27 Sharp Corp 表示装置
CN1955824A (zh) * 2005-10-28 2007-05-02 Nec液晶技术株式会社 液晶显示器件
CN101308296A (zh) * 2008-07-15 2008-11-19 友达光电股份有限公司 液晶显示面板及其像素结构
CN201867560U (zh) * 2010-11-08 2011-06-15 京东方科技集团股份有限公司 阵列基板和液晶显示器
CN102520555A (zh) * 2011-12-02 2012-06-27 深圳市华星光电技术有限公司 一种像素结构、阵列基板和液晶显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0830825B2 (ja) * 1990-04-20 1996-03-27 シャープ株式会社 アクティブマトリクス表示装置
JP3133140B2 (ja) * 1992-04-01 2001-02-05 株式会社半導体エネルギー研究所 表示装置
KR100870005B1 (ko) * 2002-03-07 2008-11-21 삼성전자주식회사 액정 표시 장치
KR101090246B1 (ko) * 2003-12-10 2011-12-06 삼성전자주식회사 박막 트랜지스터 표시판
JP4916770B2 (ja) * 2006-05-22 2012-04-18 三菱電機株式会社 液晶表示装置、及びその製造方法
CN101382710B (zh) * 2007-09-07 2011-06-15 群康科技(深圳)有限公司 液晶显示面板及液晶显示装置
CN102231030B (zh) * 2011-07-07 2013-04-10 南京中电熊猫液晶显示科技有限公司 薄膜晶体管液晶显示器的像素结构

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005300780A (ja) * 2004-04-08 2005-10-27 Sharp Corp 表示装置
CN1955824A (zh) * 2005-10-28 2007-05-02 Nec液晶技术株式会社 液晶显示器件
CN101308296A (zh) * 2008-07-15 2008-11-19 友达光电股份有限公司 液晶显示面板及其像素结构
CN201867560U (zh) * 2010-11-08 2011-06-15 京东方科技集团股份有限公司 阵列基板和液晶显示器
CN102520555A (zh) * 2011-12-02 2012-06-27 深圳市华星光电技术有限公司 一种像素结构、阵列基板和液晶显示装置

Also Published As

Publication number Publication date
US9182636B2 (en) 2015-11-10
US20140078437A1 (en) 2014-03-20
CN102881249A (zh) 2013-01-16

Similar Documents

Publication Publication Date Title
WO2014036730A1 (zh) 一种显示面板及液晶显示装置
WO2017092082A1 (zh) 阵列基板以及液晶显示装置
WO2018006479A1 (zh) 阵列基板及其制作方法、以及液晶显示面板
WO2015021660A1 (zh) 阵列基板及液晶显示装置
WO2019019321A1 (zh) 一种显示装置及智能移动设备
WO2013155697A1 (zh) 液晶显示模组及液晶显示装置
WO2016078204A1 (zh) 一种液晶显示面板及阵列基板
WO2016058183A1 (zh) 阵列基板及液晶显示面板
WO2019015077A1 (zh) 一种阵列基板及其制造方法、液晶显示装置
WO2019080188A1 (zh) 一种像素单元及显示基板
WO2019090919A1 (zh) 一种像素单元、阵列基板及显示面板
WO2017015993A1 (zh) 液晶显示器及其液晶面板
WO2013159417A1 (zh) 液晶显示模组及液晶显示装置
WO2018040468A1 (zh) 显示器及其显示面板
WO2017101161A1 (zh) 基于hsd结构的显示面板和显示装置
WO2015006959A1 (zh) 显示面板及显示装置
WO2017088230A1 (zh) Coa基板、液晶显示面板及液晶显示装置
WO2014153771A1 (zh) 阵列基板及液晶显示装置
WO2014023010A1 (zh) 一种阵列基板及液晶显示面板
WO2017124596A1 (zh) 液晶显示面板及液晶显示装置
WO2015000188A1 (zh) 显示面板及其驱动方法、显示装置
WO2014015494A1 (zh) 一种液晶显示面板以及液晶显示装置
WO2017117827A1 (zh) 液晶显示面板、tft基板及其制造方法
WO2014059688A1 (zh) 像素单元及主动矩阵式平面显示装置
WO2018120386A1 (zh) 显示面板及其阵列基板

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13701871

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12886657

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12886657

Country of ref document: EP

Kind code of ref document: A1