WO2014032346A1 - 利用掺杂超薄层吸附制备超薄绝缘体上材料的方法 - Google Patents
利用掺杂超薄层吸附制备超薄绝缘体上材料的方法 Download PDFInfo
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- WO2014032346A1 WO2014032346A1 PCT/CN2012/081894 CN2012081894W WO2014032346A1 WO 2014032346 A1 WO2014032346 A1 WO 2014032346A1 CN 2012081894 W CN2012081894 W CN 2012081894W WO 2014032346 A1 WO2014032346 A1 WO 2014032346A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
Definitions
- the present invention relates to the field of microelectronics and solid state electronics, and more particularly to a method for preparing a material on an ultrathin insulator by doping an ultrathin layer. Background technique
- silicon-on-insulator (SOI) materials have been widely used in low voltage, low power, high temperature, radiation resistant devices, etc. due to their unique insulating buried structure, which can reduce the parasitic capacitance and leakage current of the substrate. .
- Silicon-on-insulator application technology has been very mature in related fields.
- Strained silicon (SSOI) on insulators has also received increasing attention from relevant technicians.
- Silicon-on-insulator (SGOI) combines the advantages of silicon germanium and silicon-on-insulator. It can also reduce the parasitic capacitance and leakage current of the substrate, and can also improve the carrier mobility, and has also received extensive attention. The preparation of smaller size, higher performance devices has been the goal and direction of the semiconductor industry.
- the material on the insulator needs to be obtained through two processes of material preparation and layer transfer.
- the more common layer transfer realization techniques are bonding and stripping processes.
- the traditional smart peeling method has a thick peeling surface, a large peeling crack, a rough surface of the material obtained on the insulator after peeling, and it is difficult to prepare an ultra-thin insulator material; and because a higher injection dose is required, not only the production time is increased, but also The cost, as well as the damage to the crystal, makes it more difficult to produce high quality ultra-thin insulator materials.
- an object of the present invention is to provide a method for preparing an ultra-thin insulator material by doping an ultra-thin layer, which is suitable for solving the problem of preparing a high-quality ultra-thin insulator material in the prior art. The problem.
- the present invention provides a method for preparing an ultrathin insulator material by doping an ultrathin layer, wherein the preparation method comprises at least the following steps:
- the step a) further includes a step of epitaxially growing a buffer layer on the doped single crystal film, and further comprising removing the residual buffer layer and doping single crystal in the step d) The step of the film.
- the material of the buffer layer is selected from any one of Si, Ge, SiGe, SiGeC, GaAs, AlGaAs, InGaP or InP.
- the buffer layer has a thickness not exceeding a critical thickness of its growth on the doped single crystal film.
- the doped single crystal film is a single layer film, and the material of the single layer film is selected from the group consisting of
- the single-layer doped single crystal film has a thickness ranging from 3 to 10 nm.
- the doped single crystal film is a multilayer film
- the multilayer film is formed by stacking a plurality of double-layer films
- the material of the double-layer film is selected from Si/ Any one of Ge, Si/SiGe, Ge/SiGe, Ge/GaAs, GaAs/AlGaAs or InP/InGa, wherein a multi-layer film is grown while a dopant gas is introduced to form a multilayer doped single crystal film.
- the multilayered doped single crystal film has a total thickness of less than 10 nm.
- the impurity element is B, P, Ga, As, Sb, 3 ⁇ 4 or [.
- the concentration of the impurity element is 1E19 ⁇ 1E22 cm- 3 .
- the material of the top film is selected from any one of Si, Ge, SiGe, SiGeC, GaAs, AlGaAs, InGaP or InP.
- the thickness of the top film ranges from 5 to 50 nm.
- H ion implantation is used in the step b), or H and He ions are co-injected.
- the ion implantation dose in the step b) is 3E16 ⁇ 6E16 cm- 2 .
- the preset depth is 30 to 120 nm.
- the bonding adopts a plasma strengthening bonding method.
- the bonding adopts direct bonding, and further includes a step of performing a second annealing stage after the first annealing stage to peel off to strengthen the insulating layer and the The bonding of the top film.
- the method for preparing an ultra-thin insulator material by doping ultra-thin layer adsorption has the following beneficial effects: adsorption of implanted ions by ultra-thin doped single crystal film, formation of microcracks to cause peeling, peeling Crack occurrence
- the crack is small, the surface roughness of the material on the insulator is small after the stripping, and the ions are effectively adsorbed by the ultra-thin layer, and the distribution is more uniform, so that the defects on the insulator-on-insulator or the insulator-modified material are less.
- the impurities enhance the adsorption capacity of the ultra-thin single crystal film to ions, so that the ion implantation dose can be lower, the annealing temperature of the stripping is also lower, the damage to the material on the insulator is effectively reduced, and the cost is reduced.
- Figure 1 is a schematic view showing the structure of a method for preparing an ultrathin insulator material by doping ultra-thin layer adsorption in the first step of the first embodiment.
- Fig. 2 is a view showing the ion implantation in the second step of the first embodiment of the method for preparing an ultrathin insulator material by doping ultra-thin layer adsorption according to the present invention.
- FIG 3 is a schematic view showing a second substrate having an insulating layer in the first step of the first embodiment of the present invention for the method of preparing an ultrathin insulator by doping ultra-thin layer adsorption according to the present invention.
- Fig. 4 is a view showing the structure of the method for preparing an ultrathin insulator material by doping ultra-thin layer adsorption according to the present invention after bonding in the first step of the first embodiment.
- Fig. 5 is a view showing the method of preparing a material for an ultrathin insulator by doping ultra-thin layer adsorption according to the present invention, in the fourth step of the first embodiment, in the case of residual doping of a single crystal film on the material of the ultra-thin insulator.
- Fig. 6 is a view showing the material of the ultrathin insulator in the first step of the first embodiment of the method for preparing an ultrathin insulator by doping ultra-thin layer adsorption according to the present invention.
- Fig. 7 is a view showing the structure of the method for preparing an ultrathin insulator material by doping ultra-thin layer adsorption in the first step of the second embodiment.
- Fig. 8 is a view showing the ion implantation in the second embodiment of the method for preparing an ultrathin insulator material by doping ultra-thin layer adsorption according to the present invention.
- Figure 9 is a schematic view showing a second substrate having an insulating layer in the second embodiment of the method for preparing an ultrathin insulator material by doping ultra-thin layer adsorption according to the present invention.
- Fig. 10 is a view showing the structure of the method for preparing an ultrathin insulator material by doping ultra-thin layer adsorption in the second embodiment after bonding in the second embodiment.
- Figure 11 is a schematic view showing the material of the ultrathin insulator in the second embodiment of the method for preparing an ultrathin insulator by doping ultra-thin layer adsorption according to the present invention.
- Component label description The first substrate 1
- the present invention provides a method for preparing an ultrathin insulator material by doping an ultrathin layer, the method comprising at least the following steps:
- Step 1 refer to FIG. 1.
- a first substrate 1 is provided, and a single epitaxial growth is performed on the first substrate 1 by chemical vapor deposition, physical vapor deposition or molecular beam epitaxy.
- the layer is doped with a single crystal film 2 and a top film 3.
- the single crystal thin film material is Si, Ge, SiGe, SiGeC, GaAs, AlGaAs, InGaP or InP, wherein the composition of Ge in the SiGe is adjustable,
- the impurity element is B, P, Ga, As, Sb, In or C, the impurity concentration is 1E19 to 1E22, the thickness of the single-layer doped single crystal thin film 2 is 3 to 10 nm, and the material of the top film 3 It is Si, Ge, SiGe, SiGeC, GaAs, AlGaAs, InGaP or InP, wherein the composition of Ge in the SiGe is adjustable, and the thickness of the top film 3 is 5 to 50 nm.
- the first substrate 1 is Si, but is not limited to Si.
- the material of the single crystal thin film is preferably SiGe, wherein the ratio of Ge to Si is preferably 3:7, and the impurity element is preferably B.
- the impurity concentration is preferably 2E19 cm- 3
- the top film 3 is preferably Si has a thickness of preferably 10 nm.
- Step 2 referring to FIG. 2, as shown in the figure, ion implantation is performed to implant ions into the doped single crystal thin film 2 with specific energy and angle (this is common knowledge in the art, which will not be described herein).
- the interface with the first substrate 1 has a depth of 30 to 120 nm below.
- H ion implantation is used, or H and He ions are co-injected, and the ion implantation dose is 3E16 ⁇ 6E16 cm- 2 .
- the implanted ions are preferably H ions, and the implantation depth is 30 nm below the interface between the doped single crystal thin film 2 and the first substrate 1, and the implantation dose is 3E16 cm- 2 .
- Step 3 referring to FIG. 3 and FIG. 4, as shown, a second substrate 4 having an insulating layer 5 is provided, the insulating layer 5 is bonded to the top film 3, and then the sample is first annealed.
- the doped single crystal thin film is caused to adsorb the implanted ions from the first substrate 1 and form microcracks, thereby achieving peeling.
- the bonding adopts plasma strengthening bonding or direct bonding.
- a second annealing stage is also required after the first annealing stage to strengthen the insulating layer 5 and the The bonding of the top film 3, in the first annealing stage, the annealing temperature is 300-600 ° C, the annealing time is 30-90 minutes, and in the second annealing stage, the annealing temperature is 800-1000 ° C, The annealing time is 60 to 120 minutes.
- the bonding method is preferably a plasma hardening bonding method, that is, it is not necessary to strengthen the bonding through the second annealing stage to avoid the high temperature annealing affecting the quality of the top film.
- Step 4 referring to FIG. 5 and FIG. 6, as shown in the figure, chemical etching or chemical mechanical polishing is performed to remove the residual doped single crystal film 2 to obtain an ultra-thin insulator material.
- the removal method is preferably selective chemical etching.
- the step 1 further includes the step of epitaxially growing a buffer layer (not shown) on the single-layer doped single crystal thin film 2, and further comprising the step 4 The step of removing the residual buffer layer and doping the single crystal film.
- the presence of the buffer layer prevents the peeling crack from affecting the crystal quality of the material on the insulator.
- the material of the buffer layer is selected from any one of Si, Ge, SiGe, SiGeC, GaAs, AlGaAs, InGaP, or InP, wherein the composition of Ge in the SiGe is adjustable, and the thickness of the buffer layer does not exceed It has a critical thickness grown on the single-layer doped single crystal thin film 2.
- the buffer layer in this embodiment is preferably a SiGe single crystal material.
- the doped ultra-thin single crystal film can more effectively adsorb the implanted ions, so that the ion implantation dose can be lower, and micro-cracks are formed at a lower annealing temperature to cause peeling, and the obtained insulator material is obtained.
- Low surface roughness and low defects enable higher quality ultra-thin insulator materials to be produced at lower cost.
- the second embodiment and the first embodiment adopt substantially the same technical solutions, except that the structures of the doped single crystal films prepared by the two are different.
- the doped single crystal film is a single layer, and in the embodiment, the doped single crystal film is Multi-layered.
- the present invention provides a method for preparing an ultra-thin insulator material by doping ultra-thin layer adsorption, the method comprising at least the following steps:
- Step 1 refer to FIG. 7.
- the first substrate 1 is provided, and the first substrate 1 is epitaxially grown on the first substrate 1 by chemical vapor deposition, physical vapor deposition or molecular beam epitaxy.
- the layer is doped with a single crystal film 2 and a top film 3.
- the multi-layer doped single crystal film 2 is formed by stacking a plurality of double-layer films, and the material of the double-layer film is selected from the group consisting of Si/Ge, Si/SiGe, Ge/SiGe, Ge/GaAs, and GaAs.
- a Si layer 211 is epitaxially grown on the first substrate 1, and then a layer of Ge 1 having a Ge composition X having a value of x1 is 81 1 _ 5 ⁇ 6 5 ⁇ layer 212 is epitaxially grown on the Si layer 211, wherein 0 ⁇ 1, forming a Si/Si ⁇ Gex bilayer film 21, and then according to the preparation
- the Ge composition X is prepared to have the same or different values of the Ge composition X (i.e., the value of any two of xl, x2, x3, ...
- xn a plurality of Si/Si ⁇ Gex bilayer films which may be equal or unequal to each other; at the same time, a doping gas is introduced during the preparation of the plurality of Si/Si ⁇ Gex bilayer films, and then the first lining Get n on the bottom 1
- the second step, the third step and the fourth step are performed in substantially the same manner as in the first embodiment to obtain the material on the ultra-thin insulator.
- the step 1 further includes a step of epitaxially growing a buffer layer (not shown) on the multi-layer doped single crystal thin film 2, and further comprising the step 4 The step of removing the residual buffer layer and doping the single crystal film.
- the presence of the buffer layer prevents the peeling crack from affecting the crystal quality of the material on the insulator.
- the material of the buffer layer is selected from any one of Si, Ge, SiGe, SiGeC, GaAs, AlGaAs, InGaP, or InP, wherein the composition of Ge in the SiGe is adjustable, and the thickness of the buffer layer does not exceed It has a critical thickness grown on the multilayered doped single crystal film 2.
- the buffer layer in this embodiment is preferably a SiGe single crystal material.
- the doped ultra-thin single crystal film can more effectively adsorb the implanted ions, so that the ion implantation dose can be lower, and micro-cracks are formed at a lower annealing temperature to cause peeling, and the obtained insulator material is obtained.
- the surface roughness is low and the defects are few, wherein the multi-layer doped single crystal film is more favorable for the adsorption of the implanted ions than the single layer.
- the method for preparing an ultra-thin insulator material by doping ultra-thin layer adsorption uses the ultra-thin doped single crystal film to adsorb the implanted ions, forming micro-cracks to cause peeling, and the peeling crack occurs in the super layer sheet, cracking it Small, after peeling, the surface roughness of the material on the insulator is small, and the ions are effectively adsorbed by the ultra-thin layer, and the distribution is more uniform, so that the defects of the material on the insulator or the modified material on the insulator are less, and the impurities enhance the ultra-thin
- the ability of the single crystal film to adsorb ions can make the implantation dose of ions lower, and the annealing temperature of the stripping is lower, which effectively reduces the damage to the top film, so that the quality of the material on the insulator is higher, and at the same time, the quality is lowered. cost. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high
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US13/825,079 US9230849B2 (en) | 2012-08-28 | 2012-09-25 | Method for preparing ultra-thin material on insulator through adsorption by doped ultra-thin layer |
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CN201210310581.X | 2012-08-28 | ||
CN201210310581.XA CN103633010B (zh) | 2012-08-28 | 2012-08-28 | 利用掺杂超薄层吸附制备超薄绝缘体上材料的方法 |
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CN103972148B (zh) * | 2014-05-23 | 2017-01-25 | 中国科学院上海微系统与信息技术研究所 | 一种超薄绝缘体上材料的制备方法 |
US9752224B2 (en) * | 2015-08-05 | 2017-09-05 | Applied Materials, Inc. | Structure for relaxed SiGe buffers including method and apparatus for forming |
CN105140171B (zh) * | 2015-08-26 | 2018-06-29 | 中国科学院上海微系统与信息技术研究所 | 一种绝缘体上材料的制备方法 |
CN106373870B (zh) * | 2016-11-24 | 2020-06-02 | 清华大学 | 半导体结构以及制备方法 |
CN106449369B (zh) * | 2016-11-24 | 2020-04-28 | 清华大学 | 绝缘体上半导体结构以及制备方法 |
CN106409750B (zh) * | 2016-11-24 | 2020-04-28 | 清华大学 | 绝缘体上半导体结构以及制备方法 |
CN106449663B (zh) * | 2016-11-24 | 2020-04-28 | 清华大学 | 绝缘体上半导体结构以及制备方法 |
CN108346686B (zh) * | 2017-01-25 | 2021-07-30 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件及其制造方法 |
CN113889431A (zh) * | 2020-07-01 | 2022-01-04 | 中芯集成电路(宁波)有限公司上海分公司 | 绝缘体上半导体结构的制造方法 |
CN112750686B (zh) * | 2020-12-30 | 2021-12-07 | 济南晶正电子科技有限公司 | 一种多层衬底、电子元器件及多层衬底制备方法 |
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- 2012-08-28 CN CN201210310581.XA patent/CN103633010B/zh active Active
- 2012-09-25 US US13/825,079 patent/US9230849B2/en active Active
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US20030201508A1 (en) * | 2000-11-30 | 2003-10-30 | Seiko Epson Corporation | SOI substrate, element substrate, semiconductor device, electro-optical apparatus, electronic equipment, method of manufacturing the SOI substrate, method of manufacturing the element substrate, and method of manufacturing the electro-optical apparatus |
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CN103633010A (zh) | 2014-03-12 |
US9230849B2 (en) | 2016-01-05 |
US20150194338A1 (en) | 2015-07-09 |
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