WO2014029151A1 - 一种半导体结构及其制造方法 - Google Patents

一种半导体结构及其制造方法 Download PDF

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Publication number
WO2014029151A1
WO2014029151A1 PCT/CN2012/081512 CN2012081512W WO2014029151A1 WO 2014029151 A1 WO2014029151 A1 WO 2014029151A1 CN 2012081512 W CN2012081512 W CN 2012081512W WO 2014029151 A1 WO2014029151 A1 WO 2014029151A1
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metal interconnection
substrate
forming
metal
etching
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French (fr)
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钟汇才
梁擎擎
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to US14/423,020 priority Critical patent/US9379056B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/098—Manufacture or treatment of dielectric parts thereof by filling between adjacent conductive parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/067—Manufacture or treatment of conductive parts of the interconnections by modifying the pattern of conductive parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers

Definitions

  • the present invention relates to semiconductor fabrication techniques, and more particularly to a method of fabricating a semiconductor structure. Background technique
  • the step of forming a metal interconnection in a conventional process includes: first forming a photolithographic pattern of an interconnect on an insulating material by one-time photolithography; then etching the insulating layer to expose an underlying interconnect line, engraving a deep trench Finally, the metal is filled in the deep trench by deposition or electroplating, and chemical mechanical polishing CMP is performed to form metal interconnections which are isolated and insulated from each other.
  • the method includes the following steps: (a) forming a metal interconnection on the substrate;
  • the present invention also provides a semiconductor structure including a substrate and a metal interconnection formed in the substrate, wherein: the ends of the metal interconnection lines are disconnected by an insulating wall formed in the substrate.
  • the material of the metal interconnection is copper, aluminum, tungsten, nickel.
  • the method of etching in step c) is RIE dry etching, laser ablation, electron beam etching or focused ion beam etching.
  • the deep trench is filled, and the material filling the deep trench is SiO 2 , SiOF, SiCOH, SiO, SiCO, SiCON, or the like.
  • the interconnected metal interconnects are insulated by a single mask etching process, which is advantageous for reducing the end points of adjacent metal interconnects to the end points.
  • FIG. 1 is a flow chart of a method of fabricating a semiconductor structure in accordance with the present invention
  • FIG. 2(a) through 8 are schematic cross-sectional views showing various stages of fabricating a semiconductor structure in accordance with the flow of FIG. 1 in accordance with a preferred embodiment of the present invention.
  • the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials.
  • the structure of the first feature described below "on" the second feature may include embodiments in which the first and second features are formed in direct contact, and may include additional features formed between the first and second features. The embodiment, such that the first and second features may not be in direct contact.
  • FIG. 1 is a flow chart of a method of fabricating a semiconductor structure in accordance with the present invention
  • FIGS. 2(a) through 7(b) are diagrams showing stages of fabricating a semiconductor structure in accordance with the flow shown in FIG. 1 in accordance with an embodiment of the present invention. Schematic diagram of the section. The method of forming the semiconductor structure of Fig. 1 will be specifically described below with reference to Figs. 2(a) through 8.
  • the drawings of the embodiments of the present invention are intended to be illustrative only, and are not necessarily to scale.
  • step S101 metal interconnection lines are formed on the substrate.
  • Step S101 further includes the following three steps: i) forming a layer of photoresist on the insulating layer and patterning; ii) etching the insulating layer to form a trench; iii) forming in the trench Metal interconnects.
  • the insulating layer may be one or more layers, the material may be silicon oxide, silicon nitride, silicon oxynitride, borosilicate glass, phosphorus One or a combination of silicon glass, borophosphosilicate glass.
  • the substrate is not shown in the figures, the material of which includes a silicon substrate (e.g., a wafer).
  • the substrate may include various doping configurations in accordance with design requirements well known in the art, such as a P-type substrate or an N-type substrate.
  • the substrate in other embodiments may also include other basic semiconductors such as germanium.
  • the substrate may comprise a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide or indium phosphide.
  • the thickness of the substrate can be, but is not limited to, a few One hundred meters, for example, can be in the thickness range of ⁇ -800 ⁇ .
  • the substrate may also include circuit component structures such as field effect transistors, diodes, transistors, interconnects, and the like.
  • a photoresist 200 is formed on the insulating layer and patterned, and FIG. 2(a) and FIG. 2(b) respectively form a patterned photoresist on the insulating layer. Top and cross-section of the layer.
  • the insulating layer has a two-layer structure, an insulating layer 101 and an insulating layer 102.
  • An opening 201 is formed on the photoresist 200 by exposure development to define a pattern of metal interconnect lines.
  • the interval from the end point to the end point is relatively small, and is not blocked in step S101.
  • the insulating layer is etched through the opening 201 to form a trench 300 penetrating the insulating layer 102 and deep into the insulating layer 101, as shown in FIGS. 3(a) and 3(b).
  • the photoresist 200 is subsequently removed, as shown in Figures 4(a) and 4(b).
  • the method of etching the insulating layer may be a dry RIE etching or other etching method.
  • the trench 300 is then filled with metal and subjected to chemical mechanical polishing CMP to form metal interconnects 310, as shown in Figures 5(a) and 5(b).
  • the material of the metal interconnection is copper, aluminum, tungsten, nickel, etc., and the trench may be filled by a suitable method such as chemical vapor deposition, electroplating, sputtering, or the like.
  • a barrier layer 311 is formed on the sidewall of the trench, as shown in Figures 5(a) and 5(b), to prevent metal electromigration and to avoid device failure.
  • the material of the barrier layer 311 is Ti, TiN, Ta, TaN or the like.
  • step S102 a mask layer 210 covering the metal interconnection is formed, and the metal interconnection is exposed on the mask layer 210.
  • the material of the mask layer 210 is photoresist, silicon nitride, etc., and the mask layer 210 and the insulating layers 101 and 102 have different etching selectivity ratios, and are exposed by exposure or dry RIE. The etch forms an opening 220.
  • step S103 is performed, and the metal interconnection 310 and the barrier layer 311 are etched through the opening 220 to form a deep trench 320 to realize mutual metal.
  • the insulation of the wires is isolated.
  • the etching method includes RIE dry etching, laser ablation, electron beam etching, or focused ion beam etching.
  • the photoresist is removed to form a deep trench 320, which is etched through the metal interconnect 310 and the barrier layer 311 until the bottom insulating material.
  • the etched metal interconnection line 310 and the etched insulating layers 101 and 102 The rate may be different, so it is preferable to adopt an etching method that etches the metal interconnection line 310 faster, and the metal interconnection line 310 can be etched and disconnected.
  • the two connected metal interconnect wires are insulated, and the lithographic scale is used to control the spacing between the end points of the collinear metal interconnects and the end points, thereby reducing the distance, saving the area, and avoiding the short circuit of the metal interconnects. The problem.
  • the deep trench 320 is filled to form an insulating wall 330 (as shown in FIG. 8), and the filling material is low ⁇ such as Si0 2 , SiOF, SiCOH, SiO, SiCO, SiCON, etc. Material, which helps to reduce the capacitance between interconnects.
  • the insulating material of the insulating wall 330 may be different from the insulating layers 101 and 102 of the substrate.
  • the insulating wall 330 has a thickness smaller than a width of the metal interconnection. The distance between the ends of the smaller metal interconnect lines can be achieved by the method and structure of the present invention.
  • the fabrication of the semiconductor device is then completed in accordance with the steps of a conventional semiconductor fabrication process, such as repeating the fabrication of the metal interconnect lines described above, fabricating a new layer of metal interconnect lines, making pads, and the like.

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)

Abstract

提供一种半导体结构的制造方法，包括：a）在衬底上形成金属互连线（310）；b）形成覆盖金属互连线（310）的掩膜层（210），在掩膜层（210）上形成暴露金属互连线（310）的开口（220）；c）通过开口（220）刻蚀并断开金属互连线（310），实现金属互连线（310）的隔离。还提供一种半导体结构，包括衬底以及在衬底中形成的金属互连线（310），其中：金属互连线（310）端点之间被形成在衬底中的绝缘墙（330）所断开。提供的结构和方法利于减小相邻金属互连线端点到端点的间距，节省器件面积，以及解决金属互连线之间可能存在的短路问题。

Description

一种半导体结构及其制造方法
[0001]本申请要求了 2012年 8月 23 日提交的、 申请号为 201210303691.3、 发明名称为"一种半导体结构及其制造方法"的中国专利申请的优先权， 其全 部内容通过引用结合在本申请中。 技术领域
[0002]本发明涉及半导体制造技术， 尤其涉及一种半导体结构的制造方 法。 背景技术
[0003]随着半导体结构制造技术的发展，具有更高性能和更强功能的集成 电路要求更大的元件密度， 而且各个部件、 元件之间或各个元件自身的 尺寸、 大小和空间也需要进一步缩小， 在半导体结构的制造过程中， 光 刻技术面临了更高的要求和挑战。 传统工艺中形成金属互连线的步骤包 括： 首先通过一次性光刻在绝缘材料上形成互连线的光刻图形； 然后刻 蚀所述绝缘层， 露出底层的互连线， 刻出深槽； 最后通过沉积或电镀在 深槽中填充金属， 并进行化学机械抛光 CMP形成相互隔离和绝缘的金属 互连线。 需要注意的是， 在每一层金属互连中， 有许多共线的互连线， 它们具有相同的关键尺寸和间距。 随着器件尺寸进一步按比例缩小， 芯 片面积同时也明显减少， 传统互连线制作工艺需要进一步改进才能符合 技术发展的需求， 如减小共线互连线之间端点到端点的距离， 同时要解 决由于金属互连线间距较小可能会出现的互连线短路的问题。 发明内容
[0004]本发明的目的是提供一种金属互连线的制造方法，利于减小相邻金 属互连线端点到端点的间距， 以及解决金属互连线之间可能存在的短路 问题。 该方法包括以下步骤： ( a ) 在衬底上形成金属互连线；
( b ) 形成覆盖所述金属互连线的掩膜层，在所述掩膜层上形成暴露所述金 属互连线的开口；
( c ) 通过所述开口刻蚀并断开所述金属互连线， 实现金属互连线的绝缘隔 离。
[0005]本发明还提供一种半导体结构， 包括衬底以及在衬底中形成的金属互 联线， 其中： 金属互联线端点之间被形成在衬底中的绝缘墙所断开。
[0006]其中， 所述金属互连线的材料为铜、 铝、 钨、 镍。
[0007]步骤 c ) 中刻蚀的方法为 RIE干法刻蚀、 激光烧蚀、 电子束刻蚀或聚 焦离子束刻蚀。
[0008]可选地， 完成所述步骤 c)金属互连线刻蚀之后， 填充所述深槽， 填充 所述深槽的材料为 Si02、 SiOF、 SiCOH、 SiO、 SiCO、 SiCON等。
[0009]根据本发明提供的金属互连线结构及其制造方法，通过一步单独的掩 膜刻蚀工艺， 将相连的金属互连线隔断绝缘， 利于减小相邻金属互连线端 点到端点的间距， 节省器件面积， 以及解决金属互连线之间可能存在的 短路问题。 附图说明
[0010]通过阅读参照以下附图所作的对非限制性实施例所作的详细描述， 本 发明的其它特征、 目的和优点将会变得更明显：
[0011]图 1为根据本发明的半导体结构制造方法的流程图；
[0012]图 2(a)至图 8为根据本发明的一个优选实施例按照图 1所示流程制 造半导体结构的各个阶段的剖面示意图。
[0013 ]附图中相同或相似的附图标记代表相同或相似的部件。 具体实施方式
[0014]下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类 似功能的元件。 下面通过参考附图描述的实施例是示例性的， 仅用于解 释本发明， 而不能解释为对本发明的限制。 下文的公开提供了许多不同 下文中对特定例子的部件和设置进行描述。 当然， 它们仅仅为示例， 并 且目的不在于限制本发明。 此外， 本发明可以在不同例子中重复参考数 字和 /或字母。 这种重复是为了筒化和清楚的目的， 其本身不指示所讨论 各种实施例和 /或设置之间的关系。 此外， 本发明提供了的各种特定的工 艺和材料的例子， 但是本领域普通技术人员可以意识到其他工艺的可应 用于性和 /或其他材料的使用。 另外， 以下描述的第一特征在第二特征之 "上"的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包 括另外的特征形成在第一和第二特征之间的实施例， 这样第一和第二特 征可能不是直接接触。
[0015]图 1为根据本发明的半导体结构制造方法的流程图， 图 2(a)至图 7(b) 为根据本发明的一个实施例按照图 1所示流程制造半导体结构的各个阶段的 剖面示意图。 下面将结合图 2(a)至图 8对图 1中形成半导体结构的方法进行 具体地描述。 需要说明的是， 本发明实施例的附图仅是为了示意的目的， 因此没有必要按比例绘制。
[0016]参考图 2(a)至图 5(b), 在步骤 S101中， 在衬底上形成金属互连线。 其中， 步骤 S101 又包括以下三个步骤： i )在绝缘层上形成一层光刻胶， 并进行图形化； ii )刻蚀所述绝缘层形成沟槽； iii ) 在所述沟槽中形成金 属互连线。
[0017]其中， 所述绝缘层在所述衬底之上， 所述绝缘层可以是一层或多层 结构， 其材料可以是氧化硅、 氮化硅、 氮氧化硅、 硼硅玻璃、 磷硅玻璃、 硼磷硅玻璃中的一种或其组合。 所述衬底未在图中示出， 其材料包括硅衬 底 (例如晶片）。 根据现有技术公知的设计要求 (例如 P型衬底或者 N型衬 底）， 衬底可以包括各种掺杂配置。 其他实施例中衬底还可以包括其他基 本半导体， 例如锗。 或者， 衬底可以包括化合物半导体， 例如碳化硅、 砷化镓、 砷化铟或者磷化铟。 典型地， 衬底的厚度可以是但不限于约几 百 米， 例如可以在 ΙΟΟμηι -800μηι的厚度范围内。 所述衬底中还可以包 含场效应晶体管、 二极管、 三极管、 互连线等电路元器件结构。
[0018]具体地， 首先， 在绝缘层上形成一层光刻胶 200, 并进行图形化， 图 2(a)和图 2(b)所示分别为在绝缘层上形成图形化光刻胶层的俯视图和 剖面图。 其中所述绝缘层具有两层结构， 绝缘层 101和绝缘层 102。 通过曝 光显影， 在光刻胶 200上形成开口 201 , 定义金属互连线的图形。
[0019]特别地， 对于在电路版图设计中共线且相邻的金属互连线， 其端点到 端点的间距比较小的情况， 在步骤 S101中不将其隔断。
[0020]然后， 通过开口 201刻蚀所述绝缘层， 形成沟槽 300, 所述沟槽 300 贯穿所述绝缘层 102, 并深入绝缘层 101 中， 如图 3(a)和 3(b)所示， 随后去 除所述光刻胶 200, 如图 4(a)和 4(b)所示。 刻蚀所述绝缘层的方法可以为干 法 RIE刻蚀或其他刻蚀方法。
[0021]然后在所述沟槽 300 中填充金属， 并进行化学机械抛光 CMP, 形成 金属互连线 310, 如图 5(a)和 5(b)所示。 所述金属互连线的材料为铜、 铝、 钨、镍等， 可以通过化学气相淀积、 电镀、 溅射等合适的方法填充所述沟槽。 可选地， 在填充金属之前， 还包括在所述沟槽的侧壁形成阻挡层 311 , 如图 5(a)和 5(b)所示， 防止金属电迁移， 避免器件失效。 所述阻挡层 311的材料 为 Ti、 TiN、 Ta、 TaN等。
[0022]参考图 6(a)和图 6(b), 在步骤 S102中， 形成覆盖所述金属互连线的 掩膜层 210, 在所述掩膜层 210上形成暴露所述金属互连线的开口 220。 其 中， 所述掩膜层 210的材料为光刻胶、 氮化硅等， 所述掩膜层 210与所述绝 缘层 101、 102具有不同的刻蚀选择比， 通过曝光显影或干法 RIE刻蚀形成 开口 220。
[0023]随后如图 7(a)和图 7(b)所示， 执行步骤 S103 , 通过所述开口 220刻 蚀所述金属互连线 310和阻挡层 311 , 形成深槽 320, 实现金属互连线的绝 缘隔离。 刻蚀的方法包括 RIE干法刻蚀、 激光烧蚀、 电子束刻蚀或聚焦离子 束刻蚀。去除光刻胶，形成深槽 320,刻穿所述金属互连线 310和阻挡层 311 , 直到底部的绝缘层材料。 由于刻蚀金属互联线 310与刻蚀绝缘层 101和 102 的速率可能不同， 因此优选采用对金属互联线 310的刻蚀速率更快的刻蚀方 式， 保证金属互联线 310能够被刻蚀断开即可。 通过刻蚀， 将相连的两段金 属互连线隔断绝缘， 用光刻尺度控制共线的金属互连线端点到端点的间距， 缩小了距离， 节省了面积， 同时避免出现金属互连线短路的问题。
[0024]可选地， 形成深槽 320后， 对深槽 320进行填充， 形成绝缘墙 330 (如图 8所示） ， 填充材料为 Si02、 SiOF、 SiCOH、 SiO、 SiCO、 SiCON 等低 k材料， 利于减小互连线间的电容。 所述绝缘墙 330的填充材料可以与 衬底的绝缘层 101和 102不同。 优选地， 所述绝缘墙 330的厚度小于所述金 属互联线的宽度。通过本发明的方法和结构可以实现较小的金属互联线端点 之间的距离。
[0025]随后按照常规半导体制造工艺的步骤完成半导体器件的制造， 例如重 复上述金属互连线的制作方法， 制作新一层金属互连线， 制作焊盘等。
[0026]虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本 发明的精神和所附权利要求限定的保护范围的情况下， 可以对这些实施 例进行各种变化、 替换和修改。 对于其他例子， 本领域的普通技术人员 应当容易理解在保持本发明保护范围内的同时， 工艺步骤的次序可以变 化。
[0027]此外，本发明的应用范围不局限于说明书中描述的特定实施例的工 艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内容， 作为本领域的普通技术人员将容易地理解， 对于目前已存在或者以后即 将开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它 们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的 结果， 依照本发明可以对它们进行应用。 因此， 本发明所附权利要求旨 在将这些工艺、 机构、 制造、 物质组成、 手段、 方法或步骤包含在其保 护范围内。

Claims

权 利 要 求
1、 一种半导体结构的制造方法， 该方法包括以下步骤：
(a)在衬底上形成金属互连线；
(b)形成覆盖所述金属互连线的掩膜层， 在所述掩膜层上形成暴露所述 金属互连线的开口；
(c)通过所述开口刻蚀并断开所述金属互连线， 实现金属互连线的绝缘 隔离。
2、 根据权利要求 1所述的方法， 其中所述金属互连线的材料为铜、 钨、 铝、 镍。
3、 根据权利要求 1所述的方法， 其中步骤 a )中， 所述衬底上具有一层 或多层绝缘层。
4、 根据权利要求 3所述的方法， 其中， 所述绝缘层的材料为氧化硅、 氮化硅、 氮氧化硅、 硼硅玻璃、 磷硅玻璃、 硼磷硅玻璃中的一种或其组合。
5、根据权利要求 1所述的方法， 其中步骤 c )中刻蚀并断开所述金属互 连线的方法为 RIE干法刻蚀、 激光烧蚀、 电子束刻蚀或聚焦离子束刻蚀。
6、 根据权利要求 1所述的方法， 其中， 步骤 a ) 包括：
( i)在绝缘层上形成一层光刻胶， 并进行图形化；
(ii)刻蚀所述绝缘层形成沟槽；
(iii)在所述沟槽中形成金属互连线。
7、 根据权利要求 6所述的方法， 其中步骤 iii ) 中形成金属互连线之前 还包括在所述沟槽的侧壁形成阻挡层。
8、 根据权利要求 7所述的方法， 其中所述阻挡层的材料为 Ti、 TiN、 Ta、 TaN等。
9、 根据权利要求 1所述的方法， 其中步骤 c )中还包括： 完成所述金属 互连线刻蚀之后， 填充所述开口。
10、 根据权利要求 9所述的方法， 填充所述开口的材料为 Si02、 SiOF、 SiCOH、 SiO、 SiCO、 SiCON等。
11、一种半导体结构， 包括衬底以及在衬底中形成的金属互联线，其中： 金属互联线端点之间被形成在衬底中的绝缘墙所断开。
12、 根据权利要求 11所述的半导体结构， 其中， 所述绝缘墙的材料与 衬底的材料不同。
13、 根据权利要求 11或 12所述的半导体结构， 其中， 所述绝缘墙的厚 度小于所述金属互联线的宽度。
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