WO2014029136A1 - 半导体器件制造方法 - Google Patents

半导体器件制造方法 Download PDF

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Publication number
WO2014029136A1
WO2014029136A1 PCT/CN2012/081007 CN2012081007W WO2014029136A1 WO 2014029136 A1 WO2014029136 A1 WO 2014029136A1 CN 2012081007 W CN2012081007 W CN 2012081007W WO 2014029136 A1 WO2014029136 A1 WO 2014029136A1
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Prior art keywords
semiconductor device
etching
fluorocarbon
fabricating
opening
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PCT/CN2012/081007
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English (en)
French (fr)
Inventor
孟令款
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中国科学院微电子研究所
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Priority to US13/883,834 priority Critical patent/US20140199846A1/en
Publication of WO2014029136A1 publication Critical patent/WO2014029136A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners

Definitions

  • the present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly to a high aspect ratio silicon nitride contact hole fabrication and etching technique. Background technique
  • the contact hole etched medium of the conventional CMOS device is silicon dioxide, and silicon nitride, which is another widely used dielectric material, has hardly been used as an interlayer dielectric (ILD) layer because of its K value and large stress. It is primarily used for hard masking, etching or CMP stop layers. With the in-depth development of semiconductor devices, it has also become a useful place in the three- and five-group optoelectronic crystal devices.
  • ILD interlayer dielectric
  • fluorocarbon-based gases such as CF 4 , CHF 3 , CH 2 F 2 , CH 3 F, etc. are generally used for etching, and for the silicon oxide hole etching, in order to obtain relatively steep deep holes.
  • high-power, high-carbon chain molecular gases such as C 4 F 6 , C 4 F 8 , etc. are often used.
  • Silicon nitride has a weaker bond energy than silicon oxide and has a property between silicon oxide and silicon material.
  • an object of the present invention is to provide an innovative contact hole etching method for improving the sidewall straightness and the aspect ratio, and at the same time, improving the filling rate of the insulating medium, and finally improving the reliability of the device.
  • the above object of the present invention is to provide a method for fabricating a semiconductor device, comprising: etching a plurality of first openings in an interlayer dielectric layer on a substrate; forming an opening modification layer in the plurality of first openings; The opening modification layer is etched until the substrate is exposed to form a plurality of second openings, wherein the second opening has an aspect ratio greater than an aspect ratio of the first opening.
  • the interlayer dielectric layer comprises silicon oxide, silicon nitride, low ⁇ material and combinations thereof.
  • the opening modification layer comprises silicon nitride.
  • an opening modification layer is formed by LPCVD and PECVD deposition.
  • the opening modification layer is etched by plasma dry etching, and the etching gas includes a fluorocarbon-based gas and an oxidizing gas.
  • the fluorocarbon-based gas includes CF 4 , CHF 3 , CH 3 F, CH 2 F 2 and combinations thereof.
  • the fluorocarbon-based gas comprises a first type of fluorocarbon-based gas and a second type of fluorocarbon-based gas, and the first type of fluorocarbon-based gas has a fluorocarbon ratio lower than that of the second type of fluorocarbon-based gas.
  • the first type of fluorocarbon-based gas comprises CF 4 , CHF 3 , CH 3 F, CH 2 F 2 and combinations thereof
  • the second type of fluorocarbon-based gas comprises C 4 F 6 , C 4 F 8 and combinations thereof.
  • the oxidizing gas includes CO, 0 2 and a combination thereof.
  • the interlayer dielectric layer is etched by plasma dry etching, and the etching gas includes C 4 F 6 , C 4 F 8 and a combination thereof.
  • the underlying structure is further included in the substrate and/or the substrate, and the plurality of first openings and/or the plurality of second openings expose the underlying structure.
  • the device for etching the opening modification layer is a LAM Exelan HPt cavity or a micro-semiconductor Primo DRIE cavity, and both adopt a dual RF system.
  • a large silicon oxide deep hole is prepared under the condition of a conventional photolithography process, and then a silicon nitride film is deposited to obtain a desired feature size, and a unique fluorocarbon-based gas is used for engraving.
  • the silicon nitride is etched deep to obtain a higher aspect ratio structure.
  • FIG. 1 to 3 are schematic cross-sectional views showing respective steps of a method of fabricating a semiconductor device in accordance with the present invention
  • Fig. 4 is a flow chart showing a method of fabricating a semiconductor device in accordance with the present invention.
  • a plurality of first openings 3A are formed by etching in the interlayer dielectric layer 3 on the substrate 1.
  • the substrate 1 is provided, which may be a bulk Si, SOI, bulk Ge, GeOI, SiGe, GeSb, or a III-V or II-VI compound semiconductor substrate such as GaAs, GaN, InP, InSb or the like.
  • substrate 1 is preferably a bulk Si or SOI.
  • a plurality of underlying structures 2 are formed in the substrate 1 and/or on the substrate 1 by an existing semiconductor device manufacturing process (e.g., CMOS compatible process).
  • the lower structure 2 may be a source/drain region, a metal silicide on the source/drain region, or a gate in the MOSFET, and the lower structure 2 may also be a lower interconnection in the integrated circuit (for example, in a multilayer interconnection)
  • the lower interconnect line, or the contact pad may also be the source of the MOSFET source or drain in the memory cell, or the capacitor of a passive device such as a capacitor in the cell, or the underlying structure 2 is used for protection.
  • An etch stop layer of other device structures eg, a contact etch stop layer CESL in a back gate process, or an etch stop layer between multilayer interconnects).
  • the underlying structure 2 is formed in the substrate 1 and is located near the upper surface of the substrate 1, the underlying structure 2 may actually be formed on the upper surface of the substrate 1 (for example, a gate protruding from the surface of the substrate)
  • the electrode is formed in the lower surface of the substrate 1.
  • the lower structure 2 is shown as a whole in FIG. 1, the lower structure 2 may be divided into a plurality of parts according to the circuit layout requirements, for example, representing the source and drain regions of the MOSFET, respectively, or representing different wiring layers. .
  • ILD3 may be silicon oxide, silicon nitride, low-k materials, and combinations thereof (the combination may be stacked or hybrid), wherein low-k materials include, but are not limited to, organic low-k materials (eg, organic groups containing aryl or polycyclic rings).
  • ILD3 inorganic low-k materials (eg amorphous carbon-nitrogen thin films, polycrystalline boron-nitrogen thin films, fluorosilicate glass, BSG, PSG, BPSG), porous low-k materials (eg, disilane trioxane (SSQ) based porous low Bismuth material, porous silica, porous SiOCH, C-doped silica, F-doped amorphous carbon, porous diamond, porous organic polymer).
  • the method of forming ILD3 may be rapid thermal oxidation (RTO), LPCVD, PECVD, HDPCVD, spin coating, spray coating, screen printing, etc.
  • the thickness of the ILD 3 is greater than or equal to the thickness of the contact plug or interconnect to be formed.
  • the ILD 3 is etched until the underlying structure 2 is exposed, and a plurality of first openings 3A are formed.
  • the first opening 3A may be a contact hole (for example, a source/drain contact hole in a MOSFET), or may be a trench (for example, a multilayer interconnection corresponding to a space occupied by a certain layer of wiring in a damascene structure).
  • the aspect ratio of the first opening 3A is preferably greater than 2.5:1 and its width is greater than the actual opening width that is ultimately required to be formed.
  • the first opening 3A has a width of 180 nm and a depth of 500 nm.
  • plasma dry etching can be performed using a fluorocarbon-based gas to obtain a relatively steep and high aspect ratio opening.
  • the fluorocarbon-based gas may be CF 4 , CHF 3 , CH 2 F 2 , CH 3 F, and in order to obtain a steep opening of a higher aspect ratio, the fluorocarbon-based gas is preferably a high-power, high-carbon chain molecular gas such as C 4 F 6 , C 4 F 8 , etc.
  • the carbon fluorination of gases such as C 4 F 6 and C 4 F 8 is relatively high, in addition to being an etch gas, it is more important that it can produce more silicon oxycarbon fluoropolymer film deposited on the sidewall of the hole and At the bottom, an anisotropic etch is formed on the ILD 3 made of a material such as silicon oxide.
  • an opening modification layer 4 is formed in the plurality of first openings 3A.
  • the material of the opening modification layer 4 is different from the substrate 1 and ILD3, such as silicon nitride, for modifying the steep sidewalls of the opening and adjusting the aspect ratio of the opening.
  • the method of forming the opening modification layer 4 may be LPCVD, PECVD, HDPCVD, or the like, and is preferably LPCVD.
  • the thickness of the opening modification layer 4 is determined in accordance with the difference between the width of the first opening 3A and the width of the finally required second opening 3B (shown in Fig. 3).
  • the width of the second opening 3B will be 80 nm, which will increase the aspect ratio from 2.67:1 to 6.25:1.
  • any insulating material different from the material of the substrate 1 and the ILD 3 can be used as the opening modification layer 4 as long as the phase can be made.
  • the opening modification layer 4 is etched until the substrate 1 or the underlying structure 2 is exposed, and a plurality of second openings 3B are formed.
  • the etching method is preferably plasma dry etching.
  • the etching apparatus is, for example, a LAM Exelan HPt cavity, a dual radio frequency system, a high frequency power of 27 MHz for generating plasma for adjusting plasma density, and a low frequency system of 2 MHz. Enhance ion energy and bombardment intensity, and improve etch direction. This makes it possible to perform different optimizations depending on the specific characteristics of the etched deep holes without changing the other features of the etched holes. Other manufacturers' etching equipment is based on the same principle and can be similarly adjusted, and is also within the scope of this patent.
  • the etching gas for plasma dry etching includes a fluorocarbon-based gas and an oxidizing gas.
  • the hydrogen-containing fluorocarbon-based gases CH 3 F, CHF 3 , and CH 2 F 2 etch the silicon nitride film, and the etching rate can be improved not only by generating less polymer.
  • the cleaning step after etching is also better controlled.
  • the oxidizing gas CO, 0 2 is used to assist in the removal of the polymer that has been produced and produced during the etching process so that the etching does not stop.
  • the addition of oxidizing gas should take into account the effect of polymer removal to obtain the desired CD.
  • etching is preferably performed by CHF 3 , CH 2 F 2 , 0 2 , and the like. Due to the large number of etching equipment manufacturers, the parameter setting here is exemplified by the LAM Exelan HPt etching equipment. The chamber pressure was maintained at 60 mt, and the gas flow rates were 30 sccm CHF 3 , 20 sccm CH 2 F 2 , lOsccm 0 2 500 sccm Ar, and the high and low frequency power was selected to be 600 W/400 W, thereby etching a steep topography.
  • the above steep topography poses considerable challenges for subsequent filling.
  • the bottom size will be smaller and the top will be slightly larger.
  • the flow rate of the fluorocarbon-based gas for example, CH 2 F 2
  • the flow rate of the oxidizing gas such as 0 2
  • the polymer deposited at the bottom can be bombarded at low frequency and high power without affecting anisotropic etching.
  • a slightly slanted etched topography is formed.
  • the process parameters can be set as follows, the chamber pressure is 60 mt, and the gas flow rates are 30 sccm CHF 3 , 25 sccm CH 2 F 2 , 8 sccm 0 2 , 500 sccm Ar, and the high and low frequency power is 600 W/400 W.
  • the etching method is preferably plasma dry etching
  • the etching device is, for example, a micro-semiconductor Primo DRIE cavity, a dual-radio system, and a high-frequency power of 60 MHz.
  • a plasma is generated to adjust the plasma density; a low frequency system of 2 MHz is used to enhance ion energy and bombardment intensity, and to improve etching directivity.
  • the two are decoupled to avoid mutual influence. This allows for different optimizations based on the specific characteristics of the etched deep holes without changing the morphological features of the etched holes in other respects.
  • Other manufacturers' etching equipment is based on the same principle and can be similarly adjusted, and is also within the scope of this patent.
  • the etching gas for plasma dry etching includes a fluorocarbon-based gas and an oxidizing gas. Since the silicon nitride etching mechanism is different from that of silicon oxide, if a high carbon chain molecule (higher carbon and fluorine) is still used alone, it is easy to generate more polymer, the sidewall becomes rough, and the etched polymer The removal step is more difficult. Therefore, high bias power is often required to break high carbon chain molecules, which is easy to remove in the reaction with 0 2 . Thereby, a better etched topography is obtained.
  • the fluorocarbon-based gas includes at least two types: one is a hydrogen-containing fluorocarbon-based gas having a relatively low fluorocarbon, such as CH 3 F, CHF 3 , CH 2 F 2 and combinations thereof, for nitriding Silicon film is etched due to less poly Compound, not only can improve the etching speed, but also better control after the etching; the other is a fluorocarbon-based gas with higher fluorocarbon, such as C 4 F 6 , C 4 F 8 , due to its carbon Fluorine is relatively high.
  • a fluorocarbon-based gas with higher fluorocarbon, such as C 4 F 6 , C 4 F 8 , due to its carbon Fluorine is relatively high.
  • the oxidizing gases include CO, 02, and combinations thereof to aid in the removal of the polymer that has been produced and produced during the etching process so that the etching does not stop.
  • the addition of oxidizing gas should take into account the effect of polymer removal to obtain the desired CD.
  • etching is preferably performed on C 4 F 8 , CH 2 F 2 , 0 2 , and the like. Due to the large number of etching equipment manufacturers, the parameter setting here is exemplified by the etching equipment of the micro-semiconductor Primo DRIE. The chamber pressure was maintained at 40 mt, and the gas flow rates were 40 sccm C 4 F 8 , 80 sccm CH 2 F 2 , lOOsccm 0 2 , 400 sccm Ar, and the high and low frequency power was selected to be 600 W/1500 W, thereby etching a steep topography.
  • the above steep topography poses considerable challenges for subsequent filling.
  • the bottom size will be smaller and the top will be slightly larger.
  • the fluorocarbon-based gas for example, C 4 F 8
  • the oxidizing gas such as 0 2
  • Lateral etching is reduced.
  • the polymer deposited at the bottom can be bombarded at low frequency and high power without affecting anisotropic etching. Eventually, a slightly slanted etched topography is formed.
  • the process parameters can be set as follows, the chamber pressure is 40 mt, and the gas flow rates are 50 sccm C 4 F 8 , 80 sccm CH 2 F 2 , 90 sccm O 2 , 400 sccm Ar, and the high and low frequency power is 600 W/1500 W.
  • the finally formed second opening 3B is an actually required contact hole or interconnect trench having a width smaller than that of the first opening 3A, thereby increasing the aspect ratio.
  • the width of the first opening 3A is 180 nm and the depth is 500 nm, and the thickness of the opening modification layer 4 is 100 nm
  • the width of the second opening 3B will be 80 nm, thereby increasing the aspect ratio from 2.67:1 to 6.25: 1.
  • the thicknesses of the various layers shown in Figures 1 through 3 are not drawn to scale in accordance with the quantitative relationship, and are only intended to illustrate the mutual positional relationship and therefore should not be considered as limiting the relative thickness relationship of the various layers of the present invention.
  • any description cannot exhaust the specific etching of different films. Therefore, when selecting a gas, it depends on the needs and different films, and different etching patterns can be obtained depending on the specific conditions. If the amount of polymer is increased (increasing the flow rate of the fluorocarbon-based gas), a slightly inclined deep hole can be produced, but the filling of the subsequent medium can be facilitated; the oxidizing gas can be added, the amount of the polymer can be adjusted, and a relatively deep deep hole can be formed, but it is possible It will challenge the filling of subsequent media.
  • the etching etching layer of the present invention uses different etching gases in two different etching apparatuses
  • the apparatus and the gas composition are interchangeable, that is, the LAM Exelan HPt cavity can use the above first type.
  • Carbon The fluorine-based gas and the second-type fluorocarbon-based gas, or the micro-semiconductor Primo DRIE cavity may also use only a low carbon-to-fluorine ratio etching gas.
  • a large silicon oxide deep hole is prepared under the condition of a conventional photolithography process, and then a silicon nitride film is deposited to obtain a desired feature size, and a unique fluorocarbon-based gas is used for engraving.
  • the silicon nitride is etched deep to obtain a higher aspect ratio structure.

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Abstract

一种半导体器件制造方法，包括：在衬底（1）上的层间介质层（3）中刻蚀形成多个第一开口（3A）；在多个第一开口（3A）中形成开口修饰层（4）；刻蚀开口修饰层（4），直到暴露衬底（1），形成多个第二开口（3B），其中第二开口（3B）的深宽比大于第一开口的深宽比（3A）。依照该半导体器件制造方法，基于传统光刻工艺的条件下制备出较大的氧化硅深孔，然后沉积氮化硅薄膜获得所需要的特征尺寸，并采用独特的碳氟基气体来刻蚀氮化硅深孔，从而获得较高深宽比结构。

Description

半导体器件制造方法
本申请要求了 2012年 8月 21 日提交的、 申请号为 201210300046.6、 发明名称为
"半导体器件制造方法"的中国专利申请的优先权， 其全部内容通过引用结合在本申 请中。 技术领域
本发明涉及半导体集成电路制造领域， 更具体地， 涉及一种高深宽比氮化硅接触 孔制造及刻蚀技术。 背景技术
接触孔刻蚀是超大规模集成电路的关键技术， 随着 CMOS进入 32nm后的工艺时 代，高深宽比孔刻蚀及其填充对器件的良率有相当大的影响。对于先进的存储器而言， 深宽比已经达到了 40: 1以上的比例， 这使得挑战更加巨大。
传统的 CMOS器件的接触孔刻蚀的介质是二氧化硅，作为另一应用广泛的电介质 材料氮化硅， 由于其 K值及应力较大几乎没有使用其作为层间介质 （ILD) 层。 它主 要用于硬掩摸、 刻蚀或者 CMP的停止层。 随着半导体器件的深入发展， 在三、 五族 光电晶体器件中也有了用武之地。
对于氧化硅、 氮化硅薄膜， 一般采用碳氟基气体如 CF4、 CHF3、 CH2F2、 CH3F等 来刻蚀， 而对于氧化硅孔刻蚀为了获得较为陡直的深孔结构， 则往往采用高功率、 高 碳链分子气体如 C4F6、 C4F8等。 氮化硅具有比氧化硅更弱的键能， 特性介于氧化硅与 硅材料之间。 如果需要刻蚀高深宽比的氮化硅孔结构， 则要对氟基气体有良好控制， 同时， 大碳链分子往往会产生较多的聚合物， 以获得较陡直的深孔； 但又不至于由于 深孔内刻蚀抑制剂太多而导致刻蚀停止， 则需要氧化性气体 02能有效去除侧壁上的 聚合物。
另外， 随着摩尔定律的持续推进， 孔特征尺寸 （CD) 已经进入 lOOnm的尺寸， 如无先进的光刻工艺， 直接进行如此小氮化硅孔的制备是不可能的。 总之， 现有的高 深宽比接触孔刻蚀技术存在缺陷， 需要进一步提高接触孔刻蚀陡直度以及绝缘介质填 充率， 确保器件可靠性。 发明内容
有鉴于此， 本发明的目的在于提供一种创新性的接触孔刻蚀方法， 提高侧壁陡直 度以及深宽比， 同时还能提高绝缘介质填充率， 最终提高了器件的可靠性。
实现本发明的上述目的， 是通过提供一种半导体器件制造方法， 包括： 在衬底上 的层间介质层中刻蚀形成多个第一开口； 在多个第一开口中形成开口修饰层； 刻蚀开 口修饰层， 直至暴露衬底， 形成多个第二开口， 其中第二开口的深宽比大于第一开口 的深宽比。
其中， 层间介质层包括氧化硅、 氮化硅、 低 κ材料及其组合。
其中， 开口修饰层包括氮化硅。
其中， 采用 LPCVD、 PECVD沉积形成开口修饰层。
其中， 采用等离子体干法刻蚀来刻蚀开口修饰层， 刻蚀气体包括碳氟基气体和氧 化性气体。
其中， 碳氟基气体包括 CF4、 CHF3、 CH3F、 CH2F2及其组合。
其中， 碳氟基气体包括第一类碳氟基气体以及第二类碳氟基气体， 第一类碳氟基 气体的碳氟比要小于第二类碳氟基气体的碳氟比。
其中， 第一类碳氟基气体包括 CF4、 CHF3、 CH3F、 CH2F2及其组合， 第二类碳氟 基气体包括 C4F6、 C4F8及其组合。
其中， 氧化性气体包括 CO、 02及其组合。
其中， 采用等离子体干法刻蚀来刻蚀层间介质层， 刻蚀气体包括 C4F6、 C4F8及其 组合。
其中， 衬底中和 /或衬底上还包括下层结构， 多个第一开口和 /或多个第二开口暴 露下层结构。
其中，刻蚀开口修饰层的设备是采用 LAM Exelan HPt腔体或者中微半导体 Primo DRIE腔体， 并且均采用双射频系统。
依照本发明的半导体器件制造方法， 基于传统光刻工艺的条件下制备出较大的 氧化硅深孔， 然后沉积氮化硅薄膜获得所需要的特征尺寸， 并采用独特的碳氟基气体 来刻蚀氮化硅深孔， 从而获得较高深宽比结构。 附图说明 以下参照附图来详细说明本发明的技术方案， 其中：
图 1至图 3为依照本发明的半导体器件制造方法各步骤的剖面示意图； 以及 图 4为依照本发明的半导体器件制造方法的流程图。 具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技 术效果。 需要指出的是， 类似的附图标记表示类似的结构， 本申请中所用的术语 "第 一"、 "第二"、 "上"、 "下"、 "厚"、 "薄"等等可用于修饰各种器件结构。 这些修饰除 非特别说明并非暗示所修饰器件结构的空间、 次序或层级关系。
参照图 4以及图 1，在 S401 ,在衬底 1上的层间介质层 3中刻蚀形成多个第一开口 3A。 提供衬底 1， 其可以是体 Si、 SOI、 体 Ge、 GeOI 、 SiGe、 GeSb, 也可以是 III- V族 或者 II- VI族化合物半导体衬底，例如 GaAs、 GaN、 InP、 InSb等等。为了与现有的 CMOS 工艺兼容以应用于大规模数字集成电路制造， 衬底 1优选地为体 Si或者 SOI。 采用现有 的半导体器件制造工艺 （例如 CMOS兼容工艺）， 在衬底 1中和 /或衬底 1上形成多个下 层结构 2。 其中， 下层结构 2在 MOSFET中可以是源漏区、 源漏区上的金属硅化物、 或 者是栅极， 下层结构 2在集成电路中也可以是下层互连线 （例如多层互连中的下层互 连线， 或者是接触焊垫）， 在存储器阵列中也可以是存储器单元中的 MOSFET源端或 者漏端、 或者单元中的电容等无源器件的电极， 或者下层结构 2是用于保护其他器件 结构的刻蚀停止层 （例如后栅工艺中的接触刻蚀停止层 CESL, 或者多层互连之间的 刻蚀停止层）。 图 1中虽然仅显示了下层结构 2形成在衬底 1中并且位于衬底 1上表面附 近，但是实际上下层结构 2也可以形成在衬底 1上表面之上（例如突出衬底表面的栅极） 或者形成在衬底 1的下表面中。 此外， 虽然图 1中显示下层结构 2为相连的一个整体， 但是实际上下层结构 2可以依照电路布局需要而划分成多个部分， 例如分别代表 MOSFET源区和漏区， 或者代表不同的布线层。
在衬底 1上形成层间介质层 （ILD) 3。 ILD3可以是氧化硅、 氮化硅、 低 K材料及 其组合 （组合方式可以是堆叠也可以是混杂)， 其中低 K材料包括但不限于有机低 K材 料（例如含芳基或者多元环的有机聚合物）、 无机低 K材料（例如无定形碳氮薄膜、 多 晶硼氮薄膜、氟硅玻璃、 BSG、 PSG、 BPSG)、 多孔低 K材料（例如二硅三氧烷（SSQ) 基多孔低 Κ材料、 多孔二氧化硅、 多孔 SiOCH、 掺 C二氧化硅、 掺 F多孔无定形碳、 多 孔金刚石、 多孔有机聚合物）。 形成 ILD3的方法可以是快速热氧化 （RTO)、 LPCVD、 PECVD、 HDPCVD, 旋涂、 喷涂、 丝网印刷等等。 ILD3的厚度要大于等于需要形成 的接触塞或者互连线的厚度。
刻蚀 ILD3 , 直至暴露下层结构 2， 形成多个第一开口 3A。 第一开口 3A可以是接触 孔 （例如 MOSFET中的源漏接触孔）， 也可以是沟槽 （例如多层互连中， 对应于大马 士革结构中的某一层布线所占据的空间）。 其中， 第一开口 3A的深宽比优选地大于 2.5: 1 , 并且其宽度要大于最终需要形成的实际开口宽度。 例如第一开口 3A的宽度是 180nm， 深度是 500nm。 具体地， 对于氧化硅材质的 ILD3 , 可以采用碳氟基气体进行 等离子体干法刻蚀， 获得较为陡直的并且较高深宽比的开口。 碳氟基气体可以是 CF4、 CHF3、 CH2F2、 CH3F， 并且为了获得更高深宽比的陡直开口， 碳氟基气体优选地是高 功率、 高碳链分子气体如 C4F6、 C4F8等。 由于 C4F6、 C4F8等气体的基碳氟比较高， 除 了作为刻蚀性气体， 更重要的在于其能够产生较多的硅氧碳氟聚合物薄膜， 沉积在孔 洞侧壁及底部， 从而对氧化硅等材质的 ILD3形成各向异性刻蚀。
参照图 4以及图 2， 在 S402, 在多个第一开口 3A中形成开口修饰层 4。 开口修饰层 4 的材质不同于衬底 1以及 ILD3 , 例如是氮化硅， 用于修饰开口的陡直侧壁以及调整开 口的深宽比。 形成开口修饰层 4的方法可以是 LPCVD、 PECVD、 HDPCVD等， 并且优 选 LPCVD。 开口修饰层 4的厚度依照第一开口 3A的宽度与最终需要的第二开口 3B (图 3中所示） 的宽度之差来决定。 例如开口修饰层 4的厚度为 lOOnm时， 第二开口 3B的宽 度将为 80nm， 由此将使得深宽比从 2.67: 1增大至 6.25: 1。值得注意的是， 虽然本发明实 施例中仅列举了氮化硅材质的开口修饰层 4，但是任何与衬底 1以及 ILD3材质不同的绝 缘材料均可以用作开口修饰层 4， 只要能使得相邻材料层之间具有较大的刻蚀选择比， 也即在相同刻蚀气体下刻蚀速率不同、或者在不同刻蚀气体下刻蚀速率（更大程度地) 不同。
参照图 4以及图 3， 在 S403 , 刻蚀开口修饰层 4， 直至暴露衬底 1或者下层结构 2， 形成多个第二开口 3B。 刻蚀方法优选地是等离子体干法刻蚀。
在本发明一个实施例中， 刻蚀设备例如是采用 LAM Exelan HPt腔体， 采用双射频 系统， 高频功率为 27MHz主要用来产生等离子体， 用于调节等离子体密度； 低频系统 为 2MHz用于增强离子能量及轰击强度， 提升刻蚀方向性。 这使得可以根据刻蚀深孔 的具体特点进行不同的优化， 而不改变所刻蚀孔在其他方面的形貌特征。 其他厂商的 刻蚀设备基于同样的原理， 可以进行类似的调节， 亦属于本专利的保护范围。 等离子 体干法刻蚀的刻蚀气体包括碳氟基气体以及氧化性气体。 由于氮化硅刻蚀机制与氧化 硅不同， 如果仍然采用如此高碳链分子， 易于产生较多的聚合物， 使得侧壁变得粗糙， 并且， 刻蚀后的聚合物清除步骤较为困难。 因此， 在当前的本发明中， 优选含氢碳氟 基气体 CH3F、 CHF3、 CH2F2对氮化硅薄膜进行刻蚀， 由于产生较少的聚合物， 不仅能 够提升刻蚀速度， 而且在刻蚀后清除步骤也较好控制。 氧化性气体 CO、 02用于辅助 性的去除已产生的并且在刻蚀过程中产生的聚合物， 使得刻蚀不至于停止。 但氧化性 气体的添加大小， 要考虑到对聚合物去除的影响， 以获得理想的 CD。
具体地， 作为一个实施例， 优选 CHF3、 CH2F2、 02等进行刻蚀。 由于刻蚀设备厂 商众多， 这里的参数设定以 LAM Exelan HPt的刻蚀设备为例。 腔体压力保持在 60mt， 气体流量分别为 30sccm CHF3、 20sccm CH2F2、 lOsccm 02 500sccm Ar, 高低频功率 选择 600W/400W, 从而刻蚀出陡直的形貌。
此外，对于高深宽比的刻蚀孔， 上述陡直的形貌，会为后续的填充带来相当挑战。 有时候为了后续的工艺， 会将底部的尺寸做的小一些， 顶部的略大一些。 作为一个实 施例， 通过增加碳氟基气体 （例如 CH2F2) 的流量， 同时也可降低例如 02的氧化性气 体的流量， 增强聚合物在侧壁的沉积， 使得侧向刻蚀降低。 底部沉积的聚合物可以在 低频高功率下被轰击掉， 而不影响各向异性的刻蚀。 最终， 形成略倾斜的刻蚀形貌。 工艺参数可以设定如下，腔体压力 60mt，气体流量分别为 30sccm CHF3、 25sccm CH2F2、 8sccm 02、 500sccm Ar, 高低频功率选择 600W/400W。
在本发明另一个实施例中， 刻蚀方法优选地是等离子体干法刻蚀， 并且刻蚀设备 例如是采用中微半导体 Primo DRIE腔体， 采用双射频系统， 高频功率为 60MHz主要用 来产生等离子体， 用于调节等离子体密度； 低频系统为 2MHz用于增强离子能量及轰 击强度， 提升刻蚀方向性。 两者之间是去耦合的， 以免相互影响。 这使得可以根据刻 蚀深孔的具体特点进行不同的优化， 而不改变所刻蚀孔在其他方面的形貌特征。 其他 厂商的刻蚀设备基于同样的原理， 可以进行类似的调节， 亦属于本专利的保护范围。
等离子体干法刻蚀的刻蚀气体包括碳氟基气体以及氧化性气体。 由于氮化硅刻蚀 机制与氧化硅不同， 如果仍然单纯采用高碳链分子 （碳氟比较高）， 易于产生较多的 聚合物， 使得侧壁变得粗糙， 并且， 刻蚀后的聚合物清除步骤较为困难。 因此， 往往 需要较高的偏置功率将高碳链分子打碎， 在与 02的反应中易于去除。 从而， 获得较好 的刻蚀形貌。
在当前的本发明中， 碳氟基气体至少包括两种： 一种是碳氟比较低的含氢碳氟基 气体， 如 CH3F、 CHF3、 CH2F2及其组合， 对氮化硅薄膜进行刻蚀， 由于产生较少的聚 合物， 不仅能够提升刻蚀速度， 而且在刻蚀后清除步骤也较好控制； 另一种是碳氟比 较高的碳氟基气体， 例如 C4F6、 C4F8， 由于其碳氟比较高， 除了作为刻蚀性气体， 更 重要的在于其能够产生较多的硅氧碳氟聚合物薄膜， 沉积在孔洞侧壁及底部， 从而对 氧化硅形成各向异性刻蚀。
氧化性气体包括 CO、 02及其组合， 用于辅助性的去除已产生的并且在刻蚀过程 中产生的聚合物， 使得刻蚀不至于停止。 但氧化性气体的添加大小， 要考虑到对聚合 物去除的影响， 以获得理想的 CD。
具体地， 作为一个实施例， 优选 C4F8、 CH2F2、 02等进行刻蚀。 由于刻蚀设备厂 商众多， 这里的参数设定以中微半导体 Primo DRIE的刻蚀设备为例。 腔体压力保持在 40mt， 气体流量分别为 40sccm C4F8、 80sccm CH2F2、 lOOsccm 02、 400sccm Ar, 高低 频功率选择 600W/1500W, 从而刻蚀出陡直的形貌。
此外，对于高深宽比的刻蚀孔， 上述陡直的形貌，会为后续的填充带来相当挑战。 有时候为了后续的工艺， 会将底部的尺寸做的小一些， 顶部的略大一些。 作为一个实 施例， 通过增加高碳氟比的碳氟基气体 （例如 C4F8) 的流量， 同时也可降低例如 02的 氧化性气体的流量， 增强聚合物在侧壁的沉积， 使得侧向刻蚀降低。 底部沉积的聚合 物可以在低频高功率下被轰击掉， 而不影响各向异性的刻蚀。 最终， 形成略倾斜的刻 蚀形貌。工艺参数可以设定如下，腔体压力 40mt，气体流量分别为 50sccm C4F8、 80sccm CH2F2、 90sccm O2、 400sccm Ar, 高低频功率选择 600W/1500W。
最终形成的第二开口 3B为实际所需的接触孔或者互连线沟槽，其宽度要小于第一 开口 3A， 因此提高了深宽比。 例如第一开口 3A的宽度为 180nm且深度为 500nm， 开口 修饰层 4的厚度为 lOOnm时， 第二开口 3B的宽度将为 80nm， 由此将使得深宽比从 2.67: 1 增大至 6.25: 1。 图 1至图 3中所示各个层的厚度并非依照数量关系等比例绘制， 仅为了 示意相互位置关系， 因此不应视作限定了本发明的各个层的相对厚度关系。
此外， 由于刻蚀设备可调节的参数实在太多， 任何说明都无法穷尽不同薄膜不同 状况的具体刻蚀。 因此， 在选用气体时， 要根据需求及不同的薄膜而定， 进而视具体 情况可获得不同的刻蚀形貌。 如增加聚合物量 （增加碳氟基气体流量）， 可产生略倾 斜的深孔， 却可以方便后续介质的填充； 增加氧化性气体， 可调节聚合物数量， 形成 较为陡直的深孔， 但可能会对后续介质的填充带来挑战。
此外， 虽然本发明刻蚀修饰层时在两个不同刻蚀设备中使用了不同的刻蚀气体， 但是设备与气体组成是可以互换的， 也即 LAM Exelan HPt腔体可以使用上述第一类碳 氟基气体以及第二类碳氟基气体， 或者中微半导体 Primo DRIE腔体也可以仅使用低碳 氟比的刻蚀气体。
依照本发明的半导体器件制造方法， 基于传统光刻工艺的条件下制备出较大的氧 化硅深孔， 然后沉积氮化硅薄膜获得所需要的特征尺寸， 并采用独特的碳氟基气体来 刻蚀氮化硅深孔， 从而获得较高深宽比结构。
尽管已参照一个或多个示例性实施例说明本发明， 本领域技术人员可以知晓无需 脱离本发明范围而对形成器件结构的方法做出各种合适的改变和等价方式。 此外， 由 所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。 因 此， 本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实 施例， 而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims

权 利 要 求
1 . 一种半导体器件制造方法， 包括：
在衬底上的层间介质层中刻蚀形成多个第一开口；
在多个第一开口中形成开口修饰层；
刻蚀开口修饰层， 直至暴露衬底， 形成多个第二开口， 其中第二开口的深 宽比大于第一开口的深宽比。
2. 如权利要求 1的半导体器件制造方法， 其中， 层间介质层包括氧化硅、 氮 化硅、 低 K材料及其组合。
3. 如权利要求 1的半导体器件制造方法， 其中， 开口修饰层包括氮化硅。
4. 如权利要求 1的半导体器件制造方法， 其中， 采用 LPCVD、 PECVD沉积 形成开口修饰层。
5. 如权利要求 1的半导体器件制造方法， 其中， 采用等离子体干法刻蚀来刻 蚀开口修饰层， 刻蚀气体包括碳氟基气体和氧化性气体。
6. 如权利要求 5的半导体器件制造方法，其中，碳氟基气体包括 CF4、 CHF3、 CH3F、 CH2F2及其组合。
7. 如权利要求 5的半导体器件制造方法， 其中， 碳氟基气体包括第一类碳氟 基气体以及第二类碳氟基气体， 第一类碳氟基气体的碳氟比要小于第二类碳氟基气体 的碳氟比。
8. 如权利要求 7的半导体器件制造方法，其中，第一类碳氟基气体包括 CF4、 CHF3、 CH3F、 CH2F2及其组合， 第二类碳氟基气体包括 C4F6、 C4F8及其组合。
9. 如权利要求 5的半导体器件制造方法， 其中， 氧化性气体包括 CO、 02及 其组合。
10. 如权利要求 1的半导体器件制造方法， 其中， 采用等离子体干法刻蚀来刻 蚀层间介质层， 刻蚀气体包括 C4F6、 C4F8及其组合。
11 . 如权利要求 1 的半导体器件制造方法， 其中， 衬底中和 /或衬底上还包括 下层结构， 多个第一开口和 /或多个第二开口暴露下层结构。
12. 如权利要求 1的半导体器件制造方法， 其中， 刻蚀开口修饰层的设备是采 用 LAM Exelan HPt腔体或者中微半导体 Primo DRIE腔体， 并且均采用双射频系统。
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