WO2012092695A1 - 层间电介质的近界面平坦化回刻方法 - Google Patents

层间电介质的近界面平坦化回刻方法 Download PDF

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WO2012092695A1
WO2012092695A1 PCT/CN2011/001326 CN2011001326W WO2012092695A1 WO 2012092695 A1 WO2012092695 A1 WO 2012092695A1 CN 2011001326 W CN2011001326 W CN 2011001326W WO 2012092695 A1 WO2012092695 A1 WO 2012092695A1
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etching
etch
layer
plasma
sog
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PCT/CN2011/001326
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English (en)
French (fr)
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孟令款
殷华湘
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中国科学院微电子研究所
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Priority to US13/381,005 priority Critical patent/US8828881B2/en
Publication of WO2012092695A1 publication Critical patent/WO2012092695A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the invention relates to a Chinese patent application filed on January 7, 2011, the application number is 2011100031 18.6, and the invention name is "inter-interface flattening and etchback method for interlayer dielectric" Priority is hereby incorporated by reference in its entirety.
  • the present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly to a near-interface planarization etchback method for an interlayer dielectric layer (ILD).
  • ILD interlayer dielectric layer
  • this SOG etchback method does not provide better etch uniformity, resulting in a large variation in thickness of the entire wafer in different regions because the edge etch rate is faster than the intermediate region, which exacerbates this non-uniformity.
  • the difference in etch rate between different regions is derived from the polymer produced during the etchback SOG process because of the difference in gas pressure inside the etch chamber and the residual in different regions. The amount of polymer determines the size of the etch rate.
  • the thickness is flattened due to the difference in etching rate and etching unevenness of different dielectric materials.
  • Figure 1 shows the basic sequence of the Gate-Last process.
  • a pad oxide layer 3 is deposited on a substrate 1 having shallow trench isolation (STI) 2, and a dummy gate structure 4 is deposited on the pad oxide layer 3.
  • the dummy gate structure 4 generally includes polysilicon, non- The dummy gate of the crystalline silicon and the normally nitrided spacer sidewalls on either side of the dummy gate may also include a nitride layer on the dummy gate.
  • FIG. 1A a pad oxide layer 3 is deposited on a substrate 1 having shallow trench isolation (STI) 2, and a dummy gate structure 4 is deposited on the pad oxide layer 3.
  • the dummy gate structure 4 generally includes polysilicon, non- The dummy gate of the crystalline silicon and the normally nitrided spacer sidewalls on either side of the dummy gate may also include a nitride layer on the dummy gate.
  • ion implantation is performed using the dummy gate structure 4 as a mask, and a source-drain structure 5, preferably a lightly doped source-drain (LDD) structure, is deposited in the substrate 1, and deposited on the entire structure.
  • a source-drain structure 5 preferably a lightly doped source-drain (LDD) structure
  • LDD lightly doped source-drain
  • the oxide ILD labeleled 6 in Figure 2
  • spin-coated with SOG heat treated to reflow and then etched to form a flat ILD layer 6 until the dummy gate structure 4 is exposed.
  • the dummy gate structure 4 and the pad oxide layer 3 are usually removed by wet etching, and the first deposition in the trench left by the ILD layer 6 is usually Hf0 2 , Ti0 2 , Ta 2 0 5 , etc.
  • the gate oxide layer 7 of the high-k material is then deposited with a first layer of metal 8, typically TiN, Ti, TaN or Ta, and combinations thereof for enhancing the bond strength between the materials.
  • a second metal layer 9 is deposited for use as a gate metal layer, typically W, Cu, TiAl or A1, and combinations thereof, and polished until the ILD layer 6 is exposed.
  • the ILD is then etched to form a contact hole structure.
  • a conventional plasma etching process requires a two-step etch back.
  • the SOG etch back to the SOG/Si0 2 interface clearly has a faster etch rate at the edge of the wafer relative to the center region.
  • the thickness profile will become a convex-like topography, as shown in Figure 3.
  • the edge thickness is greatly reduced compared to the thickness of the center region because at the interface, the underlying oxide layer has been etched.
  • the rates of the upper and lower layers of the interface are different. Specifically, when the upper layer of SOG is etched, the etch rate is smaller than the rate of the lower layer of SiO 2 , which results in different etching thicknesses in different regions, so that the flatness is greatly reduced.
  • the second step is performed to form a structure as shown in FIG. 4, and the thickness thereof is as shown in FIG.
  • the horizontal axis represents the distance from the center of the wafer (here, a 4-inch wafer, for example, 10 cm in diameter, so the overall horizontal axis is -5 cm to 5 cm)
  • the vertical axis represents The thickness of the dielectric material after etching can be measured by an interference thickness tester or an ellipsometer, and the etching rate is obtained by measuring the thickness value before and after the wafer, and then dividing by the etching time.
  • the desired thickness profile and etch rate topography can be obtained by measuring the thickness values at different locations on the wafer.
  • U.S. Patent No. 5,639,345 utilizes a two-step etching to improve flatness.
  • US.5679211 achieves good homogeneity by means of in-situ treatment with oxygen, but does not treat the near-interface of the laminated composite structure, more specifically for the SOG layer. . Therefore, there is a need to develop a process that can improve overall uniformity and obtain a flat surface.
  • the present invention performs a near-interface equal-rate etchback treatment on the laminated composite structure, and obtains a good uniform hooking performance.
  • ILD interlayer dielectric
  • IMD inter-metal
  • the above object of the present invention is achieved by providing a method for planarizing a laminated structure composed of a dielectric on a semiconductor structure, including:
  • the laminated structure is heat treated to be refluxed
  • a second etch is performed until the top of the semiconductor structure is exposed.
  • the semiconductor structure is a back gate fabricated CMOS device or an integrated circuit multilayer metal interconnect structure.
  • the laminated structure comprises a double layer or a multilayer structure composed of a silicon oxide layer and an SOG layer on the silicon oxide layer.
  • the silicon oxide layer is a dielectric shield material of BPSG, BSG or PSG prepared by chemical vapor deposition or thermal oxidation.
  • the silicon oxide layer has a thickness of 2000A to 20,000A
  • the SOG layer has a thickness of 2000A to 20,000A.
  • the first etch and/or the second etch are plasma etch, the plasmon
  • the sub-etching gas includes a fluorocarbon-based or fluorine-based gas which may contain oxygen.
  • the fluorocarbon-based gas includes
  • the plasma etch gas also includes argon and oxygen, while oxygen can be used for simultaneous or subsequent in situ processing to eliminate the polymer produced by the first etch.
  • the first etching adopts a single-step, two-step or multi-step plasma etchback process.
  • the distance between the stop position of the first etch and the interlayer interface of the laminated structure is ⁇ to ⁇ .
  • the first etching has different etching rates on the upper and lower layers of the stacked layer, and the etching rate of the lower layer Si0 2 is K times of the upper layer SOG etching rate, wherein K is the laminated structure The ratio of the thickness difference between the upper and lower layers.
  • the etching rate of the second etching pair is close to the lamination structure at the interface between the layers.
  • the first etching and the second etching may be performed in the same cavity, or may be performed in different etching chambers.
  • the cavity is a plasma etch machine, a reactive ion etch machine, an inductively coupled etch machine, a cyclotron etch machine, or other etch machine based on plasma source operation.
  • the innovation of the present invention is to include a plasma etching for the effect of the single-step or multi-step etching of the SOG to eliminate the effect of the polymer generated by etching the SOG, and the etching of the near-interface laminated structure at the same rate. Process.
  • the present invention is also applicable to planarization of a multilayer stack filled with an interlayer dielectric (ILD) or an intermetal dielectric (IMD).
  • ILD interlayer dielectric
  • IMD intermetal dielectric
  • the present invention achieves a flat surface at a relatively low cost relative to CMP and can be applied to a stacked structure of two or more layers of dielectric material.
  • Figure 1 shows the basic sequence of the Gate-Last process, in which the second step is the formation of the ILD layer and the flattened diagram;
  • Figure 2 shows the thickness of the SOG after the conventional process plasma is used to etch the SOG.
  • Figure 3 shows the thickness of the SOG/Si0 2 laminated structure at the edge of the conventional process. Less than the thickness of the central area;
  • Figure 4 shows the thickness of the SOG/Si0 2 laminated structure after conventional plasma etching. Appearance
  • FIG. 5 is a schematic diagram showing the thickness profile after the SOG/Si0 2 laminated structure is etched by a conventional process plasma
  • Figure 6 is a schematic view showing the initial SOG/SiO 2 laminate structure in accordance with the present invention.
  • Figure 7 is a view showing the thickness profile of the near-interface SOG/SiO 2 laminate structure after plasma-carbon phase gas combined with 0 2 synchronization or subsequent treatment to eliminate the influence of the polymer according to the present invention
  • Figure 8 is a surface thickness profile after final etching of the SOG/SiO 2 laminate structure in accordance with the present invention.
  • Figure 9 is a graph showing the surface thickness of the SOG/SiO 2 laminate structure after final etching in accordance with the present invention. detailed description
  • a basic semiconductor structure is formed, such as a back gate structure for fabricating a CMOS device, an integrated circuit multilayer metal interconnection structure, and the like.
  • the step of fabricating the basic structure of the back gate structure of the CMOS device includes: depositing a pad oxide layer (not shown) on the typically silicon substrate 10 having an STI (not shown), depositing on the pad oxide layer A dummy gate structure, the dummy gate structure typically comprising a dummy gate 30 of polysilicon (or amorphous silicon) and a nitride spacer spacer 40 on either side of the dummy gate, and may also include a nitride on the dummy gate.
  • a cap layer (not shown) is then used for ion implantation using the dummy gate structure as a mask to form a source-drain structure, preferably an LDD structure, in the substrate 10.
  • the IC multilayer metal interconnect is, for example, a damascene structure, well known to those skilled in the art and will not be described in detail herein.
  • a laminated structure of a dielectric is formed on the basic semiconductor structure.
  • a thicker dielectric material typically undoped USG (undoped silicate glass, ie Si0 2 ) material, such as low temperature oxide (LTO), is deposited between the basic semiconductor structures that have been formed, such as sidewall spacers. 50 to obtain good insulation properties, also can be prepared by chemical vapor deposition or thermal oxidation method of borophosphosilicate glass (BPSG), borosilicate glass (BSG), A dielectric material such as phosphosilicate glass (PSG) having a thickness of, for example, 2,000 to 20,000 ⁇ .
  • BPSG borophosphosilicate glass
  • BSG borosilicate glass
  • PSG phosphosilicate glass
  • a thinner layer of SOG 60 is then spin coated on the LTO 50, for example from 2000 to 20000 A, preferably 500 ⁇ .
  • the two layers of the structure are only schematically shown in the embodiment and the drawings, and those skilled in the art will appreciate that more layers of the dielectric laminate structure can be used to obtain better insulation properties, such as three layers and four layers.
  • the combined laminated structure of LTO-SOG, however, preferably, the top and bottom of the laminated structure are the SOG and LTO layers, respectively.
  • the structure is determined by the thickness of the metal layer or any other structure protruding from the surface. After the deposition of the LTO and SOG multilayer isolation dielectric materials, the protrusions 51 and 61 will be formed on the gate, resulting in a wafer. The overall uniformity of the surface is deteriorated, so heat treatment is also performed to reflow the SOG to achieve a better flattening effect, and a preliminary relatively flat laminate structure is obtained.
  • the thickness of the protruding portion 51 of the LTO is determined by the process parameters for depositing the LTO and the thickness of the dummy gate 30 and the side wall 40 itself, and may depend, for example, on the material gas flow rate, the deposition temperature, and the like. Specifically, the thickness of the protruding portion 51 may be 10 To 200nm.
  • a plasma pair of LTO50 and SOG60 is used in a cavity such as a plasma etching machine or a reactive ion etching machine and an inductively coupled etching machine or other plasma-based etching machine.
  • the stacked structure is subjected to a first etching, mainly etching the SOG until the near SOG/Si0 2 near interface.
  • the near interface as shown in FIG. 8, is close to the plane of the SOG/Si0 2 interface, particularly the protruding portion 51 and substantially parallel to the substrate 10, specifically, the plane at the near interface may be a distance from the SOG/Si0.
  • the interface 2 is particularly 100 to 1000 A at the top of the protruding portion 51, that is, 10 to 100 nm, preferably 300 A, that is, 30 nm. That is, the first etch of the stacked structure stops at the near interface between the stacked structures.
  • the first etching in order to eliminate the influence of the polymer generated when the SOG is etched, this may be obtained by using a plasma etching gas for synchronization or subsequent in-situ processing.
  • the plasma etching gas may include a fluorocarbon-based gas such as CF 4 , CH 2 F 2 , CH 3 F, CHF 3 , C 4 F 6 , C 4 F 8 , and combinations thereof.
  • the plasma etching gas may also be a combination of SF 6 and 0 2 .
  • the fluorocarbon or fluorine based plasma etch gas may further comprise oxygen, synchronized or subsequently processed in situ to eliminate the polymer produced by the first etch, the first etch being in a single step, two steps or multiple steps Plasma etchback process.
  • this step is not directly related to the gist of the present invention, it will not be described in detail herein. They can be implemented using existing single-step, two-step or multi-step techniques, or they can be This is achieved with future developed technologies, which does not affect the invention.
  • the etching rate selection ratio of SOG/SiO 2 is a ratio of the difference between the thickness of the SOG thickness (that is, the difference between the maximum value and the minimum value of the thickness) and the thickness difference of 510 2 , expressed as 1/K ( K>1).
  • a second etch is performed until the desired surface, that is, until the dummy gate structure is exposed.
  • the second etching may use the same plasma etching gas as the first etching to perform near-equal rate etchback, such as fluorocarbon or fluorine-based gas (for example, CF 4 , CH 2 F 2 , CH 3 F, etc.) And its combination, may contain oxygen, or a combination of SF 6 and oxygen), that is, the remaining SOG at the near interface and the lower LTO by plasma etching, the etching rate is Ec (different from Eb, according to engraving Etching effect adjustment menu), because the etching rate is the same, the interface etching stability can be improved.
  • near-equal rate etchback such as fluorocarbon or fluorine-based gas (for example, CF 4 , CH 2 F 2 , CH 3 F, etc.)
  • near-equal rate etchback such as fluorocarbon or fluorine-based gas (for example, CF 4 , CH
  • the difference in etch rate at the center and edge of the wafer is shown in FIG.
  • the second etching may be the same as the cavity used for the first etching, and both are the same plasma etching machine or reactive ion etching machine and inductive coupling etching machine or other plasma-based etching machine, without Switching between multiple workstations increases batch processing power, saving time and reducing costs.
  • the surface thickness profile after the final etching of the SOG/SiO 2 laminate structure according to the present invention As shown in Fig. 8, the surface thickness profile after the final etching of the SOG/SiO 2 laminate structure according to the present invention.
  • the horizontal axis represents the distance from the opposite center on the wafer, and the vertical axis represents the thickness of the dielectric material.
  • the thickness can be measured by an interference tester or an ellipsometer, and the etching rate needs to be measured before and after the wafer. The thickness is then divided by the time of etching.
  • the desired thickness profile and etch rate topography can be obtained by measuring the thickness values at different locations on the wafer.
  • the effective area of the wafer is increased from the initial 60% to at least 80%, and the non-uniformity is reduced from 10% to 5%. Good flat performance.
  • the effective area is an area of the area on which the device on the wafer can work effectively. Specifically, as shown by the alternate long and short dash line in FIGS. 5 and 8, the dot-dash line (corresponding to a dielectric thickness of 1250 angstroms) is thinner than the dielectric thickness. These areas are over-etched more, and in the subsequent metal gate filling process, the metal will be filled into it, allowing subsequent The process is affected and therefore does not meet the requirements and does not belong to the effective area.
  • the effective area area of Fig. 5 is within 30 mm from the center
  • the effective area area of Fig. 8 is within 40 mm from the center.
  • there are two kinds of characterization methods for wafer surface thickness and etch rate non-uniformity ie, the difference (the difference between the maximum value and the minimum value), the non-uniformity and the deviation (the variance of all measurement data).
  • Uniformity then divided by twice the mean, is a representation made with very poor non-uniformity.
  • the calculation results show that the invention greatly improves the uniformity of the thickness of the dielectric, thereby increasing the effective area of the wafer surface.
  • the resulting etched device structure cross-sectional view is schematically shown in FIG. 9.
  • an excellent ILD is obtained due to the near-interface two-step etching.
  • a flat surface that is, a flat, neat ILD surface can be obtained not only in the central region but also at the edge of the wafer.

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Description

层间电介质的近界面平坦化回刻方法 本申请要求了 2011年 1月 7日提交的、申请号为 2011100031 18.6、 发明名称为"层间电介质的近界面平坦化回刻方法"的中国专利申请的 优先权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及半导体集成电路制造领域， 更具体地， 涉及一种层间 电介质层 （ILD ) 的近界面平坦化回刻方法。 背景技术
随着集成电路进入 32nm时代， 对层间电介质平坦化的要求也越来 越高。 尤其， 英特尔 45nm后栅（gate-last )工艺的量产成功， 极大的推 动了集成电路先进技术的发展。 一些新的挑战和技术不断涌现， 其中， 假栅（dummy gate )表面电介质材料的平坦化便是关键技术之一， 这 在传统的前栅 ( gate-first ) 工艺中是不存在的。
然而， 由于多晶硅栅（假栅） 与其两侧结构的表面在厚度上存在 相当大的差异， 在多层隔离电介质材料沉积后， 在栅条上将会形成突 起， 导致晶圓表面的整体均勾性变差。 因此， 在假栅上获得优良的均 匀性将对后续工艺带来重要影响， 否则， 在金属栅填充后， 将会由于 高低不平导致存在相当大的金属残余， 导致器件的可靠性问题。
为了提高晶圆均匀性， 常规的做法是首先沉积一层 Si02，或者再沉 积其他电介质层以提高器件的电学隔离性能， 最后旋涂上一层厚的旋 涂玻璃 （SOG ) 介质。 接下来， 在一定温度下进行热处理， 借助 SOG 优良的回流性能来弥补下面的电介质导致的不均匀性。 然后， 借助等 离子刻蚀方法来回刻去除 SOG和 Si02 ,直到在假栅上产生平坦均匀的表 面。
然而， 这种 SOG回刻方法无法提供较好的刻蚀均匀性， 导致整个 晶圓在不同区域厚度变化极大， 这是由于边缘刻蚀速率快于中间区域， 加剧了这种不均匀性。 不同区域刻蚀速率的差异来源于在回刻 SOG过 程中产生了聚合物， 因为刻蚀机腔体内部存在气压差， 不同区域残余 的聚合物量决定了刻蚀速率的大小。 另外一方面， 当刻蚀复合叠层界 面时， 由于不同电介质材料存在刻蚀速率差异及刻蚀不均匀性， 进一 步恶化了厚度的平坦化。
以下， 将参照图 1 ~ 5来说明常规半导体器件制造工艺中为获得平 坦的 ILD或金属间电介质 （IMD )表面所采用的等离子回刻技术。
图 1示出了制作后栅（Gate-Last )工艺的基本顺序。 首先， 如图 1A 所示， 在具有浅沟槽隔离 （ STI ) 2的衬底 1上沉积垫氧化层 3 , 在垫氧 化层 3上沉积假栅结构 4, 假栅结构 4通常包括多晶硅、 非晶硅的假栅极 以及假栅极两侧的通常为氮化物的隔离侧墙， 还可以包括假栅极上的 通常为氮化物的盖层。 然后， 如图 1B所示， 利用假栅结构 4作为掩模进 行离子注入， 在衬底 1中形成源漏结构 5， 优选地为轻掺杂源漏 （LDD ) 结构， 并在整个结构上沉积通常为氧化物的 ILD (图 2中标注为 6 )并旋 涂 SOG , 热处理回流之后再刻蚀形成平坦的 ILD层 6直至暴露出假栅结 构 4。 接着， 如图 1C所示， 通常采用湿法刻蚀去除假栅结构 4以及垫氧 化层 3， 在 ILD层 6留下的沟槽内先沉积通常为 Hf02、 Ti02、 Ta205等高 k 材料的栅极氧化层 7， 再沉积第一层金属 8， 通常为 TiN、 Ti、 TaN或 Ta 及其组合， 用于提高材料之间的接合强度。 最后， 如图 1D所示， 沉积 第二金属层 9用作栅极金属层， 通常为 W、 Cu、 TiAl或 A1及其组合， 并 抛光直至露出 ILD层 6。 随后刻蚀 ILD形成接触孔结构。
在图 1B所示的对 ILD层 6进行平坦化的步骤中， 为获得平坦均匀的 表面， 采用常规等离子刻蚀工艺需要进行两步回刻。
第一步， 进行 SOG回刻直到 SOG/Si02界面， 如图 2所示， 明显地， 在晶圓边缘有相对中心区域更快的刻蚀速率。 当刻蚀到 SOG/Si02界面 时， 厚度形貌将变成类似凸形的形貌， 如图 3所示。 在界面处， 同中心 区域厚度相比， 边缘厚度将大大降低， 这是因为在界面处， 已经刻蚀 到下面的氧化层。 界面上下两层的速率不同， 具体地， 在刻蚀上层的 SOG时， 其刻蚀速率小于下层的 Si02的速率，导致不同区域刻蚀厚度不 同， 使得平坦度大大降低。
接下来， 进行第二步回刻， 形成如图 4所示的结构,其厚度如图 5 所示。 图 5 中， 横轴代表晶片上相对中心处的距离 （此处以 4英寸晶 圆为例， 直径为 10cm,因此整体横轴为 - 5cm到 5cm距离）， 纵轴代表 电介质材料刻蚀后的厚度， 可以采用干涉厚度测试仪或者椭偏仪量测 得到， 刻蚀速率则通过测量晶圆前后的厚度值， 然后除以刻蚀的时间 得到。 很明显地， 通过测量晶圆上不同位置的厚度值便能够得到所需 的厚度形貌及刻蚀速率形貌图。 进一步来说， 在刻蚀过程中， 由于界 面两侧电介质材料不同， 不同的刻蚀速率将带来很大的刻蚀厚度差异， 即使以相同的刻蚀速率回刻， 也会由于在界面难以控制重复性及可靠 性， 使得边缘效应更趋恶化。
有鉴于此， 需要提供一种新颖的半导体器件平坦化回刻方法。
美国专利 US.5639345利用两步刻蚀提升了平坦性能， US.5679211 借助氧气原位处理获得了良好的均勾性， 然而没有对叠层复合结构近 界面进行处理， 更多地仅仅针对 SOG层。 因此， 需要开发一个能够提 高整体均匀性并获得平坦表面的工艺。
综合常规工艺及叠层结构遇到的刻蚀问题， 本发明针对叠层复合 结构进行了近界面等速率回刻处理， 获得了良好的均勾性能。 发明内容
本发明的目的是提高应用于后栅工艺及层间电介质（ILD )或金属 间 （IMD ) 填充的 SOG/Si02叠层结构的均匀性。 进一步， 本发明的目 的是近界面等离子刻蚀工艺提高回刻均匀性。
实现本发明的上述目的， 是通过提供一种方法， 用于对在半导体 结构上的电介质构成的叠层结构进行平坦化， 包括：
对所述叠层结构进行热处理， 使其回流；
进行第一刻蚀， 直至接近所述叠层结构的层间界面处；
进行第二刻蚀， 直至露出所述半导体结构的顶部。
其中，所述半导体结构是后栅制作的 CMOS器件或集成电路多层金 属互连结构。
其中， 所述叠层结构包括双层或多层结构， 由氧化硅层以及所述 氧化硅层上的 SOG层构成。 所述氧化硅层是化学气相沉积或者热氧化 方法制备的 BPSG、 BSG或 PSG的电介盾材料。 所述氧化硅层厚度为 2000A至 20000A, 所述 SOG层厚度为 2000A至 20000A。
其中， 所述第一刻蚀和 /或所述第二刻蚀是等离子刻蚀， 所述等离 子刻蚀气体包括可含氧气的碳氟基或氟基气体。 所述碳氟基气体包括
CF4、 CH2F2、 CH3F、 CHF3、 C4F6、 C4F8中的任一种及其组合， 所述氟 基气体为 SF6。 所述等离子刻蚀气体还包括氩气和氧气， 同时氧气可以 用来进行同步或随后原位处理以消除所述第一刻蚀产生的聚合物。
其中， 所述第一刻蚀采用单步、 两步或多步的等离子回刻工艺。 所述第一刻蚀的停止位置与所述叠层结构的层间界面之间的距离为 ιοοΑ至 ιοοοΑ。
其中， 所述第一刻蚀对所述叠层上下两层结构的刻蚀速率不同， 对下层 Si02的刻蚀速率是上层 SOG刻蚀速率的 K倍， 其中 K为所述叠层 结构的上下两层厚度极差的比值。 所述第二刻蚀对接近层间界面处的 叠层结构的刻蚀速率相等。
其中， 所述第一刻蚀和第二刻蚀可以在相同的腔体中进行， 也可 以在不同的刻蚀腔体进行。 所述腔体为等离子体刻蚀机、 反应离子刻 蚀机、 感应耦合刻蚀机、 回旋共振刻蚀机或其他以等离子体源工作为 基础的刻蚀机。
本发明的创新点在于包括一个对 SOG进行单步或多步回刻消除刻 蚀 SOG时产生的聚合物带来的影响的等离子刻蚀， 及以相同速率刻蚀 近界面叠层结构的回刻工艺。
另外 ,本发明还可应用于层间电介质（ ILD )或金属间电介质（ IMD ) 填充的多层堆叠的平坦化。
最后， 本发明以相对 CMP较低的成本来获得平坦的表面， 能应用 于双层或多层电介质材料的堆叠结构。 附图说明
以下参照附图来详细说明本发明的技术方案， 其中：
图 1为后栅 （Gate-Last ) 工艺的基本顺序,其中第二步为形成 ILD层 及平坦化后的图示；
图 2为采用常规工艺等离子体回刻 SOG后的厚度演示形貌； 图 3为采用常规工艺等离子体回刻 SOG/Si02叠层结构界面处的厚 度形貌示意，边缘处刻蚀剩余厚度明显小于中心区域的厚度；
图 4为采用常规工艺等离子体回刻 SOG/Si02叠层结构后的厚度演 示形貌；
图 5为采用常规工艺等离子体回刻 SOG/Si02叠层结构后的厚度形 貌示意；
图 6为依照本发明的初始的 SOG/Si02叠层结构示意图；
图 7为依照本发明的采用等离子体碳氟基气体结合 02同步或随后 处理消除聚合物影响后的近界面 SOG/Si02叠层结构厚度形貌；
图 8为依照本发明的 SOG/Si02叠层结构最终刻蚀后的表面厚度形 貌； 以及
图 9为依照本发明的 SOG/Si02叠层结构最终刻蚀后的表面厚度演 示形貌。 具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案 的特征及其技术效果。 需要指出的是， 类似的附图标记表示类似的结 构， 本申请中所用的术语 "第一" 、 "第二，， 、 "上" 、 "下" 、 "厚" 、 "薄" 等等可用于修饰各种器件结构。 这些修饰除非特别说明并非暗 示所修饰器件结构的空间、 次序或层级关系。
首先形成基本半导体结构， 例如制作 CMOS器件的后栅结构， 集成 电路多层金属互连结构等结构。 具体地， 制作 CMOS器件的后栅结构的 基本结构的步骤包括： 在具有 STI (未示出） 的通常为硅的衬底 10上沉 积垫氧化层 （未示出） ， 在垫氧化层上沉积假栅结构， 假栅结构通常 包括多晶硅 （或非晶硅） 的假栅极 30以及假栅极两侧的通常为氮化物 的隔离侧墙 40，还可以包括假栅极上的通常为氮化物的盖层（未示出）， 然后， 利用假栅结构作为掩模进行离子注入， 在衬底 10中形成源漏结 构， 优选地为 LDD结构。 IC多层金属互连例如为大马士革结构， 为本 领域技术人员公知， 在此不再详述。
然后， 参照图 6， 在基本半导体结构上形成电介质的叠层结构。 在 已经形成的基本半导体结构如侧墙之间沉积上一层较厚的电介质材 料， 通常为无掺杂的 USG (无掺杂硅酸盐玻璃， 即 Si02)材料， 如低温氧 化物 （LTO ) 50来获得良好的绝缘性能， 还可为通过化学气相沉积或 者热氧化方法制备的硼磷硅酸盐玻璃（ BPSG )、硼硅酸盐玻璃（ BSG )、 磷硅酸盐玻璃 （PSG ) 等电介质材料， 厚度例如为 2000至 20000 A。 然 后在 LTO 50上旋涂一层较薄的 SOG 60, 厚度例如为 2000至 20000 A ， 优选地为 500θΑ。 实施例以及附图中仅示意性给出了两层叠层结构， 本 领域技术人员可以知晓的是， 还可以采用更多层的电介质层叠结构以 获得更佳的绝缘性能， 例如三层、 四层 LTO-SOG的组合叠层结构， 但 是， 优选地， 叠层结构的顶部以及底部分别是 SOG和 LTO层。
值得注意的是， 由于基本半导体结构中的假栅 30与其两侧结构的 表面在厚度上存在相当大的差异 （主要是假栅 30和側墙 40本身的厚度 决定， 对于多层金属互连结构等结构而言就是金属线层或其他任何突 出于表面的结构的厚度来决定），在 LTO和 SOG多层隔离电介质材料沉 积后， 在栅条上将会形成突起部分 51与 61， 导致晶圆表面的整体均匀 性变差， 因此还要进行热处理使得 SOG回流以便取得较佳的平坦效果， 获得初步较平坦的叠层结构。 LTO的突起部分 51的厚度由沉积 LTO的工 艺参数以及假栅 30和侧墙 40本身的厚度决定， 例如可取决于原料气体 流量、 沉积温度等等， 具体地， 突起部分 51的厚度可为 10至 200nm。
接下来， 参照图 7， 在例如为等离子体刻蚀机或反应离子刻蚀机及 感应耦合刻蚀机或其他以等离子体为作用的刻蚀机的腔体中采用等离 子体对 LTO50和 SOG60的叠层结构进行第一刻蚀，主要是刻蚀 SOG，直 到下面的 SOG/Si02近界面处。 所谓近界面处， 如图 8中所示， 为 SOG60 贴近 SOG/Si02界面处特别是突起部分 51且大致平行于衬底 10的平面， 具体地， 该近界面处的平面可距离 SOG/Si02界面处特别是突起部分 51 的顶部 100至 1000 A， 也即 10至 100nm， 优选地是 300A也即 30nm。 也就 是说， 对叠层结构的第一刻蚀停止于叠层结构之间的近界面处。
在该第一刻蚀中， 为了消除刻蚀 S O G时产生的聚合物带来的影响， 这可以采用等离子刻蚀气体进行同步或随后原位处理得到。 等离子刻 蚀气体可包括碳氟基气体， 例如 CF4、 CH2F2、 CH3F、 CHF3、 C4F6、 C4F8 及其组合。 等离子刻蚀气体还可为 SF6与 02的组合。 碳氟基或氟基的等 离子刻蚀气体还可包括氧气， 进行同步或随后原位处理以消除所述第 一刻蚀产生的聚合物， 第一刻蚀采用单步、 两步或多步的等离子回刻 工艺。 由于这一步回刻与本发明的主旨并无直接关联， 在此不进行详 细描述。 它们可以采用现有单步， 两步或多步技术来实现， 也可以采 用将来发展的技术来实现， 这并不影响本发明。
具体地， 在刻蚀 SOG时， 需要选择一定的刻蚀速率， 即对下层的 Si02层有一定的选择比。 在本发明中， SOG/Si02的刻蚀速率选择比为 SOG厚度的极差（也即厚度最大值与最小值之间的差）与5102厚度的极 差比， 表示为 1/K ( K>1 ) 。 设 SOG刻蚀速率为 Ea，下层 Si02的刻蚀速率 为 Eb, 则有 Eb: Ea = K, 显然地， Eb = K Ea, Ea: Eb = 1/K。
图 7所示的等离子回刻到叠层结构近界面处的示意图中， 图两侧弯 曲边缘所示代表的是晶片边缘与中心处的刻蚀差异。
然后， 再进行第二刻蚀直到所需的表面， 也即直至暴露出假栅结 构。 该第二刻蚀可采用与第一刻蚀相同的等离子刻蚀气体进行近界面 等速率回刻， 例如为碳氟基或氟基气体 （例如 CF4、 CH2F2、 CH3F等等 及其组合， 可包含氧气， 也可为 SF6与氧气的组合） ， 也即用等离子刻 蚀近界面处剩余的 SOG以及下方的 LTO, 刻蚀速率均为 Ec (不同于 Eb， 可根据刻蚀效果调整菜单）， 由于刻蚀速率相同， 因此可提高界面刻蚀 稳定性。 其中晶片中心处与边缘处的刻蚀速率差别如图 9所示。 第二刻 蚀与第一刻蚀所用的腔体可相同， 均为同一个等离子体刻蚀机或反应 离子刻蚀机及感应耦合刻蚀机或其他以等离子体为作用的刻蚀机， 无 需在多个工作站之间转换， 因此提高了批量处理能力， 节省了时间降 低了成本。
如图 8所示， 为依照本发明的 SOG/Si02叠层结构最终刻蚀后的表面 厚度形貌。 其中， 与图 5类似地， 横轴代表晶片上相对中心处的距离， 纵轴代表电介质材料的厚度， 厚度可以采用干涉测试仪或者椭偏仪量 测得到， 刻蚀速率则需要测量晶圓前后的厚度， 然后除以刻蚀的时间 得到。 很明显地， 通过测量晶圆上不同位置的厚度值便能够得到所需 的厚度形貌及刻蚀速率形貌图。
对比现有技术 （图 5 ) 与本发明 （图 8 ) 的数据经过计算可知， 晶 圓有效面积从最初的 60%提高到至少 80%， 非均匀性大小从 10%降低到 5%, 从而实现了良好的平坦性能。 其中， 有效面积为晶圓上器件能够 有效工作的面积区域， 具体地， 如图 5、 图 8中的点划线所示， 点划线 (对应电介质厚度为 1250埃） 以下电介质厚度较薄表明这些区域过刻 蚀较多， 在后续的金属栅填充工艺， 金属将会填充到里面， 使得随后 的工艺受到影响， 因此不符合要求， 不属于有效面积区域。 由图中可 见， 图 5的有效面积区域为距离中心 30mm以内， 图 8的有效面积区域为 距离中心 40mm以内。 另外， 需要补充说明的是， 晶圆表面厚度及刻蚀 速率的非均匀性有两种表征方法即极差 （最大值与最小值之差） 非均 匀性和偏差 （所有测量数据的方差） 非均匀性， 然后除以两倍的均值， 这里是用极差非均匀性作出的表征。 计算结果表明， 本发明大大提高 了电介质厚度的均匀性， 从而增大了晶圓表面的有效面积。
最终得到的刻蚀后的器件结构剖面图示意性地如图 9所示， 与常规 工艺得到的图 4所示的示意图相比， 由于采用了近界面两步刻蚀， 得到 了极佳的 ILD平整表面，也即不仅在中心区而且乃至在晶片边缘处也仍 然能得到平坦整齐的 ILD表面。
尽管已参照一个或多个示例性实施例说明本发明， 本领域技术人 员可以知晓无需脱离本发明范围而对形成器件结构的方法做出各种合 适的改变和等价方式。 此外， 由所公开的教导可做出许多可能适于特 定情形或材料的修改而不脱离本发明范围。 因此， 本发明的目的不在 于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例， 而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实 施例。

Claims

权 利 要 求
1. 一种方法， 用于对在半导体结构上的电介质构成的叠层结构进 行平坦化， 包括：
对所述叠层结构进行热处理， 使其回流；
进行第一刻蚀， 直至接近所述叠层结构的层间界面处；
进行第二刻蚀， 直至露出所述半导体结构的顶部。
2. 如权利要求 1所述的方法， 其中， 所述半导体结构是后栅制作 的 CMOS器件或集成电路多层金属互连结构。
3. 如权利要求 1所述的方法， 其中， 所述叠层结构包括双层或多 层结构， 由氧化硅层以及所述氧化硅层上的 SOG层构成。
4. 如权利要求 3所述的方法， 其中， 所述氧化硅层是化学气相沉 积或者热氧化方法制备的 BPSG、 BSG或 PSG的电介质材料。
5. 如权利要求 3所述的方法， 其中， 所述氧化硅层厚度为 2000A至 20000A, 所述 SOG层厚度为 2000A至 20000A。
6. 如权利要求 1所述的方法， 其中， 所述第一刻蚀和 /或所述第二 刻蚀是等离子刻蚀。
7. 如权利要求 6所述的方法， 其中， 所述等离子刻蚀气体包括 CF4、 CH2F2、 CH3F、 CHF3、 C4F6、 C4F8任一种及其组合。
8. 如权利要求 6所述的方法， 其中， 所述等离子刻蚀气体为 SF6与
02。
9. 如权利要求 6至 8任一项所述的方法， 其中， 所述等离子刻蚀气 体还包括氧气， 进行同步或随后原位处理以消除所述第一刻蚀产生的 聚合物。
10. 如权利要求 6所述的方法， 其中， 所述第一刻蚀采用单步、 两 步或多步的等离子回刻工艺。
1 1. 如权利要求 1所述的方法， 其中， 所述第一刻蚀的停止位置与 所述叠层结构的层间界面之间的距离为 ιοοΑ至 ιοοοΑ。
12. 如权利要求 1所述的方法， 其中， 所述第一刻蚀对所述叠层结 构的刻蚀速率选择比为 1/K, 其中 K为所述叠层结构的下层与上层两层 厚度极差的比值。
13. 如权利要求 1所述的方法， 其中， 所述第二刻蚀对接近层间界 面处的叠层结构的刻蚀速率相等。
14. 如权利要求 1所述的方法， 其中， 所述第一刻蚀和第二刻蚀在 相同的腔体中进行。
15. 如权利要求 14所述的方法， 其中， 所述腔体为以等离子体源 工作为基础的刻蚀机。
16. 如权利要求 15所述的方法， 其中， 所述以等离子体源工作为 基础的刻蚀机为等离子体刻蚀机、 反应离子刻蚀机、 感应耦合刻蚀机 或回旋共振刻蚀机。
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