WO2014024611A1 - Procédé de production d'un dispositif à semi-conducteur - Google Patents

Procédé de production d'un dispositif à semi-conducteur Download PDF

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Publication number
WO2014024611A1
WO2014024611A1 PCT/JP2013/068562 JP2013068562W WO2014024611A1 WO 2014024611 A1 WO2014024611 A1 WO 2014024611A1 JP 2013068562 W JP2013068562 W JP 2013068562W WO 2014024611 A1 WO2014024611 A1 WO 2014024611A1
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semiconductor substrate
semiconductor device
manufacturing
semiconductor
bonding
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PCT/JP2013/068562
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English (en)
Japanese (ja)
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研一 井口
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富士電機株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H01L27/0694—Integrated circuits having a three-dimensional layout comprising components formed on opposite sides of a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device.
  • a VVVF (Variable Voltage Variable Frequency) inverter device that can variably control the frequency and voltage is frequently used for driving a motor or the like.
  • this inverter device is composed of a converter unit that converts commercial frequency alternating current into direct current and an inverter unit that converts this direct current into alternating current of a predetermined frequency and voltage.
  • a converter part and an inverter part as well as a large inductor (L) for smoothing current and a large capacitor (C) for suppressing voltage fluctuations are required.
  • L large inductor
  • C capacitor
  • a matrix converter device is composed of an LC filter and nine bidirectional switches.
  • the bidirectional switch can be configured using transistors and diodes such as IGBT (Insulated Gate Bipolar Transistor) and MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor).
  • IGBT Insulated Gate Bipolar Transistor
  • MOSFET Metal-Oxide-Semiconductor Field Effect Transistor
  • one bidirectional switch can be configured by arranging a unidirectional switch in which an IGBT and its reverse breakdown voltage diode are connected in series in each of the forward direction and the reverse direction. An element is required.
  • a bidirectional switch having a reduced number of elements to two has been put to practical use by using, as a unidirectional switch, a reverse blocking IGBT having the functions of an IGBT and a reverse breakdown voltage diode.
  • a structure in which a bidirectional switch is configured with one chip using a double-sided device in which the back surfaces of two IGBTs are bonded to each other has been proposed.
  • FIG. 5 is a cross-sectional view showing a main part of a semiconductor substrate in a bonding process of a conventional semiconductor device.
  • the surface of the semiconductor substrate 11 is covered with the surface protective film 13 (FIG. 5A).
  • the back surface side of each of the two semiconductor substrates 11 is ground and polished so as to be thinned (thickened) to a desired thickness, and then flattened (FIG. 5B). After the thickness reducing step, the surface protective film 13 is removed (FIG. 5C).
  • two semiconductor substrates 11 are introduced into a vacuum apparatus (not shown), and the ground back surface 14 serving as a bonding surface is irradiated with a high-speed particle beam such as an Ar atom beam or plasma. Then, contaminants on the back surface 14 of the semiconductor substrate 11 are removed to expose the active surface (FIG. 5D). Immediately after the bonding pretreatment, the back surfaces 14 of the two semiconductor substrates 11 are brought into contact with each other to bond the semiconductor substrates 11 (FIG. 5E), thereby completing the double-sided device.
  • a high-speed particle beam such as an Ar atom beam or plasma.
  • FIG. 6 shows a semiconductor substrate 11 in which a semiconductor device is manufactured by a conventional bonding process.
  • FIG. 6 is an explanatory diagram showing the configuration of the semiconductor substrate.
  • FIG. 6A is a plan view of the semiconductor substrate 11, and
  • FIG. 6B is a side view of the semiconductor substrate 11.
  • a cut portion when the semiconductor substrate 11 is cut into chips is defined as a scribe region 16.
  • a scribe region 16 exists on both the front surface and the back surface of the semiconductor substrate 11.
  • a broken-line square is a chip region 12, and a portion sandwiched between the chip regions 12 is a scribe region 16.
  • FIG. 7 is a cross-sectional view showing the main part of the bonding state between the semiconductor substrates when particles invade in the conventional semiconductor device manufacturing method.
  • FIG. 7 shows a bonding state between the semiconductor substrates in the case where the particles 18 exist in the portion cut along the line A-A ′ in FIG. 6.
  • the void defect 19 is generated. Since the void defect 19 is electrically insulated, the device bonding area is reduced and the mounting area is reduced, leading to an increase in on-resistance.
  • the present invention provides a method for manufacturing a semiconductor device using a wafer bonding process that has less adverse effects on bonding of adjacent chips even when particles are mixed between semiconductor substrates, in order to eliminate the above-described problems caused by the prior art.
  • the purpose is to do.
  • a semiconductor device manufacturing method has the following characteristics. First, a first step of forming a device structure on each front surface of the first semiconductor substrate and the second semiconductor substrate is performed. Next, a second step of forming a plurality of grooves on the back surface of at least one of the first semiconductor substrate and the second semiconductor substrate is performed. Next, a third step of bonding back surfaces of the first semiconductor substrate and the second semiconductor substrate is performed. At this time, in the second step, the groove having a depth or width equal to or larger than the diameter of the particles attached to the back surface of the first semiconductor substrate or the second semiconductor substrate is formed.
  • the semiconductor device manufacturing method according to the present invention is characterized in that, in the above-described invention, in the second step, the groove is formed at a position corresponding to a scribe line.
  • each of the first semiconductor substrate and the second semiconductor substrate is placed from the back surface between the first step and the second step.
  • the method further includes a thickness reducing step of removing the thickness to a desired thickness.
  • the method for manufacturing a semiconductor device according to the present invention is characterized in that the width of the groove is not less than 100 ⁇ m and not more than 300 ⁇ m.
  • the groove has a tapered shape having a side wall that forms an angle of not less than 45 degrees and not more than 75 degrees with respect to the back surface of the semiconductor substrate on which the groove is formed. It is characterized by doing.
  • the third step is performed in a vacuum, and the temperatures of the first semiconductor substrate and the second semiconductor substrate in the third step are The temperature is from room temperature to 400 ° C.
  • the back surfaces of the first semiconductor substrate and the second semiconductor substrate may be separated from each other between the second step and the third step. Etching with lines or plasma.
  • the crystal orientation of the material of the first semiconductor substrate is the same as the crystal orientation of the material of the second semiconductor substrate in the above-described invention, and the first semiconductor substrate
  • the material of the second semiconductor substrate is silicon.
  • void defects due to particles are alleviated by the groove pattern, and it is possible to suppress the void defects from extending to the adjacent chip region. There is an effect that it can be improved.
  • FIG. 1 is a cross-sectional view showing the main part of the semiconductor substrate in the bonding process of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view showing a cross-sectional structure of the semiconductor device manufactured by the method of manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 3 is a cross-sectional view showing a main part of a bonding state between semiconductor substrates when particles invade in the method of manufacturing a semiconductor device according to the present invention.
  • FIG. 4 is a characteristic diagram showing the void defect rate, the number of non-defective joints, and the total number of chips when the groove width of the groove pattern of the semiconductor device according to the example is changed.
  • FIG. 1 is a cross-sectional view showing the main part of the semiconductor substrate in the bonding process of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view showing a cross-sectional structure of the semiconductor device manufactured by the method of manufacturing a
  • FIG. 5 is a cross-sectional view showing a main part of a semiconductor substrate in a bonding process of a conventional semiconductor device.
  • FIG. 6 is an explanatory diagram showing the configuration of the semiconductor substrate.
  • FIG. 7 is a cross-sectional view showing a main part of a bonding state between semiconductor substrates when particles invade in a conventional method for manufacturing a semiconductor device.
  • FIG. 1 is a cross-sectional view showing the main part of the semiconductor substrate in the bonding process of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view showing a cross-sectional structure of the semiconductor device manufactured by the method of manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FZ-n type silicon wafers A and B are prepared as a semiconductor substrate 11, and a MOS gate (metal-oxide film-semiconductor) is provided as an element active portion 31 through which main current flows in the chip region 12 on the front surface side.
  • An insulating gate) structure and an emitter electrode 29 are formed.
  • a breakdown voltage structure portion 32 surrounding the periphery of the element active portion 31 is formed on the outer periphery of the element active portion 31 on the front surface side of each of the FZ-n type silicon wafers A and B.
  • a buffer region 33 that surrounds the periphery of the breakdown voltage structure 32 is formed on the outer periphery of the breakdown voltage structure 32.
  • the FZ-n-type silicon wafer is an n-type wafer manufactured by a floating zone method (hereinafter simply referred to as a wafer).
  • the MOS gate structure is a general element structure of a MOS type semiconductor device having a p + type base layer 23, an n + type emitter layer 24, a gate insulating film 25, a gate electrode 26 and an interlayer insulating film 27.
  • the chip size (the size of the chip region 12) may be 8 mm ⁇ 8 mm, for example.
  • the chip region 12 of each chip is, for example, as shown in the plan view of FIG.
  • the wafers A and B are arranged in a matrix.
  • a scribe region 16 that is a cutting portion when the semiconductor substrate 11 is cut into chips exists, for example, on both the front and back surfaces of the wafers A and B.
  • a photoresist film is formed as the surface protective film 13 (FIG. 1A).
  • the surface protective film 13 may be any material that can protect the device structure from process damage described later, and may be formed using other materials.
  • the back side is ground and thinned (thickened) to a thickness of 200 ⁇ m.
  • a tape for grinding (not shown) is applied to the front surfaces of the wafers A and B, that is, the surface on which the surface protective film 13 is formed, and desired from the back surfaces of the wafers A and B. Grind until near the thickness.
  • the back surfaces of the wafers A and B are flattened by CMP (Chemical Mechanical Polishing) (FIG. 1B).
  • the surface roughness Ra of the flatness of the bonded surface 14 is desirably lower than 1 nm.
  • the back surface flattening processing of the wafers A and B can be performed using any processing such as polishing or etching. Further, the back surface flattening of the wafers A and B may be performed at any timing in the process from the back surface grinding to the bonding of the bonding surfaces 14 of the wafers A and B. In this way, device structures, back surface grinding, and back surface planarization are performed on the wafers A and B prepared as the semiconductor substrate 11, respectively.
  • a groove pattern 17 is formed in the scribe region 16 on the back surface of the wafer.
  • a resist opening pattern 15 having an opening with a width of 200 ⁇ m is formed by a photolithography process so that the scribe region 16 on the back surface of the wafer A is exposed (FIG. 1C).
  • the wafer A is anisotropically etched using the resist opening pattern 15 as a mask, thereby forming a groove pattern 17 having a depth of, for example, 30 ⁇ m on the back surface of the wafer A (FIG. 1D).
  • the depth or width of the groove pattern 17 may be a dimension capable of etching control and not less than the diameter of the assumed particle 18.
  • the particle diameter is about 0.2 ⁇ m to 0.5 ⁇ m, and therefore the depth or width of the groove pattern 17 is 5 ⁇ m or more is sufficient.
  • the groove pattern 17 causes the substrate to break due to internal stress on the wafer when the depth of the groove is 1 ⁇ 2 or less of the substrate thickness after grinding, or the remaining thickness of the pattern portion is 100 ⁇ m or more. Can be prevented.
  • TMAH tetramethylammonium hydroxide
  • the TMAH etchant has a slow etching rate on the (111) plane of silicon, so that the taper shape that exposes the (111) plane as a side wall that forms an angle of about 53 degrees with respect to the (100) plane on the back of the wafer. This is because the groove pattern 17 can be formed.
  • the angle formed between the extension line into the groove pattern 17 on the back surface of the wafer and the side wall of the groove pattern 17 is referred to as a taper angle.
  • the groove width of the groove pattern 17 is within a range including the scribe region 16 and the buffer region 33 of the chip region 12 adjacent to the scribe region 16 and does not cover the breakdown voltage structure portion 32. The reason is that, when the groove width of the groove pattern 17 is wide and extends to the breakdown voltage structure 32, the depletion layer extends to the groove pattern 17 at the time of reverse breakdown voltage, resulting in an adverse effect such that leakage current increases.
  • the taper angle of the side wall of the groove pattern 17 is preferably 45 degrees or more and 75 degrees or less with respect to the wafer back surface. The reason is as follows. This is because when the taper angle of the side wall of the groove pattern 17 is greater than 75 degrees with respect to the wafer back surface, the corner portion at the upper end of the side wall of the groove pattern 17 is likely to be chipped due to the process load, so that it is likely to become a particle source or a bonding failure location. . On the other hand, when the taper angle of the side wall of the groove pattern 17 is smaller than 45 degrees with respect to the back surface of the wafer, the ineffective area where the element active portion 31 cannot be disposed increases (the area of the element active portion 31 decreases). This is because there arises a problem that the use efficiency is lowered.
  • Etching for forming the groove pattern 17 on the wafer A is not necessarily wet etching, and may be performed by any method such as dry etching. Through the steps so far, the groove pattern 17 is formed on the back surface of the wafer A.
  • the wafers A and B are irradiated with a particle beam or plasma such as an Ar (argon) atomic beam as a pre-bonding process on the back surface to be the bonding surface 14 to remove contaminants on the back surface.
  • a particle beam or plasma such as an Ar (argon) atomic beam
  • the wafers A and B are moved into the high vacuum chamber, the wafers A and B are arranged so that the bonding surfaces 14 of the wafers A and B face each other, and the wafers A and B are aligned.
  • the degree of vacuum of the chamber in the bonding pretreatment is, for example, 3 ⁇ 10 ⁇ 5 Pa.
  • the back surfaces of the wafers A and B are each irradiated with a neutralized Ar atom beam.
  • the beam irradiation angle of Ar atoms is set to an angle of 45 degrees with respect to the bonding surface 14 at the wafer center position, for example.
  • the applied voltage of the Ar atom beam gun may be set to 1.2 kV, for example, and the plasma current may be set to 20 mA, for example. In this way, contaminants on the outermost surface of the bonding surface 14 of the wafers A and B are etched to expose the clean surface of the wafer material (FIG. 1 (f)).
  • the bonding surfaces 14 of the wafers A and B are brought into contact with each other to bond the back surfaces of the wafers A and B, thereby forming the bonding wafer AB (FIG. 1G). Thereby, the semiconductor device shown in FIG. 2 is completed.
  • the wafers A and B are intentionally heated and cooled during the bonding process.
  • the wafer temperature did not reach 100 ° C., and was maintained at substantially room temperature (for example, 25 ° C.).
  • it is desirable that the wafer temperature at the time of bonding is from room temperature to 400 ° C.
  • the reason is as follows. A wafer temperature of 400 ° C. or higher is not preferable because it adversely affects the device structure on the front side of the wafer.
  • lowering the wafer temperature at the time of bonding from room temperature is not practical because the manufacturing apparatus becomes larger because a new wafer cooling mechanism is required.
  • the load applied to the wafers A and B is desirably 2 MPa or less.
  • the time from the exposure of the clean surfaces of the bonding surfaces 14 of the wafers A and B to the bonding after the Ar atom beam irradiation is short. For this reason, it is desirable to perform Ar atom beam irradiation simultaneously with the wafers A and B.
  • a plurality of Ar atom beam guns may be provided. The alignment of the wafers A and B may be performed immediately after the Ar beam irradiation and immediately before the bonding of the wafers A and B.
  • FIG. 3 is a cross-sectional view showing a main part of a bonding state between semiconductor substrates when particles invade in the method of manufacturing a semiconductor device according to the present invention.
  • FIG. 3 shows a bonding state between the semiconductor substrates 11 in the case where the particles 18 exist in the portion cut along the line A-A ′ in FIG. 6.
  • the groove pattern 17 having a depth or width equal to or larger than the diameter of the particles 18 is formed so as to surround the chip region 12 where the particles 18 exist.
  • distortion generated on the back surface of the semiconductor substrate 11 by the particles 18 can be suppressed in the chip region 12 where the particles 18 exist. For this reason, it can suppress that the void defect 19 produced by the particle 18 extends to the adjacent chip region 12.
  • the manufacturing method of the semiconductor device according to the second embodiment is the same as the manufacturing method of the semiconductor device according to the first embodiment, except that the groove width of the groove pattern 17 is changed to 30 ⁇ m to 500 ⁇ m in the back surface patterning of the wafer A. is there.
  • the groove width of the groove pattern 17 is 100 ⁇ m or more, the width of the portion including the buffer region 33 in the scribe region 16 is increased to be equal to the groove width of the groove pattern 17, thereby forming the groove pattern 17 in the buffer region 33 of the chip region 12. It may be adjusted so that it does not reach the pressure-resistant structure 32.
  • the bonding surfaces 14 of the wafers A and B are flattened (FIG. 1B), and the groove pattern 17 is formed on the bonding surface 14 of the wafer A ( 1 (c) to 1 (e)), a semiconductor device is manufactured by bonding the bonding surfaces 14 of the wafers A and B through bonding pretreatment (FIGS. 1 (f) and 1 (g)) Example).
  • FIG. 4 illustrates a comparative example in which the groove width of the groove pattern 17 is zero.
  • FIG. 4 is a characteristic diagram showing the void defect rate, the number of non-defective products, and the total number of chips when the groove width of the groove pattern of the semiconductor device according to the example is changed.
  • the total number of chips is the total number of chips cut out from one bonded wafer AB. From the results shown in FIG. 4, the void defect rate decreased rapidly as the groove width of the groove pattern 17 widened, and a tendency to saturate when the groove width of the groove pattern 17 was 100 ⁇ m or more was observed. Further, when the groove width of the groove pattern 17 is increased, the total number of chips that can be cut out from the bonded wafer AB is reduced due to the widening of the scribe region 16 including the buffer region 33.
  • the groove width of the groove pattern 17 is preferably 100 ⁇ m or more.
  • the groove width of the groove pattern 17 is increased, the number of non-defective products relative to the total number of chips is high. Therefore, it is desirable that the groove width of the groove pattern 17 be as small as possible within the allowable range in design, for example, 300 ⁇ m or less.
  • a groove pattern having a depth or width greater than the diameter of the assumed particle is formed in the scribe region on the back surface of at least one of the two wafers. Then, by joining the back surfaces of the wafers, void defects due to particles can be mitigated by the groove pattern, and the void defects can be prevented from extending to the adjacent chip region, so that the yield rate can be improved. it can.
  • the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.
  • the case where a bidirectional IGBT is manufactured as the element active portion has been described as an example, but the device structure formed in the element active portion 31 is variously set according to required specifications.
  • a case where a groove pattern is formed on the back surface of one of the two wafers has been described as an example. Even if the groove pattern is formed, the same effect can be obtained. Further, the present invention is similarly established even when the conductivity type is reversed.
  • the method for manufacturing a semiconductor device according to the present invention relates to a power semiconductor device used in a power conversion device such as an inverter and a power supply device such as various industrial machines, and in particular, controls a bidirectional current. This is useful for a power semiconductor device such as a bidirectional IGBT.

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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

La présente invention a trait à un procédé de production d'un dispositif à semi-conducteur qui résulte de deux substrats semi-conducteurs (11) qui sont joints l'un à l'autre, lequel procédé de production comprend, dans un premier temps, une étape consistant à former un tracé de rainure (17) sur une région de découpe (16) du côté de la surface inverse d'au moins un des substrats semi-conducteurs (11) parmi les deux substrats semi-conducteurs (11) qui doivent être joints l'un à l'autre. A ce moment-là, le tracé de rainure (17) est formé à une profondeur ou à une largeur qui correspond au moins au diamètre des particules prévues. Par la suite, les surfaces inverses des deux substrats semi-conducteurs (11) sont jointes l'une à l'autre. En conséquence de quoi, l'effet des particules est atténué sur la partie du tracé de rainure (17), et il est de la sorte possible d'empêcher que les défauts de vide ne s'étendent aux régions de puces adjacentes (12). Par conséquent, il est possible d'augmenter le rendement en minimisant l'effet des défauts de vide sur les puces adjacentes.
PCT/JP2013/068562 2012-08-09 2013-07-05 Procédé de production d'un dispositif à semi-conducteur WO2014024611A1 (fr)

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WO2016006663A1 (fr) * 2014-07-10 2016-01-14 株式会社豊田自動織機 Substrat semi-conducteur et procédé de fabrication de substrat semi-conducteur
JP2016039271A (ja) * 2014-08-08 2016-03-22 株式会社ニコン 基板
US10297578B2 (en) 2017-03-07 2019-05-21 Toshiba Memory Corporation Memory device
US11152345B2 (en) 2019-09-13 2021-10-19 Kioxia Corporation Method for manufacturing semiconductor device

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JPH0963912A (ja) * 1995-08-18 1997-03-07 Hoya Corp 貼り合わせ基板製造方法
JPH1022184A (ja) * 1996-06-28 1998-01-23 Sony Corp 基板張り合わせ装置
WO1999046809A1 (fr) * 1998-03-09 1999-09-16 Harris Corporation Dispositifs pouvant etre formes par procede de liaison directe a basse temperature
WO2005045908A1 (fr) * 2003-11-06 2005-05-19 Matsushita Electric Industrial Co., Ltd. Procede de liaison de substrat, substrat lie, et substrat a liaison directe

Cited By (10)

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WO2016006663A1 (fr) * 2014-07-10 2016-01-14 株式会社豊田自動織機 Substrat semi-conducteur et procédé de fabrication de substrat semi-conducteur
CN106489187A (zh) * 2014-07-10 2017-03-08 株式会社丰田自动织机 半导体基板和半导体基板的制造方法
KR20170028428A (ko) * 2014-07-10 2017-03-13 가부시키가이샤 도요다 지도숏키 반도체 기판 및 반도체 기판의 제조 방법
JPWO2016006663A1 (ja) * 2014-07-10 2017-04-27 株式会社豊田自動織機 半導体基板および半導体基板の製造方法
US9773678B2 (en) 2014-07-10 2017-09-26 Kabushiki Kaisha Toyota Jidoshokki Semiconductor substrate and method for manufacturing semiconductor substrate
CN106489187B (zh) * 2014-07-10 2019-10-25 株式会社希克斯 半导体基板和半导体基板的制造方法
JP2016039271A (ja) * 2014-08-08 2016-03-22 株式会社ニコン 基板
US10297578B2 (en) 2017-03-07 2019-05-21 Toshiba Memory Corporation Memory device
US10741527B2 (en) 2017-03-07 2020-08-11 Toshiba Memory Corporation Memory device
US11152345B2 (en) 2019-09-13 2021-10-19 Kioxia Corporation Method for manufacturing semiconductor device

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