WO2014024611A1 - Method for producing semiconductor device - Google Patents
Method for producing semiconductor device Download PDFInfo
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- WO2014024611A1 WO2014024611A1 PCT/JP2013/068562 JP2013068562W WO2014024611A1 WO 2014024611 A1 WO2014024611 A1 WO 2014024611A1 JP 2013068562 W JP2013068562 W JP 2013068562W WO 2014024611 A1 WO2014024611 A1 WO 2014024611A1
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- semiconductor substrate
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 140
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 46
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
- H01L27/0694—Integrated circuits having a three-dimensional layout comprising components formed on opposite sides of a semiconductor substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a method for manufacturing a semiconductor device.
- a VVVF (Variable Voltage Variable Frequency) inverter device that can variably control the frequency and voltage is frequently used for driving a motor or the like.
- this inverter device is composed of a converter unit that converts commercial frequency alternating current into direct current and an inverter unit that converts this direct current into alternating current of a predetermined frequency and voltage.
- a converter part and an inverter part as well as a large inductor (L) for smoothing current and a large capacitor (C) for suppressing voltage fluctuations are required.
- L large inductor
- C capacitor
- a matrix converter device is composed of an LC filter and nine bidirectional switches.
- the bidirectional switch can be configured using transistors and diodes such as IGBT (Insulated Gate Bipolar Transistor) and MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor).
- IGBT Insulated Gate Bipolar Transistor
- MOSFET Metal-Oxide-Semiconductor Field Effect Transistor
- one bidirectional switch can be configured by arranging a unidirectional switch in which an IGBT and its reverse breakdown voltage diode are connected in series in each of the forward direction and the reverse direction. An element is required.
- a bidirectional switch having a reduced number of elements to two has been put to practical use by using, as a unidirectional switch, a reverse blocking IGBT having the functions of an IGBT and a reverse breakdown voltage diode.
- a structure in which a bidirectional switch is configured with one chip using a double-sided device in which the back surfaces of two IGBTs are bonded to each other has been proposed.
- FIG. 5 is a cross-sectional view showing a main part of a semiconductor substrate in a bonding process of a conventional semiconductor device.
- the surface of the semiconductor substrate 11 is covered with the surface protective film 13 (FIG. 5A).
- the back surface side of each of the two semiconductor substrates 11 is ground and polished so as to be thinned (thickened) to a desired thickness, and then flattened (FIG. 5B). After the thickness reducing step, the surface protective film 13 is removed (FIG. 5C).
- two semiconductor substrates 11 are introduced into a vacuum apparatus (not shown), and the ground back surface 14 serving as a bonding surface is irradiated with a high-speed particle beam such as an Ar atom beam or plasma. Then, contaminants on the back surface 14 of the semiconductor substrate 11 are removed to expose the active surface (FIG. 5D). Immediately after the bonding pretreatment, the back surfaces 14 of the two semiconductor substrates 11 are brought into contact with each other to bond the semiconductor substrates 11 (FIG. 5E), thereby completing the double-sided device.
- a high-speed particle beam such as an Ar atom beam or plasma.
- FIG. 6 shows a semiconductor substrate 11 in which a semiconductor device is manufactured by a conventional bonding process.
- FIG. 6 is an explanatory diagram showing the configuration of the semiconductor substrate.
- FIG. 6A is a plan view of the semiconductor substrate 11, and
- FIG. 6B is a side view of the semiconductor substrate 11.
- a cut portion when the semiconductor substrate 11 is cut into chips is defined as a scribe region 16.
- a scribe region 16 exists on both the front surface and the back surface of the semiconductor substrate 11.
- a broken-line square is a chip region 12, and a portion sandwiched between the chip regions 12 is a scribe region 16.
- FIG. 7 is a cross-sectional view showing the main part of the bonding state between the semiconductor substrates when particles invade in the conventional semiconductor device manufacturing method.
- FIG. 7 shows a bonding state between the semiconductor substrates in the case where the particles 18 exist in the portion cut along the line A-A ′ in FIG. 6.
- the void defect 19 is generated. Since the void defect 19 is electrically insulated, the device bonding area is reduced and the mounting area is reduced, leading to an increase in on-resistance.
- the present invention provides a method for manufacturing a semiconductor device using a wafer bonding process that has less adverse effects on bonding of adjacent chips even when particles are mixed between semiconductor substrates, in order to eliminate the above-described problems caused by the prior art.
- the purpose is to do.
- a semiconductor device manufacturing method has the following characteristics. First, a first step of forming a device structure on each front surface of the first semiconductor substrate and the second semiconductor substrate is performed. Next, a second step of forming a plurality of grooves on the back surface of at least one of the first semiconductor substrate and the second semiconductor substrate is performed. Next, a third step of bonding back surfaces of the first semiconductor substrate and the second semiconductor substrate is performed. At this time, in the second step, the groove having a depth or width equal to or larger than the diameter of the particles attached to the back surface of the first semiconductor substrate or the second semiconductor substrate is formed.
- the semiconductor device manufacturing method according to the present invention is characterized in that, in the above-described invention, in the second step, the groove is formed at a position corresponding to a scribe line.
- each of the first semiconductor substrate and the second semiconductor substrate is placed from the back surface between the first step and the second step.
- the method further includes a thickness reducing step of removing the thickness to a desired thickness.
- the method for manufacturing a semiconductor device according to the present invention is characterized in that the width of the groove is not less than 100 ⁇ m and not more than 300 ⁇ m.
- the groove has a tapered shape having a side wall that forms an angle of not less than 45 degrees and not more than 75 degrees with respect to the back surface of the semiconductor substrate on which the groove is formed. It is characterized by doing.
- the third step is performed in a vacuum, and the temperatures of the first semiconductor substrate and the second semiconductor substrate in the third step are The temperature is from room temperature to 400 ° C.
- the back surfaces of the first semiconductor substrate and the second semiconductor substrate may be separated from each other between the second step and the third step. Etching with lines or plasma.
- the crystal orientation of the material of the first semiconductor substrate is the same as the crystal orientation of the material of the second semiconductor substrate in the above-described invention, and the first semiconductor substrate
- the material of the second semiconductor substrate is silicon.
- void defects due to particles are alleviated by the groove pattern, and it is possible to suppress the void defects from extending to the adjacent chip region. There is an effect that it can be improved.
- FIG. 1 is a cross-sectional view showing the main part of the semiconductor substrate in the bonding process of the semiconductor device according to the first embodiment of the present invention.
- FIG. 2 is a cross-sectional view showing a cross-sectional structure of the semiconductor device manufactured by the method of manufacturing a semiconductor device according to the first embodiment of the present invention.
- FIG. 3 is a cross-sectional view showing a main part of a bonding state between semiconductor substrates when particles invade in the method of manufacturing a semiconductor device according to the present invention.
- FIG. 4 is a characteristic diagram showing the void defect rate, the number of non-defective joints, and the total number of chips when the groove width of the groove pattern of the semiconductor device according to the example is changed.
- FIG. 1 is a cross-sectional view showing the main part of the semiconductor substrate in the bonding process of the semiconductor device according to the first embodiment of the present invention.
- FIG. 2 is a cross-sectional view showing a cross-sectional structure of the semiconductor device manufactured by the method of manufacturing a
- FIG. 5 is a cross-sectional view showing a main part of a semiconductor substrate in a bonding process of a conventional semiconductor device.
- FIG. 6 is an explanatory diagram showing the configuration of the semiconductor substrate.
- FIG. 7 is a cross-sectional view showing a main part of a bonding state between semiconductor substrates when particles invade in a conventional method for manufacturing a semiconductor device.
- FIG. 1 is a cross-sectional view showing the main part of the semiconductor substrate in the bonding process of the semiconductor device according to the first embodiment of the present invention.
- FIG. 2 is a cross-sectional view showing a cross-sectional structure of the semiconductor device manufactured by the method of manufacturing a semiconductor device according to the first embodiment of the present invention.
- FZ-n type silicon wafers A and B are prepared as a semiconductor substrate 11, and a MOS gate (metal-oxide film-semiconductor) is provided as an element active portion 31 through which main current flows in the chip region 12 on the front surface side.
- An insulating gate) structure and an emitter electrode 29 are formed.
- a breakdown voltage structure portion 32 surrounding the periphery of the element active portion 31 is formed on the outer periphery of the element active portion 31 on the front surface side of each of the FZ-n type silicon wafers A and B.
- a buffer region 33 that surrounds the periphery of the breakdown voltage structure 32 is formed on the outer periphery of the breakdown voltage structure 32.
- the FZ-n-type silicon wafer is an n-type wafer manufactured by a floating zone method (hereinafter simply referred to as a wafer).
- the MOS gate structure is a general element structure of a MOS type semiconductor device having a p + type base layer 23, an n + type emitter layer 24, a gate insulating film 25, a gate electrode 26 and an interlayer insulating film 27.
- the chip size (the size of the chip region 12) may be 8 mm ⁇ 8 mm, for example.
- the chip region 12 of each chip is, for example, as shown in the plan view of FIG.
- the wafers A and B are arranged in a matrix.
- a scribe region 16 that is a cutting portion when the semiconductor substrate 11 is cut into chips exists, for example, on both the front and back surfaces of the wafers A and B.
- a photoresist film is formed as the surface protective film 13 (FIG. 1A).
- the surface protective film 13 may be any material that can protect the device structure from process damage described later, and may be formed using other materials.
- the back side is ground and thinned (thickened) to a thickness of 200 ⁇ m.
- a tape for grinding (not shown) is applied to the front surfaces of the wafers A and B, that is, the surface on which the surface protective film 13 is formed, and desired from the back surfaces of the wafers A and B. Grind until near the thickness.
- the back surfaces of the wafers A and B are flattened by CMP (Chemical Mechanical Polishing) (FIG. 1B).
- the surface roughness Ra of the flatness of the bonded surface 14 is desirably lower than 1 nm.
- the back surface flattening processing of the wafers A and B can be performed using any processing such as polishing or etching. Further, the back surface flattening of the wafers A and B may be performed at any timing in the process from the back surface grinding to the bonding of the bonding surfaces 14 of the wafers A and B. In this way, device structures, back surface grinding, and back surface planarization are performed on the wafers A and B prepared as the semiconductor substrate 11, respectively.
- a groove pattern 17 is formed in the scribe region 16 on the back surface of the wafer.
- a resist opening pattern 15 having an opening with a width of 200 ⁇ m is formed by a photolithography process so that the scribe region 16 on the back surface of the wafer A is exposed (FIG. 1C).
- the wafer A is anisotropically etched using the resist opening pattern 15 as a mask, thereby forming a groove pattern 17 having a depth of, for example, 30 ⁇ m on the back surface of the wafer A (FIG. 1D).
- the depth or width of the groove pattern 17 may be a dimension capable of etching control and not less than the diameter of the assumed particle 18.
- the particle diameter is about 0.2 ⁇ m to 0.5 ⁇ m, and therefore the depth or width of the groove pattern 17 is 5 ⁇ m or more is sufficient.
- the groove pattern 17 causes the substrate to break due to internal stress on the wafer when the depth of the groove is 1 ⁇ 2 or less of the substrate thickness after grinding, or the remaining thickness of the pattern portion is 100 ⁇ m or more. Can be prevented.
- TMAH tetramethylammonium hydroxide
- the TMAH etchant has a slow etching rate on the (111) plane of silicon, so that the taper shape that exposes the (111) plane as a side wall that forms an angle of about 53 degrees with respect to the (100) plane on the back of the wafer. This is because the groove pattern 17 can be formed.
- the angle formed between the extension line into the groove pattern 17 on the back surface of the wafer and the side wall of the groove pattern 17 is referred to as a taper angle.
- the groove width of the groove pattern 17 is within a range including the scribe region 16 and the buffer region 33 of the chip region 12 adjacent to the scribe region 16 and does not cover the breakdown voltage structure portion 32. The reason is that, when the groove width of the groove pattern 17 is wide and extends to the breakdown voltage structure 32, the depletion layer extends to the groove pattern 17 at the time of reverse breakdown voltage, resulting in an adverse effect such that leakage current increases.
- the taper angle of the side wall of the groove pattern 17 is preferably 45 degrees or more and 75 degrees or less with respect to the wafer back surface. The reason is as follows. This is because when the taper angle of the side wall of the groove pattern 17 is greater than 75 degrees with respect to the wafer back surface, the corner portion at the upper end of the side wall of the groove pattern 17 is likely to be chipped due to the process load, so that it is likely to become a particle source or a bonding failure location. . On the other hand, when the taper angle of the side wall of the groove pattern 17 is smaller than 45 degrees with respect to the back surface of the wafer, the ineffective area where the element active portion 31 cannot be disposed increases (the area of the element active portion 31 decreases). This is because there arises a problem that the use efficiency is lowered.
- Etching for forming the groove pattern 17 on the wafer A is not necessarily wet etching, and may be performed by any method such as dry etching. Through the steps so far, the groove pattern 17 is formed on the back surface of the wafer A.
- the wafers A and B are irradiated with a particle beam or plasma such as an Ar (argon) atomic beam as a pre-bonding process on the back surface to be the bonding surface 14 to remove contaminants on the back surface.
- a particle beam or plasma such as an Ar (argon) atomic beam
- the wafers A and B are moved into the high vacuum chamber, the wafers A and B are arranged so that the bonding surfaces 14 of the wafers A and B face each other, and the wafers A and B are aligned.
- the degree of vacuum of the chamber in the bonding pretreatment is, for example, 3 ⁇ 10 ⁇ 5 Pa.
- the back surfaces of the wafers A and B are each irradiated with a neutralized Ar atom beam.
- the beam irradiation angle of Ar atoms is set to an angle of 45 degrees with respect to the bonding surface 14 at the wafer center position, for example.
- the applied voltage of the Ar atom beam gun may be set to 1.2 kV, for example, and the plasma current may be set to 20 mA, for example. In this way, contaminants on the outermost surface of the bonding surface 14 of the wafers A and B are etched to expose the clean surface of the wafer material (FIG. 1 (f)).
- the bonding surfaces 14 of the wafers A and B are brought into contact with each other to bond the back surfaces of the wafers A and B, thereby forming the bonding wafer AB (FIG. 1G). Thereby, the semiconductor device shown in FIG. 2 is completed.
- the wafers A and B are intentionally heated and cooled during the bonding process.
- the wafer temperature did not reach 100 ° C., and was maintained at substantially room temperature (for example, 25 ° C.).
- it is desirable that the wafer temperature at the time of bonding is from room temperature to 400 ° C.
- the reason is as follows. A wafer temperature of 400 ° C. or higher is not preferable because it adversely affects the device structure on the front side of the wafer.
- lowering the wafer temperature at the time of bonding from room temperature is not practical because the manufacturing apparatus becomes larger because a new wafer cooling mechanism is required.
- the load applied to the wafers A and B is desirably 2 MPa or less.
- the time from the exposure of the clean surfaces of the bonding surfaces 14 of the wafers A and B to the bonding after the Ar atom beam irradiation is short. For this reason, it is desirable to perform Ar atom beam irradiation simultaneously with the wafers A and B.
- a plurality of Ar atom beam guns may be provided. The alignment of the wafers A and B may be performed immediately after the Ar beam irradiation and immediately before the bonding of the wafers A and B.
- FIG. 3 is a cross-sectional view showing a main part of a bonding state between semiconductor substrates when particles invade in the method of manufacturing a semiconductor device according to the present invention.
- FIG. 3 shows a bonding state between the semiconductor substrates 11 in the case where the particles 18 exist in the portion cut along the line A-A ′ in FIG. 6.
- the groove pattern 17 having a depth or width equal to or larger than the diameter of the particles 18 is formed so as to surround the chip region 12 where the particles 18 exist.
- distortion generated on the back surface of the semiconductor substrate 11 by the particles 18 can be suppressed in the chip region 12 where the particles 18 exist. For this reason, it can suppress that the void defect 19 produced by the particle 18 extends to the adjacent chip region 12.
- the manufacturing method of the semiconductor device according to the second embodiment is the same as the manufacturing method of the semiconductor device according to the first embodiment, except that the groove width of the groove pattern 17 is changed to 30 ⁇ m to 500 ⁇ m in the back surface patterning of the wafer A. is there.
- the groove width of the groove pattern 17 is 100 ⁇ m or more, the width of the portion including the buffer region 33 in the scribe region 16 is increased to be equal to the groove width of the groove pattern 17, thereby forming the groove pattern 17 in the buffer region 33 of the chip region 12. It may be adjusted so that it does not reach the pressure-resistant structure 32.
- the bonding surfaces 14 of the wafers A and B are flattened (FIG. 1B), and the groove pattern 17 is formed on the bonding surface 14 of the wafer A ( 1 (c) to 1 (e)), a semiconductor device is manufactured by bonding the bonding surfaces 14 of the wafers A and B through bonding pretreatment (FIGS. 1 (f) and 1 (g)) Example).
- FIG. 4 illustrates a comparative example in which the groove width of the groove pattern 17 is zero.
- FIG. 4 is a characteristic diagram showing the void defect rate, the number of non-defective products, and the total number of chips when the groove width of the groove pattern of the semiconductor device according to the example is changed.
- the total number of chips is the total number of chips cut out from one bonded wafer AB. From the results shown in FIG. 4, the void defect rate decreased rapidly as the groove width of the groove pattern 17 widened, and a tendency to saturate when the groove width of the groove pattern 17 was 100 ⁇ m or more was observed. Further, when the groove width of the groove pattern 17 is increased, the total number of chips that can be cut out from the bonded wafer AB is reduced due to the widening of the scribe region 16 including the buffer region 33.
- the groove width of the groove pattern 17 is preferably 100 ⁇ m or more.
- the groove width of the groove pattern 17 is increased, the number of non-defective products relative to the total number of chips is high. Therefore, it is desirable that the groove width of the groove pattern 17 be as small as possible within the allowable range in design, for example, 300 ⁇ m or less.
- a groove pattern having a depth or width greater than the diameter of the assumed particle is formed in the scribe region on the back surface of at least one of the two wafers. Then, by joining the back surfaces of the wafers, void defects due to particles can be mitigated by the groove pattern, and the void defects can be prevented from extending to the adjacent chip region, so that the yield rate can be improved. it can.
- the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.
- the case where a bidirectional IGBT is manufactured as the element active portion has been described as an example, but the device structure formed in the element active portion 31 is variously set according to required specifications.
- a case where a groove pattern is formed on the back surface of one of the two wafers has been described as an example. Even if the groove pattern is formed, the same effect can be obtained. Further, the present invention is similarly established even when the conductivity type is reversed.
- the method for manufacturing a semiconductor device according to the present invention relates to a power semiconductor device used in a power conversion device such as an inverter and a power supply device such as various industrial machines, and in particular, controls a bidirectional current. This is useful for a power semiconductor device such as a bidirectional IGBT.
Abstract
In this method for producing a semiconductor device resulting from two semiconductor substrates (11) being joined, first, a groove pattern (17) is formed at a scribing region (16) at the reverse surface side of at least one of the semiconductor substrates (11) of the two semiconductor substrates (11) that are to be joined. As such a time, the groove pattern (17) is formed at a depth or width that is at least the diameter of envisioned particles. Next, the reverse surfaces of the two semiconductor substrates (11) are joined to each other. As a result, the effect of the particles is mitigated at the groove pattern (17) portion, and so it is possible to suppress void defects from extending to adjacent chip regions (12). Therefore it is possible to increase yield by minimizing the effect of void defects on adjacent chips.
Description
この発明は、半導体装置の製造方法に関する。
The present invention relates to a method for manufacturing a semiconductor device.
周波数や電圧を可変制御することができるＶＶＶＦ（Ｖａｒｉａｂｌｅ Ｖｏｌｔａｇｅ Ｖａｒｉａｂｌｅ Ｆｒｅｑｕｅｎｃｙ）インバータ装置がモータなどの駆動用に多用されている。通常、このインバータ装置は、商用周波数の交流を直流に変換するコンバータ部と、この直流を所定の周波数および電圧の交流に変換するインバータ部とから構成されている。このため、電力変換装置としてはコンバータ部とインバータ部、さらには電流を平滑化するための大きなインダクタ（Ｌ）や電圧の変動を抑制するための大きなコンデンサ（Ｃ）が必要となり、装置が大型となる。そこで、電力変換装置の小型化と高効率化を図るために、商用周波数の交流から直接、所定の交流に変換することができるマトリックスコンバータ装置が注目されている。
A VVVF (Variable Voltage Variable Frequency) inverter device that can variably control the frequency and voltage is frequently used for driving a motor or the like. Usually, this inverter device is composed of a converter unit that converts commercial frequency alternating current into direct current and an inverter unit that converts this direct current into alternating current of a predetermined frequency and voltage. For this reason, as a power converter, a converter part and an inverter part, as well as a large inductor (L) for smoothing current and a large capacitor (C) for suppressing voltage fluctuations are required. Become. Therefore, in order to reduce the size and increase the efficiency of the power conversion device, attention has been focused on a matrix converter device that can directly convert commercial frequency alternating current into predetermined alternating current.
一般に、マトリックスコンバータ装置は、ＬＣフィルタと９個の双方向スイッチとで構成される。ここで、双方向スイッチは、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）やＭＯＳＦＥＴ（Ｍｅｔａｌ－Ｏｘｉｄｅ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）などのトランジスタとダイオードとを用いて構成することができる。例えば、１つの双方向スイッチは、ＩＧＢＴとその逆耐圧用ダイオードとを直列に接続した単方向スイッチを、順方向と逆方向とのそれぞれに配置することにより構成することができるが、合計４つの素子が必要となる。
Generally, a matrix converter device is composed of an LC filter and nine bidirectional switches. Here, the bidirectional switch can be configured using transistors and diodes such as IGBT (Insulated Gate Bipolar Transistor) and MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). For example, one bidirectional switch can be configured by arranging a unidirectional switch in which an IGBT and its reverse breakdown voltage diode are connected in series in each of the forward direction and the reverse direction. An element is required.
この場合、デバイス面積は電流容量に概ね比例するため、電流容量が大きくなるとチップサイズが大きくなり、実装面積、ひいてはモジュールサイズが大きくなってしまう。そこで、ＩＧＢＴおよび逆耐圧用ダイオードの機能を併せ持った逆阻止ＩＧＢＴを単方向スイッチとして用いることで、素子数を２つに低減した双方向スイッチが実用化されている。また、更なる小型化のために、２つのＩＧＢＴの裏面同士を貼り合わせた両面デバイスを用いて、１つのチップで双方向スイッチを構成する構造が提案されている。
In this case, since the device area is approximately proportional to the current capacity, the chip size increases as the current capacity increases, resulting in an increase in the mounting area and consequently the module size. Therefore, a bidirectional switch having a reduced number of elements to two has been put to practical use by using, as a unidirectional switch, a reverse blocking IGBT having the functions of an IGBT and a reverse breakdown voltage diode. For further miniaturization, a structure in which a bidirectional switch is configured with one chip using a double-sided device in which the back surfaces of two IGBTs are bonded to each other has been proposed.
このような両面デバイスの作製（製造）方法として、おもて面素子構造を形成した後に裏面電極を形成した２つのデバイスを作製し、裏面電極まで形成したデバイスの裏面同士を接合する方法が提案されている（例えば、下記特許文献１，２参照。）。また、両面デバイスの別の作製方法として、２つのデバイスのドリフト層同士を接合することで、デバイス厚さを薄くして損失を低減する方法が提案されている（例えば、下記特許文献３参照。）。さらに、両面デバイスの別の作製方法として、材料同士を接合する場合、例えば接合面をＡｒ原子ビームなど高速粒子線やプラズマにより最表面のみエッチングし、エッチング面同士を接合する方法が提案されている（例えば、下記特許文献４～７参照。）。
As a method for manufacturing (manufacturing) such a double-sided device, a method is proposed in which two devices in which a back surface electrode is formed after forming a front surface element structure are manufactured, and the back surfaces of the devices formed up to the back surface electrode are bonded to each other. (For example, see Patent Documents 1 and 2 below.) As another method for manufacturing a double-sided device, a method has been proposed in which the drift layers of two devices are joined together to reduce the device thickness and reduce loss (see, for example, Patent Document 3 below). ). Furthermore, as another method for manufacturing a double-sided device, a method has been proposed in which materials are bonded to each other, for example, the bonding surfaces are etched only at the outermost surface with a high-speed particle beam such as an Ar atom beam or plasma, and the etching surfaces are bonded to each other. (For example, see Patent Documents 4 to 7 below.)
ここで、下記特許文献１～７のいずれの方法においても、電極または半導体層などの材料同士を接合するためには、接合面は平坦に加工することが前提となっている。また、チップ単位で接合することは、生産性が乏しく実用的ではないことから、ウェハ等の大面積基板での接合が一般的である。このような接合例として、最表面をエッチングした接合面同士を接触させて接合する方法を用いた従来の半導体装置の製造方法について説明する。図５は、従来の半導体装置の貼り合せ工程における半導体基板の要部を示す断面図である。
Here, in any of the methods of Patent Documents 1 to 7 below, in order to join materials such as electrodes or semiconductor layers, it is premised that the joining surface is processed flat. In addition, bonding on a chip basis is not practical because of low productivity, and bonding with a large-area substrate such as a wafer is generally used. As such a bonding example, a conventional method for manufacturing a semiconductor device using a method in which bonding surfaces whose outermost surfaces are etched is brought into contact with each other will be described. FIG. 5 is a cross-sectional view showing a main part of a semiconductor substrate in a bonding process of a conventional semiconductor device.
初めに、２枚の半導体基板１１を用意し、それぞれの半導体基板１１のおもて面側のチップ領域１２に、デバイス構造を形成する。次に、半導体基板１１のおもて面側に形成したデバイス構造を機械的ダメージおよび化学的ダメージから保護するために、表面保護膜１３により半導体基板１１の表面を被覆する（図５（ａ））。次に、２枚の半導体基板１１のそれぞれについて、裏面側を研削・研磨して所望の厚さまで薄く（減厚）した後、平坦化する（図５（ｂ））。減厚工程の後、表面保護膜１３は除去する（図５（ｃ））。
First, two semiconductor substrates 11 are prepared, and a device structure is formed in the chip region 12 on the front surface side of each semiconductor substrate 11. Next, in order to protect the device structure formed on the front surface side of the semiconductor substrate 11 from mechanical damage and chemical damage, the surface of the semiconductor substrate 11 is covered with the surface protective film 13 (FIG. 5A). ). Next, the back surface side of each of the two semiconductor substrates 11 is ground and polished so as to be thinned (thickened) to a desired thickness, and then flattened (FIG. 5B). After the thickness reducing step, the surface protective film 13 is removed (FIG. 5C).
次に、接合前処理として、２枚の半導体基板１１を真空装置（不図示）内に導入し、接合面となる研削後の裏面１４にＡｒ原子ビームなどの高速粒子線、またはプラズマを照射して、半導体基板１１の裏面１４の汚染物を除去して活性な表面を露出させる（図５（ｄ））。接合前処理後、直ちに２枚の半導体基板１１の裏面１４同士を接触させて半導体基板１１を接合することで（図５（ｅ））、両面デバイスが完成する。
Next, as a pre-bonding treatment, two semiconductor substrates 11 are introduced into a vacuum apparatus (not shown), and the ground back surface 14 serving as a bonding surface is irradiated with a high-speed particle beam such as an Ar atom beam or plasma. Then, contaminants on the back surface 14 of the semiconductor substrate 11 are removed to expose the active surface (FIG. 5D). Immediately after the bonding pretreatment, the back surfaces 14 of the two semiconductor substrates 11 are brought into contact with each other to bond the semiconductor substrates 11 (FIG. 5E), thereby completing the double-sided device.
半導体装置を従来の貼り合せ工程で作製した半導体基板１１を図６に示す。図６は、半導体基板の構成を示す説明図である。図６（ａ）は半導体基板１１の平面図であり、図６（ｂ）は半導体基板１１の側面図である。本明細書では、半導体基板１１をチップに切断する際の切断部をスクライブ領域１６と定義する。半導体基板１１のおもて面および裏面ともにスクライブ領域１６が存在している。図６において、破線の正方形はチップ領域１２であり、チップ領域１２間に挟まれた部分がスクライブ領域１６となる。このような大面積の半導体基板１１同士を接合する際に、両者の間にパーティクルが存在する場合、パーティクルが存在する部分とその周辺が接合されず、ボイド欠陥となる。
FIG. 6 shows a semiconductor substrate 11 in which a semiconductor device is manufactured by a conventional bonding process. FIG. 6 is an explanatory diagram showing the configuration of the semiconductor substrate. FIG. 6A is a plan view of the semiconductor substrate 11, and FIG. 6B is a side view of the semiconductor substrate 11. In the present specification, a cut portion when the semiconductor substrate 11 is cut into chips is defined as a scribe region 16. A scribe region 16 exists on both the front surface and the back surface of the semiconductor substrate 11. In FIG. 6, a broken-line square is a chip region 12, and a portion sandwiched between the chip regions 12 is a scribe region 16. When bonding such large-area semiconductor substrates 11 to each other, if particles exist between the two, the portion where the particles exist and the periphery thereof are not bonded, resulting in a void defect.
図７は、従来例の半導体装置の製造方法におけるパーティクルが侵入したときの半導体基板間の接合状態の要部を示す断面図である。図７には、図６のＡ－Ａ’線で切断した部分にパーティクル１８が存在する場合の半導体基板間の接合状態を示す。半導体基板１１間にパーティクル１８が存在した場合、パーティクル１８を中心にその周辺が接合されないため、ボイド欠陥１９となる。このボイド欠陥１９の領域は電気的に絶縁状態であるため、デバイスの接合面積が減少し、実装面積が減少することとなるため、オン抵抗の上昇を招く。
FIG. 7 is a cross-sectional view showing the main part of the bonding state between the semiconductor substrates when particles invade in the conventional semiconductor device manufacturing method. FIG. 7 shows a bonding state between the semiconductor substrates in the case where the particles 18 exist in the portion cut along the line A-A ′ in FIG. 6. When the particles 18 are present between the semiconductor substrates 11, since the periphery of the particles 18 is not bonded, the void defect 19 is generated. Since the void defect 19 is electrically insulated, the device bonding area is reduced and the mounting area is reduced, leading to an increase in on-resistance.
また、パーティクル１８を起点に半導体基板１１が割れたり、半導体基板１１に欠陥が生じたりするおそれがある。また、ボイド欠陥１９の領域と接合面１４の境界部には応力が集中するため、ここを起点として接合の剥離が生じやすくなる。なお、パーティクル１８の形状にもよるが、直径１μｍのパーティクル１８でさえ、直径数ｍｍのボイド欠陥１９が形成される。このため、ボイド欠陥１９は容易にチップ領域１２間を跨ぐように発生し、１つのボイド欠陥１９が複数のチップを不良にしてしまう。
Further, there is a possibility that the semiconductor substrate 11 is cracked starting from the particles 18 or that the semiconductor substrate 11 is defective. In addition, since stress concentrates on the boundary between the void defect 19 region and the bonding surface 14, bonding peeling is likely to occur from this point. Depending on the shape of the particles 18, even a particle 18 having a diameter of 1 μm forms a void defect 19 having a diameter of several millimeters. For this reason, the void defect 19 is easily generated across the chip regions 12, and one void defect 19 causes a plurality of chips to be defective.
本発明は、上述した従来技術による問題点を解消するため、半導体基板間にパーティクルが混入した場合でも隣接するチップの接合に悪影響の少ないウェハの貼り合せ工程を用いた半導体装置の製造方法を提供することを目的とする。
The present invention provides a method for manufacturing a semiconductor device using a wafer bonding process that has less adverse effects on bonding of adjacent chips even when particles are mixed between semiconductor substrates, in order to eliminate the above-described problems caused by the prior art. The purpose is to do.
上述した課題を解決し、本発明の目的を達成するため、この発明にかかる半導体装置の製造方法は、次の特徴を有する。まず、第１半導体基板および第２半導体基板のそれぞれのおもて面にデバイス構造を形成する第１工程を行う。次に、前記第１半導体基板および前記第２半導体基板のうち、少なくともいずれかの一方の半導体基板の裏面に複数の溝を形成する第２工程を行う。次に、前記第１半導体基板と前記第２半導体基板との裏面同士を接合する第３工程を行う。このとき、前記第２工程では、前記第１半導体基板または前記第２半導体基板の裏面に付着するパーティクルの直径以上の深さまたは幅の前記溝を形成する。
In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device manufacturing method according to the present invention has the following characteristics. First, a first step of forming a device structure on each front surface of the first semiconductor substrate and the second semiconductor substrate is performed. Next, a second step of forming a plurality of grooves on the back surface of at least one of the first semiconductor substrate and the second semiconductor substrate is performed. Next, a third step of bonding back surfaces of the first semiconductor substrate and the second semiconductor substrate is performed. At this time, in the second step, the groove having a depth or width equal to or larger than the diameter of the particles attached to the back surface of the first semiconductor substrate or the second semiconductor substrate is formed.
また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記第２工程では、スクライブラインに対応する位置に前記溝を形成することを特徴とする。
Further, the semiconductor device manufacturing method according to the present invention is characterized in that, in the above-described invention, in the second step, the groove is formed at a position corresponding to a scribe line.
また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記第１工程と前記第２工程との間に、前記第１半導体基板および前記第２半導体基板のそれぞれを、裏面から一様に除去して所望の厚さにする減厚工程をさらに含むことを特徴とする。
In the semiconductor device manufacturing method according to the present invention, in the above-described invention, each of the first semiconductor substrate and the second semiconductor substrate is placed from the back surface between the first step and the second step. In this case, the method further includes a thickness reducing step of removing the thickness to a desired thickness.
また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記溝の幅は、１００μｍ以上３００μｍ以下であることを特徴とする。
Also, in the above-described invention, the method for manufacturing a semiconductor device according to the present invention is characterized in that the width of the groove is not less than 100 μm and not more than 300 μm.
また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記溝は、当該溝が形成される半導体基板の裏面に対して４５度以上７５度以下の角度を為す側壁を有するテーパー形状を為すことを特徴とする。
In the semiconductor device manufacturing method according to the present invention, in the above-described invention, the groove has a tapered shape having a side wall that forms an angle of not less than 45 degrees and not more than 75 degrees with respect to the back surface of the semiconductor substrate on which the groove is formed. It is characterized by doing.
また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記第３工程は真空中で行われ、前記第３工程の際の前記第１半導体基板および前記第２半導体基板の温度は、室温以上４００℃以下であることを特徴とする。
In the semiconductor device manufacturing method according to the present invention, in the above-described invention, the third step is performed in a vacuum, and the temperatures of the first semiconductor substrate and the second semiconductor substrate in the third step are The temperature is from room temperature to 400 ° C.
また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記第２工程と前記第３工程との間に、前記第１半導体基板および前記第２半導体基板のそれぞれの裏面を、粒子線またはプラズマによりエッチングする工程を含むことを特徴とする。
According to the semiconductor device manufacturing method of the present invention, in the above-described invention, the back surfaces of the first semiconductor substrate and the second semiconductor substrate may be separated from each other between the second step and the third step. Etching with lines or plasma.
また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記第１半導体基板の材料の結晶方位と前記第２半導体基板の材料の結晶方位が同じであり、かつ前記第１半導体基板および前記第２半導体基板の材料はシリコンであることを特徴とする。
In the method of manufacturing a semiconductor device according to the present invention, the crystal orientation of the material of the first semiconductor substrate is the same as the crystal orientation of the material of the second semiconductor substrate in the above-described invention, and the first semiconductor substrate The material of the second semiconductor substrate is silicon.
本発明によれば、半導体基板に溝パターンを形成することにより、パーティクルによるボイド欠陥が溝パターンで緩和され、ボイド欠陥が隣接するチップ領域に延伸することを抑制することができるため、良品率を向上させることができるという効果を奏する。
According to the present invention, by forming a groove pattern on the semiconductor substrate, void defects due to particles are alleviated by the groove pattern, and it is possible to suppress the void defects from extending to the adjacent chip region. There is an effect that it can be improved.
以下、本発明にかかる半導体装置の製造方法の好適な実施の形態について、添付図面を用いて詳細に説明する。本明細書および添付図面においては、ｎまたはｐを冠記した層や領域では、それぞれ電子または正孔が多数キャリアであることを意味する。また、ｎやｐに付す＋および－は、それぞれそれが付されていない層や領域よりも高不純物濃度および低不純物濃度であることを意味する。なお、以下の実施の形態の説明および添付図面において、同様の構成には同一の符号を付し、重複する説明を省略する。また、本発明は、その要旨を超えない限り、以下に説明する実施の形態の記載に限定されるものではない。
Hereinafter, preferred embodiments of a method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region not attached thereto. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted. Moreover, this invention is not limited to description of embodiment demonstrated below, unless the summary is exceeded.
（実施の形態１）
実施の形態１にかかる半導体装置の製造方法について、半導体装置として双方向ＩＧＢＴを作製（製造）する場合を例に説明する。半導体装置の製造途中の状態を図１に示す。半導体装置の製造方法により製造するデバイスの構造断面の一例を図２に示す。図１は、本発明の実施の形態１にかかる半導体装置の貼り合せ工程における半導体基板の要部を示す断面図である。図２は、本発明の実施の形態１にかかる半導体装置の製造方法により製造した半導体装置の断面構造を示す断面図である。 (Embodiment 1)
The method for manufacturing a semiconductor device according to the first embodiment will be described by taking as an example the case where a bidirectional IGBT is manufactured (manufactured) as a semiconductor device. A state in the middle of manufacturing the semiconductor device is shown in FIG. An example of a structural cross section of a device manufactured by a method for manufacturing a semiconductor device is shown in FIG. FIG. 1 is a cross-sectional view showing the main part of the semiconductor substrate in the bonding process of the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view showing a cross-sectional structure of the semiconductor device manufactured by the method of manufacturing a semiconductor device according to the first embodiment of the present invention.
実施の形態１にかかる半導体装置の製造方法について、半導体装置として双方向ＩＧＢＴを作製（製造）する場合を例に説明する。半導体装置の製造途中の状態を図１に示す。半導体装置の製造方法により製造するデバイスの構造断面の一例を図２に示す。図１は、本発明の実施の形態１にかかる半導体装置の貼り合せ工程における半導体基板の要部を示す断面図である。図２は、本発明の実施の形態１にかかる半導体装置の製造方法により製造した半導体装置の断面構造を示す断面図である。 (Embodiment 1)
The method for manufacturing a semiconductor device according to the first embodiment will be described by taking as an example the case where a bidirectional IGBT is manufactured (manufactured) as a semiconductor device. A state in the middle of manufacturing the semiconductor device is shown in FIG. An example of a structural cross section of a device manufactured by a method for manufacturing a semiconductor device is shown in FIG. FIG. 1 is a cross-sectional view showing the main part of the semiconductor substrate in the bonding process of the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view showing a cross-sectional structure of the semiconductor device manufactured by the method of manufacturing a semiconductor device according to the first embodiment of the present invention.
まず、半導体基板１１としてＦＺ－ｎ型シリコンウェハＡ，Ｂを用意し、それぞれのおもて面側のチップ領域１２に、主電流の流れる素子活性部３１としてＭＯＳゲート（金属－酸化膜－半導体からなる絶縁ゲート）構造およびエミッタ電極２９を形成する。また、ＦＺ－ｎ型シリコンウェハＡ，Ｂそれぞれのおもて面側の素子活性部３１の外周に、素子活性部３１の周囲を囲む耐圧構造部３２を形成する。耐圧構造部３２の外周には、耐圧構造部３２の周囲を囲むバッファ領域３３が形成される。
First, FZ-n type silicon wafers A and B are prepared as a semiconductor substrate 11, and a MOS gate (metal-oxide film-semiconductor) is provided as an element active portion 31 through which main current flows in the chip region 12 on the front surface side. An insulating gate) structure and an emitter electrode 29 are formed. Further, a breakdown voltage structure portion 32 surrounding the periphery of the element active portion 31 is formed on the outer periphery of the element active portion 31 on the front surface side of each of the FZ-n type silicon wafers A and B. A buffer region 33 that surrounds the periphery of the breakdown voltage structure 32 is formed on the outer periphery of the breakdown voltage structure 32.
ここで、ＦＺ－ｎ型シリコンウェハとは、フローティング・ゾーン法で製作されたｎ型ウェハのことである（以下、単にウェハとする）。また、ＭＯＳゲート構造は、ｐ+型ベース層２３、ｎ+型エミッタ層２４、ゲート絶縁膜２５、ゲート電極２６および層間絶縁膜２７を有するＭＯＳ型半導体装置の一般的な素子構造である。チップサイズ（チップ領域１２の大きさ）は例えば８ｍｍ×８ｍｍとしてもよい。また、チップ領域１２の外周にはチップ状に切断するときの切り代として例えば幅１００μｍのスクライブ領域１６を設けており、個々のチップのチップ領域１２は、例えば、図６の平面図のようにウェハＡ，Ｂのマトリクス状に配置される。半導体基板１１をチップに切断する際の切断部であるスクライブ領域１６は、例えば、ウェハＡ，Ｂのおもて面および裏面ともに存在している。
Here, the FZ-n-type silicon wafer is an n-type wafer manufactured by a floating zone method (hereinafter simply referred to as a wafer). The MOS gate structure is a general element structure of a MOS type semiconductor device having a p + type base layer 23, an n + type emitter layer 24, a gate insulating film 25, a gate electrode 26 and an interlayer insulating film 27. The chip size (the size of the chip region 12) may be 8 mm × 8 mm, for example. In addition, a scribe region 16 having a width of 100 μm, for example, is provided on the outer periphery of the chip region 12 as a cutting allowance when cutting into a chip shape. The chip region 12 of each chip is, for example, as shown in the plan view of FIG. The wafers A and B are arranged in a matrix. A scribe region 16 that is a cutting portion when the semiconductor substrate 11 is cut into chips exists, for example, on both the front and back surfaces of the wafers A and B.
次に、ウェハＡ，Ｂのおもて面側に形成したデバイス構造（素子活性部３１および耐圧構造部３２）を機械的ダメージおよび化学的ダメージから保護するために、おもて面側を覆う表面保護膜１３としてフォトレジスト膜を形成する（図１（ａ））。表面保護膜１３は、後述のプロセスダメージからデバイス構造を保護することができる材料であればよく、他の材料を用いて形成されてもよい。
Next, in order to protect the device structure (element active portion 31 and pressure-resistant structure portion 32) formed on the front surface side of the wafers A and B from mechanical damage and chemical damage, the front surface side is covered. A photoresist film is formed as the surface protective film 13 (FIG. 1A). The surface protective film 13 may be any material that can protect the device structure from process damage described later, and may be formed using other materials.
次に、ウェハＡ，Ｂのそれぞれについて、裏面側を研削して２００μｍの厚さにまで薄く（減厚）する。具体的には、まず、ウェハＡ，Ｂのおもて面、すなわち表面保護膜１３を形成した側の面に研削加工用のテープ（不図示）を貼り、ウェハＡ，Ｂの裏面側から所望の厚さ近傍になるまで研削する。さらに、ＣＭＰ（Ｃｈｅｍｉｃａｌ Ｍｅｃｈａｎｉｃａｌ Ｐｏｌｉｓｈｉｎｇ）によりウェハＡ，Ｂの裏面の平坦化を行う（図１（ｂ））。
Next, for each of wafers A and B, the back side is ground and thinned (thickened) to a thickness of 200 μm. Specifically, first, a tape for grinding (not shown) is applied to the front surfaces of the wafers A and B, that is, the surface on which the surface protective film 13 is formed, and desired from the back surfaces of the wafers A and B. Grind until near the thickness. Further, the back surfaces of the wafers A and B are flattened by CMP (Chemical Mechanical Polishing) (FIG. 1B).
ここで、ウェハＡ，Ｂの平坦化した面が最終的な接合面１４となるため、接合面１４の平坦度の表面粗さＲａは１ｎｍより低いことが望ましい。また、ウェハＡ，Ｂの裏面平坦化加工は研磨やエッチングなどの任意の加工を用いることができる。また、ウェハＡ，Ｂの裏面平坦化加工は、裏面研削後からウェハＡ，Ｂの接合面１４同士を接合するまでの工程のいずれのタイミングで行ってもよい。このように、半導体基板１１として用意したウェハＡ，Ｂに対してそれぞれ、デバイス構造の形成、裏面研削、および裏面平坦化加工を行う。
Here, since the planarized surfaces of the wafers A and B become the final bonded surface 14, the surface roughness Ra of the flatness of the bonded surface 14 is desirably lower than 1 nm. Further, the back surface flattening processing of the wafers A and B can be performed using any processing such as polishing or etching. Further, the back surface flattening of the wafers A and B may be performed at any timing in the process from the back surface grinding to the bonding of the bonding surfaces 14 of the wafers A and B. In this way, device structures, back surface grinding, and back surface planarization are performed on the wafers A and B prepared as the semiconductor substrate 11, respectively.
次に、ウェハＡ，Ｂのうち少なくともいずれか一方のウェハについて、ウェハ裏面のスクライブ領域１６に溝パターン１７を形成する。例えば、具体的には、ウェハＡの裏面に溝パターン１７を形成する場合を例に説明する。まず、フォトリソグラフィプロセスにより、ウェハＡの裏面のスクライブ領域１６が露出されるように、幅２００μｍの開口部を有するレジスト開口パターン１５を形成する（図１（ｃ））。
Next, for at least one of the wafers A and B, a groove pattern 17 is formed in the scribe region 16 on the back surface of the wafer. For example, specifically, a case where the groove pattern 17 is formed on the back surface of the wafer A will be described as an example. First, a resist opening pattern 15 having an opening with a width of 200 μm is formed by a photolithography process so that the scribe region 16 on the back surface of the wafer A is exposed (FIG. 1C).
次に、レジスト開口パターン１５をマスクとしてウェハＡを異方性エッチングすることで、ウェハＡの裏面に例えば深さ３０μｍの溝パターン１７を形成する（図１（ｄ））。溝パターン１７の深さまたは幅は、エッチング制御が可能な寸法で、かつ想定されるパーティクル１８の直径以上あればよい。例えば通常の半導体製造ラインの管理状態でクリーンルームや処理装置内の清浄度が確保されている場合、パーティクルの直径は０．２μｍから０．５μｍ程度であるので、溝パターン１７の深さまたは幅は５μｍ以上あれば十分である。また、溝パターン１７は、溝の深さを研削後の基板厚さの１／２以下とする、或いはパターン部の残り厚さが１００μｍ以上とすることにより、ウェハへの内部応力により基板が割れることを防止できる。
Next, the wafer A is anisotropically etched using the resist opening pattern 15 as a mask, thereby forming a groove pattern 17 having a depth of, for example, 30 μm on the back surface of the wafer A (FIG. 1D). The depth or width of the groove pattern 17 may be a dimension capable of etching control and not less than the diameter of the assumed particle 18. For example, when cleanliness in a clean room or a processing apparatus is ensured in a normal semiconductor production line management state, the particle diameter is about 0.2 μm to 0.5 μm, and therefore the depth or width of the groove pattern 17 is 5 μm or more is sufficient. In addition, the groove pattern 17 causes the substrate to break due to internal stress on the wafer when the depth of the groove is ½ or less of the substrate thickness after grinding, or the remaining thickness of the pattern portion is 100 μm or more. Can be prevented.
また、ウェハＡに溝パターン１７を形成するために用いるエッチング液には、例えばＴＭＡＨ（テトラメチルアンモニウムヒドロキシド）を用いてもよい。その理由は、ＴＭＡＨエッチング液ではシリコンの（１１１）面のエッチング速度が遅いため、ウェハ裏面である（１００）面に対して約５３度の角度を為す（１１１）面を側壁として露出するテーパー形状の溝パターン１７を形成することができるからである。以下、ウェハ裏面の溝パターン１７内への延長線と溝パターン１７の側壁との為す角度をテーパー角度とする。
Further, TMAH (tetramethylammonium hydroxide), for example, may be used as an etchant used for forming the groove pattern 17 on the wafer A. The reason for this is that the TMAH etchant has a slow etching rate on the (111) plane of silicon, so that the taper shape that exposes the (111) plane as a side wall that forms an angle of about 53 degrees with respect to the (100) plane on the back of the wafer. This is because the groove pattern 17 can be formed. Hereinafter, the angle formed between the extension line into the groove pattern 17 on the back surface of the wafer and the side wall of the groove pattern 17 is referred to as a taper angle.
また、溝パターン１７の溝幅は、スクライブ領域１６とその両隣にあるチップ領域１２のバッファ領域３３を含めた範囲内に収め、耐圧構造部３２にはかからないことが重要である。その理由は、溝パターン１７の溝幅が広く耐圧構造部３２にまでかかる場合、逆耐圧時に空乏層が溝パターン１７まで広がりリーク電流が増加するといった悪影響がでてくるためである。
Further, it is important that the groove width of the groove pattern 17 is within a range including the scribe region 16 and the buffer region 33 of the chip region 12 adjacent to the scribe region 16 and does not cover the breakdown voltage structure portion 32. The reason is that, when the groove width of the groove pattern 17 is wide and extends to the breakdown voltage structure 32, the depletion layer extends to the groove pattern 17 at the time of reverse breakdown voltage, resulting in an adverse effect such that leakage current increases.
また、溝パターン１７の側壁のテーパー角度は、ウェハ裏面に対して４５度以上７５度以下であることが好ましい。その理由は、次のとおりである。溝パターン１７の側壁のテーパー角度がウェハ裏面に対して７５度より大きい場合、溝パターン１７の側壁の上端の角部分がプロセス負荷により欠けやすくなるため、パーティクル源や接合不良箇所となりやすいからである。一方、溝パターン１７の側壁のテーパー角度がウェハ裏面に対して４５度より小さい場合、素子活性部３１が配置できない無効面積が増加（素子活性部３１の面積が減少）してしまうためウェハＡの利用効率が下がるという問題が生ずるからである。
Further, the taper angle of the side wall of the groove pattern 17 is preferably 45 degrees or more and 75 degrees or less with respect to the wafer back surface. The reason is as follows. This is because when the taper angle of the side wall of the groove pattern 17 is greater than 75 degrees with respect to the wafer back surface, the corner portion at the upper end of the side wall of the groove pattern 17 is likely to be chipped due to the process load, so that it is likely to become a particle source or a bonding failure location. . On the other hand, when the taper angle of the side wall of the groove pattern 17 is smaller than 45 degrees with respect to the back surface of the wafer, the ineffective area where the element active portion 31 cannot be disposed increases (the area of the element active portion 31 decreases). This is because there arises a problem that the use efficiency is lowered.
ウェハＡに溝パターン１７を形成するためのエッチング後、ウェハおもて面の表面保護膜１３、および裏面のレジスト開口パターン１５を除去する（図１（ｅ））。ウェハＡに溝パターン１７を形成するためのエッチングは、必ずしもウェットエッチングである必要はなく、ドライエッチングなど、いずれの方法で行ってもよい。ここまでの工程により、ウェハＡの裏面に溝パターン１７が形成される。
After the etching for forming the groove pattern 17 on the wafer A, the front surface protective film 13 on the front surface of the wafer and the resist opening pattern 15 on the back surface are removed (FIG. 1E). Etching for forming the groove pattern 17 on the wafer A is not necessarily wet etching, and may be performed by any method such as dry etching. Through the steps so far, the groove pattern 17 is formed on the back surface of the wafer A.
次に、ウェハＡ，Ｂについて、接合面１４となる裏面に接合前処理として例えばＡｒ（アルゴン）原子ビームなど粒子線やプラズマを照射して、裏面の汚染物を除去する。具体的には、まず、ウェハＡ，Ｂを高真空チャンバー内に移動し、ウェハＡ，Ｂの接合面１４同士が対向するようにウェハＡ，Ｂを配置し、ウェハＡ，Ｂの位置合わせを行う。接合前処理における、チャンバーの真空度は例えば３×１０-5Ｐａである。そして、Ａｒイオンを加速した後、ウェハＡ，Ｂの裏面にそれぞれ中性化したＡｒ原子ビームを照射する。Ａｒ原子のビーム照射角度は、例えばウェハ中央位置で接合面１４に対して４５度の角度となるようにする。また、Ａｒ原子ビームガンの印加電圧を例えば１．２ｋＶとし、プラズマ電流を例えば２０ｍＡとしてもよい。このように、ウェハＡ，Ｂの接合面１４の最表面の汚染物をエッチングして、ウェハ材料の清浄面を露出させる（図１（ｆ））。
Next, the wafers A and B are irradiated with a particle beam or plasma such as an Ar (argon) atomic beam as a pre-bonding process on the back surface to be the bonding surface 14 to remove contaminants on the back surface. Specifically, first, the wafers A and B are moved into the high vacuum chamber, the wafers A and B are arranged so that the bonding surfaces 14 of the wafers A and B face each other, and the wafers A and B are aligned. Do. The degree of vacuum of the chamber in the bonding pretreatment is, for example, 3 × 10 −5 Pa. Then, after accelerating Ar ions, the back surfaces of the wafers A and B are each irradiated with a neutralized Ar atom beam. The beam irradiation angle of Ar atoms is set to an angle of 45 degrees with respect to the bonding surface 14 at the wafer center position, for example. Further, the applied voltage of the Ar atom beam gun may be set to 1.2 kV, for example, and the plasma current may be set to 20 mA, for example. In this way, contaminants on the outermost surface of the bonding surface 14 of the wafers A and B are etched to expose the clean surface of the wafer material (FIG. 1 (f)).
次に、Ａｒ原子ビーム照射後、直ちにウェハＡ，Ｂの接合面１４同士を接触させることでウェハＡ，Ｂの裏面同士を接合し、接合ウェハＡＢを形成する（図１（ｇ））。これにより、図２に示す半導体装置が完成する。
Next, immediately after the Ar atomic beam irradiation, the bonding surfaces 14 of the wafers A and B are brought into contact with each other to bond the back surfaces of the wafers A and B, thereby forming the bonding wafer AB (FIG. 1G). Thereby, the semiconductor device shown in FIG. 2 is completed.
上述した実施の形態１にかかる半導体装置の製造方法にしたがい、接合ウェハＡＢからなる半導体装置を作製（製造）した結果、接合プロセス中、ウェハＡ，Ｂには意図的な加熱や冷却は行っていないが、ウェハ温度は１００℃までも達することなく、ほぼ室温（例えば２５℃）を維持していた。ここで、接合時のウェハ温度は室温以上４００℃以下であることが望ましい。その理由は、次のとおりである。ウェハ温度が４００℃以上の場合、ウェハおもて面側のデバイス構造に悪影響が出るため好ましくない。一方、接合時のウェハ温度を室温より下げることは、新たなウェハ冷却機構が必要となる分、製造装置が大型化するため現実的ではない。
According to the manufacturing method of the semiconductor device according to the first embodiment described above, as a result of manufacturing (manufacturing) the semiconductor device including the bonded wafer AB, the wafers A and B are intentionally heated and cooled during the bonding process. However, the wafer temperature did not reach 100 ° C., and was maintained at substantially room temperature (for example, 25 ° C.). Here, it is desirable that the wafer temperature at the time of bonding is from room temperature to 400 ° C. The reason is as follows. A wafer temperature of 400 ° C. or higher is not preferable because it adversely affects the device structure on the front side of the wafer. On the other hand, lowering the wafer temperature at the time of bonding from room temperature is not practical because the manufacturing apparatus becomes larger because a new wafer cooling mechanism is required.
また、ウェハ面内において均一な接合強度でウェハＡ，Ｂ同士を接合するために、ウェハＡ，Ｂの接合時にはウェハＡ，Ｂ同士を互いに押し付ける方向にウェハ全体に均一に荷重をかけることが望ましい。上述したように接合前処理としてウェハＡ，Ｂの接合面１４にそれぞれＡｒ原子ビームを照射する場合は、ウェハ全体に均一に荷重をかけることができればよく、ウェハにかける荷重の大きさはウェハの接合強度には関係しない。このため、デバイス構造へのダメージを避けるために、ウェハＡ，Ｂにかける荷重は２ＭＰａ以下が望ましい。また、Ａｒ原子ビーム照射によりウェハＡ，Ｂの接合面１４の清浄面を露出させてから接合するまでの時間は短いほうが好ましい。このため、Ａｒ原子ビーム照射はウェハＡ，Ｂ同時に行うほうが望ましく、そのためにＡｒ原子ビームガンを複数設置してもよい。また、ウェハＡ，Ｂの位置合わせは、Ａｒビーム照射後、ウェハＡ，Ｂの接合の直前に行ってもよい。
Further, in order to bond the wafers A and B with uniform bonding strength within the wafer surface, it is desirable to apply a load uniformly to the whole wafer in the direction in which the wafers A and B are pressed together when bonding the wafers A and B. . As described above, when the Ar atom beam is irradiated to the bonding surfaces 14 of the wafers A and B as bonding pretreatment, it is sufficient that a load can be uniformly applied to the entire wafer. It is not related to bonding strength. For this reason, in order to avoid damage to the device structure, the load applied to the wafers A and B is desirably 2 MPa or less. Further, it is preferable that the time from the exposure of the clean surfaces of the bonding surfaces 14 of the wafers A and B to the bonding after the Ar atom beam irradiation is short. For this reason, it is desirable to perform Ar atom beam irradiation simultaneously with the wafers A and B. For this purpose, a plurality of Ar atom beam guns may be provided. The alignment of the wafers A and B may be performed immediately after the Ar beam irradiation and immediately before the bonding of the wafers A and B.
次に、実施の形態１にかかる半導体装置の製造方法によって作製された半導体装置の半導体基板１１間にパーティクルが存在したときの状態について説明する。図３は、本発明にかかる半導体装置の製造方法におけるパーティクルが侵入したときの半導体基板間の接合状態の要部を示す断面図である。図３には、図６のＡ－Ａ’線で切断した部分にパーティクル１８が存在する場合の半導体基板１１間の接合状態を示す。図３に示すように、半導体基板１１間にパーティクル１８が存在する場合であっても、パーティクル１８が存在するチップ領域１２を囲むようにパーティクル１８の直径以上の深さまたは幅の溝パターン１７を形成することにより、パーティクル１８によって半導体基板１１の裏面に生じる歪みを、当該パーティクル１８が存在するチップ領域１２内に抑えることができる。このため、パーティクル１８によって生じるボイド欠陥１９が隣接するチップ領域１２に延伸することを抑制することができる。
Next, a state when particles are present between the semiconductor substrates 11 of the semiconductor device manufactured by the semiconductor device manufacturing method according to the first embodiment will be described. FIG. 3 is a cross-sectional view showing a main part of a bonding state between semiconductor substrates when particles invade in the method of manufacturing a semiconductor device according to the present invention. FIG. 3 shows a bonding state between the semiconductor substrates 11 in the case where the particles 18 exist in the portion cut along the line A-A ′ in FIG. 6. As shown in FIG. 3, even when the particles 18 exist between the semiconductor substrates 11, the groove pattern 17 having a depth or width equal to or larger than the diameter of the particles 18 is formed so as to surround the chip region 12 where the particles 18 exist. By forming, distortion generated on the back surface of the semiconductor substrate 11 by the particles 18 can be suppressed in the chip region 12 where the particles 18 exist. For this reason, it can suppress that the void defect 19 produced by the particle 18 extends to the adjacent chip region 12.
（実施の形態２）
次に、実施の形態２にかかる半導体装置の製造方法について説明する。実施の形態２にかかる半導体装置の製造方法は、ウェハＡの裏面パターニングにおいて、溝パターン１７の溝幅を３０μｍ～５００μｍと変えた以外は、実施の形態１にかかる半導体装置の製造方法と同様である。溝パターン１７の溝幅が１００μｍ以上の場合、スクライブ領域１６にバッファ領域３３を含めた部分の幅を溝パターン１７の溝幅と同等に広げることで、溝パターン１７をチップ領域１２のバッファ領域３３内に収めて、耐圧構造部３２にかからないように調整すればよい。 (Embodiment 2)
Next, a method for manufacturing the semiconductor device according to the second embodiment will be described. The manufacturing method of the semiconductor device according to the second embodiment is the same as the manufacturing method of the semiconductor device according to the first embodiment, except that the groove width of thegroove pattern 17 is changed to 30 μm to 500 μm in the back surface patterning of the wafer A. is there. When the groove width of the groove pattern 17 is 100 μm or more, the width of the portion including the buffer region 33 in the scribe region 16 is increased to be equal to the groove width of the groove pattern 17, thereby forming the groove pattern 17 in the buffer region 33 of the chip region 12. It may be adjusted so that it does not reach the pressure-resistant structure 32.
次に、実施の形態２にかかる半導体装置の製造方法について説明する。実施の形態２にかかる半導体装置の製造方法は、ウェハＡの裏面パターニングにおいて、溝パターン１７の溝幅を３０μｍ～５００μｍと変えた以外は、実施の形態１にかかる半導体装置の製造方法と同様である。溝パターン１７の溝幅が１００μｍ以上の場合、スクライブ領域１６にバッファ領域３３を含めた部分の幅を溝パターン１７の溝幅と同等に広げることで、溝パターン１７をチップ領域１２のバッファ領域３３内に収めて、耐圧構造部３２にかからないように調整すればよい。 (Embodiment 2)
Next, a method for manufacturing the semiconductor device according to the second embodiment will be described. The manufacturing method of the semiconductor device according to the second embodiment is the same as the manufacturing method of the semiconductor device according to the first embodiment, except that the groove width of the
（実施例）
上述した実施の形態１に係る半導体装置の製造方法にしたがい、ウェハＡ，Ｂの接合面１４を平坦化し（図１（ｂ））、ウェハＡの接合面１４に溝パターン１７を形成した後に（図１（ｃ）～１（ｅ））、接合前処理を経てウェハＡ，Ｂの接合面１４同士を接合する（図１（ｆ），１（ｇ））ことによって半導体装置を作製した（以下、実施例とする）。比較として、ウェハＡ，Ｂの裏面平坦化後、図１（ｃ），１（ｄ）に相当するウェハ裏面の溝パターン形成工程を行うことなく、ウェハＡ，Ｂの接合工程を行った半導体装置を作製した（以下、比較例とする）。比較例の製造方法は、溝パターン形成工程を行っていないこと以外は実施例と同様とした（図５）。そして、実施例の溝パターン１７の溝幅を変えたときのボイド不良率および接合良品数について検証した。その結果を図４に示す。図４には、溝パターン１７の溝幅＝０として比較例を図示する。 (Example)
In accordance with the semiconductor device manufacturing method according to the first embodiment described above, the bonding surfaces 14 of the wafers A and B are flattened (FIG. 1B), and thegroove pattern 17 is formed on the bonding surface 14 of the wafer A ( 1 (c) to 1 (e)), a semiconductor device is manufactured by bonding the bonding surfaces 14 of the wafers A and B through bonding pretreatment (FIGS. 1 (f) and 1 (g)) Example). As a comparison, a semiconductor device in which the bonding process of wafers A and B is performed after the back surface flattening of wafers A and B, without performing the groove pattern forming process on the back surface of the wafer corresponding to FIGS. 1 (c) and 1 (d). (Hereinafter, referred to as a comparative example). The manufacturing method of the comparative example was the same as that of the example except that the groove pattern forming step was not performed (FIG. 5). And it verified about the void defect rate when the groove width of the groove pattern 17 of an Example was changed, and the number of good joining. The result is shown in FIG. FIG. 4 illustrates a comparative example in which the groove width of the groove pattern 17 is zero.
上述した実施の形態１に係る半導体装置の製造方法にしたがい、ウェハＡ，Ｂの接合面１４を平坦化し（図１（ｂ））、ウェハＡの接合面１４に溝パターン１７を形成した後に（図１（ｃ）～１（ｅ））、接合前処理を経てウェハＡ，Ｂの接合面１４同士を接合する（図１（ｆ），１（ｇ））ことによって半導体装置を作製した（以下、実施例とする）。比較として、ウェハＡ，Ｂの裏面平坦化後、図１（ｃ），１（ｄ）に相当するウェハ裏面の溝パターン形成工程を行うことなく、ウェハＡ，Ｂの接合工程を行った半導体装置を作製した（以下、比較例とする）。比較例の製造方法は、溝パターン形成工程を行っていないこと以外は実施例と同様とした（図５）。そして、実施例の溝パターン１７の溝幅を変えたときのボイド不良率および接合良品数について検証した。その結果を図４に示す。図４には、溝パターン１７の溝幅＝０として比較例を図示する。 (Example)
In accordance with the semiconductor device manufacturing method according to the first embodiment described above, the bonding surfaces 14 of the wafers A and B are flattened (FIG. 1B), and the
図４は、実施例にかかる半導体装置の溝パターンの溝幅を変えたときのボイド不良率、接合良品数およびチップ総数を示す特性図である。図４において、チップ総数とは、１枚の接合ウェハＡＢから切り出されるチップの総数である。図４に示す結果より、ボイド不良率は、溝パターン１７の溝幅が広がるとともに急激に減少し、溝パターン１７の溝幅が１００μｍ以上で飽和する傾向が見られた。また、溝パターン１７の溝幅が大きくなると、スクライブ領域１６にバッファ領域３３を含めた幅を広げたことに起因して接合ウェハＡＢから切り出せるチップ総数が減少した。このボイド不良率とチップ総数とのトレードオフのために、接合良品数は溝パターン１７の溝幅として１００μｍ以上２００μｍ以下の領域で最大となっている。これらの結果から溝パターン１７の溝幅は１００μｍ以上であるのがよい。ただし、溝パターン１７の溝幅が広くなると、チップ総数に対する接合良品数は高いものの、チップ総数自体が減少するため、接合良品数も減少する。したがって、溝パターン１７の溝幅は、設計上許容される範囲内で可能な限り小さい値であるのが望ましく、例えば３００μｍ以下であるとよい。
FIG. 4 is a characteristic diagram showing the void defect rate, the number of non-defective products, and the total number of chips when the groove width of the groove pattern of the semiconductor device according to the example is changed. In FIG. 4, the total number of chips is the total number of chips cut out from one bonded wafer AB. From the results shown in FIG. 4, the void defect rate decreased rapidly as the groove width of the groove pattern 17 widened, and a tendency to saturate when the groove width of the groove pattern 17 was 100 μm or more was observed. Further, when the groove width of the groove pattern 17 is increased, the total number of chips that can be cut out from the bonded wafer AB is reduced due to the widening of the scribe region 16 including the buffer region 33. Due to the trade-off between the void defect rate and the total number of chips, the number of non-defective products is maximum in the region of 100 μm or more and 200 μm or less as the groove width of the groove pattern 17. From these results, the groove width of the groove pattern 17 is preferably 100 μm or more. However, when the groove width of the groove pattern 17 is increased, the number of non-defective products relative to the total number of chips is high. Therefore, it is desirable that the groove width of the groove pattern 17 be as small as possible within the allowable range in design, for example, 300 μm or less.
以上、説明したように、各実施の形態によれば、２枚のウェハの少なくともいずれか一方のウェハの裏面のスクライブ領域に、想定されるパーティクルの直径以上の深さまたは幅の溝パターンを形成した後に、ウェハの裏面同士を接合することにより、パーティクルによるボイド欠陥が溝パターンで緩和され、ボイド欠陥が隣接するチップ領域に延伸することを抑制することができるため、良品率を向上させることができる。
As described above, according to each embodiment, a groove pattern having a depth or width greater than the diameter of the assumed particle is formed in the scribe region on the back surface of at least one of the two wafers. Then, by joining the back surfaces of the wafers, void defects due to particles can be mitigated by the groove pattern, and the void defects can be prevented from extending to the adjacent chip region, so that the yield rate can be improved. it can.
以上において本発明は、上述した実施の形態に限らず、本発明の趣旨を逸脱しない範囲で種々変更可能である。例えば、素子活性部として双方向ＩＧＢＴを作製する場合を例に説明したが、素子活性部３１に形成するデバイス構造は要求される仕様等に応じて種々設定される。また、上述した各実施の形態では、２枚のウェハのうち一方のウェハの裏面に溝パターンを形成する場合を例に説明しているが、２枚のウェハともに、ウェハ裏面のスクライブ領域にそれぞれ溝パターンを形成しても同様の効果が得られる。また、本発明は、導電型を反転させても同様に成り立つ。
As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, the case where a bidirectional IGBT is manufactured as the element active portion has been described as an example, but the device structure formed in the element active portion 31 is variously set according to required specifications. Further, in each of the above-described embodiments, a case where a groove pattern is formed on the back surface of one of the two wafers has been described as an example. Even if the groove pattern is formed, the same effect can be obtained. Further, the present invention is similarly established even when the conductivity type is reversed.
以上のように、本発明にかかる半導体装置の製造方法は、インバータなどの電力変換装置や種々の産業用機械などの電源装置に使用されるパワー半導体装置に関し、特に、双方向の電流を制御することができる双方向ＩＧＢＴなどのパワー半導体装置に有用である。
As described above, the method for manufacturing a semiconductor device according to the present invention relates to a power semiconductor device used in a power conversion device such as an inverter and a power supply device such as various industrial machines, and in particular, controls a bidirectional current. This is useful for a power semiconductor device such as a bidirectional IGBT.
１１ 半導体基板
１２ チップ領域（素子活性部＋耐圧構造部）
１３ 表面保護膜
１４ 接合面
１５ レジスト開口パターン
１６ スクライブ領域
１７ 溝パターン
１８ パーティクル
１９ ボイド欠陥
２３ ｐ+型ベース層
２４ ｎ+型エミッタ層
２５ ゲート絶縁膜
２６ ゲート電極
２７ 層間絶縁膜
２９ エミッタ電極
３１ 素子活性部
３２ 耐圧構造部
３３ バッファ領域11 Semiconductor substrate 12 Chip region (element active part + breakdown voltage structure part)
DESCRIPTION OFSYMBOLS 13 Surface protective film 14 Bonding surface 15 Resist opening pattern 16 Scribe area | region 17 Groove pattern 18 Particle | grain 19 Void defect 23 p + type | mold base layer 24 n + type emitter layer 25 Gate insulating film 26 Gate electrode 27 Interlayer insulating film 29 Emitter electrode 31 Element Active part 32 Withstand voltage structure part 33 Buffer area
１２ チップ領域（素子活性部＋耐圧構造部）
１３ 表面保護膜
１４ 接合面
１５ レジスト開口パターン
１６ スクライブ領域
１７ 溝パターン
１８ パーティクル
１９ ボイド欠陥
２３ ｐ+型ベース層
２４ ｎ+型エミッタ層
２５ ゲート絶縁膜
２６ ゲート電極
２７ 層間絶縁膜
２９ エミッタ電極
３１ 素子活性部
３２ 耐圧構造部
３３ バッファ領域
DESCRIPTION OF
Claims (8)
- 第１半導体基板および第２半導体基板のそれぞれのおもて面にデバイス構造を形成する第１工程と、
前記第１工程後、前記第１半導体基板および前記第２半導体基板のうち、少なくともいずれか一方の半導体基板の裏面に複数の溝を形成する第２工程と、
前記第２工程後、前記第１半導体基板と前記第２半導体基板との裏面同士を接合する第３工程と、
を含み、
前記第２工程では、前記第１半導体基板または前記第２半導体基板の裏面に付着するパーティクルの直径以上の深さまたは幅の前記溝を形成することを特徴とする半導体装置の製造方法。 A first step of forming a device structure on each front surface of the first semiconductor substrate and the second semiconductor substrate;
A second step of forming a plurality of grooves on the back surface of at least one of the first semiconductor substrate and the second semiconductor substrate after the first step;
A third step of bonding back surfaces of the first semiconductor substrate and the second semiconductor substrate after the second step;
Including
In the second step, the groove having a depth or width equal to or larger than the diameter of the particles attached to the back surface of the first semiconductor substrate or the second semiconductor substrate is formed. - 前記第２工程では、スクライブラインに対応する位置に前記溝を形成することを特徴とする請求項１に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the second step, the groove is formed at a position corresponding to a scribe line.
- 前記第１工程と前記第２工程との間に、前記第１半導体基板および前記第２半導体基板のそれぞれを、裏面から一様に除去して所望の厚さにする減厚工程をさらに含むことを特徴とする請求項１に記載の半導体装置の製造方法。 The method further includes a thickness reducing step between the first step and the second step, wherein each of the first semiconductor substrate and the second semiconductor substrate is uniformly removed from the back surface to obtain a desired thickness. The method of manufacturing a semiconductor device according to claim 1.
- 前記溝の幅は、１００μｍ以上３００μｍ以下であることを特徴とする請求項１に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein the width of the groove is 100 μm or more and 300 μm or less.
- 前記溝は、当該溝が形成される半導体基板の裏面に対して４５度以上７５度以下の角度を為す側壁を有するテーパー形状を為すことを特徴とする請求項１に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein the groove has a tapered shape having a side wall that forms an angle of 45 degrees or more and 75 degrees or less with respect to the back surface of the semiconductor substrate on which the groove is formed. .
- 前記第３工程は真空中で行われ、
前記第３工程の際の前記第１半導体基板および前記第２半導体基板の温度は、室温以上４００℃以下であることを特徴とする請求項１に記載の半導体装置の製造方法。 The third step is performed in a vacuum,
2. The method of manufacturing a semiconductor device according to claim 1, wherein temperatures of the first semiconductor substrate and the second semiconductor substrate in the third step are not less than room temperature and not more than 400 ° C. 3. - 前記第２工程と前記第３工程との間に、前記第１半導体基板および前記第２半導体基板のそれぞれの裏面を、粒子線またはプラズマによりエッチングする工程を含むことを特徴とする請求項１に記載の半導体装置の製造方法。 2. The method according to claim 1, further comprising: etching a back surface of each of the first semiconductor substrate and the second semiconductor substrate with a particle beam or plasma between the second step and the third step. The manufacturing method of the semiconductor device of description.
- 前記第１半導体基板の材料の結晶方位と前記第２半導体基板の材料の結晶方位が同じであり、かつ前記第１半導体基板および前記第２半導体基板の材料はシリコンであることを特徴とする請求項１～７のいずれか一つに記載の半導体装置の製造方法。 The crystal orientation of the material of the first semiconductor substrate is the same as the crystal orientation of the material of the second semiconductor substrate, and the material of the first semiconductor substrate and the second semiconductor substrate is silicon. Item 8. The method for manufacturing a semiconductor device according to any one of Items 1 to 7.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016006663A1 (en) * | 2014-07-10 | 2016-01-14 | 株式会社豊田自動織機 | Semiconductor substrate and semiconductor substrate production method |
| JP2016039271A (en) * | 2014-08-08 | 2016-03-22 | 株式会社ニコン | substrate |
| US10297578B2 (en) | 2017-03-07 | 2019-05-21 | Toshiba Memory Corporation | Memory device |
| US11152345B2 (en) | 2019-09-13 | 2021-10-19 | Kioxia Corporation | Method for manufacturing semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0963912A (en) * | 1995-08-18 | 1997-03-07 | Hoya Corp | Manufacture of joined substrate |
| JPH1022184A (en) * | 1996-06-28 | 1998-01-23 | Sony Corp | Substrate bonding device |
| WO1999046809A1 (en) * | 1998-03-09 | 1999-09-16 | Harris Corporation | Devices formable by low temperature direct bonding |
| WO2005045908A1 (en) * | 2003-11-06 | 2005-05-19 | Matsushita Electric Industrial Co., Ltd. | Method for bonding substrate, bonded substrate, and direct bonded substrate |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3924810B2 (en) * | 1995-07-19 | 2007-06-06 | 松下電器産業株式会社 | Piezoelectric element and manufacturing method thereof |
| JP2791429B2 (en) * | 1996-09-18 | 1998-08-27 | 工業技術院長 | Room-temperature bonding of silicon wafers |
| JP4479052B2 (en) * | 2000-05-09 | 2010-06-09 | 富士電機システムズ株式会社 | Semiconductor device |
| JP2004111521A (en) * | 2002-09-17 | 2004-04-08 | Shin Etsu Handotai Co Ltd | Soi wafer and its manufacturing method |
-
2013
- 2013-07-05 WO PCT/JP2013/068562 patent/WO2014024611A1/en active Application Filing
- 2013-07-05 JP JP2014529390A patent/JPWO2014024611A1/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0963912A (en) * | 1995-08-18 | 1997-03-07 | Hoya Corp | Manufacture of joined substrate |
| JPH1022184A (en) * | 1996-06-28 | 1998-01-23 | Sony Corp | Substrate bonding device |
| WO1999046809A1 (en) * | 1998-03-09 | 1999-09-16 | Harris Corporation | Devices formable by low temperature direct bonding |
| WO2005045908A1 (en) * | 2003-11-06 | 2005-05-19 | Matsushita Electric Industrial Co., Ltd. | Method for bonding substrate, bonded substrate, and direct bonded substrate |
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