WO2014012271A1 - 半导体器件制造方法 - Google Patents

半导体器件制造方法 Download PDF

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WO2014012271A1
WO2014012271A1 PCT/CN2012/079348 CN2012079348W WO2014012271A1 WO 2014012271 A1 WO2014012271 A1 WO 2014012271A1 CN 2012079348 W CN2012079348 W CN 2012079348W WO 2014012271 A1 WO2014012271 A1 WO 2014012271A1
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dielectric layer
gate dielectric
gate
etching
layer
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French (fr)
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刘云飞
尹海洲
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/022—Manufacture or treatment of FETs having insulated gates [IGFET] having lightly-doped source or drain extensions selectively formed at the sides of the gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0218—Manufacture or treatment of FETs having insulated gates [IGFET] having pocket halo regions selectively formed at the sides of the gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/22—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks
    • H10P30/221—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping using masks characterised by the angle between the ion beam and the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface

Definitions

  • the present disclosure relates to the field of semiconductors and, more particularly, to a method of fabricating a semiconductor device. Background technique
  • oblique ion implantation is often performed.
  • a shallow junction is formed, and ion implantation is usually performed at a certain inclination angle.
  • halo implantation is usually performed with a large tilt angle.
  • oblique ion implantation causes implanted ions to pass through the gate dielectric layer, causing damage to the gate dielectric layer, causing the device to fail due to a sharp increase in gate leakage current.
  • This problem is particularly acute when high-energy, high-dose injections of large impurity ions such as P, Ge, and As ions are observed.
  • a conventional solution is to deposit a dielectric spacer (e.g., silicon oxide or silicon nitride) on the sidewalls of the gate stack prior to the ion implantation process to attenuate the damage of the implanted ions to the gate dielectric layer.
  • a dielectric spacer e.g., silicon oxide or silicon nitride
  • this method does not completely eliminate the damage of the gate dielectric layer, thereby degrading the device performance to some extent.
  • a method of fabricating a semiconductor device comprising: forming a gate stack on a substrate, the gate stack including a gate dielectric layer and a gate conductor layer; selectively etching an end of the gate dielectric layer, thereby Forming a void; and filling the material of the gate dielectric layer in the void.
  • the gate dielectric layer is processed by selectively etching the ends of the gate dielectric layer and then backfilling, such that defects that may be present at the ends of the gate dielectric layer, such as defects due to oblique ion implantation, can be removed.
  • FIG. 1-3 are schematic views showing a flow of fabricating a semiconductor device in accordance with an embodiment of the present disclosure. detailed description
  • a layer/element when a layer/element is referred to as being "on" another layer/element, the layer/element may be located directly on the other layer/element, or a central layer may be present between them. element. In addition, if a layer/element is "on” another layer/element, the layer/element may be "under” the other layer/element when the orientation is reversed.
  • the substrate 100 may be a substrate of various forms such as, but not limited to, a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor-on-insulator (SOI) substrate, a SiGe substrate, or the like.
  • a body Si substrate will be described as an example for convenience of explanation.
  • the gate stack may include a gate dielectric layer 102 and a gate conductor layer 104.
  • the gate dielectric layer 102 may include a dielectric layer such as silicon oxide or may include a high K gate dielectric.
  • the gate conductor layer 104 may include polysilicon or a metal gate conductor.
  • a work function adjusting layer (not shown) may be sandwiched between the gate dielectric layer 102 and the gate conductor layer 104.
  • the source/drain regions 106 can then be formed by gate stacking as a mask, such as by ion implantation.
  • oblique ion implantation may also be performed to form, for example, a halo structure 108 or a lightly doped drain (LDD).
  • LDD lightly doped drain
  • implanted ions may pass through the gate dielectric layer 102, particularly the ends of the gate dielectric layer 102, causing damage 110 in the gate dielectric layer 102.
  • the end of the gate dielectric layer 102, particularly the region containing the damage 110 may be removed by selective etching.
  • selective etching can be performed by wet etching, dry etching, or a combination thereof.
  • the structure shown in Figure 1 can be immersed in an etching solution.
  • the etching solution may, for example, comprise an HF solution diluted at about 100:1.
  • the region affected by the oblique ion implantation (including the damage 110) at the end of the gate dielectric layer 102 can be specifically removed by controlling the etching time.
  • the etching time may be determined, for example, according to an etching rate of the gate dielectric and an amount of etching required for the gate dielectric.
  • the etch rate of the gate dielectric depends on various factors such as the material of the gate dielectric itself, the etch scheme, and the ambient temperature.
  • the amount of etching required for the gate dielectric depends, for example, on the tilt angle of the ion implantation, the implantation energy, the implant dose, and the like.
  • a substantially damage-free gate can be obtained by filling the material of the gate dielectric layer (for example, silicon oxide) at the end of the gate dielectric layer 102 (there is a void due to the selective etching described above). Dielectric layer 102'. Such filling can be accomplished, for example, by depositing a thick layer of gate dielectric material over substrate 100 and performing etch back. Such deposition may include, for example, low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD).
  • LPCVD low pressure chemical vapor deposition
  • ALD atomic layer deposition
  • a portion of the gate dielectric layer material on the sidewalls of the gate stack is retained during etchback, such as by controlling parameters of the etch process, thereby forming a first sidewall spacer of the gate stack.
  • etchback such as by controlling parameters of the etch process
  • the device can include a substrate 100 and a gate stack formed on the substrate 100.
  • the gate stack includes a gate dielectric layer 102' and a gate conductor layer 104.
  • Gate dielectric layer 102' includes a backfill portion at the end.
  • the backfill portion extends along a sidewall of the gate stack to serve as a first sidewall of the gate stack.
  • the gate dielectric layer can be selectively etched and backfilled even without oblique ion implantation to remove possible damage to the ends of the gate dielectric layer.

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种制造半导体器件的方法，该方法包括：在衬底（100）上形成栅堆叠，栅堆叠包括栅介质层（102）和栅导体层（104）；选择性刻蚀栅介质层（102）的端部，从而形成空隙；以及在空隙中填充栅介质层（102）的材料。

Description

半导体器件制造方法
本申请要求了 2012年 7月 18日提交的、 申请号为 201210249429.5、 发明名称为
"半导体器件制造方法"的中国专利申请的优先权， 其全部内容通过引用结合在本申 请中。 技术领域
本公开涉及半导体领域， 更具体地， 涉及一种制造半导体器件的方法。 背景技术
在半导体工艺中， 经常会进行倾斜离子注入。 例如， 在使用离子注入工艺形成 CMOS器件源漏区的过程中， 为了避免隧道效应而形成浅结， 通常沿一定倾斜角度进 行离子注入。 另外， 在短沟道器件的制作中， 为了控制短沟道效应， 通常采用大倾斜 角度进行暈圈 （halo) 注入。
然而， 倾斜离子注入会使注入离子穿过栅介质层， 从而造成栅介质层的损伤， 使 得器件由于栅漏电流急剧增加而失效。特别当高能量、大剂量注入大型杂质离子如 P、 Ge、 As离子等时， 这一问题更加突出。
常规解决方案是在离子注入工艺之前在栅堆叠侧壁上淀积一层电介质侧墙 （例 如， 氧化硅或氮化硅）， 以减弱注入离子对栅介质层的损伤效果。 然而， 这种方法并 不能完全消除栅介质层的损伤， 从而使器件性能在一定程度上被降低。 发明内容
本公开的目的至少部分地在于提供一种制造半导体器件的方法。
根据本公开的一个方面， 提供了一种制造半导体器件的方法， 包括： 在衬底上形 成栅堆叠， 栅堆叠包括栅介质层和栅导体层； 选择性刻蚀栅介质层的端部， 从而形成 空隙； 以及在空隙中填充栅介质层的材料。
通过选择性刻蚀栅介质层的端部然后再回填， 对栅介质层进行处理， 使得可以去 除栅介质层端部可能存在的缺陷， 例如由于倾斜离子注入而导致的缺陷。 附图说明
通过以下参照附图对本公开实施例的描述， 本公开的上述以及其他目的、 特征和 优点将更为清楚， 在附图中：
图 1-3是示出了根据本公开实施例的制造半导体器件流程的示意图。 具体实施方式
以下， 将参照附图来描述本公开的实施例。 但是应该理解， 这些描述只是示例性 的， 而并非要限制本公开的范围。 此外， 在以下说明中， 省略了对公知结构和技术的 描述， 以避免不必要地混淆本公开的概念。
在附图中示出了根据本公开实施例的各种结构示意图。 这些图并非是按比例绘制 的， 其中为了清楚表达的目的， 放大了某些细节， 并且可能省略了某些细节。 图中所 示出的各种区域、 层的形状以及它们之间的相对大小、 位置关系仅是示例性的， 实际 中可能由于制造公差或技术限制而有所偏差， 并且本领域技术人员根据实际所需可以 另外设计具有不同形状、 大小、 相对位置的区域 /层。
在本公开的上下文中， 当将一层 /元件称作位于另一层 /元件 "上" 时， 该层 /元件 可以直接位于该另一层 /元件上， 或者它们之间可以存在居中层 /元件。 另外， 如果在 一种朝向中一层 /元件位于另一层 /元件"上"， 那么当调转朝向时， 该层 /元件可以位于 该另一层 /元件 "下"。
如图 1所示， 提供衬底 100。 衬底 100可以是各种形式的衬底， 例如但不限于体半 导体材料衬底如体 Si衬底、 绝缘体上半导体 （SOI) 衬底、 SiGe衬底等。 在以下的描 述中， 为方便说明， 以体 Si衬底为例进行描述。
在衬底 100上， 可以形成栅堆叠。 栅堆叠可以包括栅介质层 102和栅导体层 104。 栅介质层 102可以包括电介质层如氧化硅， 或者可以包括高 K栅介质。 栅导体层 104可 以包括多晶硅， 或者金属栅导体。 在栅介质层 102包括高 K栅介质、 栅导体层 104包括 金属栅导体的情况下， 还可以存在功函数调节层 （未示出） 夹于栅介质层 102和栅导 体层 104之间。 然后， 可以栅堆叠为掩模， 例如通过离子注入， 形成源 /漏区 106。
在进行源 /漏注入之前， 如图 1中的箭头所示， 还可以进行倾斜离子注入， 以便形 成例如暈圈 （halo) 结构 108或轻掺杂漏 （LDD)。 在倾斜离子注入过程中， 注入离子 可能会穿过栅介质层 102， 特别是栅介质层 102的端部， 从而在栅介质层 102中造成损 伤 110。 接下来， 如图 2所示， 可以通过选择性刻蚀， 去除栅介质层 102的端部， 特别是包 含损伤 110的区域。 例如， 这种选择性刻蚀可以通过湿法刻蚀、 干法刻蚀或其组合来 进行。例如，可以将图 1所示的结构浸入刻蚀溶液中。刻蚀溶液例如可以包括按约 100: 1 稀释的 HF溶液。 在刻蚀过程中， 可以通过控制刻蚀时间， 来特别去除栅介质层 102端 部受倾斜离子注入影响的区域 （包含损伤 110)。
根据本公开的实施例， 刻蚀时间例如可以根据栅介质的刻蚀速率以及栅介质需要 刻蚀的量来确定。 栅介质的刻蚀速率取决于多种因素， 例如栅介质本身的材质、 刻蚀 方案以及环境温度等。 栅介质需要刻蚀的量例如取决于离子注入的倾斜角度、 注入能 量和注入剂量等。
然后， 如图 3所示， 可以通过在栅介质层 102的端部 （由于上述选择性刻蚀而存在 空隙） 填充栅介质层的材料 （例如， 氧化硅）， 来获得基本上无损伤的栅介质层 102'。 这种填充例如可以通过在衬底 100上淀积一层厚的栅介质材料层， 并进行回蚀来完成。 这种淀积例如可以包括低压化学气相淀积 （LPCVD) 或者原子层淀积 （ALD)。 根据 本公开的一示例， 在回蚀过程中， 例如通过控制刻蚀工艺的参数， 保留栅介质层材料 位于栅堆叠侧壁上的部分， 从而形成栅堆叠的第一侧墙。 本领域技术人员知道这种通 过回蚀形成侧墙的工艺， 在此不再赘述。
这样， 就获得了最终的器件。 如图 3所述， 该器件可以包括衬底 100和在衬底 100 上形成的栅堆叠。 栅堆叠包括栅介质层 102'和栅导体层 104。 栅介质层 102'包括位于端 部的回填部分。 可选地， 该回填部分沿栅堆叠的侧壁延伸， 充当栅堆叠的第一侧墙。
这里需要指出的是， 尽管在以上的说明中， 针对由于倾斜离子注入而造成栅介质 损伤的情况， 描述了对栅介质层进行选择性刻蚀和回填的处理。 但是， 本公开不限于 此。 例如， 即便不进行倾斜离子注入， 也可以对栅介质层进行选择性刻蚀和回填的处 理， 以便去除栅介质层端部可能存在的损伤。
以上对本公开的实施例进行了描述。 但是， 这些实施例仅仅是为了说明的目的， 而并非为了限制本公开的范围。 本公开的范围由所附权利要求及其等价物限定。 不脱 离本公开的范围， 本领域技术人员可以做出多种替代和修改， 这些替代和修改都应落 在本公开的范围之内。

Claims

权 利 要 求
1. 一种制造半导体器件的方法， 包括：
在衬底上形成栅堆叠， 栅堆叠包括栅介质层和栅导体层；
选择性刻蚀栅介质层的端部， 从而形成空隙； 以及
在空隙中填充栅介质层的材料。
2. 根据权利要求 1所述的方法， 在空隙中填充栅介质层的材料包括： 淀积所 述材料并回蚀， 其中， 在回蚀过程中， 保留所述材料位于栅堆叠侧壁上的部分， 以用 作栅堆叠的第一侧墙。
3. 根据权利要求 2所述的方法，其中，淀积包括低压化学气相淀积（LPCVD) 或者原子层淀积 （ALD)。
4. 根据权利要求 1所述的方法， 选择性刻蚀通过湿法刻蚀、干法刻蚀或其组 合来进行。
5. 根据权利要求 4所述的方法， 其中， 湿法刻蚀通过稀释 HF溶液进行。
6. 根据权利要求 1所述的方法，其中，在选择性刻蚀栅介质层端部的操作中， 控制刻蚀时间， 以去除栅介质层端部受倾斜离子注入影响的区域。
7. 根据权利要求 1所述的方法， 其中， 在形成栅堆叠之后且在选择性刻蚀栅 介质层的端部之前， 该方法还包括：
进行倾斜离子注入。
8. 根据权利要求 7所述的方法， 其中， 倾斜离子注入用于形成暈圈区（halo) 或者轻掺杂漏 （LDD)。
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