WO2014005371A1 - 半导体器件制造方法 - Google Patents

半导体器件制造方法 Download PDF

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WO2014005371A1
WO2014005371A1 PCT/CN2012/081009 CN2012081009W WO2014005371A1 WO 2014005371 A1 WO2014005371 A1 WO 2014005371A1 CN 2012081009 W CN2012081009 W CN 2012081009W WO 2014005371 A1 WO2014005371 A1 WO 2014005371A1
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etching
semiconductor device
dielectric material
fabricating
material layer
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French (fr)
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孟令款
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to US13/700,775 priority Critical patent/US8728948B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01316—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]

Definitions

  • the present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly to a sidewall etching method. Background technique
  • a dielectric spacer is required before the lightly doped drain (LDD) implant process to prevent a larger dose of source-drain implants from approaching the channel and causing source-drain punch-through, resulting in device failure. And the yield is reduced.
  • LDD lightly doped drain
  • a layer of silicon dioxide film such as rapid thermal oxidation (RTO) growth of about 30A Silica, as a subsequent etch barrier, to protect the substrate, especially the interface between the source and drain regions near the channel region, from damage, to avoid an increase in defect density; and to deposit a good conformal nitridation A thin film of silicon, surrounded by a polysilicon gate.
  • RTO rapid thermal oxidation
  • the silicon nitride film on the substrate and on the gate is removed by plasma etching, and the underlying oxide layer is stopped to form sidewall spacers.
  • the traditional gate oxide/polysilicon gate structure is increasingly unable to meet the requirements of advanced logic devices, and is gradually replaced by high-k-metal gate structures.
  • the back gate process can control the thermal effect and the good control of the threshold voltage, it has gradually become the mainstream process, leading to many new process difficulties and challenges.
  • the height of the gate is reduced to meet the challenges of metal gate filling due to CMOS fabrication techniques. In order to completely fill the metal, it is necessary to reduce the aspect ratio of the grid. Moreover, due to the gradual reduction of the grid pitch, the thickness of the first side wall is continuously reduced.
  • the etching rate In order to accurately control the repeatability, reliability, and stability of the etching process, the etching rate must be reduced to meet the increasing challenges of the etching process, which tends to make the uniformity of the sidewall etching rate worse.
  • current sidewall etching techniques are generally based on Ar-based gases, which tend to cause damage to the substrate under nanoscale device conditions, especially when the silicon oxide liner on the gate is extremely thin, oxygen plasma. It is easy to penetrate the thin oxide layer and react with the substrate, resulting in a large silicon loss value.
  • the above object of the present invention is achieved by providing a semiconductor device manufacturing method comprising: forming a gate stack structure on a substrate; sequentially depositing a first dielectric material layer and a second dielectric material on the substrate and the gate stack structure a second dielectric material layer and a first dielectric material layer are sequentially etched by using an etching gas containing germanium to form a second spacer and a first spacer.
  • the step of etching the second dielectric material layer and the first dielectric material layer further includes: performing a main etch, etching the second dielectric material layer to form a second spacer, and leaving a second layer on the first dielectric material layer Residue of the dielectric material layer; performing etching to remove residual of the second dielectric material layer; performing etching to remove the exposed first dielectric material layer on the substrate.
  • the gate stack structure includes a gate insulating layer and a gate electrode layer, the gate electrode layer includes polysilicon, amorphous silicon, and a metal gate, and the gate insulating layer includes silicon dioxide, silicon oxynitride, and a high-k material.
  • the first dielectric material layer comprises silicon dioxide, which is deposited by a method selected from the group consisting of RTO, PECVD, and SACVD.
  • the second dielectric material layer comprises silicon nitride, diamond-like amorphous carbon, and is deposited by LPCVD or PECVD.
  • the etching gas includes a fluorine-based gas, an oxidizing gas, and a cerium-based gas.
  • the ratio of the electrode power, the cavity pressure and the reaction gas flow rate is adjusted to enhance the anisotropy and form a steep side wall.
  • the ratio of the pole power, the chamber pressure and the reaction gas flow rate is adjusted to obtain a high selection ratio of the dielectric material layer to the substrate.
  • the selection ratio is greater than 10:1.
  • the fluorine-based gas includes a fluorocarbon-based gas, F 3 .
  • the main etched fluorine-based gas includes CF 4 , CHF 3 , and CH 2 F 2 .
  • the over-etched fluorine-based gas includes CF 4 , CH 3 F, and CH 2 F 2 .
  • the oxidizing gas comprises 0 2 .
  • the sulfhydryl gas includes a mixture of helium, neon and argon.
  • the endpoint detection is automatically triggered by the spectral changes of the reactants and the product.
  • the system ends the main etch and enters the over-etching to etch the dielectric layer in all areas of the wafer.
  • the etching time required is calculated by the etching rate until the surface of the substrate is approached, the main etching is finished and the over etching is performed, and the dielectric layer in the entire area of the wafer is etched clean.
  • the main etching and/or over etching is performed by an etching device based on CCP or ICP mode.
  • the first dielectric material layer is wet etched by using an HF-based etching solution.
  • the method further includes: forming a source/drain region by ion implantation on both sides by using the second sidewall and the first sidewall as a mask; removing the dummy gate stack structure to form a gate trench; filling the gate trench with a high K material
  • the gate insulating layer and the gate conductive layer of the metal material form a high K-metal gate structure.
  • a two-layer composite sidewall spacer and a helium-containing etching gas are used for two-step etching, which reduces damage to the substrate while reducing process complexity, and optimizes the valve.
  • Value voltage, effective reduction of EoT, improved gate control capability and drive current are used for two-step etching, which reduces damage to the substrate while reducing process complexity, and optimizes the valve.
  • FIG. 1 to 5 are schematic cross-sectional views showing respective steps of a method of fabricating a semiconductor device in accordance with the present invention
  • Fig. 6 is a flow chart showing a method of fabricating a semiconductor device in accordance with the present invention.
  • a gate stack structure is formed on a substrate, which may be a gate stack of a front gate process or a dummy gate stack of a back gate process.
  • a substrate 1 is provided which may be bulk Si, SOI, bulk Ge, GeOI, SiGe, GeSb, or a III-V or II-VI compound semiconductor substrate such as GaAs, GaN, InP, InSb or the like.
  • substrate 1 is preferably bulk Si or SOI.
  • a thinner gate insulating layer (gate oxide layer) 2 is formed on the substrate 1 by a deposition method such as LPCVD, PECVD, thermal oxidation, RTO, etc., for example, a thin SiO 2 layer having a thickness of, for example, 1 to 5 nm, which is used later
  • the back gate process protects the substrate when the dummy gate is removed.
  • the gate insulating layer 2 is a high K material for a back gate process.
  • the electrode layer 3 is made of, for example, polycrystalline silicon or amorphous silicon.
  • the dummy gate layer 3 is then patterned using a photolithography/etching process
  • a dummy gate stack structure is formed.
  • the etching process may include plasma etching (using inert ions such as Ar), reactive ion etching (RIE, using fluorine-based gas), or anisotropic wet etching (for example, TMAH etching solution etching Si material, HF basis)
  • TMAH etching solution etching Si material, HF basis
  • the etching solution etches the SiO material
  • the etching stop point may be at the interface between the gate oxide layer 2 and the gate electrode layer (dummy gate layer) 3, or may be slightly over-etched until the substrate 1 is exposed.
  • the layout of the gate stack 2/3 is not limited to the single line shown in FIG.
  • the sides of the gate stack structure are substantially steep, i.e., the angle between the gate stack structure and the substrate is substantially equal to 90 degrees (e.g., in the range of 90 degrees ⁇ 2.5 degrees).
  • a dielectric material is deposited over the gate stack structure. If the gate oxide layer 2 is not etched in Fig. 1, it is preferable to first remove the gate oxide layer 2 outside the gate stack by HF-based wet etching. Then, a uniform thickness of the first dielectric material 4 and the second dielectric material 5 are sequentially formed on the entire substrate (wafer).
  • the first dielectric material 4 which may be silicon dioxide, is used as a subsequent etch barrier by (rapid) thermal oxidation (RTO), PECVD, atmospheric pressure CVD (SACVD), HDPCVD, or the like.
  • the first dielectric material 4 is sufficiently thin to well control the final morphology of the sidewalls, preferably having a thickness of from 1 to 3 nm.
  • the second dielectric material 5 is formed by a conventional deposition method such as LPCVD, PECVD, etc., which may be a hard material such as silicon nitride or diamond-like amorphous carbon (DLC) and has a high etching selectivity ratio with each of the previously deposited materials.
  • the material in addition to being used as the gate sidewall isolation isolation, can further stress the channel region to enhance device drive capability.
  • the silicon nitride film is deposited by PECVD.
  • the thickness of the second dielectric material 5 is, for example, 50 to 70 nm.
  • the layer of the first dielectric material 4 and the layer of the second dielectric material 5 are conformed to the gate stack structure as shown in FIG.
  • the second dielectric material 5 is anisotropically etched, and the first dielectric material 4 is stopped to obtain the second spacer 5A.
  • an etching device based on CCP or ICP mode, adjusting the power of the electrode, the pressure of the cavity, and the flow rate of the reactive gas, enhancing the anisotropic etching, so that the top of the gate stack structure is second.
  • the dielectric material 5 is completely removed, the second dielectric material 5 of the sidewall of the gate stack structure is substantially retained to constitute the second spacer 5A, and only a small amount is left on the surface of the substrate (the first dielectric material 4) in the active region.
  • the residue 5B of the dielectric material that is, the second dielectric material 5 is etched until the first dielectric material 4 is exposed.
  • the etching gas mainly includes a fluorine-based gas such as a fluorocarbon-based gas, and F 3 , SF 6 or the like can also be used.
  • the fluorocarbon-based gas of the present invention may include CF 4 , CHF 3 , CH 3 F, CH 2 F 2 .
  • the amount of polymer is removed in combination with the oxidizing gas 02 and CO.
  • the main etching etching gas is CF 4 and CHF 3 , or CF 4 and CH 2 F 2 Or only CHF 3 is used, and the oxidizing gas is 0 2 .
  • the etching rate In addition, in order to accurately control the repeatability, reliability, and stability of the etching process, the etching rate must be reduced.
  • the prior art often adds Ar as a diluent to reduce the etch rate.
  • Ar As a diluent to reduce the etch rate.
  • the bombardment of the substrate is obvious.
  • damage to the underlying material is more likely to occur.
  • the silicon oxide liner on the polysilicon gate is extremely thin, the oxygen plasma easily penetrates the thin oxide layer and reacts with the substrate, causing a large The value of silicon loss.
  • the etching gas component of the present invention introduces a cerium-based gas such as a helium gas or a helium/argon gas mixture, which can significantly reduce the lining. Bottom damage.
  • a cerium-based gas such as a helium gas or a helium/argon gas mixture
  • the etching uniformity is improved, that is, the cerium-based gas is preferably a mixture of helium and argon.
  • the end point detection system When etched to the surface of the underlying silicon substrate 1, the end point detection system is automatically triggered by the spectral line changes of the reactants and products, the main etching step is stopped, and then the over-etching of the next step is quickly changed.
  • the required etching time can be calculated by etching rate until nearly half of the surface of the silicon substrate is used to achieve a steep surface without footing, and then proceed to the next over-etching.
  • the width of the second spacer 5A is substantially equal to the thickness of the second original dielectric material 5, or the ratio of reduction is not more than 10%, and the width may specifically be 50-70 nm; and the second dielectric material 5 remains on the surface of the substrate 1.
  • the thickness of the residual 5B is much smaller than the thickness of the original second dielectric material 5, for example, less than 20% of the original thickness, and specifically may be 10-15 nm.
  • the second side wall 5A is substantially steep, that is, the angle between the second side wall 5A and the substrate 1 is preferably 90 degrees.
  • over-etching is performed to remove residual second dielectric material.
  • the main etching obtaining the topography of the steep second side wall 5A, it is necessary to remove the remaining second dielectric material film 5B on the entire wafer. Since the thickness of the film deposition of the second dielectric material 5 varies across the wafer, a certain proportion of overetching needs to be added.
  • the dielectric material 5 has a high selectivity ratio to the silicon oxide of the first dielectric material 4 and the silicon of the substrate 1, thereby improving device performance.
  • plasma etching systems, etching devices based on CCP or ICP mode are used.
  • the choice of the second dielectric material 5 (e.g., silicon nitride) for the first dielectric material 4 and the substrate silicon selectivity is primarily dependent on the flow rate of the reactive gas and its ratio. Similar to the main etch shown in FIG. 3, the overetch shown in FIG. 4 mainly uses a fluorine-based gas (the same as the step shown in FIG.
  • the overetched etching gas is CF 4 and CH 3 F, or CF 4 and CH 2 F 2 or only CH 3 F, and the oxidizing gas is 0 2 .
  • the second dielectric material 5 only has a portion of the second spacer 5A remaining, while the first dielectric material 4 remains intact, and the portion of the first dielectric material 4 on the side of the dummy gate stack is covered by the second spacer 5A, and the rest Partially exposed on the substrate 1.
  • HF and LF represent high frequency and low frequency power, respectively. Only a few specific etching gases and parameters are given in Table 1, but other gases listed above in this specification can also be used and the parameter range can be reasonably adjusted as long as a sufficiently high selection ratio is obtained in the overetching step ( For example, 15: 1 or more).
  • the first dielectric material 4 exposed on the surface of the substrate 1 is etched away to form a first sidewall spacer 4A, and the first side wall 4A and the second sidewall spacer 5A form a double-layer composite side.
  • Wall structure For the first dielectric material 4 made of silicon oxide, an HF-based wet etching solution such as 5-10% HF diluent (DHF) or a slow-release etching solution (BOE, HF and H 4 F) may be used.
  • the mixed solution) the working temperature is, for example, 25 degrees Celsius, and the etching time is selected according to the thickness.
  • the first sidewall 4A and the second spacer 5A are left on both sides of the gate stack structure to form a double-layer composite sidewall structure.
  • the back gate process can be used to form a source/drain region by using a double-layer composite sidewall structure as a mask, and a metal silicide is formed on/in the source/drain region to reduce source-drain resistance on the entire wafer.
  • an interlayer dielectric layer depositing an interlayer dielectric layer, dry etching or etching to remove the dummy gate stack to form a gate trench, sequentially depositing a gate insulating layer of a high-K material, and a gate conductive layer of a metal material in the gate trench, The interlayer dielectric layer is etched until the source/drain region and/or the metal silicide is exposed to form a source/drain contact hole, and a filling metal material is deposited in the source/drain contact hole to form a source/drain contact plug.
  • a double-layer composite sidewall and a helium-containing etching gas are used for two-step etching to reduce damage to the substrate while reducing process complexity, and optimization Threshold voltage, effective EoT reduction, improved gate control capability, and drive current.

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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

本发明提供一种半导体器件制造方法，包括，在衬底（1）上形成栅极堆叠结构；在衬底（1）以及栅极堆叠结构上依次沉积第一介质材料层（4）和第二介质材料层（5）；采用含氦的刻蚀气体，依次刻蚀第二介质材料层（5）和第一介质材料层（4），分别形成第二侧墙（5A）和第一侧墙（4A）。依照本发明的半导体器件制造方法，采用了双层复合侧墙以及含氦气的刻蚀气体进行两步刻蚀，降低对衬底（1）的损伤的同时还降低了工艺复杂性，此外还能优化阈值电压、有效降低EoT、提高栅控制能力以及驱动电流。

Description

半导体器件制造方法
本申请要求了 2012年 7月 3 日提交的、 申请号为 201210229524.9、 发明名称为
"半导体器件制造方法"的中国专利申请的优先权， 其全部内容通过引用结合在本申 请中。 技术领域
本发明涉及半导体集成电路制造领域， 更具体地， 涉及一种侧墙刻蚀方法。 背景技术
在超大规模集成电路制造中， 在轻掺杂漏 (LDD)注入工艺之前需要制作介质侧墙 ( spacer), 防止更大剂量的源漏注入过于接近沟道而导致源漏穿通， 从而造成器件失 效及良率降低。
当前应用于主流 65nm甚至 45nm侧墙制作工艺为：在轻掺杂漏 (LDD)注入工艺之 前,首先沉积或热生长一层二氧化硅薄膜， 如采用快速热氧化法（RTO)生长 30A左右 的二氧化硅， 作为随后的刻蚀阻挡层， 以保护衬底特别是源漏区靠近沟道区的界面处 不受损伤， 以避免缺陷密度增大； 再沉积一层良好共形性的氮化硅薄膜， 包围在多晶 硅栅极周围。 最后， 采用等离子体刻蚀去掉衬底上及栅极上的氮化硅薄膜， 停止在下 面的氧化层上， 形成侧墙。
另一方面， 依据摩尔定律， 随着器件关键尺寸的持续微缩， 传统的栅氧 /多晶硅栅 结构越来越无法满足先进逻辑器件的要求， 逐渐为高 K-金属栅结构所取代。 并且， 由 于后栅工艺可以控制热效应及对阀值电压的良好控制， 逐渐成为主流工艺， 引出了许 多新的工艺难点及挑战。栅的高度要降低， 以满足 CMOS制造技术带来的金属栅填充 的挑战。 为使金属填充完全， 需要降低栅条的深宽比。而且， 由于栅间距的逐渐缩小， 都使得第一道侧墙的厚度要持续降低。 为了精确控制刻蚀工艺的重复性、 可靠性及稳 定性， 必须降低刻蚀速率以满足刻蚀工艺日益增加的挑战， 这往往使得侧墙刻蚀速率 的均匀性变差。 特别地， 当前的侧墙刻蚀技术一般基于 Ar基气体， 在纳米级器件条 件下， 易于造成对衬底的损伤， 尤其当栅极上的氧化硅衬层极薄的情况下， 氧等离子 体易于穿透薄氧化层而与衬底反应， 造成大的硅损失值。 发明内容
有鉴于此， 本发明的目的在于提供一种创新性的侧墙刻蚀方法， 避免损伤衬底的 同时还能有效降低 EoT、 提高栅控能力以及驱动电流。
实现本发明的上述目的， 是通过提供一种半导体器件制造方法， 包括： 在衬底上 形成栅极堆叠结构； 在衬底以及栅极堆叠结构上依次沉积第一介质材料层和第二介质 材料层； 采用含氦的刻蚀气体， 依次刻蚀第二介质材料层和第一介质材料层， 分别形 成第二侧墙和第一侧墙。
其中， 刻蚀第二介质材料层和第一介质材料层的步骤进一步包括： 执行主刻蚀， 刻蚀第二介质材料层形成第二侧墙， 并在第一介质材料层上留有第二介质材料层的残 留； 执行过刻蚀， 去除第二介质材料层的残留； 执行腐蚀， 去除衬底上暴露的第一介 质材料层。
其中， 栅极堆叠结构包括栅绝缘层和栅电极层， 栅电极层包括多晶硅、 非晶硅、 金属栅， 栅绝缘层包括二氧化硅、 氮氧化硅、 高 K材料。
其中， 第一介质材料层包括二氧化硅， 采用选自 RTO、 PECVD, SACVD的方法 沉积形成。
其中，第二介质材料层包括氮化硅、类金刚石无定形碳，采用 LPCVD或者 PECVD 的方法沉积形成。
其中， 刻蚀气体包括氟基气体、 氧化性气体以及氦基气体。
其中， 在主刻蚀过程中， 调节电极功率、 腔体压力和反应气体流量比例， 增强各 向异性， 形成陡直的侧墙。
其中， 在过刻蚀过程中， 调节极功率、 腔体压力和反应气体流量比例， 获得介质 材料层对衬底的高选择比。
其中， 选择比大于 10: 1。
其中， 氟基气体包括碳氟基气体、 F3。
其中， 主刻蚀的氟基气体包括 CF4、 CHF3、 CH2F2。
其中， 过刻蚀的氟基气体包括 CF4、 CH3F、 CH2F2。
其中， 氧化性气体包括 02。
其中， 氦基气体包括氦气、 氦气与氩气的混合物。
其中， 在主刻蚀过程中， 通过反应物以及生成物的谱线变化， 自动触发终点检测 系统， 结束主刻蚀而进入过刻蚀， 将晶片全部区域的介质层刻蚀干净。
其中， 在主刻蚀过程中， 通过刻蚀速率计算所需的刻蚀时间直到接近衬底表面， 结束主刻蚀而进入过刻蚀， 将晶片全部区域的介质层刻蚀干净。
其中， 主刻蚀和 /或过刻蚀采用基于 CCP或者 ICP模式的刻蚀设备。
其中， 采用 HF基腐蚀液湿法刻蚀第一介质材料层。
进一步包括： 以第二侧墙与第一侧墙为掩模， 在两侧离子注入形成源漏区； 去除 伪栅极堆叠结构， 形成栅极沟槽； 在栅极沟槽中填充高 K材料的栅极绝缘层以及金属 材料的栅极导电层， 形成高 K-金属栅极结构。
依照本发明的半导体器件制造方法， 采用了双层复合侧墙以及含氦气的刻蚀气体 进行两步刻蚀， 降低对衬底的损伤的同时还降低了工艺复杂性， 此外还能优化阀值电 压、 有效降低 EoT、 提高栅控能力以及驱动电流。 附图说明
以下参照附图来详细说明本发明的技术方案， 其中：
图 1至图 5为依照本发明的半导体器件制造方法各步骤的剖面示意图； 以及 图 6为依照本发明的半导体器件制造方法的流程图。 具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技 术效果。 需要指出的是， 类似的附图标记表示类似的结构， 本申请中所用的术语 "第 一"、 "第二"、 "上"、 "下"、 "厚"、 "薄"等等可用于修饰各种器件结构。 这些修饰除 非特别说明并非暗示所修饰器件结构的空间、 次序或层级关系。
参照图 6以及图 1， 在 S601 , 在衬底上形成栅极堆叠结构， 其可以是前栅工艺的栅 极堆叠， 也可以是后栅工艺的伪栅极堆叠。 提供衬底 1， 其可以是体 Si、 SOI、 体 Ge、 GeOI 、 SiGe、 GeSb, 也可以是 III- V族或者 II- VI族化合物半导体衬底， 例如 GaAs、 GaN、 InP、 InSb等等。 为了与现有的 CMOS工艺兼容以应用于大规模数字集成电路制 造， 衬底 1优选地为体 Si或者 SOI。 在衬底 1上通过 LPCVD、 PECVD、 热氧化、 RTO等 沉积方法形成较薄的栅绝缘层 （栅氧化层） 2， 例如为薄 Si02层， 其厚度例如 l-5nm， 用于在稍后的后栅工艺去除假栅极时保护衬底。 或者可选地， 栅绝缘层 2是用于后栅 工艺的高 K材料。 在栅氧化层 2上通过 LPCVD、 扩散炉管等方法沉积栅电极层 （假栅 极层） 3， 其材质例如为多晶硅、 非晶硅。 随后采用光刻 /刻蚀工艺图形化假栅极层 3
(优选地以及栅氧化层 2)，形成假栅极堆叠结构。刻蚀工艺可以包括等离子体刻蚀（采 用 Ar等惰性离子）、 反应离子刻蚀 （RIE， 采用氟基气体）、 或者各向异性的湿法腐蚀 (例如 TMAH腐蚀液刻蚀 Si材质、 HF基腐蚀液刻蚀 SiO材质）， 刻蚀停止点可以在栅氧 化层 2与栅电极层 （假栅极层） 3的界面处， 也可以稍微过刻蚀直至暴露衬底 1。 栅极 堆叠 2/3的布图不限于图 1所示的单个线条， 而是可以依照版图设计需要为多个平行或 者局部相交的线条， 具体地对应于以后将要形成的 MOSFET的栅极位置处。 栅极堆叠 结构的侧面基本是陡直的， 也即栅极堆叠结构与衬底之间的夹角基本等于 90度 （例如 在 90度 ±2.5度范围内）。
参照图 6以及图 2， 在 S602, 在栅极堆叠结构上沉积介质材料。 如果图 1中未刻蚀 栅氧化层 2， 则优选地先采用 HF基湿法腐蚀去除栅极堆叠之外的栅氧化层 2。然后依次 在整个衬底（晶片）上形成均匀厚度的第一介质材料 4与第二介质材料 5。采用（快速) 热氧化（RTO)、 PECVD、常压 CVD ( SACVD)、 HDPCVD等方法形成第一介质材料 4， 可以是二氧化硅， 用作后续蚀刻阻挡层。 第一介质材料 4足够薄以良好控制侧墙最终 形态， 优选地其厚度为 l-3nm。 采用 LPCVD、 PECVD等常规沉积方法， 形成第二介质 材料 5， 其可以是氮化硅、 类金刚石无定形碳 （DLC) 等材质较硬且与之前沉积的各 个材料具有较高刻蚀选择比的材质， 除了用作栅极侧壁绝缘隔离之外还可以进一步为 沟道区提供应力以增强器件驱动能力。优选地， 通过 PECVD沉积氮化硅薄膜。第二介 质材料 5的厚度例如为 50-70nm。 第一介质材料 4的层以及第二介质材料 5的层如图 2所 示与栅极堆叠结构共型。
参照图 6以及图 3， 在 S603 , 执行主刻蚀， 各向异性刻蚀第二介质材料 5， 停止在 第一介质材料 4上， 得到第二侧墙 5A。 例如采用等离子体刻蚀系统、 基于 CCP或者 ICP 模式的刻蚀设备， 调整电极的功率、 腔体的压力和反应气体的流量比例， 增强各向异 性刻蚀， 使得栅极堆叠结构顶部的第二介质材料 5完全被去除、 栅极堆叠结构侧壁的 第二介质材料 5基本保留而构成第二侧墙 5A、而有源区中衬底表面上（第一介质材料 4) 仅留下少量的介质材料的残余 5B， 也即刻蚀第二介质材料 5直至暴露第一介质材料 4。 刻蚀气体主要包括氟基气体， 例如碳氟基气体， 此外还可以使用 F3、 SF6等。 为了实 现陡直的刻蚀形貌， 需要优化碳氟基气体的自由基及离子比例， 并且需要调节聚合物 量。 本发明碳氟基气体可以包括 CF4、 CHF3、 CH3F、 CH2F2。 优选地， 结合氧化性气 体 02、 CO去除聚合物量。在实施例中，主刻蚀的刻蚀气体为 CF4与 CHF3、或 CF4与 CH2F2 或者仅采用 CHF3， 氧化气体为 02 。
此外， 为了精确控制刻蚀工艺的重复性、 可靠性及稳定性， 必须降低刻蚀速率。 现有技术往往添加 Ar作为稀释剂来降低刻蚀速率。 然而由于氩气原子量大， 动量大， 对衬底的轰击明显。 对于纳米级器件来讲， 较易造成对下层材料的损伤， 尤其当多晶 硅栅极上的氧化硅衬层极薄的情况下， 氧等离子体易于穿透薄氧化层而与衬底反应， 造成大的硅损失值。 因此， 本发明的刻蚀气体成分中除了主要的氟基气体（和 /或氧化 性气体）之外， 还引入了氦基气体， 例如氦气、 氦气 /氩气混合物， 可以明显降低对衬 底的损伤。 另外， 由于氦气原子量小， 碰撞截面小， 因此单纯的氦气较难获得稳定的 等子体， 可用优选地采用氦气与氩气结合， 使得易于在腔体内形成分散更均匀的等离 子体， 提升刻蚀均匀性， 也即氦基气体优选地为氦气与氩气的混合物。
当刻蚀到下面的硅衬底 1表面时， 通过反应物及生成物的谱线变化， 自动触发终 点检测系统， 停止主刻蚀步骤， 然后迅速转变到下一步骤的过刻蚀。 此外， 还可以通 过刻蚀速率计算所需的刻蚀时间直到接近半导致硅衬底表面， 以实现无墙脚（footing) 的陡直形貌， 然后进入下一步过刻蚀。第二侧墙 5A的宽度基本等于第二原始介质材料 5的厚度， 或者减小的比例不大于 10 %， 宽度具体地可以为 50-70nm; 而第二介质材料 5留在衬底 1表面的残余 5B的厚度远小于原始第二介质材料 5的厚度， 例如小于原厚度 的 20 %， 具体可以为 10-15nm。 第二侧墙 5A基本是陡直的， 也即第二侧墙 5A与衬底 1 的夹角优选为 90度。 特别地， 在第二侧墙 5A与衬底 1交接处， 由于刻蚀停止条件的选 择， 拐角处可以基本或者完全没有介质材料 5残余， 也即此处局部的介质材料厚度可 以为 0。
参照图 6以及图 4， 在 S604, 执行过刻蚀， 去除残余的第二介质材料。 在主刻蚀获 得陡直第二侧墙 5A形貌的基础上， 需要去除整个晶片上残余的第二介质材料薄膜 5B。 由于第二介质材料 5薄膜沉积的厚度在整个晶片上有差异， 需要增加一定比例的过刻 蚀。 为了降低对衬底硅的损伤， 必然要求介质材料 5对第一介质材料 4的氧化硅以及衬 底 1的硅具有高的选择比， 从而提升器件性能。例如采用等离子体刻蚀系统、基于 CCP 或者 ICP模式的刻蚀设备。 第二介质材料 5 (例如氮化硅） 对第一介质材料 4以及衬底 硅选择比的获得， 主要依赖于反应气体的流量及其比例。 与图 3所示的主刻蚀类似， 图 4所示的过刻蚀主要采用氟基气体 （与图 3所示步骤相同， 采用氟代烃， 优选地包括 CF4、 CH3F、 CH2F2) 并结合氧化性气体 （与前述相同， 优选 02) 以及氦基气体 （作 为稀释剂）， 通过调节电极的功率、 腔体的压力和反应气体的流量比例， 以获得 10: 1 以上的高选择比 （优选地在 15: 1以上）， 从而实现对半导体衬底有较小的损伤 。 在一 个实施例中， 过刻蚀的刻蚀气体为 CF4与 CH3F、 或 CF4与 CH2F2或者仅采用 CH3F， 氧化 气体为 02。根据负载状况可以增加一定程度的过刻蚀， 如 10 %-30 %。此时， 第二介质 材料 5仅剩余第二侧墙 5A部分， 而第一介质材料 4完整保留， 第一介质材料 4在伪栅极 堆叠结构侧面的部分被第二侧墙 5A覆盖， 而其余部分暴露在衬底 1上。
由于刻蚀设备制造厂商众多， 其腔体设计亦有所不同， 但基于的原理是一样的。 这里， 以 LAM Exelan Hpt机台为基础， 上述主刻蚀与过刻蚀推荐的工艺参数如下表 1 所示：
表 1
Figure imgf000008_0001
其中 HF、 LF分别代表高频和低频功率。 表 1中仅给出了几种具体的刻蚀气体以及 参数， 但是也可以选用本说明书以上列出的其他气体并合理调整参数范围， 只要能使 得过刻蚀步骤中获得足够高的选择比 （例如 15: 1以上）。
参照图 6以及图 5， 在 S605 , 刻蚀去除衬底 1表面暴露的第一介质材料 4， 形成第一 侧墙 4A， 第一侧墙 4A与第二侧墙 5A—同构成双层复合侧墙结构。 对于氧化硅材质的 第一介质材料 4而言， 可以采用 HF基湿法刻蚀液， 例如 5-10 %的 HF稀释液（DHF)、 或 者缓释刻蚀液 （BOE， HF与 H4F的混合溶液）， 工作温度例如 25摄氏度， 腐蚀时间依 照厚度选定。 腐蚀完成之后， 在栅极堆叠结构两侧留下第一侧墙 4A与第二侧墙 5A， 一同构成双层复合侧墙结构。
由此， 最终形成了双层复合侧墙结构。 之后可以参照后栅工艺， 以双层复合侧墙 结构为掩模进行源漏离子注入掺杂形成源漏区，在源漏区上 /中形成金属硅化物以降低 源漏电阻， 在整个晶片上沉积层间介质层， 干法刻蚀或者腐蚀去除伪栅极堆叠形成栅 极沟槽， 在栅极沟槽中依次沉积高 K材料的栅极绝缘层、 以及金属材质的栅极导电层， 刻蚀层间介质层直至暴露源漏区和 /或金属硅化物形成源漏接触孔，在源漏接触孔中沉 积填充金属材料形成源漏接触塞。
依照本发明的侧墙刻蚀方法， 采用了双层复合侧墙以及含氦气的刻蚀气体进行两 步刻蚀， 降低对衬底的损伤的同时还降低了工艺复杂性， 此外还能优化阀值电压、 有 效降低 EoT、 提高栅控能力以及驱动电流。
尽管已参照一个或多个示例性实施例说明本发明， 本领域技术人员可以知晓无需 脱离本发明范围而对形成器件结构的方法做出各种合适的改变和等价方式。 此外， 由 所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。 因 此， 本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实 施例， 而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims

权 利 要 求
1 . 一种半导体器件制造方法， 包括：
在衬底上形成栅极堆叠结构；
在衬底以及栅极堆叠结构上依次沉积第一介质材料层和第二介质材料层； 采用含氦的刻蚀气体， 依次刻蚀第二介质材料层和第一介质材料层， 分别形成第 二侧墙和第一侧墙。
2. 如权利要求 1 的半导体器件制造方法， 其中， 刻蚀第二介质材料层和第一介 质材料层的步骤进一步包括：
执行主刻蚀， 刻蚀第二介质材料层形成第二侧墙， 并在第一介质材料层上留有第 二介质材料层的残留；
执行过刻蚀， 去除第二介质材料层的残留；
执行腐蚀， 去除衬底上暴露的第一介质材料层。
3. 如权利要求 1的半导体器件制造方法， 其中， 栅极堆叠结构包括栅绝缘层 和栅电极层， 栅电极层包括多晶硅、 非晶硅、 金属栅， 栅绝缘层包括二氧化硅、 氮氧 化硅、 高 K材料。
4. 如权利要求 1的半导体器件制造方法， 其中， 第一介质材料层包括二氧化 硅， 采用选自 RTO、 PECVD、 SACVD的方法沉积形成。
5. 如权利要求 1的半导体器件制造方法，其中，第二介质材料层包括氮化硅、 类金刚石无定形碳， 采用 LPCVD或者 PECVD的方法沉积形成。
6. 如权利要求 1的半导体器件制造方法， 其中， 刻蚀气体包括氟基气体、 氧 化性气体以及氦基气体。
7. 如权利要求 6的半导体器件制造方法， 其中， 在主刻蚀过程中， 调节电极 功率、 腔体压力和反应气体流量比例， 增强各向异性， 形成陡直的侧墙。
8. 如权利要求 6的半导体器件制造方法， 其中， 在过刻蚀过程中， 调节极功 率、 腔体压力和反应气体流量比例， 获得介质材料层对衬底的高选择比。
9. 如权利要求 8的半导体器件制造方法， 其中， 选择比大于 10: 1。
10. 如权利要求 6的半导体器件制造方法， 其中， 氟基气体包括碳氟基气体、 F3。
11 . 如权利要求 10的半导体器件制造方法，其中，主刻蚀的氟基气体包括 CF4、 CHF3、 CH2F2。
12. 如权利要求 10的半导体器件制造方法，其中，过刻蚀的氟基气体包括 CF4、 CH3F、 CH2F2。
13. 如权利要求 6的半导体器件制造方法， 其中， 氧化性气体包括 02。
14. 如权利要求 6的半导体器件制造方法， 其中， 氦基气体包括氦气、 氦气与 氩气的混合物。
15. 如权利要求 2的半导体器件制造方法， 其中， 在主刻蚀过程中， 通过反应 物以及生成物的谱线变化， 自动触发终点检测系统， 结束主刻蚀而进入过刻蚀， 将晶 片全部区域的介质层刻蚀干净。
16. 如权利要求 2的半导体器件制造方法， 其中， 在主刻蚀过程中， 通过刻蚀 速率计算所需的刻蚀时间直到接近衬底表面， 结束主刻蚀而进入过刻蚀， 将晶片全部 区域的介质层刻蚀干净。
17. 如权利要求 2 的半导体器件制造方法， 其中， 主刻蚀和 /或过刻蚀采用基 于 CCP或者 ICP模式的刻蚀设备。
18. 如权利要求 2的半导体器件制造方法， 其中， 采用 HF基腐蚀液湿法刻蚀 第一介质材料层。
19. 如权利要求 1的半导体器件制造方法， 进一步包括：
以第二侧墙与第一侧墙为掩模， 在两侧离子注入形成源漏区；
去除伪栅极堆叠结构， 形成栅极沟槽；
在栅极沟槽中填充高 κ材料的栅极绝缘层以及金属材料的栅极导电层， 形成高 K-金属栅极结构。
PCT/CN2012/081009 2012-07-03 2012-09-05 半导体器件制造方法 Ceased WO2014005371A1 (zh)

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