WO2020048524A1 - 一种半导体结构的形成方法 - Google Patents

一种半导体结构的形成方法 Download PDF

Info

Publication number
WO2020048524A1
WO2020048524A1 PCT/CN2019/104666 CN2019104666W WO2020048524A1 WO 2020048524 A1 WO2020048524 A1 WO 2020048524A1 CN 2019104666 W CN2019104666 W CN 2019104666W WO 2020048524 A1 WO2020048524 A1 WO 2020048524A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
fin
etching
forming
hard mask
Prior art date
Application number
PCT/CN2019/104666
Other languages
English (en)
French (fr)
Inventor
王伟军
林宏
Original Assignee
上海集成电路研发中心有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 上海集成电路研发中心有限公司 filed Critical 上海集成电路研发中心有限公司
Priority to US17/284,849 priority Critical patent/US20220059402A1/en
Publication of WO2020048524A1 publication Critical patent/WO2020048524A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon

Definitions

  • the invention relates to the technical field of semiconductor integrated circuit manufacturing processes, and in particular, to a method for forming a semiconductor structure having a fin structure and an isolation structure.
  • the CMOS manufacturing process began to transition from planar transistors to three-dimensional FinFET device structures. Compared with planar transistors, FinFET devices improve channel control and reduce short-channel effects. In addition, the gate of the planar transistor is above the channel, and the gate of FinFET usually surrounds the channel from three sides, so that the channel can be electrostatically controlled on both sides. The changes in the device structure mentioned above have brought great challenges to the CMOS manufacturing process. At 22nm process nodes, the aspect ratio of the fin structure is usually greater than 3. For bulk silicon FinFET devices, the higher fin structure etches the corresponding fin structure, etches the grooves of the isolation structure, and Shape control becomes more difficult.
  • the mainstream FinFET process flow can be divided into SOI substrate process flow or bulk silicon substrate process flow according to the substrate type. Because the oxide buried layer of the SOI substrate can control the height of the fin structure and achieve electrical isolation between the fins, the process flow is relatively simple. However, due to the consideration of device cost and other factors, the process flow based on bulk silicon substrates has also received increasing attention. For bulk silicon substrate process development, because there is no intrinsic isolation layer, there is no clear interface at the bottom of the fin structure, and it is more difficult to control the consistency of height and width.
  • the morphology control of the fin structure is also one of the technical difficulties.
  • the data simulation results show that the fin structure remains close to the vertical state, which helps to improve and optimize the relevant electrical performance of the device (such as significantly increasing the switching current ratio).
  • the isolation structure usually requires a certain slope in the sidewall of the active region, which helps to fill the dielectric material and facilitate ion implantation at the bottom of the fin structure to achieve device isolation.
  • the fin structure and the active area structure are formed by a single patterning process. The overall morphology and the slope of the sidewall are generally consistent, and it is difficult to form the ideal fin structure and active area structure morphology respectively. .
  • a Chinese invention patent application with a publication number of CN1581431A, "Multi-Structured Silicon Fins and Manufacturing Method” discloses a fin structure with different top and bottom regions having different morphologies.
  • the application had the following problems:
  • the method of the above application still has considerable difficulty in realizing the ideal morphology of the fin structure and the structure of the active region in the actual process.
  • An object of the present invention is to overcome the above defects in the prior art and provide a method for forming a semiconductor structure having a fin structure and an isolation structure.
  • a method for forming a semiconductor structure including the following steps:
  • the photolithographic pattern is used as a mask to pattern the hard mask layer and the semiconductor substrate below it to obtain a hard mask layer pattern and a semiconductor substrate with a fin structure; the fin structure has a steep Morphology of straight sidewalls;
  • Groove etching is performed on the dielectric layer to form a fin structure and an isolation structure with inclined sidewalls.
  • the modification treatment is thermal oxidation, so that the thickness of the material of the semiconductor substrate consumed by the thermal oxidation corresponds to the thickness of the protective layer, and the protective layer and the modified treatment layer are wet-etched. Perform simultaneous removal.
  • an atomic layer etching method is used to pattern the hard mask layer and the semiconductor substrate to obtain the fin structure having a steep side wall morphology.
  • the process gas flow, the pressure of the etching chamber, and the time of different process steps are controlled to control the etching amount of each cycle of the atomic layer etching to be 0.5 to 5 nm, thereby accurately Control the line width and height of the fin structure.
  • the protective layer includes SiO 2 or SiN, or a combination of film layers of SiO 2 and SiN.
  • a conformal deposition method is used to form a protective layer on a sidewall surface of the fin structure.
  • the conformal deposition method includes an ALD, PEALD or thermal oxidation deposition process.
  • the hard mask layer includes SiN, SiON, SiC, or SiO 2 , or a combination of at least two of SiN, SiON, SiC, and SiO 2 .
  • the isolation structure groove is formed by dry etching.
  • the combination of etching gases used for the etching is: HBr, He and O 2 , etching gas flow is: HBr 180 ⁇ 220sccm, He 350 ⁇ 450sccm, O 2 4 ⁇ 6sccm; etching chamber pressure is 70 ⁇ 90mtorr; source power range is 800 ⁇ 1200W to improve Si / SiO 2 Etch selection ratio.
  • the isolation structure groove is formed by a wet etching or dry release process, and the specific crystal orientation of the Si substrate is used to achieve alignment.
  • Anisotropic etching of a Si substrate forms the isolation structure with a specific slope sidewall.
  • the remaining hard mask layer is used as a protective mask to etch the dielectric layer around the fin structure, and the fin structure with steep and straight sidewalls and The morphology of the isolation structure with inclined sidewalls below is different.
  • the end point detection method is used to control the etching depth.
  • the advantage of the present invention is that the method of the present invention adjusts the process flow to form a fin structure and a device isolation structure in steps, so the physical morphology of the sidewalls of both the fin structure and the isolation structure can be adjusted and used.
  • Advanced process control improves process accuracy, uniformity and stability, breaks through the existing technical difficulties, and can more accurately control the uniformity and consistency of the physical morphology of the fin structure and the isolation structure, thereby helping to improve the field effect tube The electrical performance and reliability of the device.
  • FIG. 1 is a schematic process flow diagram of a method for forming a semiconductor structure according to the present invention.
  • FIG. 2 to FIG. 8 are schematic structural diagrams of steps in forming a semiconductor structure according to the method of FIG. 1 in a preferred embodiment of the present invention.
  • the core idea of the method for forming a semiconductor structure provided by the present invention is to use an advanced process control to form a fin channel structure (fin) and a device isolation structure in steps, and thereby independently adjust the physical morphology of the two to improve Process accuracy, uniformity, and stability.
  • the process results help to improve the related electrical performance of the FET device (such as the switching current ratio I on / I off ).
  • the method for forming a semiconductor structure for forming a fin-shaped structure and an isolation structure provided by the present invention is mainly applicable to the formation process of source and drain and channel physical structures of semiconductor process technologies below 20 nm. Use for reference.
  • the following specific embodiments take the formation process of a fin structure (fin) of a FinFET device on a bulk silicon substrate with a 20 nm technology as an example.
  • fin and the isolation structure In order to obtain better device electrical performance and process convenience considerations (such as a larger switching current ratio I on / I off , good electrical isolation between devices), there are certain morphological requirements for fin and the isolation structure below it.
  • the drain and channel regions (fin structures) need to be relatively steep, while the isolation structures need to have a certain slope for dielectric filling.
  • a method for forming a semiconductor structure according to the present invention includes the following steps:
  • Step S010 Provide a semiconductor substrate, and form a hard mask layer on the semiconductor substrate.
  • the semiconductor substrate 100 may be a silicon substrate, or a substrate formed of other suitable semiconductor materials. According to design requirements, the substrate 100 may be a P-type substrate or an N-type substrate, and has a doped region therein. For this embodiment, the substrate material is uniform, and there is no intrinsic isolation layer in the middle, and a bulk silicon substrate is preferred here.
  • the hard mask layer 120 includes SiN, SiON, SiC, SiO 2 or a combination of the above-mentioned film layers, and can be used, for example, by plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and plasma enhanced ALD. (PEALD), thermal oxidation and other suitable deposition processes.
  • PECVD plasma enhanced chemical vapor deposition
  • ALD atomic layer deposition
  • PEALD plasma enhanced ALD.
  • thermal oxidation thermal oxidation and other suitable deposition processes.
  • the hard mask layer 120 is preferably SiON, and is formed by a PECVD method.
  • the thickness of the hard mask layer 120 may be 5 to 15 nm, and preferably 10 nm.
  • Step S020 forming a lithographic pattern of a fin structure on the hard mask layer.
  • the lithographic pattern used to form the fin structure may be a photoresist (PR) pattern formed using electron beam lithography, or a lithographic pattern formed using a sacrificial layer spacer (that is, self-aligned dual imaging) Technology Self-aligned Double Patterning (SADP).
  • PR photoresist
  • SADP technology Self-aligned Double Patterning
  • a photoresist is used as the photolithographic pattern 150, and its thickness is 80 to 150 nm, preferably 100 nm.
  • the line width of the fin structure pattern to be formed is 5 to 60 nm, preferably 8 nm; the fin interval is 8 to 60 nm, preferably 10 nm.
  • the lithographic pattern 150 has a size and a pitch corresponding thereto.
  • FIG. 1 is a simplified illustration to illustrate the core idea of the present invention. Only two fin lithographic patterns 150 are shown.
  • Step S030 Use the photolithographic pattern as a mask to pattern the hard mask layer and the semiconductor substrate below it to obtain a hard mask layer pattern and a semiconductor substrate with a fin structure; the fin structure has a steep straight Topography.
  • the fin lithography pattern 150 is used to etch the hard mask layer 120 and the substrate 100 to achieve patterning, and a hard mask layer pattern 120 'and a substrate 100' with a fin structure 155 are obtained.
  • the substrate etching depth is 30 to 35 nm, and preferably 32 nm.
  • the film layers involved in this etching process are: hard mask layer SiON 10nm, Si 32nm.
  • this etch uses the newer atomic layer etching (ALE) technology, which can improve the accuracy of etching to the order of a single atomic layer by accurately controlling the flow of reactive gas and the pulsed input power.
  • ALE newer atomic layer etching
  • Etching rate is low.
  • the yield is in an acceptable range because the etching depth is small, only 40-50 nm.
  • ALE single cycle can be divided into 3 steps:
  • the corresponding process parameters can be:
  • the removed gas is Ar, N 2 , He or a combination thereof.
  • Ar is preferred, and the flow rate is 300 to 400 sccm, preferably 350 sccm. 100 to 1500W, preferably 800W, and a bias power range of 0 to 500W, preferably 300W.
  • the above process conditions can etch 0.5 ⁇ 5nm Si per cycle.
  • the process gas flow rate and the pressure of the etching chamber are controlled, and the single-cycle etching amount is about 1nm by adjusting the time of each step.
  • the ALE process can be used to precisely control the line width and height of each fin structure, so that the difference in line width and height (etching depth) of each fin are less than 1 nm, and a fairly steep morphology is obtained through anisotropy, so that The fin structure maintains good morphological consistency, and also eliminates the effect of the high aspect ratio of the structure on the etching effect.
  • Step S040 forming a protective layer on the surface of the sidewall of the fin structure.
  • a protective layer 160 needs to be formed on the fin sidewall.
  • the sidewall protection layer 160 includes SiO 2 or SiN or a combination of film layers, and a formation method thereof may be a suitable deposition process such as ALD, PEALD, and thermal oxidation.
  • This process requires conformal deposition of the protective layer 160, and the thickness of the film layer is thin and needs to be precisely controlled to make it uniform.
  • the sidewall protection layer is SiO 2 and is formed by an ALD method; the film thickness is 1 to 3 nm, and preferably 1.5 nm.
  • the protective layer 160 covers the top surface of the fin structure 155 (ie, the upper surface of the hard mask layer pattern 120 ') and the sidewall surface (including the hard mask layer pattern 120' side wall surface) and the substrate between the fin structure 155 intervals 100 'on the surface.
  • This process uses ALD to form a sidewall protection layer, so its film thickness can be very thin, for example, it can be less than 5nm, without having to form a sidewall spacer structure like in the prior art. Therefore, the problem of obvious horizontal steps can be avoided in the subsequent structure formed, so that the morphology of the fin structure can be controlled more accurately.
  • Step S050 Use the fin structure as a mask to etch the semiconductor substrate underneath to form an isolation structure groove.
  • This step is used to etch the structure of the isolation portion.
  • the structure needs to maintain a certain slope (slope) in order to facilitate the subsequent filling of the medium and ion implantation, and its slope is 82 ° to 86 °.
  • the formed fin structure can be used as a mask to etch the underlying substrate to form an isolation structure groove 170, so as to obtain a substrate 100 with a fin155 and an isolation structure groove 170 ".
  • the depth of the isolation structure is highly related to fin, which is preferably 50 nm in this embodiment.
  • the Si / SiO 2 etching selection ratio can reach or approach 100, and thus, the sidewall protection layer 160 can well protect the formed fin structure from the influence of the process.
  • the protective layer of the space between the fins can be etched first by using an atomic layer etching technique, or a breakdown process can be added before the main etching process to form an etching window on the space between the fins.
  • etching gas used for the subsequent main etching is HBr / He / O 2
  • the process conditions can be: HBr 180-220 sccm, preferably 200 sccm; He 350-450 sccm, preferably 400 sccm; O 2 4-6 sccm, preferably It is 5 sccm; the chamber pressure is 70-90mtorr, preferably 80mtorr; the source power range is 800-1200W, preferably 1000W.
  • the Si / SiO 2 etching selection ratio of the above etching process conditions can reach 100.
  • the loss of the side wall protective layer of the fin structure will be less than 1 nm, so the fin structure will be effectively protected.
  • the thickness of the SiN protective layer is 1 to 3 nm, and preferably 1.5 nm.
  • an isolation structure interface with a slope of 54.7 ° can be obtained as a mask along the ⁇ 110> crystal direction.
  • the fin sidewall protection layer can also protect the fin structure from being affected during this etching stage. This layer and the remaining hard mask layer can be removed simultaneously using wet etching.
  • This process introduces advanced Atomic Layer Etching (ALE) technology and gives process examples to help improve the etching depth and line width uniformity of the isolation pattern structure, and improve the load effect.
  • ALE Atomic Layer Etching
  • the protective layer of the fin sidewall needs to be removed.
  • the exposed surface of the formed isolation structure groove needs to be modified to form a modified treatment layer with a certain thickness on the exposed surface of the isolation structure groove. Then, the protective layer and the modified treatment layer are simultaneously removed. In this way, the problem of forming a horizontal step at the interface between the lower end of the protective layer and the substrate due to the direct removal of the protective layer on the sidewall of the fin in the prior art can be effectively eliminated, thereby avoiding damage to the topography of fin.
  • the above-mentioned modified treatment layer can be formed by thermally oxidizing the surface of the formed isolation structure groove and consuming a substrate silicon material with a certain thickness on the surface of the isolation structure groove. Then, the protective layer and the thermal oxidation layer are removed simultaneously (synchronously) by wet etching. This can not only eliminate the platform formed in the previous etching step, but also remove the etching damage layer on the surface of the groove of the isolation structure.
  • the control of the above-mentioned thermal oxidation process is to make the thickness of the silicon layer consumed by the thermal oxidation correspond to the thickness of the side wall protection layer to achieve at least a substantially consistent state.
  • Step S060 filling a dielectric layer in the isolation structure groove until the fin structure is covered.
  • This deposition process step requires that the dielectric layer 180 can fill very deep trenches with a large aspect ratio without generating holes and other defects.
  • the filled dielectric layer 180 may be SiO 2 through a suitable deposition process such as plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPCVD), ALD, flowable chemical vapor deposition (FCVD), or the like. Combination formed.
  • PECVD plasma enhanced chemical vapor deposition
  • HDPCVD high density plasma chemical vapor deposition
  • ALD flowable chemical vapor deposition
  • FCVD flowable chemical vapor deposition
  • the dielectric layer fills the groove 170 and covers the top surface of the fin structure 155 (that is, the surface of the hard mask layer pattern 120 '), and the thickness of the surface layer above the top of the fin structure is 10-20 nm. Is preferably 15 nm.
  • Step S070 planarize the dielectric layer until the hard mask layer on the top of the fin structure is exposed.
  • the filled dielectric layer film has certain undulations, a planarization process is required.
  • the implementation methods thereof include methods such as chemical mechanical polishing (CMP) and film layer etchback.
  • CMP is preferred, and the surface of the dielectric layer is preferably CMP. Grind and polish until the hard mask layer on top of fin is exposed. After the planarization, the remaining hard mask layer pattern 120 "and the planarized filling dielectric layer 180 'are formed.
  • the loss of the hard mask layer can be controlled to 3 to 5 nm.
  • Step S080 groove etching is performed on the dielectric layer to form a fin structure and an isolation structure with inclined sidewalls.
  • This process uses the remaining hard mask layer 120 "as a protective layer (protective mask) to etch the dielectric layer between fin. Since the bulk silicon substrate does not have an obvious etch stop layer, its etching depth mainly depends on At the etching time, for the device structure formed by the above process, due to the difference in the morphology of fin and the isolation structure below, the subtle changes in the spectrum can be detected during the etching process using a highly accurate endpoint detection method (etching The exposure area is gradually reduced), so that the etching process is terminated near the interface between the two, thereby controlling the etching depth.
  • the remaining hard mask layer can be removed by wet etching.
  • the isolation structure 190 between the fin structure 155 and fin has been formed.
  • the fin structure 155 is relatively steep and straight, while the isolation structure 190 has a certain slope, and the remaining dielectric layer 180 "fill height and fin height are well controlled.
  • the line width, height, slope and other morphological parameters between the fin structures Uniform.
  • the method of the present invention utilizes advanced process control to adjust the process flow to form a fin structure and a device isolation structure in steps, and independently adjust the physics of the sidewalls of both the fin structure and the isolation structure.
  • Morphology to improve process accuracy, uniformity and stability, and to break through the difficulties of the existing technology, it can control the uniformity and consistency of the physical morphology of the fin structure and the isolation structure more accurately.
  • the process results help Improve the related electrical performance of the FET device (such as the switching current ratio I on / I off ), improve the reliability of the device and obtain a higher product yield.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种半导体结构的形成方法，包括：在半导体衬底上形成硬掩模层和鳍形结构的光刻图形（S010，S020）；对硬掩模层和半导体衬底进行图形化，获得具有陡直侧壁形貌的鳍形结构（S030）；在鳍形结构的侧壁表面形成保护层（S040）；对鳍形结构下方的半导体衬底进行刻蚀，形成隔离结构凹槽；对隔离结构凹槽的露出表面进行改性处理，形成一定厚度的改性处理层；对保护层及改性处理层进行同时去除（S050）；在隔离结构凹槽内填充介质层及进行平坦化（S060，S070）；对介质层进行凹槽刻蚀，形成鳍形结构和具有倾斜侧壁的隔离结构（S080）。上述方法可分别调节鳍形结构与隔离结构两者侧壁的物理形貌，改善工艺精度、均匀性和稳定性，有助于提升场效应管器件的电学性能及器件的可靠性。

Description

一种半导体结构的形成方法
交叉引用
本申请要求2018年9月7日提交的申请号为CN201811044219.6的中国专利申请的优先权。上述申请的内容以引用方式被包含于此。
技术领域
本发明涉及半导体集成电路制造工艺技术领域，尤其涉及一种具有鳍形结构和隔离结构的半导体结构的形成方法。
技术背景
当半导体工艺发展到22nm技术节点后，CMOS制造工艺开始从平面型晶体管向三维FinFET器件结构过渡。与平面型晶体管相比，FinFET器件改进了对沟道的控制，减小了短沟道效应。此外，平面型晶体管的栅极位于沟道上方，而FinFET的栅极则通常从三面包围沟道，从而可在两侧对沟道进行静电控制。上述器件结构的变革给CMOS制造工艺带来了极大的挑战。在22nm工艺节点，鳍形(Fin)结构的高宽比通常大于3，对于体硅FinFET器件而言，较高的鳍形结构使相应的鳍形结构刻蚀、隔离结构的凹槽刻蚀及形貌控制变得更为困难。
主流的FinFET工艺流程根据衬底类型，可分为SOI基片工艺流程或体硅基片工艺流程。由于SOI基片的氧化埋层可以控制鳍形结构的高度及实现鳍之间的电学隔离，因而工艺流程相对简单。但限于器件成本及其它因素考虑，基于体硅基片的工艺流程也日益受到重视。对于体硅基片工艺开发，由于不存在本征隔离层，鳍形结构的底部不存在清晰界面，其高度与宽度一致 性控制更为困难。
此外，鳍形结构的形貌控制也是工艺难点之一，数据仿真结果表明，鳍形结构保持接近垂直的状态，有助于改善优化器件的相关电学性能(如能明显增大开关电流比)。但与之相反，隔离结构通常需要有源区侧壁保持一定的斜率，这有助于介质材料的填充及便于对鳍形结构底部进行离子注入以实现器件隔离。而在常规工艺流程中，鳍形结构及有源区结构是通过一次图形化工艺形成的，整体形貌及侧壁斜率通常较为一致，难以分别形成理想的鳍形结构及有源区结构形貌。
鉴于上述问题，可以通过调整工艺流程，增加相应工艺步骤以分别形成鳍形结构及隔离结构。
公开号为CN1581431A的中国发明专利申请《多结构的硅鳍形及制造方法》公开了一种上下区域具有不同形貌的鳍形结构。然而，该申请存在以下问题：
(1)其通过形成侧壁隔片(spacer)，保护已形成的第一图形(fin)；但该方式会在侧壁隔片下端的第一图形上形成水平台阶部分，因而对fin的形貌造成一定破坏；
(2)其在第一、第二刻蚀中，采用的是常规干法刻蚀工艺，难以对鳍形结构间的均匀性、负载效应进行精确控制。
因而上述申请的方法在实际工艺中对实现理想的鳍形结构及有源区结构形貌仍存在相当难度。
因此，针对上述鳍形结构的工艺开发，有必要提供一种具备可操作性、工艺均匀性及稳定性较好的新工艺方法。
发明概要
本发明的目的在于克服现有技术存在的上述缺陷，提供一种具有鳍形结构和隔离结构的半导体结构的形成方法。
为实现上述目的，本发明的技术方案如下：
一种半导体结构的形成方法，其特征在于，包括以下步骤：
提供一半导体衬底，在所述半导体衬底上形成硬掩模层；
在所述硬掩模层上形成鳍形结构的光刻图形；
利用所述光刻图形为掩模，对其下方的硬掩模层和半导体衬底进行图形化，获得硬掩模层图形及带有鳍形结构的半导体衬底；所述鳍形结构具有陡直的侧壁形貌；
在所述鳍形结构的侧壁表面形成保护层；
利用所述鳍形结构为掩模，对其下方的半导体衬底进行刻蚀，形成隔离结构凹槽；
对所述隔离结构凹槽的露出表面进行改性处理，形成一定厚度的改性处理层；
对所述保护层及改性处理层进行同时去除；
在所述隔离结构凹槽内填充介质层，直至将所述鳍形结构覆盖；
对所述介质层进行平坦化，直至鳍形结构顶部的硬掩模层暴露；
对所述介质层进行凹槽刻蚀，形成鳍形结构和具有倾斜侧壁的隔离结构。
进一步地，所述改性处理为热氧化，使热氧化消耗的所述半导体衬底的材料厚度与所述保护层的厚度对应，并采用湿法刻蚀对所述保护层及改性处理层进行同时去除。
进一步地，采用原子层刻蚀方法，对所述硬掩模层和半导体衬底进行图形化，以获得具有陡直侧壁形貌的所述鳍形结构。
进一步地，进行原子层刻蚀时，通过对工艺气体流量、刻蚀腔室压强以及不同工艺步骤时间进行控制，以控制使原子层刻蚀每次循环的刻蚀量为0.5～5nm，从而精确控制鳍形结构的线宽和高度。
进一步地，所述保护层包括SiO 2或SiN，或者SiO 2和SiN的膜层组合。
进一步地，采用保形沉积方法，在所述鳍形结构的侧壁表面形成保护层。
进一步地，所述保形沉积方法包括ALD、PEALD或热氧化沉积工艺。
进一步地，所述硬掩模层包括SiN、SiON、SiC或SiO 2，或者SiN、SiON、SiC和SiO 2其中至少两种的膜层组合。
进一步地，当所述保护层材料为SiO 2、半导体衬底材料为Si时，采用干法刻蚀形成所述隔离结构凹槽，通过使刻蚀采用的刻蚀气体组合为：HBr、He和O 2，刻蚀气体流量为：HBr 180～220sccm，He 350～450sccm，O 2 4～6sccm；刻蚀腔室压强为70～90mtorr；源功率范围为800～1200W，以提高Si/SiO 2的刻蚀选择比。
进一步地，当所述保护层材料为SiN、半导体衬底材料为Si时，采用湿法刻蚀或干法释放工艺形成所述隔离结构凹槽，通过利用Si衬底的特定晶向，实现对Si衬底的各向异性刻蚀，形成具有特定斜率侧壁的所述隔离结构。
进一步地，对所述介质层进行凹槽刻蚀时，利用余留的硬掩模层作为保护掩模，刻蚀鳍形结构周围的介质层，并利用具有陡直侧壁的鳍形结构及其下方具有倾斜侧壁的隔离结构两者形貌上的差异，采用终点探测方法控制刻蚀深度。
本发明的优点在于，本发明的方法通过对工艺流程进行调整，以分步形成鳍形结构及器件隔离结构，因而可分别调节鳍形结构与隔离结构两者侧壁的物理形貌，并利用先进的工艺控制改善工艺精度、均匀性和稳定性，突破 了现有技术难点，能够较为精确地控制鳍形结构和隔离结构物理形貌的均匀性、一致性，从而有助于提升场效应管器件的电学性能及器件的可靠性。
附图说明
图1是本发明一种半导体结构的形成方法的工艺流程示意图。
图2-图8是本发明一较佳实施例中根据图1的方法形成半导体结构时的各步骤结构示意图。
发明内容
本发明提供的半导体结构的形成方法的核心思想为利用先进的工艺过程控制分步形成鳍形沟道结构(fin)及器件隔离结构，并藉此独立调节两者的物理形貌，以此改善工艺精度、均匀性、稳定性，其工艺结果有助于提升场效应管器件的相关电学性能(如开关电流比I on/I off)。
本发明提供的用于形成鳍形结构及隔离结构的半导体结构的形成方法，主要适用于20nm以下半导体工艺技术代的源漏及沟道物理结构的形成工艺，对于其他鳍形物理结构的形成也有借鉴意义。
以下将结合说明书附图对本发明的内容作进一步的详细描述。应理解的是本发明能够在不同的示例上具有各种的变化，其皆不脱离本发明的范围，且其中的说明及图示在本质上当作说明之用，而非用以限制本发明。需说明的是，附图均采用非常简化的形式且均使用非精准的比率，仅用以方便、明晰地辅助说明本发明实施例的目的。
以下具体实施方式以20nm技术代体硅基片上FinFET器件的鳍形结构(fin)的形成工艺为例。
为获得较好的器件电学性能及工艺便利考虑(如较大的开关电流比 I on/I off、器件间良好的电学隔离)，对fin及其下方的隔离结构有一定的形貌要求，源漏及沟道区域(fin结构)需较为陡直，而隔离结构则需有一定坡度以便介质填充。
有数值仿真结果显示，鳍形状对FinFET的开关电流比的影响明显，I on/I off随底部倾角q增大而单调递增，在垂直形貌时(q＝90°)达到最大。同时对于深亚微米及纳米级器件而言，工艺控制的精度与均匀性也十分重要，对产品良率有直接影响。
请参考图1和图2-图8。本发明的一种半导体结构的形成方法，包括以下步骤：
步骤S010：提供一半导体衬底，在半导体衬底上形成硬掩模层。
请参考图2。半导体衬底100可以为硅衬底，或其他合适的半导体材料形成的衬底。根据设计需要，衬底100可以是P型衬底或N型衬底，并且其中具有掺杂区域。对于本实施例，衬底材质均匀，中间不存在本征隔离层，在此优选为体硅基片。
硬掩模层(hard mask)120包括SiN、SiON、SiC、SiO 2或者上述膜层的组合，并且可通过诸如等离子体增强化学气相沉积(PECVD)、原子层沉积(ALD)、等离子体增强ALD(PEALD)、热氧化等合适的沉积工艺形成。
本实施例中，硬掩模层120优选为SiON，并采用PECVD方式形成。硬掩模层120的厚度可为5～15nm，优选为10nm。
步骤S020：在硬掩模层上形成鳍形结构的光刻图形。
请继续参考图2。用于形成鳍形结构的光刻图形，可以为利用电子束光刻形成的光刻胶(PR)图形，或者为利用牺牲层间隔物(spacer)形成的光刻图形(即自对准双重成像技术Self-aligned Double Patterning,SADP)。SADP技术属较为成熟的工艺，在此不再赘述。
在本实施例中，以光刻胶作为光刻图形150，其厚度为80～150nm，优选为100nm。
需要形成的fin结构图形线宽为5～60nm，优选为8nm；fin间隔为8～ 60nm，优选为10nm。光刻图形150具有与此对应的尺寸及间距。
FinFET在制造中会形成多个fin，以获得更大的沟道宽度从而得到更大的电流，一般fin组合个数为4～10，图2为说明本发明的核心思想，作了一定简化，仅示出2个fin的光刻图形150。
步骤S030：利用光刻图形为掩模，对其下方的硬掩模层和半导体衬底进行图形化，获得硬掩模层图形及带有鳍形结构的半导体衬底；鳍形结构具有陡直的侧壁形貌。
请参考图3。利用fin光刻图形150，对硬掩模层120、衬底100进行刻蚀实现图形化，获得硬掩模层图形120’和带有fin结构155的衬底100’。
Fin结构的高宽比(AR:aspect ratio)通常为3～6，本实施例中以AR＝4为例，则衬底刻蚀深度为30～35nm，优选为32nm。
本道刻蚀工艺所涉及膜层依次为：硬掩模层SiON 10nm，Si 32nm。
由于fin结构的各项形貌参数(如线宽、高度、侧壁倾角)以及fin结构间的一致性对器件性能影响显著，形成规整度高度统一的fin能有效改善器件性能，因此本道刻蚀工艺需要精确控制。为此，本道刻蚀采用较新的原子层刻蚀(ALE)技术，该技术通过精确控制反应气体流量及脉冲式输入功率，可以将刻蚀精度提高到单原子层的量级，其缺点是刻蚀速率较低。但对于fin结构刻蚀，由于刻蚀深度较小，仅为40～50nm，因此产额处于可接受的范围。
ALE单个循环可分为3个步骤：
①通刻蚀性气体；
②通去除气体；
③清洗。
相应的工艺参数可为：
①通刻蚀性气体，其中Cl 2 50～100sccm，优选为80sccm；腔室压强5～50mtorr，优选为15mtorr；功率0。
②通去除气体，其中去除气体为Ar、N 2、He或其组合，本实施例优选 为Ar，流量300～400sccm，优选为350sccm；腔室压强100～300mtorr，优选为250mtorr；源功率范围为100～1500W，优选为800W，偏置功率范围为0～500W，优选为300W。
③清洗步骤，其中O 2 500～1000sccm，优选为800sccm，腔室压强200～500mtorr，优选为300mtorr；功率0。
上述工艺条件每个循环可刻蚀Si 0.5～5nm，本实施例通过对工艺气体流量、刻蚀腔室压强进行控制，并通过调节各步时间，使单循环刻蚀量约在1nm。利用ALE工艺可以精确控制各个fin结构的线宽、高度，使每个fin的线宽差异、高度(刻蚀深度)差异均小于1nm，并通过各向异性方式获得相当陡直的形貌，使fin结构间保持良好的形貌一致性，同时还消除了结构的高深宽比对刻蚀效果的影响。
原子层刻蚀完成后，可进行常规的去胶及湿法清洗。
步骤S040：在鳍形结构的侧壁表面形成保护层。
请参考图4。为在后续工艺过程中维持所得的fin结构155陡直的形貌，需要在fin侧壁形成保护层160。
侧壁保护层160包括SiO 2或SiN或者其膜层组合，其形成方式可以为ALD、PEALD、热氧化等合适的沉积工艺。
本道工艺需要对保护层160进行保形沉积，膜层厚度较薄并且需精确控制使其均匀一致。
本实施例中，侧壁保护层为SiO 2，采用ALD方式形成；膜厚为1～3nm，优选为1.5nm。该保护层160覆盖于fin结构155的顶部表面(即硬掩模层图形120’上表面)和侧壁表面(包括硬掩模层图形120’侧壁表面)及fin结构155间隔间的衬底100’表面上。
本道工艺利用ALD形成侧壁保护层，因而其膜厚可以很薄，比如可为5nm以下，而不必形成如同现有技术中的侧壁隔片结构。因此，在形成的后续结构中就可避免出现明显的水平台阶的问题，从而可以较精确地控制fin结构形貌。
步骤S050：利用鳍形结构为掩模，对其下方的半导体衬底进行刻蚀，形成隔离结构凹槽。
请参考图5。本步骤用于刻蚀隔离部分的结构。该结构需要保持一定坡度(斜率)，以便于后续介质的填充及离子注入，其坡度如82°～86°。
可利用已形成的fin结构为掩模，对下方的衬底进行刻蚀，形成隔离结构凹槽170，从而获得带有fin155及隔离结构凹槽170的衬底100”。
隔离结构的深度与fin高度相关，本实施例优选为50nm。通过调节优化刻蚀工艺参数，可以使Si/SiO 2刻蚀选择比达到或接近100，由此，侧壁保护层160可以很好地保护已形成的fin结构免受本道工艺影响。
可先利用原子层刻蚀技术，将fin之间间隔表面的保护层刻开，或者可在主刻蚀工艺前加入一道击穿工艺(breakthrough)来将fin之间间隔表面形成刻蚀窗口。
当保护层材料为SiO 2时，可采用干法刻蚀形成隔离结构凹槽。其后的主刻蚀采用的刻蚀气体组合为HBr/He/O 2，工艺条件可以为：HBr 180～220sccm，优选为200sccm；He 350～450sccm，优选为400sccm；O 2 4～6sccm，优选为5sccm；腔室压强70～90mtorr，优选为80mtorr；源功率范围为800～1200W，优选为1000W。
上述刻蚀工艺条件的Si/SiO 2刻蚀选择比可达到100，加之刻蚀的各向异性，fin结构的侧壁保护层损失量将小于1nm，由此fin结构将得到有效的保护。
作为其他的可选实施例，当保护层材料为SiN时，使SiN保护层厚度为1～3nm，优选为1.5nm。在先采用干法刻蚀去除fin间隔表面的保护层后，可继续采用湿法刻蚀或干法释放工艺方式形成隔离结构凹槽，如利用氢氧化钾(KOH)或四甲基氢氧化铵(TMAH)等碱性溶液刻蚀衬底。由于Si衬底具有的特定晶向，可实现对Si衬底的各向异性刻蚀，形成具有特定斜率(坡度)侧壁的隔离结构。对于(100)晶面的Si衬底，沿<110>晶向作掩模，可获得坡度为54.7°的隔离结构界面。fin侧壁保护层在此刻蚀阶段还可保护 fin结构不受影响，该层与残留的硬掩模层可利用湿法刻蚀同步去除。本实施例上述材料及工艺步骤的调整为实现相应工艺效果提供了另一种解决方法。
本道工艺引入先进的原子层刻蚀(ALE)技术，并给出工艺示例，有助于提高隔离图形结构的刻蚀深度和线宽均匀性，改善负载效应。
在隔离部分刻蚀完成后，需要去除fin侧壁的保护层。
在这之前，需要先对所形成的隔离结构凹槽的露出表面进行改性处理，以在隔离结构凹槽的露出表面形成具有一定厚度的改性处理层。然后，再对保护层及改性处理层进行同时去除。这样，可有效消除现有技术中因直接去除fin侧壁的保护层，而在保护层下端与衬底之间的界面处形成水平台阶的问题，从而避免了对fin的形貌造成破坏。
作为一优选的实施方式，可通过对所形成的隔离结构凹槽表面进行热氧化，消耗隔离结构凹槽表面一定厚度的衬底硅材料，来形成上述的改性处理层(热氧化层)。然后，再利用湿法刻蚀同时(同步)去除保护层及热氧化层。这样不但可以消除以往该刻蚀步骤形成的平台，还可以去除隔离结构凹槽表面的刻蚀损伤层。
上述热氧化工艺的控制重点在于，应使得热氧化消耗的硅层厚度与侧壁保护层的厚度相对应，达到至少基本一致的状态。
步骤S060：在隔离结构凹槽内填充介质层，直至将鳍形结构覆盖。
请参考图6。本沉积工艺步骤要求介质层180能很好地填充很深的、且深宽比大的沟槽，不产生孔洞及其他缺陷。
填充的介质层180可为SiO 2，通过诸如等离子体增强化学气相沉积(PECVD)、高密度等离子体化学气相沉积(HDPCVD)、ALD、可流动化学气相沉积(FCVD)等合适的沉积工艺或其组合形成。本实施例所填充的沟槽顶部宽度可为10nm，总深度可为92nm，深宽比可超过9。对于该深宽比数值，一般的沉积工艺较难实现，在此优选为FCVD，所形成的介质材料是可流动的，因此填充性能较好，在后续退火/固化步骤后，所形成的介质层可 转变为固态。
本工艺步骤完成后，介质层填满凹槽170并覆盖于fin结构155顶部表面上(即覆盖于硬掩模层图形120’表面上)，高于fin结构顶部的表面层厚度为10～20nm，优选为15nm。
步骤S070：对介质层进行平坦化，直至鳍形结构顶部的硬掩模层暴露。
请参考图7。由于填充的介质层薄膜有一定起伏，需要进行平坦化工艺，其实现方式有诸如化学机械抛光(CMP)、膜层反刻(etch back)等方式，本实施例优选为CMP，对介质层表面进行磨削抛光直至fin顶部的硬掩模层暴露。平坦化后形成剩余硬掩模层图形120”，以及平坦化后的填充介质层180’。
本实施例中，硬掩模层损失量可控制在3～5nm。
步骤S080：对介质层进行凹槽刻蚀，形成鳍形结构和具有倾斜侧壁的隔离结构。
请参考图8。通过对介质层180’进行凹槽刻蚀，使fin相互独立，为后续栅极形成留出空间。
该道工艺利用余留的硬掩模层120”作为保护层(保护掩模)，刻蚀fin之间的介质层。由于体硅基片没有明显的刻蚀停止层，其刻蚀深度主要取决于刻蚀时间。对于上述工艺形成的器件结构，由于fin及其下方的隔离结构形貌有一定差异，在刻蚀过程中利用精度较高的终点探测方法可以探测到光谱的细微变化(刻蚀暴露面积逐步减小)，从而将刻蚀过程终止于两者的交界面附近，以此控制刻蚀深度。
最后，可利用湿法刻蚀去除残留的硬掩模层。
至此，fin结构155及fin之间的隔离结构190已经形成。其中，fin结构155较为陡直，而隔离结构190则有一定坡度，且剩余的介质层180”填充高度及fin高度控制较好，同时各个fin结构间的线宽、高度、斜率等形貌参数均匀一致。
此外，为形成fin间的绝缘隔离，后续还需要通过高剂量、大角度离子 注入，在fin底部形成掺杂PN结，以实现电学隔离，在此不再赘述。
综上所述，本发明的方法利用先进的工艺过程控制，通过对工艺流程进行调整，以分步形成鳍形结构及器件隔离结构，并独立调节鳍形结构与隔离结构两者侧壁的物理形貌，以此改善工艺精度、均匀性和稳定性，并突破了现有技术难点，能够较为精确地控制鳍形结构和隔离结构物理形貌的均匀性、一致性，其工艺结果有助于提升场效应管器件的相关电学性能(如开关电流比I on/I off)，提高器件可靠性并获得较高的产品良率。
以上所述的仅为本发明的实施例，所述实施例并非用以限制本发明专利保护范围，因此凡是运用本发明的说明书及附图内容所作的等同结构变化，同理均应包含在本发明的保护范围内。

Claims (10)

  1. 一种半导体结构的形成方法，其特征在于，包括以下步骤：
    提供一半导体衬底，在所述半导体衬底上形成硬掩模层；
    在所述硬掩模层上形成鳍形结构的光刻图形；
    利用所述光刻图形为掩模，对其下方的硬掩模层和半导体衬底进行图形化，获得硬掩模层图形及带有鳍形结构的半导体衬底；所述鳍形结构具有陡直的侧壁形貌；
    在所述鳍形结构的侧壁表面形成保护层；
    利用所述鳍形结构为掩模，对其下方的半导体衬底进行刻蚀，形成隔离结构凹槽；
    对所述隔离结构凹槽的露出表面进行改性处理，形成一定厚度的改性处理层；
    对所述保护层及改性处理层进行同时去除；
    在所述隔离结构凹槽内填充介质层，直至将所述鳍形结构覆盖；
    对所述介质层进行平坦化，直至鳍形结构顶部的硬掩模层暴露；
    对所述介质层进行凹槽刻蚀，形成鳍形结构和具有倾斜侧壁的隔离结构。
  2. 根据权利要求1所述的半导体结构的形成方法，其特征在于，所述改性处理为热氧化，使热氧化消耗的所述半导体衬底的材料厚度与所述保护层的厚度对应，并采用湿法刻蚀对所述保护层及改性处理层进行同时去除。
  3. 根据权利要求1所述的半导体结构的形成方法，其特征在于，采用原子层刻蚀方法，对所述硬掩模层和半导体衬底进行图形化；其中，进行原子层刻蚀时，每次循环的刻蚀量为0.5～5nm。
  4. 根据权利要求1所述的半导体结构的形成方法，其特征在于，所述保护层为SiO 2或SiN，或者SiO 2和SiN的膜层组合。
  5. 根据权利要求1所述的半导体结构的形成方法，其特征在于，采用 保形沉积方法，在所述鳍形结构的侧壁表面形成保护层。
  6. 根据权利要求5所述的半导体结构的形成方法，其特征在于，所述保形沉积方法为ALD、PEALD或热氧化沉积。
  7. 根据权利要求1所述的半导体结构的形成方法，其特征在于，所述硬掩模层为SiN、SiON、SiC或SiO 2，或者SiN、SiON、SiC和SiO 2其中至少两种的膜层组合。
  8. 根据权利要求1所述的半导体结构的形成方法，其特征在于，当所述保护层材料为SiO 2、半导体衬底材料为Si时，采用干法刻蚀形成所述隔离结构凹槽，采用的刻蚀气体组合为：HBr、He和O 2，刻蚀气体流量为：HBr 180～220sccm，He 350～450sccm，O 2 4～6sccm；刻蚀腔室压强为70～90mtorr；源功率范围为800～1200W。
  9. 根据权利要求1所述的半导体结构的形成方法，其特征在于，当所述保护层材料为SiN、半导体衬底材料为Si时，采用湿法刻蚀或干法释放工艺形成所述隔离结构凹槽。
  10. 根据权利要求1所述的半导体结构的形成方法，其特征在于，对所述介质层进行凹槽刻蚀时，利用余留的硬掩模层作为保护掩模，刻蚀鳍形结构周围的介质层，并利用具有陡直侧壁的鳍形结构及其下方具有倾斜侧壁的隔离结构两者形貌上的差异，采用终点探测方法控制刻蚀深度。
PCT/CN2019/104666 2018-09-07 2019-09-06 一种半导体结构的形成方法 WO2020048524A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/284,849 US20220059402A1 (en) 2018-09-07 2019-09-06 Formation method of semiconductor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811044219.6A CN109411415B (zh) 2018-09-07 2018-09-07 一种半导体结构的形成方法
CN201811044219.6 2018-09-07

Publications (1)

Publication Number Publication Date
WO2020048524A1 true WO2020048524A1 (zh) 2020-03-12

Family

ID=65464612

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/104666 WO2020048524A1 (zh) 2018-09-07 2019-09-06 一种半导体结构的形成方法

Country Status (3)

Country Link
US (1) US20220059402A1 (zh)
CN (1) CN109411415B (zh)
WO (1) WO2020048524A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109411415B (zh) * 2018-09-07 2021-04-30 上海集成电路研发中心有限公司 一种半导体结构的形成方法
CN112117192A (zh) * 2019-06-21 2020-12-22 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
CN113451121A (zh) * 2020-03-24 2021-09-28 广东汉岂工业技术研发有限公司 FinFET器件的鳍片制作方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140273292A1 (en) * 2013-03-14 2014-09-18 Applied Materials, Inc. Methods of forming silicon nitride spacers
CN105914206A (zh) * 2015-02-24 2016-08-31 三星电子株式会社 集成电路器件及其制造方法
CN106601683A (zh) * 2015-10-15 2017-04-26 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法、电子装置
CN106601687A (zh) * 2015-10-16 2017-04-26 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法、电子装置
CN106601678A (zh) * 2015-10-14 2017-04-26 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法、电子装置
CN109411415A (zh) * 2018-09-07 2019-03-01 上海集成电路研发中心有限公司 一种半导体结构的形成方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8174073B2 (en) * 2007-05-30 2012-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structures with multiple FinFETs
US8765556B2 (en) * 2009-12-23 2014-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating strained structure in semiconductor device
US9287385B2 (en) * 2011-09-01 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-fin device and method of making same
CN104425263B (zh) * 2013-08-20 2017-06-13 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
US8951884B1 (en) * 2013-11-14 2015-02-10 United Microelectronics Corp. Method for forming a FinFET structure
CN105576024B (zh) * 2014-10-15 2019-03-12 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US9761584B2 (en) * 2015-06-05 2017-09-12 Taiwan Semiconductor Manufacturing Co., Ltd. Buried channel semiconductor device and method for manufacturing the same
KR102410146B1 (ko) * 2015-06-26 2022-06-16 삼성전자주식회사 반도체 장치의 제조 방법
US10796912B2 (en) * 2017-05-16 2020-10-06 Lam Research Corporation Eliminating yield impact of stochastics in lithography
US10861698B2 (en) * 2017-08-29 2020-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Pattern fidelity enhancement
CN108470685B (zh) * 2018-03-30 2022-02-01 中国科学院微电子研究所 一种纳米线结构及其制造方法
US10559685B2 (en) * 2018-06-13 2020-02-11 International Business Machines Corporation Vertical field effect transistor with reduced external resistance
US10930569B2 (en) * 2018-07-31 2021-02-23 Taiwan Semiconductor Manufacturing Co., Ltd. Dual crystal orientation for semiconductor devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140273292A1 (en) * 2013-03-14 2014-09-18 Applied Materials, Inc. Methods of forming silicon nitride spacers
CN105914206A (zh) * 2015-02-24 2016-08-31 三星电子株式会社 集成电路器件及其制造方法
CN106601678A (zh) * 2015-10-14 2017-04-26 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法、电子装置
CN106601683A (zh) * 2015-10-15 2017-04-26 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法、电子装置
CN106601687A (zh) * 2015-10-16 2017-04-26 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法、电子装置
CN109411415A (zh) * 2018-09-07 2019-03-01 上海集成电路研发中心有限公司 一种半导体结构的形成方法

Also Published As

Publication number Publication date
CN109411415B (zh) 2021-04-30
CN109411415A (zh) 2019-03-01
US20220059402A1 (en) 2022-02-24

Similar Documents

Publication Publication Date Title
TWI416634B (zh) 形成積體電路結構的方法
US10699939B2 (en) FinFET semiconductor structure with equal pitches and fabrication method thereof
US10211062B2 (en) Semiconductor structures and fabrication methods thereof
US20140306272A1 (en) Method of forming a finfet structure
WO2020048524A1 (zh) 一种半导体结构的形成方法
US9214529B2 (en) Fin Fet device with independent control gate
CN104124168B (zh) 半导体结构的形成方法
CN107785315B (zh) 半导体结构的形成方法
US20230238245A1 (en) Semiconductor structure and forming method thereof
CN109285875A (zh) 鳍式晶体管及其形成方法
CN104051248B (zh) 栅极的形成方法
US8883584B2 (en) Method of manufacturing semiconductor device with well etched spacer
CN104425264B (zh) 半导体结构的形成方法
CN109037068A (zh) 半导体结构及其形成方法
CN109950311B (zh) 半导体结构及其形成方法
CN111129142B (zh) 半导体器件及其形成方法
US10957550B2 (en) Semiconductor structure and formation method thereof
US10522619B2 (en) Three-dimensional transistor
US8728948B2 (en) Method of manufacturing semiconductor device
CN108630611A (zh) 半导体结构及其形成方法
WO2014005371A1 (zh) 半导体器件制造方法
CN103531476A (zh) 半导体器件制造方法
TWI518792B (zh) 半導體製程
CN108122965B (zh) 半导体结构及其形成方法
CN110690218A (zh) 半导体器件及其形成方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19857493

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19857493

Country of ref document: EP

Kind code of ref document: A1