WO2014002913A1 - 不揮発性半導体記憶装置 - Google Patents
不揮発性半導体記憶装置 Download PDFInfo
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- WO2014002913A1 WO2014002913A1 PCT/JP2013/067146 JP2013067146W WO2014002913A1 WO 2014002913 A1 WO2014002913 A1 WO 2014002913A1 JP 2013067146 W JP2013067146 W JP 2013067146W WO 2014002913 A1 WO2014002913 A1 WO 2014002913A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
Definitions
- the present invention relates to a nonvolatile semiconductor memory device, for example, a nonvolatile semiconductor memory device capable of writing data to a predetermined memory cell among a plurality of memory cell transistors (hereinafter simply referred to as memory cells) arranged in a matrix. It is suitable for application to.
- a nonvolatile semiconductor memory device for example, a nonvolatile semiconductor memory device capable of writing data to a predetermined memory cell among a plurality of memory cell transistors (hereinafter simply referred to as memory cells) arranged in a matrix. It is suitable for application to.
- FIG. 13 shows a conventional nonvolatile semiconductor memory device 501, which includes, for example, a plurality of P-type memory wells W503a, W503b, W503c, and W503d arranged in the row direction (left-right direction), and each P-type memory well W503a. .., W503d each have a configuration in which a plurality of memory cells C are formed in a matrix.
- a plurality of common word lines 502a, 502b, 502c, 502d, 502e, and 502f extending in the row direction are arranged at equal intervals in the column direction (vertical direction).
- the common word lines 502a to 502f and the P-type memory wells W503a to W503d are arranged so as to intersect each other.
- Each common word line 502a to 502f is connected to a plurality of memory cells C arranged in the same row across a plurality of P-type memory wells W503a to W503d, and all of the memory cells C arranged in the same row are connected.
- a predetermined gate voltage can be uniformly applied to each control gate.
- Each of the P-type memory wells W503a to W503d is provided with a plurality of first bit lines L1 extending in the column direction and a plurality of second bit lines L2 extending in the column direction.
- Each P-type memory well W503a to W503d has a pair of a first bit line L1 and a second bit line L2 adjacent to the first bit line L1.
- a plurality of memory cells C are arranged in parallel between the bit lines L2.
- the first bit line L1 is connected to one end of each memory cell C, and the second bit line L2 is connected to the other end.
- the first bit line L1 and the second bit line L2 are connected to the other end.
- a write voltage or a write inhibit voltage can be applied to one end and the other end.
- the memory cells C all have the same configuration, and are made of an N-channel type in which the semiconductor substrate is composed of P-type memory wells W503a to W503d.
- Each memory cell C includes a channel region between one end and the other end formed at a predetermined interval on a semiconductor substrate (P-type memory well W503a), for example, and a tunnel insulating layer is interposed on the channel region.
- the charge storage layer, the interlayer insulating layer, and the control gate are sequentially stacked.
- charges are injected into the charge storage layer due to a voltage difference between a voltage applied between one end and the other end and a voltage applied to the control gate, and data is written.
- the data stored in the charge storage layer may be extracted and data may be erased.
- the voltages applied to the first bit line L1, the second bit line L2, the common word lines 502a to 502f, and the P-type memory wells W503a to W503d respectively.
- data can be written to a predetermined memory cell C, data can be read from the predetermined memory cell C, or data written to the memory cell C can be erased.
- FIG. 13 shows that data is written only in the memory cell C arranged in the first row and first column of the P-type memory well W503a in the first column among the plurality of memory cells C, and all other memories.
- the voltage value at each location when data is not written to the cell C is shown.
- the memory cell C to which data is written is referred to as a selected memory cell C1
- the memory cell C to which data is not written is referred to as an unselected memory cell C2.
- the common word line 502a to which the selected memory cell C1 is connected is selected as the selected common word line 515
- the first bit line L1 and the second bit line L2 to which the selected memory cell C1 is also connected is selected as the first bit line L1a.
- the common word lines 502b, 502c, 502d, 502e, and 502f, to which only the non-selected memory cell C2 is connected are referred to as the non-selected common word line 516 and also the non-selected memory cell C2.
- the first bit line L1 and the second bit line L2 to which are connected are referred to as unselected first bit lines L1b and L1c and unselected second bit lines L2b and L2c.
- 0 [V] is applied to each of the P-type memory wells W503a to W503d.
- a description will be given focusing on a P-type memory well W503a (hereinafter simply referred to as a selected byte) in which a selected memory cell C1 is arranged, and then a P-type in which only an unselected memory cell C2 is arranged.
- Description will be made focusing on the memory wells W503b to W503d (hereinafter simply referred to as non-selected bytes).
- a write gate voltage of 12 [V] is applied to the selected common word line 515, and a write voltage of 0 [V] is applied to the selected first bit line L1a and the selected line. Each is applied to the second bit line L2a.
- a write gate voltage of 12 [V] is applied to the selected memory cell C1 from the selected common word line 515 to the control gate, and one end and the other from the selected first bit line L1a and the selected second bit line L2a.
- a write voltage of 0 [V] may be applied to the end.
- the voltage difference between the control gate and the channel region becomes large in the selected memory cell C1, a quantum tunnel effect occurs, charge is injected into the charge storage layer, and data can be written.
- a write inhibit voltage of 6 [V] is applied as an intermediate voltage to the unselected first bit line L1b and the unselected second bit line L2b.
- the unselected memory cell C2 connected to the unselected first bit line L1b and the unselected second bit line L2b has a write gate voltage of 12 [V] from the selected common word line 515 to the control gate.
- a 6 [V] write inhibit voltage is applied to one end and the other end from the unselected first bit line L1b and the unselected second bit line L2b, the voltage between the control gate and the channel region is applied.
- a write inhibit gate voltage of 0 [V] is applied to the non-selected common word line 516.
- the selected first bit line L1a and the selected bit are selected.
- a write voltage of 0 [V] is applied from one end to the other end of the second bit line L2a
- a write inhibit gate voltage of 0 [V] is applied from the non-selected common word line 516 to the control gate.
- a write inhibit voltage of 12 [V] is applied to the non-selected first bit line L1c and the non-selected second bit line L2c in the non-selected byte.
- a write gate voltage of 12 [V] is applied from the selected common word line 515 to the control gate to each non-selected memory cell C2 in the third area AR503 where the non-selected byte and the selected row intersect. Since a write inhibit voltage of 12 [V] is applied to one end and the other end from the selected first bit line L1c and the non-selected second bit line L2c, the control gate and the channel region have the same voltage. A tunnel effect does not occur, and no data can be written without charge being injected into the charge storage layer.
- a write inhibit gate voltage of 0 [V] is applied from the non-selected common word line 516 to the control gate of each non-selected memory cell C2 in the fourth area AR504 where the non-selected row and the non-selected byte intersect.
- the voltage value on the control gate side is changed to the voltage value on the channel region side by applying a write inhibit voltage of 12 [V] to one end and the other end from the unselected first bit line L1c and the unselected second bit line L2c.
- a plurality of memories arranged in a matrix are adjusted by adjusting the voltage values applied to the common word lines 502a to 502f, the first bit line L1, and the second bit line L2.
- data can be written only to a predetermined selected memory cell C1.
- the 12 [V] applied to the selected common word line 515 is used.
- the write gate voltage is also applied to each non-selected memory cell C2 in the same row arranged in the third area AR503 of the non-selected byte. Therefore, in the nonvolatile semiconductor memory device 501, as described above, the rewrite prohibition voltage of 12 [V] is also applied to the non-selected first bit line L1c and the non-selected second bit line L2c in the third area AR503. This prevents the charge from being injected into the charge storage layer in the non-selected memory cell C2 in the third region AR503.
- a rewrite prohibition voltage of 12 [V] is applied to the non-selected first bit line L1c and the non-selected second bit line L2c in accordance with the selected common word line 515. Since 0 [V] is applied to the P-type memory wells W503b to W503d, the voltage values of the P-type memory wells W503b to W503d are the selected common word line 515, the non-selected first bit line L1c, and the non-selected first bit line L1c. The voltage value becomes lower than the voltage value of the selected second bit line L2c.
- the voltage difference between the P-type memory wells W503b to W503d is eventually increased.
- a phenomenon hereinafter referred to as disturb
- unintended charges are injected into the charge storage layer of the selected memory cell C2 and the charge storage state of the charge storage layer changes.
- a write inhibit voltage of 12 [V] is applied to the non-selected first bit line L1c and the non-selected second bit line L2c arranged in the non-selected byte.
- the non-selected common word line 516 to which the write inhibit gate voltage of 0 [V] is applied in the non-selected row, the non-selected first bit line L1c to which the write inhibit voltage of 12 [V] is applied, and the non-selected There is a problem that a voltage difference becomes large in the fourth area AR504 where the first bit line L2c intersects, and as a result, disturbance occurs in each non-selected memory cell C2 in the fourth area AR504.
- the disturbance occurs not only in the third area AR503 but also in each non-selected memory cell C2 in the fourth area AR504, and the number of common word lines 502a to 502f increases.
- the number of memory cells C to which data can be written in the selected byte increases, the number of times data is written to the selected memory cell C1 in the selected byte increases accordingly. Disturbance frequently occurs in unselected memory cells that are not subjected to.
- the nonvolatile semiconductor memory device 501 if such disturbance repeatedly occurs in the non-selected byte, a weak write operation or a weak erase operation occurs. As a result, the threshold voltage of each non-selected memory cell in the non-selected byte. May fluctuate and eventually data may be lost. For this reason, in particular, in the nonvolatile semiconductor memory device 501 that operates as an EEPROM having a rewrite unit as small as 1 byte, it is desired to be able to suppress the disturbance in the non-selected memory cell C2 at the time of data writing.
- a row direction address decoder that applies a gate voltage to a word line is provided for each selected byte and each non-selected byte, and each row direction address decoder is provided. It is conceivable that the coater is operated independently so that an optimum gate voltage is applied to each byte, and the selected byte and the non-selected byte are completely separated by the row direction address decoder.
- another row direction address is not restricted by the row direction address decoder that applies a write gate voltage of 12 [V] to the selected word line by the selected byte.
- the decoder can apply a low-voltage write inhibit gate voltage to each unselected word line of the unselected byte.
- the voltage value of the write inhibit voltage of the unselected first bit line and the unselected second bit line and the voltage value of the P-type memory well are the same as the low voltage write inhibit gate voltage. Since the voltage value can be selected, the disturbance in the non-selected memory cell of the non-selected byte can be suppressed.
- an object of the present invention is to propose a nonvolatile semiconductor memory device that can suppress the occurrence of disturbance more than ever while achieving downsizing.
- claim 1 of the present invention provides a plurality of word lines formed in a matrix shape to which one of a charge storage gate voltage and a charge storage inhibition gate voltage is applied, and is connected to each of the word lines.
- a non-volatile semiconductor memory device that accumulates electric charge in a selected memory cell among the plurality of memory cells, and a power supply unit provided for each word line column and a common provided for each word line row
- Each of the common lines applies a predetermined common voltage to each of the power supply units in units of the word line row, and each of the power supply units is provided for each of the word lines.
- Wiring is provided, and based on the voltage difference between the unit voltage applied to each power supply unit and the common voltage, the switching mechanism of each power supply unit is turned on and off, thereby the power supply
- the nonvolatile semiconductor memory device is characterized in that the charge storage gate voltage or the charge storage inhibition gate voltage is individually applied to each of the word lines via a unit.
- the selected word line with the selected memory cell in the power supply unit is connected.
- the NMOS switch is turned off and the PMOS switch in which the charge storage gate voltage is applied to the source is turned on, so that the charge storage gate voltage is applied from the drain of the PMOS switch to the selected word line.
- the charge storage gate voltage is applied from the unit wiring to the source of the PMOS switch, while in the seventh embodiment (FIG. 9), A charge storage gate voltage is applied from the common line to the source of the PMOS switch.
- the selected word line having the selected memory cell is connected in the power supply unit.
- the selected power supply unit when a charge accumulation prohibition gate voltage is applied to an unselected word line in which only unselected memory cells are arranged, the PMOS switch is turned off and the charge accumulation prohibition gate voltage is applied to the source.
- the NMOS switch is turned on, a charge accumulation prohibiting gate voltage is applied from the drain of the NMOS switch to the unselected word line.
- the charge accumulation inhibition gate voltage is applied from the unit wiring to the source of the NMOS switch, while in the seventh embodiment (FIG. 9).
- the charge accumulation prohibiting gate voltage is applied from the common line to the NMOS switch.
- the third embodiment (FIG. 4), the fourth embodiment (FIG. 6), the fifth embodiment (FIG. 7), the sixth embodiment (FIG. 8), and In the seventh embodiment (FIG. 9), among the power supply units, in the unselected power supply unit having only the unselected word line in which only the unselected memory cells are arranged, the charge accumulation prohibiting gate voltage is applied to the source. When the auxiliary switch is turned on, the charge accumulation prohibiting gate voltage is applied from the drain of the auxiliary switch to the unselected word line.
- the auxiliary switch Is an auxiliary NMOS switch, while in the fourth embodiment (FIG. 6), the auxiliary switch is an auxiliary PMOS switch.
- the charge accumulation prohibiting gate voltage is applied from the unit wiring to the auxiliary switch.
- a different unit voltage is applied to each power supply unit depending on whether or not there is a selected memory cell in the word line column, and each power supply is based on the voltage difference between the unit voltage and the common voltage.
- the charge storage gate voltage or the charge storage prohibition gate voltage can be individually applied to each word line via the power supply unit, and thus applied to one word line column.
- the voltage value of the charge accumulation prohibiting gate voltage and the voltage value of the bit line can be freely set to voltage values that can suppress the occurrence of disturbance, for example, in other word line columns without being restricted by the voltage to be disturbed.
- a plurality of power supply units are connected by a common wiring, and by adjusting the common voltage applied to the common wiring, the switching mechanism of each power supply unit is turned on and off, and all the word lines Since the selected word line can be selectively determined from the above, it is not necessary to provide an independent row direction address decoder for each word line column, and miniaturization can be achieved as in the prior art.
- FIG. 1 is a circuit diagram showing a circuit configuration of a nonvolatile semiconductor memory device according to a first embodiment and voltage values at various points during data writing.
- FIG. FIG. 6 is a circuit diagram showing a circuit configuration of a nonvolatile semiconductor memory device according to a second embodiment and voltage values at various points during data writing.
- FIG. 5 is a circuit diagram showing a circuit configuration of a nonvolatile semiconductor memory device according to a second embodiment and voltage values at various points during a data erasing operation.
- FIG. 6 is a circuit diagram showing a circuit configuration of a nonvolatile semiconductor memory device according to a third embodiment and voltage values at various points during data writing.
- FIG. 6 is a circuit diagram showing a circuit configuration of a nonvolatile semiconductor memory device according to a third embodiment and voltage values at various points during a data erasing operation. It is a circuit diagram which shows the circuit structure of the non-volatile semiconductor memory device by 4th Embodiment, and the voltage value of each location at the time of the data writing.
- FIG. 10 is a circuit diagram showing a circuit configuration of a nonvolatile semiconductor memory device according to a fifth embodiment and voltage values at various points during data writing. It is a circuit diagram which shows the circuit structure of the non-volatile semiconductor memory device by 6th Embodiment, and the voltage value of each location at the time of the data writing.
- FIG. 1 is a nonvolatile semiconductor memory device according to the present invention
- a plurality of unit columns 2 having the same configuration are arranged side by side in the row direction (left-right direction).
- the plurality of unit columns 2 all have the same configuration, the following description will be made with attention paid to the unit column 2 in the first column.
- an N-type well NW1, a P-type well PW1, and a P-type memory well PW2 are sequentially arranged in the unit row 2.
- a power supply unit 4 is formed in the N-type well NW1 and the P-type well PW1, and the memory well
- a plurality of memory cells C are formed in a matrix in a P-type memory well PW2.
- a first power supply line 5a extending in the column direction (vertical direction) is formed in the N-type well NW1, and a plurality of PMOS switches 8a, 8c,... It is provided along the first power supply line 5a.
- the PMOS switches 8a, 8c,... Have their sources connected to the first power supply line 5a and their drains connected to a word line 15 to be described later, and are applied to the source from the first power supply line 5a by turning on.
- a write gate voltage, a write inhibit gate voltage, or the like can be applied to the word line 15 from the drain.
- a second power supply line 6a extending in the column direction is formed in the P-type well PW1, and NMOS switches 9a, 9c,... That pair with the PMOS switches 8a, 8c,.
- the second power supply line 6a is provided at a predetermined interval in the column direction.
- the NMOS switches 9a, 9c,... Have their sources connected to the second power supply line 6a and their drains connected to a word line 15 to be described later, and are applied to the source from the second power supply line 6a by turning on.
- a write inhibit gate voltage or the like can be applied to the word line 15 from the drain.
- the P-type memory well PW2 of the unit column 2 is provided with a plurality of word lines 15 corresponding to pairs of PMOS switches 8a, 8c,... And NMOS switches 9a, 9c,.
- a plurality of (in this case, two) memory cells C are formed.
- a plurality of word lines 15 extending in the row direction (left-right direction) are arranged in the P-type memory well PW2 at predetermined intervals in the column direction.
- the word line 15 includes drains of PMOS switches 8a (8c,%) And NMOS switches 9a (9c,%) Provided in the power supply unit 4 and memories in the same row arranged in the P-type memory well.
- the control gate of the cell C is connected.
- each word line 15 applies a predetermined gate voltage (write gate voltage or write inhibit gate voltage) applied from any one of the PMOS switches 8a, 8c,... Or the NMOS switches 9a, 9c,.
- the voltage can be uniformly applied to all the memory cells C arranged in the same row within 2.
- the P-type memory well PW2 is provided with a plurality of first bit lines L1 extending in the column direction and a plurality of second bit lines L2 extending in the column direction.
- the P-type memory well PW2 has a pair of a first bit line L1 and a second bit that run in parallel with a pair of a first bit line L1 and a second bit line L2 adjacent to the first bit line L1.
- a plurality of memory cells C are arranged in parallel between the lines L2.
- Each memory cell C has a first bit line L1 connected to one end and a second bit line L2 connected to the other end.
- the first bit line L1 and the second bit line L2 are connected to one end and the second bit line L2.
- a write voltage or a write inhibit voltage can be applied to the other end.
- Each of the memory cells C has the same configuration, is an N-channel type in which the semiconductor substrate is a P-type memory well PW2, and is formed at a predetermined interval in the P-type memory well PW2 (semiconductor substrate).
- a charge storage layer, an interlayer insulating layer, and a control gate are sequentially stacked via a tunnel insulating layer.
- a first MOS power supply line VL1 and a second MOS power supply line VL2 are provided in parallel in the column direction, and 12 [V The first control voltage of 0 [V] is applied to the second MOS power supply line VL2.
- the first MOS power supply line VL1 and the second MOS power supply line VL2 are provided with a plurality of inverter circuits 11 at a predetermined interval in the column direction, and a common PMOS control line PGa (PGb, PGc) extending in the row direction.
- PGd a common NMOS control line NGa (NGb, NGc, NGd), which is paired with this common PMOS control line PGa (PGb, PGc, PGd) and also extends in the row direction, at the output section of each inverter circuit 11 It is connected.
- the common PMOS control line PGa (PGb, PGc, PGd) is extended so as to cross all the unit columns 2, and PMOS switches 8a, 8b (8c, 8d) arranged in the same row of each unit column 2 ,...), And the output from the inverter circuit 11 can be uniformly applied to the gates of all the PMOS switches 8a, 8b (8c, 8d,...) Arranged in the same row. .
- the PMOS switches 8a and 8b connected to the common PMOS control line PGa are turned on and off by the voltage difference between the common PMOS control line PGa and the first power supply lines 5a and 5b.
- the lines 5a and 5b and the word line 15 can be electrically connected.
- the common NMOS control line NGa (NGb, NGc, NGd) is also extended so as to intersect all the unit columns 2, and the NMOS switches 9a, 9b (9c) arranged in the same row of each unit column 2 , 9d,..., And the output from the inverter circuit 11 can be applied uniformly to the gates of all NMOS switches 9a, 9b (9c, 9d,...) Arranged in the same row. ing.
- each NMOS switch 9a, 9b connected to the common NMOS control line NGa is turned on / off by the voltage difference between the common NMOS control line NGa and the second power supply lines 6a, 6b, and the second power supply is turned on during the on operation.
- the lines 6a and 6b and the word line 15 can be electrically connected.
- the first power supply lines 5a, 5b and the second power supply lines 6a, 6a, 8d are turned on and off by turning on and off the PMOS switches 8a, 8b, 8c, 8d and the NMOS switches 9a, 9b, 9c, 9d.
- the voltage value of the memory cell C can be adjusted by applying the output of 6b to the predetermined word line 15.
- the selected memory cell in the P-type memory well PW2 in the first column Data can be written by accumulating charges only in the charge accumulation layer of C1.
- the state in which charges are accumulated in the charge accumulation layer of the selected memory cell C1 is the state in which data is written, and the state in which no charges are accumulated in the charge accumulation layer.
- the present invention is not limited to this.
- the state in which no charge is accumulated in the charge accumulation layer of the selected memory cell C1 is defined as the data written state, and the charge accumulation layer is charged.
- the state where the data is stored may be the state where the data is erased.
- FIG. 1 is arranged in the first row and first column of the first unit column 2 among the plurality of unit columns 2 in the nonvolatile semiconductor memory device 1.
- the voltage values at the respective locations when the memory cell C is a selected memory cell C1 to which data is written and the memory cells C of all other unit columns 2 are non-selected memory cells C2 are shown.
- the unit column 2 in which the selected memory cell C1 is arranged is called a selected unit column 2a
- the unit column 2 in which only the non-selected memory cell C2 is arranged is called an unselected unit column 2b.
- the power supply unit 4 in the selected unit row 2a is called a selected power supply unit 4a
- the power supply unit 4 in the non-selected unit row 2b is called a non-selected power supply unit 4b.
- the selected memory cell C1 is arranged in the row where the common PMOS control line PGa (PGb, PGc, PGd) and the common NMOS control line NGa (NGb, NGc, NGd) are arranged as the common wiring.
- a row is called a selected row 3a, while a row in which only the non-selected memory cell C2 is arranged in the row is called a non-selected row 3b.
- the unselected unit column Description will be made by paying attention to the order of the third region AR3 in which 2b intersects the selected row 3a and the non-selected row 3b.
- the inverter circuit 11 causes the common PMOS control line PGa and the common NMOS control line NGa to be supplied with 0 [V] in the second MOS power supply line VL2 as a common voltage.
- the second control voltage is applied.
- a write gate voltage charge storage gate voltage
- 12 [V] charge storage gate voltage
- 0 [V] is applied to the second power supply line 6a as a unit voltage.
- the write inhibit gate voltage charge accumulation inhibit gate voltage
- the PMOS switch 8a arranged in the selected row 3a of the selected unit column 2a is applied with the second control voltage of 0 [V] from the common PMOS control line PGa to the gate, and from the first power supply line 5a to the source.
- a 12 [V] write gate voltage is applied to turn on, so that the 12 [V] write gate voltage can be applied from the drain to the selected word line (word line 15 to which the selected memory cell C1 is connected) 15a. Has been made.
- the NMOS switch 9a paired with the PMOS switch 8a is applied with the second control voltage of 0 [V] from the common NMOS control line NGa to the gate,
- a write inhibit gate voltage of 0 [V] is applied from the second power supply line 6a to the source to turn off, and the write inhibit gate voltage of 0 [V] can be cut off.
- a write gate voltage of 12 [V] can be applied to the selected word line 15a in the first area AR1 via the PMOS switch 8a.
- 0 [V] is applied to the P-type memory well PW2 of the selected unit column 2a, and a write voltage of 0 [V] is applied to the selected first bit line L1a and the selected second bit line L2a.
- a write gate voltage of 12 [V] is applied to the control gate from the PMOS switch 8a via the selected word line 15a in the selected memory cell C1 connected to the selected first bit line L1a and the selected second bit line L2a.
- the write voltage of 0 [V] can be applied to one end and the other end from the selected first bit line L1a and the selected second bit line L2a.
- the voltage value of the control gate becomes extremely larger than the voltage value of the channel region, and as a result, a quantum tunnel effect occurs and charges can be injected from the channel region into the charge storage layer. It is made like that.
- the write gate voltage of 12 [V] is applied from the PMOS switch 8a to the control gate via the selected word line 15a, but the unselected first bit Since the write inhibit voltage of 6 [V] is applied to one end and the other end from the line L1b and the non-selected second bit line L2b, the voltage difference between the control gate and the channel region is reduced, and as a result, the quantum tunnel There is no effect, and charge cannot be injected from the channel region into the charge storage layer.
- the PMOS switch 8a is turned on to apply the high write gate voltage to the selected word line 15a, and the charge is generated in the selected memory cell C1 connected to the selected word line 15a. Charges can be injected into the storage layer.
- the inverter circuit 11 causes the first control voltage of 12 [V] in the first MOS power supply line VL1 to be the common PMOS control line PGb (PGc , PGd) and the common NMOS control line NGb (NGc, NGd).
- the first control voltage of 12 [V] is applied from the common PMOS control line PGb to the gate, and the first power supply line 5a.
- the 12 [V] write gate voltage is applied from the source to the source to turn off, and the 12 [V] write gate voltage can be cut off.
- the NMOS switch 9c paired with the PMOS switch 8c in the non-selected row 3b of the selected unit column 2a is supplied with the first control voltage of 12 [V] from the common NMOS control line NGb to the gate, and the second power supply line.
- 6a to the source is applied with a write inhibit gate voltage of 0 [V] to turn on, and the write inhibit gate voltage of 0 [V] is connected to the unselected word line (only unselected memory cell C2) in the second area AR2.
- the applied word line 15) 15c can be applied.
- a write inhibit gate voltage of 0 [V] can be applied to the unselected word line 15c in the second area AR2 via the NMOS switch 9c.
- the non-selected memory cell C2 connected to the non-selected first bit line L1b and the non-selected second bit line L2b is also switched from the non-selected word line 15c to the control gate via the NMOS switch 9c. Since the write inhibit gate voltage of [V] is applied and the write inhibit voltage of 6 [V] is applied to one end and the other end from the unselected first bit line L1b and the unselected second bit line L2b, the control gate In addition, the voltage difference between the channel region and the channel region becomes small. As a result, the quantum tunnel effect does not occur, and charge cannot be injected from the channel region into the charge storage layer.
- the NMOS switch 9c is turned on to apply a low-voltage write inhibit gate voltage to the non-selected word line 15c, and the non-selected memory connected to the non-selected word line 15c. In the cell C2, charge is not injected into the charge storage layer.
- a 6 [V] write inhibit gate voltage charge accumulation inhibit gate voltage
- 12 [V] is applied to the N-type well NW1 in which the first power supply line 5b is formed
- 0 [0] is applied to the P-type well PW1 in which the second power supply line 6b is formed.
- V] is applied.
- the inverter circuit 11 applies the second control voltage of 0 [V] in the second MOS power supply line VL2 to the common PMOS control line PGa and the common NMOS control line NGa. Has been.
- the PMOS switch 8b in the selected row 3a of the non-selected unit column 2b is applied with the second control voltage of 0 [V] from the common PMOS control line PGa to the gate, and from the first power supply line 5b to the source 6 [
- the write inhibit gate voltage of V] is applied to turn on, and the write inhibit gate voltage of 6 [V] can be applied from the drain to the unselected word line 15b.
- the NMOS switch 9b paired with the PMOS switch 8b is applied with the second control voltage of 0 [V] from the common NMOS control line NGa to the gate line, and
- the 6 [V] write inhibit gate voltage is applied from the second power supply line 6 b to the source to turn off, and the 6 [V] write inhibit gate voltage can be cut off.
- a write inhibit gate voltage of 6 [V] can be applied to the unselected word line 15b arranged in the selected row 3a of the third region AR3 via the PMOS switch 8b.
- a write inhibit voltage of 6 [V] is applied to the non-selected first bit line L1c and the non-selected second bit line L2c.
- a 6 [V] write inhibit gate voltage is applied from the unselected word line 15b to the control gate via the PMOS switch 8b.
- the write inhibit voltage of 6 [V] is applied to one end and the other end from the unselected first bit line L1c and the unselected second bit line L2c, the same voltage is applied between the control gate and the channel region. As a result, the quantum tunnel effect does not occur, and charge cannot be injected from the channel region into the charge storage layer.
- the inverter circuit 11 applies the first control voltage of 12 [V] in the first MOS power supply line VL1 to the common PMOS control line PGb and the common NMOS control line NGb.
- the PMOS switch 8d of the non-selected row 3b of the non-selected unit column 2b is applied with the first control voltage of 12 [V] from the common PMOS control line PGb to the gate, and from the first power supply line 5b to the source 6
- the write inhibit gate voltage of [V] is applied to turn off and the 6 [V] write inhibit gate voltage can be cut off.
- the NMOS switch 9d paired with the PMOS switch 8d has a first control voltage of 12 [V] from the common NMOS control line NGb to the gate line.
- 6 [V] write inhibit gate voltage is applied from the second power supply line 6b to the source to turn on, and the 6 [V] write inhibit gate voltage is applied from the drain to the unselected word line 15d.
- a write inhibit gate voltage of 6 [V] can be applied to the non-selected word line 15d arranged in the non-selected row 3b of the third area AR3 via the NMOS switch 9d.
- a write inhibit gate voltage of 6 [V] is applied to the control gate from the NMOS switch 9d via the non-selected word line 15d.
- a write inhibit voltage of 6 [V] is applied to one end and the other end from the non-selected first bit line L1c and the non-selected second bit line L2c, the control gate and the channel region have the same voltage. In this case, charge cannot be injected from the channel region into the charge storage layer without the quantum tunnel effect.
- the non-selected power supply unit 4b is provided with the first power supply line 5b and the second power supply line 6b which are independent from the first power supply line 5a and the second power supply line 6a provided in the selected power supply unit 4a.
- the unselected word lines 15b and 15d in the selected row 3a and the unselected row 3b in the third area AR3 thus, a write inhibit gate voltage of 6 [V] can be applied.
- the third area AR3 is not constrained by the selected unit column 2a, and the write inhibit gate voltage applied to the unselected word lines 15b and 15d, the unselected first bit line L1c, and the unselected second bit line.
- the write inhibit voltage applied to L2c and the voltage applied to the P-type memory well PW2 can all be set at the same voltage of 6 [V].
- the plurality of word lines 15 formed in a matrix, the plurality of memory cells C connected to each word line 15, and the plurality A first bit line L1 and a second bit line L2 capable of applying a selective voltage to the memory cell C, and a plurality of power supply units 4 provided corresponding to each word line column, respectively, and a word line 15
- NMOS switches 9a (9b, 9c, 9d,...) Are provided in each power supply unit 4, respectively.
- common PMOS control lines PGa to PGd and common NMOS control lines NGa to NGd are provided in units of word lines, and PMOSs in the same row are provided by the common PMOS control line PGa (PGb).
- the first PMOS control voltage or the second PMOS control voltage is applied to the switches 8a and 8b (8c and 8d), and the first NMOS control voltage is applied to the NMOS switches 9a and 9b (9c and 9d) in the same row by the common NMOS control line NGa (NGb).
- the second NMOS control voltage is applied.
- the first power supply lines 5a and 5b to which the write gate voltage or the write inhibit gate voltage is applied and the second power supply lines 6a and 6b to which the write inhibit gate voltage is applied are respectively provided.
- a first power supply line 5a, 5b is provided for each power supply unit 4 and connected to the word line 15 via the PMOS switches 8a, 8c,... (8b, 8d,...),
- the second power supply lines 6a, 6b. Are connected to the word line 15 through the NMOS switches 9a, 9c,... (9b, 9d,).
- the PMOS switches 8 a, 8 c,... are written for each power supply unit 4 by the voltage difference between the common PMOS control lines PGa to PGd and the first power supply line 5 a (5 b). (8b, 8d,...) Are turned on and off, and the NMOS switches 9a, 9c,... (9b, 9d,%) Are also turned on / off due to the voltage difference between the common NMOS control lines NGa to NGd and the second power supply line 6a (6b).
- a write gate voltage or a write inhibit gate voltage is individually applied to each P-type memory well PW2.
- the voltage value of the write inhibit gate voltage and the P-type memory at that time are not restricted by the voltage applied to one word line row, but the other word line row.
- the voltage value applied to the well PW2, the voltage values of the unselected first bit line L1c and the unselected second bit line L2c can be freely set to voltage values that can suppress the occurrence of disturbance in the unselected memory cell C2, for example. Can be set.
- the write prohibition gate voltage from the second power supply line 6a to the source.
- the NMOS switch 9a to which the (charge accumulation inhibition gate voltage) is applied is turned off, and the PMOS switch 8a to which the write gate voltage (charge accumulation gate voltage) is applied from the first power supply line 5a to the source is turned on.
- the write gate voltage charge storage gate voltage
- the write-inhibited gate voltage (charge) is applied to the unselected word line 15c in which only the unselected memory cell C2 is arranged.
- the PMOS switch 8c to which the write gate voltage (charge storage gate voltage) is applied from the first power supply line 5a to the source is turned off, and writing is performed from the second power supply line 6a to the source.
- the NMOS switch 9c to which the prohibited gate voltage (charge accumulation prohibited gate voltage) is applied is turned on, the write prohibited gate voltage (charge accumulation prohibited gate voltage) from the drain of the NMOS switch 9c to the unselected word line 15c is turned on. Apply.
- the write gate voltage (charge) is applied to the selected word line 15a in the power supply unit 4 in the other column.
- the PMOS switch 8b When there is a PMOS switch 8b that shares a common PMOS control line PGa and a PMOS switch 8a that applies a storage gate voltage), the PMOS switch 8b is turned on and an NMOS switch 9b that is paired with the PMOS switch 8b is turned off By entering the state, the write inhibit gate voltage (charge accumulation inhibit gate voltage) applied from the first power supply line 5b to the source of the PMOS switch 8b is applied from the drain of the PMOS switch 8b to the unselected word line 15b. .
- charge accumulation inhibit gate voltage charge accumulation inhibit gate voltage
- the write inhibit gate voltage to the unselected word line 15c in the power supply unit 4 in the other column in the non-selected power supply unit 4b having only the non-selected word line in which only the non-selected memory cell C2 is arranged.
- each of the non-selected unit columns 2b in the non-selected unit column 2b is not restricted by the write gate voltage of 12 [V] applied to the selected word line 15a of the selected unit column 2a.
- the write inhibit gate voltage applied to the unselected word lines 15b and 15d can be set to a low voltage of 6 [V], and the voltage value of the P-type memory well PW2, the unselected first bit line L1c, the unselected second Since all the voltage values of the bit line L2c can be set to 6 [V] of the same voltage, even if the data write operation to the selected memory cell C1 is repeated in the selected unit column 2a, each of the unselected unit column 2b It is possible to suppress the occurrence of disturbance without affecting the non-selected memory cell C2.
- the power supply units 4 are common to each other.
- the PMOS switch 8a is connected by the PMOS control lines PGa to PGd and the common NMOS control lines NGa to NGd, and the PMOS switch 8a is adjusted by adjusting the voltage value applied to the common PMOS control lines PGa to PGd and the common NMOS control lines NGa to NGd. , 8c,... (8b, 8d,...) And NMOS switches 9a, 9c,...
- reference numeral 21 denotes a nonvolatile semiconductor memory device according to the second embodiment
- a first PMOS power supply line VL3 and a second PMOS power supply line VL4 are provided in place of the first MOS power supply line VL1 and the second MOS power supply line VL2 shown in FIG. 1
- a first NMOS power supply line VL5 and a second NMOS power supply line VL6 are provided in place of the first MOS power supply line VL1 and the second MOS power supply line VL2 shown in FIG.
- a first PMOS power supply line VL3 and a second PMOS power supply line VL4 and a first NMOS power supply line VL5 and a second NMOS power supply line VL6 are provided. This is different from the nonvolatile semiconductor memory device 1 according to the first embodiment described above.
- the first PMOS power supply line VL3 and the second PMOS power supply line VL4 are extended in the column direction, and run in parallel with the first PMOS power supply line VL3 and the second PMOS power supply line VL4.
- the first NMOS power supply line VL5 and the second NMOS power supply line VL6 are also extended in the column direction.
- a plurality of first inverter circuits 24 are connected to the first PMOS power supply line VL3 and the second PMOS power supply line VL4, and only the common PMOS control lines PGa, PGb, PGc, and PGd are connected to the output portions of the first inverter circuits 24, respectively. Is connected.
- Each first inverter circuit 24 selects, for each row, either the first PMOS control voltage applied to the first PMOS power supply line VL3 or the second PMOS control voltage applied to the second PMOS power supply line VL4. Can be applied to the common PMOS control lines PGa, PGb, PGc, and PGd.
- a plurality of second inverter circuits 25 are also connected to the first NMOS power supply line VL5 and the second NMOS power supply line VL6, and common NMOS control lines NGa, NGb, NGc, NGd are connected to the output portions of the respective second inverter circuits 25. Only connected.
- Each second inverter circuit 25 selects, for each row, either the first NMOS control voltage applied to the first NMOS power supply line VL5 or the second NMOS control voltage applied to the second NMOS power supply line VL6. Can be applied to the common NMOS control lines NGa, NGb, NGc, NGd.
- FIG. 2 data is written in the memory cell C in the first row and the first column in the unit column 2 of the first column among the plurality of memory cells C, as in the first embodiment described above.
- the voltage values at the respective locations when the selected memory cell C1 is used and the memory cells C of all other unit columns 2 are the non-selected memory cells C2 are shown.
- a first PMOS control voltage of 12 [V] is applied to the first PMOS power supply line VL3
- a second PMOS control voltage of 4 [V] is applied to the second PMOS power supply line VL4.
- a first NMOS control voltage of 8 [V] is applied to the first NMOS power supply line VL5, and a second NMOS control voltage of 0 [V] is applied to the second NMOS power supply line VL6.
- a write gate voltage of 12 [V] is applied to the first power supply line 5a as a unit voltage and the other power supply line 6a has a unit voltage of 0 [V to the selected power supply unit 4a in the selected unit row 2a.
- the write inhibit gate voltage is applied.
- the first inverter circuit 24 connected to the first PMOS power supply line VL3 and the second PMOS power supply line VL4 uses 4 [V] in the second PMOS power supply line VL4 as a common voltage.
- the second PMOS control voltage is applied to the common PMOS control line PGa.
- the PMOS switch 8a arranged in the selected row 3a of the selected unit column 2a is applied with the second PMOS control voltage of 4 [V] from the common PMOS control line PGa to the gate, and from the first power supply line 5a to the source.
- a write gate voltage of 12 [V] is applied to turn on, and the write gate voltage of 12 [V] can be applied from the drain to the selected word line 15a.
- a write voltage of 0 [V] is applied to the selected first bit line L1a and the selected second bit line L2a connected to the selected memory cell C1, and the non-selected memory cell C2 is connected.
- a write inhibit voltage of 6 [V] is applied to the unselected first bit line L1b and the unselected second bit line L2b.
- the selected word line 15a is connected to the control gate 12 [ Although a write gate voltage of V] is applied, a write inhibit voltage of 6 [V] is applied to one end and the other end from the non-selected first bit line L1b and the non-selected second bit line L2b.
- V write gate voltage
- 6 [V] write inhibit voltage
- the voltage difference between the channel region and the channel region becomes small. As a result, the quantum tunnel effect does not occur, and charge cannot be injected from the channel region into the charge storage layer.
- the second inverter circuit 25 connected to the first NMOS power supply line VL5 and the second NMOS power supply line VL6 causes the second NMOS control voltage of 0 [V] in the second NMOS power supply line VL6 to be the common voltage.
- the NMOS switch 9a arranged in the selected row 3a of the selected unit column 2a is applied with the second NMOS control voltage of 0 [V] from the common NMOS control line NGa to the gate and from the second power supply line 6a to one end.
- a write inhibit gate voltage of 0 [V] is applied to turn off and the write inhibit gate voltage can be cut off.
- a write gate voltage of 12 [V] can be applied to the selected word line 15a in the first region AR1 via the PMOS switch 8a.
- the nonvolatile semiconductor memory device 21 according to the second embodiment is applied to the gate of the PMOS switch 8a when the PMOS switch 8a is turned on in the selected row 3a of the selected unit column 2a.
- the voltage difference between the second PMOS control voltage (4 [V]) and the write gate voltage (12 [V]) applied to the source can be set to 8 [V] or lower, which is lower than in the first embodiment. It is made like that.
- the first inverter circuit 24 causes the first PMOS control voltage of 12 [V] in the first PMOS power supply line VL3 to be the common PMOS control line.
- the PMOS switch 8c arranged in the non-selected row 3b of the selected unit column 2a is supplied with the first PMOS control voltage of 12 [V] from the common PMOS control line PGb to the gate and from the first power supply line 5a to the source.
- a write gate voltage of 12 [V] is applied to turn off and the write gate voltage can be cut off.
- the second inverter circuit 25 applies the first NMOS control voltage of 8 [V] in the first NMOS power supply line VL5 to the common NMOS control lines NGb, NGc, NGd as a common voltage. .
- the first NMOS control voltage of 8 [V] is applied from the common NMOS control line NGb to the gate, and the source from the second power supply line 6a.
- the write inhibit gate voltage of 0 [V] is applied to the ON state, and the write inhibit gate voltage of 0 [V] can be applied from the drain to the unselected word line 15c.
- the NMOS switch 9c when the NMOS switch 9c is turned on in the non-selected row 3b of the selected unit column 2a, the first applied to the gate in the NMOS switch 9c.
- the voltage difference between the 1NMOS control voltage (8 [V]) and the write inhibit gate voltage (0 [V]) applied to the source can be set to 8 [V] or less, which is lower than in the first embodiment. It is made like that.
- the non-selected memory cell C2 connected to the selected first bit line L1a and the selected second bit line L2a has one end from the selected first bit line L1a and the selected second bit line L2a, and although the write voltage of 0 [V] is applied to the other end, the write gate voltage of 0 [V] is similarly applied to the control gate from the non-selected word line 15c via the NMOS switch 9c. As a result, the quantum voltage is not generated between the channel region and the channel region, and charge cannot be injected from the channel region to the charge storage layer.
- the PMOS switch 8b arranged in the selected row 3a of the non-selected unit column 2b is supplied with the second PMOS control voltage of 4 [V] from the common PMOS control line PGa to the gate, and from the first power supply line 5b to the source.
- a write inhibit gate voltage of 6 [V] is applied to turn on, and the write inhibit gate voltage can be applied from the drain to the unselected word line 15b.
- a write inhibit voltage of 6 [V] is applied to the non-selected first bit line L1c and the non-selected second bit line L2c.
- a write voltage of 6 [V] is applied to one end and the other end from the non-selected first bit line L1c and the non-selected second bit line L2c.
- a 6 [V] write inhibit gate voltage is applied to the control gate from the unselected word line 15b via the PMOS switch 8b, so that the voltage between the control gate and the channel region becomes the same. The quantum tunnel effect does not occur, and charge cannot be injected from the channel region into the charge storage layer.
- the NMOS switch 9b arranged in the selected row 3a of the non-selected unit column 2b receives the second NMOS control voltage of 0 [V] from the common NMOS control line NGa to the gate, and from the second power supply line 6b to the source.
- a 6 [V] write inhibit gate voltage is applied to turn off, and the write inhibit gate voltage can be cut off.
- the write-inhibited gate voltage of 6 [V] can be applied to the unselected word line 15b arranged in the selected row 3a of the third area AR3 via the PMOS switch 8b.
- the first inverter circuit 24 applies a 12 [V] first PMOS control voltage in the first PMOS power supply line VL3 to the common PMOS control lines PGb, PGc, and PGd.
- the PMOS switch 8d arranged in the non-selected row 3b of the non-selected unit column 2b is applied with the first PMOS control voltage of 12 [V] from the common PMOS control lines PGb, PGc, PGd to the gate, and the first A 6 [V] write inhibit gate voltage is applied from the power supply line 5b to the source to turn it off so that the write inhibit gate voltage can be cut off.
- the first NMOS control voltage of 8 [V] in the first NMOS power supply line VL5 is applied to the common NMOS control lines NGb, NGc, and NGd by the second inverter circuit 25.
- the first NMOS control voltage of 8 [V] is applied from the common NMOS control line NGb (NGc, NGd) to the gate, and the first A 6 [V] write inhibit gate voltage is applied from the two power supply lines 6b to the source to turn it on, so that the write inhibit gate voltage can be applied to the unselected word line 15d.
- a write inhibit gate voltage of 6 [V] can be applied to the non-selected word line 15d arranged in the non-selected row 3b of the third area AR3 via the NMOS switch 9d.
- nonvolatile semiconductor memory device 21 in the nonvolatile semiconductor memory device 21 according to the second embodiment, data is written only in the selected memory cell C1 of the first selected unit column 2a among the plurality of memory cells C, Data may not be written to all the non-selected memory cells C2 in the non-selected unit column 2b other than.
- FIG. 3 shows the nonvolatile semiconductor memory device 27 according to the second embodiment that performs the data erasing operation.
- the voltage values at the respective locations when the data of all the memory cells C in the area AR1 are erased and the data of all the other memory cells C are not erased are shown.
- a first PMOS control voltage of 10 [V] different from that at the time of data writing is applied to the first PMOS power line VL3, and the same 4 [V] as at the time of data writing is applied to the second PMOS power line VL4.
- a second PMOS control voltage is applied.
- the same first NMOS control voltage of 8 [V] as that at the time of data writing is applied to the first NMOS power line VL5, and the same 0 [V] as that at the time of data writing is also applied to the second NMOS power line VL6. 2NMOS control voltage is applied.
- the description will be given first focusing on the first area AR1, and then in the order of the second area AR2 and the third area AR3.
- the selected power supply unit 4a of the selected unit column 2a in which the memory cell C3 for erasing data (hereinafter referred to as an erased memory cell) C3 is arranged has 10 [V] non-erased on the first power supply line 5a.
- a gate voltage is applied, and an erase gate voltage of 0 [V] is applied to the other second power supply line 6a.
- the first PMOS control voltage of 10 [V] in the first PMOS power supply line VL3 is set to the common PMOS control by the first inverter circuit 24 connected to the first PMOS power supply line VL3 and the second PMOS power supply line VL4. Applied to the line PGa.
- the PMOS switch 8a arranged in the selected row 3a of the selected unit column 2a is applied with the first PMOS control voltage of 10 [V] from the common PMOS control line PGa to the gate, and from the first power supply line 5a to the source.
- a non-erasable gate voltage of 10 [V] is applied to turn off and the non-erasable gate voltage can be cut off.
- the second NMOS circuit 25 connected to the first NMOS power supply line VL5 and the second NM power supply line VL6 causes the first NMOS control voltage of 8 [V] in the first NMOS power supply line VL5 to be the common NMOS control line.
- the NMOS switch 9a arranged in the selected row 3a of the selected unit column 2a is applied with the first NMOS control voltage of 8 [V] from the common NMOS control line NGa to the gate, and from the second power supply line 6a to the source.
- An erase gate voltage of 0 [V] is applied to turn on, and the erase gate voltage can be applied from the drain to the selected word line 15a.
- an erase gate voltage of 0 [V] can be applied to the selected word line 15a in the first area AR1 via the NMOS switch 9a.
- 10 [V] is applied to the P-type memory well PW2 in which a plurality of memory cells C are formed, and the selection first bit line L1d and the selection second bit line L2d are applied.
- An erase voltage of 10 [V] is applied.
- an erase gate voltage of 0 [V] is applied from the selected word line 15a to the control gate to each erase memory cell C3 in the first region AR1, and the selected first bit line L1d and the selected second bit line L2d.
- An erasing voltage of 10 [V] can be applied to one end and the other end.
- the voltage value on the channel region side becomes extremely larger than the voltage value on the control gate side, and the charge accumulated in the charge accumulation layer is drawn into the channel region having a high voltage, Data can be erased by removing charges from the storage layer.
- the first inverter circuit 24 causes 4 [V] of the second PMOS power supply line VL4 to The second PMOS control voltage is applied to the common PMOS control lines PGb, PGc, and PGd.
- the PMOS switch 8c arranged in the non-selected row 3b of the selected unit column 2a is supplied with the second PMOS control voltage of 4 [V] from the common PMOS control line PGb to the gate, and from the first power supply line 5a to the source. Then, a non-erasable gate voltage of 10 [V] is applied to turn on, and this non-erasable gate voltage can be applied from the drain to the unselected word line 15c.
- the PMOS switch 8c is turned on. Since a non-erasable gate voltage of 10 [V] is applied to the control gate from the unselected word line 15c, the voltage between the control gate and the channel region becomes the same, and as a result, charges are extracted from the charge storage layer. Without any problem, the charge state in the charge storage layer can be maintained.
- the second NMOS circuit 25 applies the second NMOS control voltage of 0 [V] in the second NMOS power supply line VL6 to the common NMOS control lines NGb, NGc, and NGd.
- each NMOS switch 9c arranged in the non-selected row 3b of the selected unit column 2a is applied with the second NMOS control voltage of 0 [V] from the common NMOS control line NGb to the gate, and from the second power supply line 6a.
- An erase gate voltage of 0 [V] is applied to the source to turn off, and the erase gate voltage of 0 [V] can be cut off.
- a non-erasable gate voltage of 10 [V] can be applied to the non-selected word line 15c in the second area AR2 via the PMOS switch 8c.
- the PMOS switch 8b arranged in the selected row 3a of the non-selected unit column 2b is applied with the first PMOS control voltage of 10 [V] from the common PMOS control line PGa to the gate, and the source from the first power supply line 5b.
- a non-erasable gate voltage of 6 [V] is applied to turn off and the non-erasable gate voltage can be cut off.
- the second NMOS circuit 25 applies the first NMOS control voltage of 8 [V] in the first NMOS power supply line VL5 to the common NMOS control line NGa.
- the NMOS switch 9b arranged in the selected row 3a of the non-selected unit column 2b is supplied with the first NMOS control voltage of 8 [V] from the common NMOS control line NGa to the gate, and from the second power supply line 6b to the source.
- a non-erasable gate voltage of 6 [V] is applied to turn on, and the non-erasable gate voltage can be applied from the drain to the unselected word line 15b.
- a non-erasable gate voltage of 6 [V] can be applied to the non-selected word line 15b arranged in the selected row 3a in the third area AR3 via the NMOS switch 9b. ing.
- a non-erasing voltage of 6 [V] is applied to the non-selected first bit line L1e and the non-selected second bit line L2e, respectively.
- the non-erased voltage of 6 [V] from the non-selected first bit line L1e and the non-selected second bit line L2e is once applied to the non-erased memory cell C4 arranged in the selected row 3a of the third area AR3.
- a non-erase gate voltage of 6 [V] can be applied to the control gate from the non-selected word line 15b via the NMOS switch 9b.
- the non-erasable memory cell C4 arranged in the selected row 3a of the third region AR3 has the same voltage between the control gate and the channel region. As a result, charge is not extracted from the charge storage layer, and charge storage is performed. The charge state in the layer can be maintained.
- the first inverter circuit 24 applies the 4 [V] second PMOS control voltage in the second PMOS power supply line VL4 to the common PMOS control lines PGb, PGc, and PGd.
- the PMOS switch 8d arranged in the non-selected row 3b of the non-selected unit column 2b is applied with the second PMOS control voltage of 4 [V] from the common PMOS control line PGb to the gate, and from the first power supply line 5b.
- a non-erasable gate voltage of 6 [V] is applied to the source to turn it on, and the non-erasable gate voltage can be applied from the drain to the unselected word line 15d.
- the non-erased memory cell C4 arranged in the non-selected row 3b of the third area AR3 has 6 [V] at one end and the other end from the non-selected first bit line L1e and the non-selected second bit line L2e.
- a non-erasing voltage can be applied, and a non-erasing gate voltage of 6 [V] can be applied from the unselected word line 15d to the control gate via the PMOS switch 8d.
- the non-erasable memory cell C4 in the non-selected row 3b in the third region AR3 has the same voltage between the control gate and the channel region. As a result, the charge is not extracted from the charge storage layer, and the charge storage layer The charge state can be maintained.
- the second NMOS control voltage of 0 [V] in the second NMOS power supply line VL6 is applied to the common NMOS control lines NGb, NGc, and NGd by the second inverter circuit 25.
- each NMOS switch 9d arranged in the non-selected row 3b of the non-selected unit column 2b is applied with the second NMOS control voltage of 0 [V] from the common NMOS control line NGb to the gate, and the second power supply line 6b.
- the erase gate voltage of 6 [V] is applied from the source to the source to be turned off so that the erase gate voltage can be cut off.
- a non-erasable gate voltage of 6 [V] can be applied to the non-selected word line 15d arranged in the non-selected row 3b of the third area AR3 via the PMOS switch 8d. ing.
- the nonvolatile semiconductor memory device 27 can collectively erase only the data of the erase memory cell C3 arranged in the selected row 3a of the selected unit column 2a by adjusting the voltage value of each location. Has been made.
- this nonvolatile semiconductor memory device 21 can also obtain the same effect as that of the first embodiment described above. That is, even in the nonvolatile semiconductor memory device 21, for example, the unselected word line 15b of the unselected unit column 2b is not restricted by the write gate voltage of 12 [V] applied to the selected word line 15a of the selected unit column 2a.
- 15d can be set to 6 [V], and the voltage value of the P-type memory well PW2 and the voltage values of the unselected first bit line L1c and the unselected second bit line L2c Since all can be set to the same voltage, even if the data write operation to the selected memory cell C1 is repeated in the selected unit column 2a, the occurrence of disturbance in each unselected memory cell C2 in the unselected unit column 2b is suppressed. obtain.
- the first power supply lines 5 a and 5 b and the second power supply lines 6 a and 6 b are individually provided for each power supply unit 4, but a common PMOS control line is provided between the power supply units 4.
- PGa to PGd and common NMOS control lines NGa to NGd are connected, and by adjusting the voltage values applied to these common PMOS control lines PGa to PGd and common NMOS control lines NGa to NGd, The PMOS switches 8a, 8b, 8c, 8d,... And the NMOS switches 9a, 9b, 9c, 9d,... Can be turned on / off to selectively determine the selected word line 15a from the plurality of word lines 15.
- the control voltage of either the first PMOS power supply line VL3 or the second PMOS power supply line VL4 (first PMOS control voltage or second PMOS control voltage).
- first PMOS control voltage or second PMOS control voltage are applied to the PMOS switches 8a, 8b, 8c, 8d,... Via the common PMOS control lines PGa to PGd, and separately from this, control of either the first NMOS power supply line VL5 or the second NMOS power supply line VL6.
- a voltage (first NMOS control voltage or second NMOS control voltage) is applied to each NMOS switch 9a, 9b, 9c, 9d,... Via the common NMOS control lines NGa to NGd.
- the control voltage for turning on / off the NMOS switches 9a, 9b, 9c, 9d,... Is freely set without being restricted by the control voltage required for turning on / off the PMOS switches 8a, 8b, 8c, 8d,.
- the common PMOS control lines PGa to PGd and the common NMOS control lines NGa to NGd have full amplitude. Since there is a voltage difference of 12 [V] (12 [V] / 0 [V]), the PMOS switches 8a, 8b, 8c, 8d,... And the NMOS switches 9a, 9b, 9c, 9d,. A withstand voltage structure for a voltage difference of 12 [V] is required.
- the PMOS switches 8a, 8b, 8c, 8d if the allowable electric field of the gate insulating film is 7 [MV / cm], the PMOS switches 8a, 8b, 8c, 8d,. It was also necessary to use 9a, 9b, 9c, 9d, ...
- the difference is 8 [V] or less, and in the same way as the PMOS switches 8a, 8b, 8c, 8d,... And the NMOS switches 9a, 9b, 9c, 9d,. It can be a structure.
- the non-selected power supply unit 4b when data is written, 12 [V] is applied to the N-type well NW1 in which the PMOS switches 8b, 8d,... Are formed, but the PMOS switches 8b, 8d,.
- a non-selected word line 15b, 15d,... Connected to the drain is applied with a 6 [V] write inhibit gate voltage having a slightly high voltage value, and the drains of these PMOS switches 8b, 8d,. Since the voltage difference with the well NW1 is made relatively small at 6 [V], the voltage burden on the PMOS switches 8b, 8d,... Is reduced correspondingly, and the reliability of the PMOS switches 8b, 8d,. Can be improved.
- reference numeral 31 denotes a nonvolatile semiconductor memory device according to the third embodiment
- Switches 36a, 36c,... (36b, 36d,%) Are provided in each power supply unit 34, and when data is written, 0 [V] is written to each unselected word line 15b, 15d,. .. Is different from the nonvolatile semiconductor memory device 21 according to the second embodiment described above in that the forbidden gate voltage is applied by the auxiliary NMOS switches 36b, 36d,.
- the nonvolatile semiconductor memory device 31 has such a configuration, so that these PMOS switches 8a, 8c,... (8b, 8d,%) And NMOS switches 9a, 9c ,... (9b, 9d,%) Can be set to 6 [V] or less, which is much lower than that of the second embodiment. ing.
- FIG. 4 shows the first row and first column in the unit column 32 of the first column among the plurality of memory cells C, similarly to the nonvolatile semiconductor memory device 21 according to the second embodiment described above.
- the voltage values at the respective locations when the memory cell C is a selected memory cell C1 to which data is written and the memory cells C of all other unit columns 32 are non-selected memory cells C2 are shown.
- the first PMOS control voltage of 12 [V] is applied to the first PMOS power supply line VL3 as in the second embodiment described above, but the second PMOS power supply line VL4 is applied to the second PMOS power supply line VL4.
- a second PMOS control voltage of 6 [V] higher than that of the embodiment is applied, and the voltage difference between the first PMOS control voltage and the second NMOS control voltage is smaller than that of the second embodiment described above. V].
- the common PMOS control lines PGa to PGd connected to the first PMOS power line VL3 and the second PMOS power line VL4 via the first inverter circuit 24 are connected to the non-selected row 3b by the first inverter circuit 24.
- the first PMOS control voltage of 12 [V] is applied
- the second PMOS control voltage of 6 [V] may be applied when the selected row 3a.
- the common PMOS control lines PGa to PGd are set to have a voltage amplitude of 6 [V] (that is, 12 [V] -6 [V]) between the selected row 3a and the unselected row 3b. The voltage amplitude is reduced.
- the second NMOS power supply line VL6 is applied with the second NMOS control voltage of 0 [V] as in the second embodiment, but the first NMOS power supply line VL5 has the above-mentioned.
- a first NMOS control voltage of 6 [V] lower than that in the second embodiment is applied, and the voltage difference between the first NMOS control voltage and the second NMOS control voltage is larger than that in the second embodiment described above. It is a small 6 [V].
- the common NMOS control lines NGa to NGd connected to the first NMOS power line VL5 and the second NMOS power line VL6 via the second inverter circuit 25 are connected to the non-selected row 3b by the second inverter circuit 25.
- the first NMOS control voltage of 6 [V] is applied
- the second NMOS control voltage of 0 [V] may be applied when the selected row 3a.
- the common NMOS control lines NGa to NGd are set to have a voltage amplitude of 6 [V] (ie, 6 [V] -0 [V]) between the selected row 3a and the unselected row 3b. Therefore, the amplitude of the voltage amplitude is reduced.
- the P-type well PW1 in which the NMOS switches 9a, 9c,... (9b, 9d,...) Are formed is associated with the NMOS switches 9a, 9c,.
- Auxiliary NMOS switches 36a, 36c,... (36b, 36d,%) Having a transistor structure are formed.
- the P-type well PW1 has an auxiliary MOS power supply extending in the column direction so as to run in parallel with the second power supply line 6a (6b).
- Line 7a (7b) is provided.
- the auxiliary MOS power line 7a (7b) is connected to the control gate of each auxiliary NMOS switch 36a, 36c,... (36b, 36d,...) Disposed in the power supply unit 34, and the auxiliary NMOS switch in these power supply units 34.
- a predetermined auxiliary control voltage can be applied uniformly to 36a, 36c,... (36b, 36d,).
- an auxiliary control voltage of 0 [V] is applied from the auxiliary MOS power line 7a to the gate of the auxiliary NMOS switches 36a, 36c,... Arranged in the selected unit row 32a, while the auxiliary NMOS switches 36a, 36c,.
- an auxiliary control voltage of 6 [V] can be applied to the gate from the auxiliary MOS power line 7b.
- each auxiliary NMOS switch 36a, 36c,... (36b, 36d,...) Has a second power supply line 6a (6b) connected to the source and a word line 15 connected to the drain.
- a write voltage or a write inhibit voltage can be applied to the source from the two power supply lines 6a (6b).
- the selection power supply unit 34a of the selection unit row 32a has a 12 [V] write gate on the first power supply line 5a. A voltage is applied, and a write inhibit gate voltage of 0 [V] is applied to the other second power supply line 6a.
- the 1P inverter circuit 24 applies the second PMOS control voltage of 6 [V] in the second PMOS power supply line VL4 to the common PMOS control line PGa as a common voltage.
- the PMOS switch 8a arranged in the selected row 3a of the selected unit column 32a is applied with the second PMOS control voltage of 6 [V] from the common PMOS control line PGa to the gate, and from the first power supply line 5a to the source.
- the write gate voltage of 12 [V] is applied to turn on, and the write gate voltage of 12 [V] can be applied from the drain to the selected word line 15a.
- the first applied to the gate in the PMOS switch 8a when the PMOS switch 8a is turned on in the selected row 3a of the selection unit column 32a, the first applied to the gate in the PMOS switch 8a.
- the voltage difference between the 2PMOS control voltage (6 [V]) and the write gate voltage (12 [V]) applied to the source can be set to 6 [V] or lower, which is much lower than that of the second embodiment. It is made like that.
- 6 [V] is written from the non-selected first bit line L1b and the non-selected second bit line L2b as in the first embodiment described above. Since the forbidden voltage is applied to one end and the other end, even if a write gate voltage of 12 [V] is applied from the selected word line 15a to the control gate, the voltage difference between the control gate and the channel region is small. The quantum tunnel effect does not occur and charge cannot be injected from the channel region into the charge storage layer.
- the second NMOS control voltage of 0 [V] in the second NMOS power supply line VL6 is applied to the common NMOS control line NGa by the second inverter circuit 25.
- the NMOS switch 9a arranged in the selected row 3a of the selected unit column 32a is applied with the second NMOS control voltage of 0 [V] from the common NMOS control line NGa to the gate, and from the second power supply line 6a to the source.
- a write inhibit gate voltage of 0 [V] is applied to turn off and the write inhibit gate voltage can be cut off.
- an auxiliary control voltage of 0 [V] is applied to the auxiliary MOS power line 7a.
- the auxiliary NMOS switch 36a arranged in the selected row 3a of the selection unit column 32a is applied with the auxiliary control voltage of 0 [V] from the auxiliary MOS power supply line 7a to the gate, and from the second power supply line 6a to the source.
- a write inhibit gate voltage of 0 [V] is applied to turn off and the write inhibit gate voltage can be cut off.
- a write gate voltage of 12 [V] can be applied to the selected word line 15a in the first region AR1 via the PMOS switch 8a.
- the first PMOS control voltage of 12 [V] applied to the first PMOS power supply line VL3 is selected by the first inverter circuit 24, and the first PMOS control voltage is selected as the common PMOS control line PGb, Applied to PGc and PGd.
- the PMOS switch 8c arranged in the non-selected row 3b of the selected unit column 32a is supplied with the first PMOS control voltage of 12 [V] from the common PMOS control line PGb to the gate, and from the first power supply line 5a to the source.
- a write gate voltage of 12 [V] is applied to turn off and the write gate voltage can be cut off.
- the first NMOS control voltage of 6 [V] in the first NMOS power supply line VL5 is applied to the common NMOS control lines NGb, NGc, and NGd by the second inverter circuit 25.
- the NMOS switch 9c arranged in the non-selected row 3b of the selected unit column 32a is applied with the first NMOS control voltage of 6 [V] from the common NMOS control line NGb to the gate, and from the second power supply line 6a to the source.
- the write inhibit gate voltage of 0 [V] is applied to the ON state, and the write inhibit gate voltage of 0 [V] can be applied from the drain to the unselected word line 15c.
- the non-selected memory cell C2 connected to the selected first bit line L1a and the selected second bit line L2a is connected to the selected first bit line L1a and the selected second bit line L2a at one end and Although the write voltage of 0 [V] is applied to the other end, the write inhibit gate voltage of 0 [V] is also applied from the unselected word line 15c to the control gate, so that the control gate and the channel region are the same. As a result, the quantum tunnel effect does not occur, and charge cannot be injected from the channel region into the charge storage layer.
- the non-selected first bit line L1b and the non-selected second bit line L2b are connected to one end and the other end. Since a write inhibit voltage of 6 [V] is applied and a write inhibit gate voltage of 0 [V] is also applied from the unselected word line 15c to the control gate, the voltage difference between the control gate and the channel region is small. As a result, the quantum tunnel effect does not occur, and no charge is injected from the channel region into the charge storage layer, so that data cannot be written.
- the NMOS switch 9c when the NMOS switch 9c is turned on in the non-selected row 3b of the selected unit column 32a, the NMOS switch 9c is applied to the gate.
- the voltage difference between the 1NMOS control voltage (6 [V]) and the write inhibit gate voltage (0 [V]) applied to the source can be set to 6 [V], which is much lower than that of the second embodiment. It is made like that.
- the auxiliary NMOS switch 36c arranged in the non-selected row 3b of the selected unit column 32a is supplied with an auxiliary control voltage of 0 [V] from the auxiliary MOS power line 7a to the gate, and from the second power line 6a to the source.
- a write inhibit gate voltage of 0 [V] is applied to turn off, and the write inhibit gate voltage can be cut off.
- a write inhibit gate voltage of 0 [V] can be applied to the unselected word line 15c in the second region AR2 via the NMOS switch 9c.
- the third area AR3 in the non-selected unit row 32b attention is focused on the third area AR3 in the non-selected unit row 32b.
- the off-voltage of 6 [V] is applied to the first power supply line 5b and the non-selected power supply unit 34b of the non-selected unit row 32b is applied to the other second power supply line 6b.
- a voltage is applied.
- the first inverter circuit 24 applies the second PMOS control voltage of 6 [V] in the second PMOS power supply line VL4 to the common PMOS control line PGa.
- the PMOS switch 8b arranged in the selected row 3a of the non-selected unit column 32b is applied with the second PMOS control voltage of 6 [V] from the common PMOS control line PGa to the gate, and the source from the first power supply line 5b.
- an off voltage of 6 [V] is applied to the off state, so that the off voltage can be cut off.
- the second NMOS control voltage of 0 [V] in the second NMOS power supply line VL6 is applied to the common NMOS control line NGa by the second inverter circuit 25.
- the NMOS switch 9b arranged in the selected row 3a of the non-selected unit column 32b receives the second NMOS control voltage of 0 [V] from the common NMOS control line NGa to the gate and the source from the second power supply line 6b.
- the write inhibit gate voltage of 0 [V] is applied to the transistor in the off state, so that the write inhibit gate voltage can be cut off.
- an auxiliary control voltage of 6 [V] is applied to the auxiliary MOS power line 7b.
- the auxiliary NMOS switch 36b arranged in the selected row 3a of the non-selected unit column 32b is supplied with the auxiliary control voltage of 6 [V] from the auxiliary MOS power supply line 7b to the gate, and from the second power supply line 6b to the source.
- the write inhibit gate voltage of 0 [V] is applied to the ON state, and the write inhibit gate voltage can be applied from the drain to the unselected word line 15b.
- a write inhibit gate voltage of 0 [V] can be applied to the unselected word line 15b in the selected row 3a of the third area AR3 via the auxiliary NMOS switch 36b.
- a write inhibit voltage of 0 [V] is applied to the non-selected first bit line L1c and the non-selected second bit line L2c in the non-selected unit column 32b.
- 0 [V] is also applied to the P-type memory well PW2.
- the first inverter circuit 24 applies a 12 [V] first PMOS control voltage in the first PMOS power supply line VL3 to the common PMOS control lines PGb, PGc, and PGd.
- the PMOS switch 8d arranged in the non-selected row 3b of the non-selected unit column 32b is applied with the first PMOS control voltage of 12 [V] from the common PMOS control line PGb to the gate, and from the first power supply line 5b.
- An off voltage of 6 [V] is applied to the source to enter an off state, and the off voltage can be cut off.
- the second NMOS circuit 25 applies the first NMOS control voltage of 6 [V] in the first NMOS power supply line VL5 to the common NMOS control lines NGb, NGc, and NGd.
- the NMOS switch 9d arranged in the non-selected row 3b of the non-selected unit column 32b is applied with the first NMOS control voltage of 6 [V] from the common NMOS control line NGb to the gate, and from the second power supply line 6b.
- a 0 [V] write inhibit gate voltage is applied to the source to turn it on, and the write inhibit gate voltage can be applied from the drain to the unselected word line 15d.
- the auxiliary NMOS switch 36d arranged in the non-selected row 3b of the non-selected unit column 32b is supplied with an auxiliary control voltage of 6 [V] from the auxiliary MOS power line 7b to the gate and is supplied from the second power line 6b. Then, a write inhibit gate voltage of 0 [V] is applied to the ON state, and the write inhibit gate voltage can be applied from the drain to the non-selected word line 15d. Thus, a write inhibit gate voltage of 0 [V] can be applied to the non-selected word line 15d of the non-selected row 3b in the third area AR3 via the NMOS switch 9d and the auxiliary NMOS switch 36d. .
- the nonvolatile semiconductor memory device 31 when the NMOS switch 9d,... Is turned on in the non-selected row 3b of the non-selected unit column 32b, the NMOS switch 9d,.
- the voltage difference between the first NMOS control voltage (6 [V]) applied to the gate and the write inhibit gate voltage (0 [V]) applied to the source is much lower than that of the second embodiment. V] can be set.
- the non-volatile semiconductor storage device 31 is configured such that when the auxiliary NMOS switches 36b, 36d,... Are turned on in the non-selected unit row 32b, the auxiliary NMOS switches 36b, 36d,.
- the voltage difference between the control voltage (6 [V]) and the write inhibit gate voltage (0 [V]) applied to the source can be set to 6 [V].
- the operation of the switching mechanism will be summarized.
- the selected power supply unit 34a to which the selected word line 15a having the selected memory cell C1 is connected the write-prohibited gate voltage from the second power supply line 6a to the source.
- the PMOS switch to which the NMOS switch 9a and the auxiliary NMOS switch 36a to which the (charge accumulation prohibiting gate voltage) is applied is turned off and the write gate voltage (charge accumulation gate voltage) is applied from the first power supply line 5a to the source.
- a write gate voltage charge storage gate voltage
- the write-inhibited gate voltage (charge) is applied to the unselected word line 15c in which only the unselected memory cell C2 is arranged.
- the PMOS switch 8c in which the write gate voltage (charge storage gate voltage) is applied from the first power supply line 5a to the source, and the write prohibition gate voltage (from the second power supply line 6a to the source).
- the auxiliary NMOS switch 36c to which the charge accumulation inhibiting gate voltage is applied is turned off, and the NMOS switch 9c to which the write inhibiting gate voltage (charge accumulation inhibiting gate voltage) is applied from the second power supply line 6a to the source By turning on, the write-inhibited gate voltage (charge accumulation-inhibited gate voltage) from the drain of the NMOS switch 9c to the unselected word line 15c It is applied to.
- the write gate voltage (charge) is applied to the selected word line 15a by the power supply unit 34 in the other column.
- the write-inhibited gate voltage to the unselected word line 15c in the power supply unit 34 in the other column When there is an NMOS switch 9d sharing the common NMOS control line NGb with the NMOS switch 9c to which (charge accumulation inhibition gate voltage) is applied, the NMOS switch 9d and the auxiliary NMOS switch 36d are turned on, and are paired with this.
- the write inhibit gate voltage charge accumulation inhibit gate voltage
- the write inhibit gate voltage charge accumulation inhibit gate voltage
- the auxiliary NMOS switch 36d is changed to the NMOS switch 9d and The voltage is applied from the drain of the auxiliary NMOS switch 36d to the unselected word line 15d.
- FIG. 5 shows the nonvolatile semiconductor memory device 38 according to the third embodiment when performing a data erasing operation.
- the voltage values at the respective locations when the data of all the memory cells C in the first area AR1 are erased and the data are not erased for all other memory cells C are shown.
- a first PMOS control voltage of 10 [V] is applied to the first PMOS power supply line VL3
- a second PMOS control voltage of 8 [V] is applied to the second PMOS power supply line VL4.
- a first NMOS control voltage of 4 [V] is applied to the first NMOS power supply line VL5, and a second NMOS control voltage of 0 [V] is applied to the second NMOS power supply line VL6.
- the first PMOS control voltage of 10 [V] in the first PMOS power supply line VL3 is set to the common PMOS control by the first inverter circuit 24 connected to the first PMOS power supply line VL3 and the second PMOS power supply line VL4. Applied to the line PGa.
- the PMOS switch 8a arranged in the selection row 3a of the selection unit column 32a is applied with the first PMOS control voltage of 10 [V] from the common PMOS control line PGa to the gate, and from the first power supply line 5a to the source.
- a non-erasable gate voltage of 10 [V] is applied to turn off and the non-erasable gate voltage can be cut off.
- the first NMOS control voltage of 4 [V] in the first NMOS power supply line VL5 is applied to the common NMOS control line NGa by the second inverter circuit 25.
- the NMOS switch 9a arranged in the selected row 3a of the selected unit column 32a is supplied with the first NMOS control voltage of 4 [V] from the common NMOS control line NGa to the gate, and from the second power supply line 6a to the source.
- the erase gate voltage of 0 [V] is applied to turn on, and the erase gate voltage of 0 [V] can be applied from the drain to the selected word line 15a.
- 10 [V] is applied to the P-type memory well PW2 in which a plurality of memory cells C are formed, and the selection first bit line L1d and the selection second bit line L2d are applied.
- An erase voltage of 10 [V] is applied.
- an erase gate voltage of 0 [V] is applied from the selected word line 15a to the control gate to each erase memory cell C3 in the first region AR1, and the selected first bit line L1d and the selected second bit line L2d.
- An erasing voltage of 10 [V] can be applied to one end and the other end.
- the voltage value on the channel region side becomes higher than the voltage value on the control gate side, and the charge accumulated in the charge accumulation layer is drawn into the channel region having a high voltage, and the charge accumulation Data can be erased by removing charges from the layer.
- an auxiliary control voltage of 0 [V] is applied to the auxiliary MOS power line 7a.
- the auxiliary NMOS switch 36a arranged in the selected row 3a of the selection unit column 32a is applied with the auxiliary control voltage of 0 [V] from the auxiliary MOS power supply line 7a to the gate, and from the second power supply line 6a to the source.
- An erase gate voltage of 0 [V] is applied to turn off, and the erase gate voltage can be cut off.
- an erase gate voltage of 0 [V] can be applied to the selected word line 15a in the first area AR1 via the NMOS switch 9a.
- the first PMOS circuit 24 applies the second PMOS control voltage of 8 [V] in the second PMOS power supply line VL4 to the common PMOS control lines PGb, PGc, and PGd.
- the PMOS switch 8c arranged in the non-selected row 3b of the selected unit column 32a is supplied with the second PMOS control voltage of 8 [V] from the common PMOS control line PGb to the gate, and from the first power supply line 5a to the source.
- a non-erasable gate voltage of 10 [V] is applied to turn on, and this non-erasable gate voltage can be applied from the drain to the unselected word line 15c.
- the non-erased memory cell C4 arranged in the non-selected row 3b of the selected unit column 32a is applied with the erase voltage of 10 [V] from the selected first bit line L1d and the selected second bit line L2d.
- 10 [V] non-erasable gate voltage is applied to the control gate from the non-selected word line 15c via the PMOS switch 8c, so that the voltage between the control gate and the channel region becomes the same, and as a result, the charge storage layer The charge state in the charge storage layer can be maintained without the charge being extracted from the inside.
- the second NMOS circuit 25 applies the second NMOS control voltage of 0 [V] in the second NMOS power supply line VL6 to the common NMOS control lines NGb, NGc, and NGd.
- the NMOS switch 9c arranged in the non-selected row 3b of the selected unit column 32a is applied with the second NMOS control voltage of 0 [V] from the common NMOS control line NGb to the gate, and from the second power supply line 6a to the source.
- an erase gate voltage of 0 [V] is applied to the transistor in an off state so that the erase gate voltage can be cut off.
- the auxiliary NMOS switch 36c arranged in the non-selected row 3b of the selected unit column 32a is applied with the auxiliary control voltage of 0 [V] from the auxiliary MOS power line 7a to the gate, and the second power line.
- An erase gate voltage of 0 [V] is applied from 6a to the source to turn off, and the erase gate voltage can be cut off.
- a non-erasable gate voltage of 10 [V] can be applied to the unselected word line 15c in the second area AR2 via the PMOS switch 8c.
- the PMOS switch 8b arranged in the selected row 3a of the non-selected unit column 32b is applied with the first PMOS control voltage of 10 [V] from the common PMOS control line PGa to the gate, and the source from the first power supply line 5b.
- an off voltage of 8 [V] is applied to the off state, and the off voltage can be cut off.
- the second inverter circuit 25 applies the first NMOS control voltage of 4 [V] in the first NMOS power supply line VL5 to the common NMOS control line NGa.
- the NMOS switch 9b arranged in the selected row 3a of the non-selected unit column 32b is supplied with the first NMOS control voltage of 4 [V] from the common NMOS control line NGa to the gate, and from the second power supply line 6b to the source.
- a non-erasable gate voltage of 4 [V] is applied to turn off and the non-erasable gate voltage can be cut off.
- an auxiliary control voltage of 6 [V] is applied to the auxiliary MOS power supply line 7b.
- the auxiliary NMOS switch 36b arranged in the selected row 3a of the non-selected unit column 32b is supplied with the auxiliary control voltage of 6 [V] from the auxiliary MOS power supply line 7b to the gate, and from the second power supply line 6b to the source.
- a non-erasable gate voltage of 4 [V] is applied to turn on and the non-erasable gate voltage can be applied from the drain to the non-selected word line 15b.
- a non-erasable gate voltage of 4 [V] can be applied to the non-selected word line 15b arranged in the selected row 3a of the third area AR3 via the auxiliary NMOS switch 36b.
- the unselected unit column 32b 4 [V] is applied to the P-type memory well PW2, and 6 [V] is not applied to the unselected first bit line L1e and the unselected second bit line L2e.
- An erase voltage is applied.
- the non-erased memory cell C4 arranged in the selected row 3a of the third region AR3 has a non-selected first bit line L1e and a non-selected second bit line L2e at one end and the other end of 6 [V].
- An erasing voltage is applied, and a non-erasing gate voltage of 4 [V] can be applied from the unselected word line 15b to the control gate via the auxiliary NMOS switch 36b.
- the non-erasable memory cell C4 arranged in the selected row 3a of the third region AR3 has a small voltage difference between the control gate and the channel region, so that charge is not drawn out from the charge storage layer, and charge storage is performed. The charge state in the layer can be maintained.
- the first inverter circuit 24 applies the second PMOS control voltage of 8 [V] in the second PMOS power supply line VL4 to the common PMOS control lines PGb, PGc, and PGd.
- the PMOS switch 8d arranged in the non-selected row 3b of the non-selected unit column 32b is applied with the second PMOS control voltage of 8 [V] from the common PMOS control line PGb to the gate, and from the first power supply line 5b.
- An off voltage of 8 [V] is applied to the source so that the source is turned off, and the off voltage can be cut off.
- the second inverter circuit 25 causes the second NMOS control voltage of 0 [V] in the second NMOS power supply line VL6 to be applied to the common NMOS control lines NGb, NGc, NGd. Applied.
- the NMOS switch 9d disposed in the non-selected row 3b of the non-selected unit column 32b is applied with the second NMOS control voltage of 0 [V] from the common NMOS control line NGb to the gate, and from the second power supply line 6b.
- a non-erasable gate voltage of 4 [V] is applied to the source to turn off the non-erasable gate voltage.
- auxiliary control voltage of 6 [V] is applied from the auxiliary MOS power line 7b to the gate, and the second power line
- a non-erasable gate voltage of 4 [V] is applied from 6b to the source to turn it on, and the non-erasable gate voltage can be applied from the drain to the unselected word line 15d.
- a non-erasable gate voltage of 4 [V] can be applied to the non-selected word line 15d arranged in the non-selected row 3b of the third area AR3 via the auxiliary NMOS switch 36d.
- the non-erased memory cell C4 arranged in the non-selected row 3b of the third area AR3 has 6 [V] at one end and the other end from the non-selected first bit line L1e and the non-selected second bit line L2e.
- a non-erasing voltage can be applied, and a non-erasing gate voltage of 4 [V] can be applied from the unselected word line 15d to the control gate via the auxiliary NMOS switch 36d.
- the non-erasable memory cell C4 arranged in the non-selected row 3b of the third region AR3 has a small voltage difference between the control gate and the channel region, so that the charge is not extracted from the charge storage layer. The charge state in the storage layer can be maintained.
- the nonvolatile semiconductor memory device 38 includes the first PMOS power line VL3, the second PMOS power line VL4, the first NMOS power line VL5, the second NMOS power line VL6, the first power lines 5a and 5b, and the second power line 6a. , 6b, auxiliary MOS power supply lines 7a, 7b, first bit line L1, second bit line L2, etc., by adjusting the voltage value at each location, for example, erase memory cells arranged in selected row 3a of selected unit column 32a Only C3 can be erased.
- reference numeral 41 denotes a nonvolatile semiconductor memory device according to the fourth embodiment
- auxiliary PMOS switches 46a, 46c,... (46b, 46d,... (46b, 46d,...) are replaced with the auxiliary NMOS switches 36a, 36c,.
- the non-selected unit column 42b applies a 12 [V] write inhibit gate voltage to each non-selected word line 15b, 15d,... By the auxiliary PMOS switches 46b, 46d,.
- the N-type well NW1 of the power supply unit 44 is associated with the PMOS switches 8a, 8c,... (8b, 8d,...), And the auxiliary PMOS switches 46a, 46c,. 7) is formed.
- the N-type well NW1 includes an auxiliary MOS power supply extending in the column direction so as to run in parallel with the first power supply line 5a (5b).
- a line 45a (45b) is provided.
- Each auxiliary MOS power line 45a (45b) is connected to each gate of a plurality of auxiliary PMOS switches 46a, 46c,... (46b, 46d,...) In the power supply unit 44.
- An auxiliary control voltage of 12 [V] is applied, while an auxiliary control voltage of 6 [V] can be applied in the non-selected unit row 42b.
- Each of the auxiliary PMOS switches 46a, 46c,... (46b, 46d,...) Has a source connected to the first power supply line 5a (5b), a drain connected to the word line 15, and an auxiliary MOS power supply line 45a (45b). ) From the auxiliary control voltage applied to the gate and the write voltage or write inhibit voltage applied to the source from the first power supply line 5a (5b) so that the on / off operation can be performed.
- the selection power supply unit 44a of the selection unit row 42a has a 12 [V] write gate on the first power supply line 5a. A voltage is applied, and a write inhibit gate voltage of 0 [V] is applied to the other second power supply line 6a.
- the first inverter circuit 24 applies the 6 [V] second PMOS control voltage in the second PMOS power supply line VL4 to the common PMOS control line PGa. .
- the PMOS switch 8a arranged in the selection row 3a of the selection unit column 42a is applied with the second PMOS control voltage of 6 [V] from the common PMOS control line PGa to the gate, and from the first power supply line 5a to the source.
- the write gate voltage of 12 [V] is applied to turn on, and the write gate voltage of 12 [V] can be applied from the drain to the selected word line 15a.
- the second PMOS applied to the gate in the PMOS switch 8a when the PMOS switch 8a is turned on in the selected row 3a of the selection unit column 42a, the second PMOS applied to the gate in the PMOS switch 8a.
- the voltage difference between the control voltage (6 [V]) and the write gate voltage (12 [V]) applied to the source can be set to 6 [V] or less, which is much lower than in the second embodiment. Has been made.
- the selected word line 15a is the same as in the first embodiment described above.
- a write gate voltage of 12 [V] is applied to the control gate from 1 to 6
- a write inhibit voltage of 6 [V] is applied to one end and the other end from the unselected first bit line L1b and the unselected second bit line L2b.
- the second NMOS control voltage of 0 [V] in the second NMOS power supply line VL6 is applied to the common NMOS control line NGa by the second inverter circuit 25.
- the NMOS switch 9a arranged in the selected row 3a of the selected unit column 42a is applied with the second NMOS control voltage of 0 [V] from the common NMOS control line NGa to the gate, and from the second power supply line 6a to the source.
- a write inhibit gate voltage of 0 [V] is applied to turn off and the write inhibit gate voltage can be cut off.
- an auxiliary control voltage of 12 [V] is applied to the auxiliary MOS power line 45a.
- the auxiliary PMOS switch 46a arranged in the selected row 3a of the selection unit column 42a is supplied with the auxiliary control voltage of 12 [V] from the auxiliary MOS power supply line 45a to the gate, and from the first power supply line 5a to the source.
- a write gate voltage of 12 [V] is applied to turn off and the write gate voltage can be cut off.
- a write gate voltage of 12 [V] can be applied to the selected word line 15a in the first region AR1 via the PMOS switch 8a.
- the first inverter circuit 24 causes the first PMOS control voltage of 12 [V] in the first PMOS power supply line VL3 to be changed to the common PMOS control lines PGb and PGc. , Is applied to PGd.
- the PMOS switch 8c arranged in the non-selected row 3b of the selected unit column 42a is supplied with the first PMOS control voltage of 12 [V] from the common PMOS control line PGb to the gate, and from the first power supply line 5a to the source.
- a write gate voltage of 12 [V] is applied to turn off and the write gate voltage can be cut off.
- the second NMOS circuit 25 applies the first NMOS control voltage of 6 [V] in the first NMOS power supply line VL5 to the common NMOS control lines NGb, NGc, and NGd.
- the NMOS switch 9c arranged in the non-selected row 3b of the selected unit column 42a is applied with the first NMOS control voltage of 6 [V] from the common NMOS control line NGb to the gate, and from the second power supply line 6a to the source.
- the write inhibit gate voltage of 0 [V] is applied to the ON state, and the write inhibit gate voltage of 0 [V] can be applied from the drain to the unselected word line 15c.
- the nonvolatile semiconductor memory device 41 according to the fourth embodiment is also applied to the gate of the NMOS switch 9c when the NMOS switch 9c is turned on in the non-selected row 3b of the selected unit column 42a.
- the voltage difference between the first NMOS control voltage (6 [V]) and the write inhibit gate voltage (0 [V]) applied to the source is set to 6 [V], which is much lower than that of the second embodiment. Has been made to get.
- the non-selected memory cell C2 connected to the selected first bit line L1a and the selected second bit line L2a is connected to the selected first bit line L1a and the selected second bit line L2a at one end and the other.
- a write voltage of 0 [V] is applied to the end
- a write inhibit gate voltage of 0 [V] is also applied to the control gate from the unselected word line 15c via the NMOS switch 9c.
- the channel region has the same voltage. As a result, the quantum tunnel effect does not occur, and charge cannot be injected from the channel region into the charge storage layer.
- the auxiliary PMOS switch 46c arranged in the non-selected row 3b of the selected unit column 42a is supplied with the auxiliary control voltage of 12 [V] from the auxiliary MOS power line 45a to the gate, and from the first power line 5a to the source.
- a write gate voltage of 12 [V] is applied to turn off, and the write gate voltage can be cut off.
- a write inhibit gate voltage of 0 [V] can be applied to the unselected word line 15c in the second region AR2 via the NMOS switch 9c.
- the non-selected power supply unit 44b in the non-selected unit row 42b is supplied with the 12 [V] write inhibit gate voltage on the first power supply line 5b and the other second power supply line 6b is turned off 6 [V]. A voltage is applied.
- the first inverter circuit 24 applies the second PMOS control voltage of 6 [V] in the second PMOS power supply line VL4 to the common PMOS control line PGa.
- the PMOS switch 8b arranged in the selected row 3a of the non-selected unit column 42b is applied with the second PMOS control voltage of 6 [V] from the common PMOS control line PGa to the gate, and is sourced from the first power supply line 5b. Then, a 12 [V] write inhibit gate voltage is applied to turn on, and the 12 [V] write inhibit gate voltage can be applied from the drain to the unselected word line 15b.
- an auxiliary control voltage of 6 [V] is applied to the auxiliary MOS power line 45b.
- the auxiliary PMOS switch 46b arranged in the selected row 3a of the non-selected unit column 42b is supplied with the auxiliary control voltage of 6 [V] from the auxiliary MOS power line 45b to the gate, and from the first power line 5b to the source.
- a 12 [V] write inhibit gate voltage is applied to turn on, and the 12 [V] write inhibit gate voltage can be applied from the drain to the unselected word line 15b.
- the second NMOS control voltage of 0 [V] in the second NMOS power supply line VL6 is applied to the common NMOS control line NGa by the second inverter circuit 25.
- the NMOS switch 9b arranged in the selected row 3a of the non-selected unit column 42b is applied with the second NMOS control voltage of 0 [V] from the common NMOS control line NGa to the gate, and from the second power supply line 6b to the source.
- an off voltage of 6 [V] is applied to the off state, so that the off voltage can be cut off.
- a write inhibit gate voltage of 12 [V] can be applied to the non-selected word line 15b in the selected row 3a of the third area AR3 via the auxiliary PMOS switch 46b and the PMOS switch 8b.
- a write inhibit voltage of 12 [V] is applied to the non-selected first bit line L1c and the non-selected second bit line L2c in the non-selected unit column 42b.
- 12 [V] is applied to the memory well PW2.
- a write inhibit gate voltage of 12 [V] is applied from the unselected word line 15b to the control gate, and further, the P-type memory well PW2 is set to a high voltage of 12 [V].
- the voltage between the control gate and the channel region becomes the same voltage. As a result, the quantum tunnel effect does not occur, and charge cannot be injected from the channel region into the charge storage layer.
- the first PMOS control voltage of 12 [V] in the first PMOS power supply line VL3 is applied to the common PMOS control lines PGb, PGc, and PGd by the first inverter circuit 24.
- the PMOS switch 8d arranged in the non-selected row 3b of the non-selected unit column 42b is supplied with the first PMOS control voltage of 12 [V] from the common PMOS control line PGb to the gate, and from the first power supply line 5b.
- a 12 [V] write inhibit gate voltage is applied to the source to turn it off so that the write inhibit gate voltage can be cut off.
- the second NMOS circuit 25 applies the first NMOS control voltage of 6 [V] in the first NMOS power supply line VL5 to the common NMOS control lines NGb, NGc, and NGd.
- the NMOS switch 9d arranged in the non-selected row 3b of the non-selected unit column 42b is applied with the first NMOS control voltage of 6 [V] from the common NMOS control line NGb to the gate, and from the second power supply line 6b.
- An off voltage of 6 [V] is applied to the source to enter an off state, and the off voltage can be cut off.
- auxiliary PMOS switch 46d arranged in the non-selected row 3b of the non-selected unit column 42b
- an auxiliary control voltage of 6 [V] is applied from the auxiliary MOS power line 45b to the gate, and the first power line Since the write inhibit gate voltage of 12 [V] is applied from 5b to the source, it is turned on so that the write inhibit gate voltage can be applied from the drain to the unselected word line 15d.
- a write inhibit gate voltage of 12 [V] can be applied to the non-selected word line 15d arranged in the non-selected row 3b of the third area AR3 via the auxiliary PMOS switch 46d.
- the non-selected memory cell C2 arranged in the non-selected row 3b of the third area AR3 also writes 12 [V] to one end and the other end from the non-selected first bit line L1c and the non-selected second bit line L2c.
- a inhibit voltage is applied, and a write inhibit gate voltage of 12 [V] is applied from the non-selected word line 15d to the control gate via the auxiliary PMOS switch 46d, and the P-type memory well PW2 is as high as 12 [V]. Since the voltage is set, the voltage between the control gate and the channel region is the same. As a result, the quantum tunnel effect does not occur, and charge cannot be injected from the channel region into the charge storage layer.
- the nonvolatile semiconductor memory device 41 can also achieve the same effect as that of the second embodiment described above.
- the NMOS switches 9a, 9c in the nonvolatile semiconductor memory device 41 according to the fourth embodiment, the PMOS switches 8a, 8c,... (8b, 8d,...)
- the NMOS switches 9a, 9c in the nonvolatile semiconductor memory device 41 according to the fourth embodiment, the PMOS switches 8a, 8c,... (8b, 8d,...)
- the NMOS switches 9a, 9c in the nonvolatile semiconductor memory device 41 according to the fourth embodiment.
- Auxiliary PMOS switches 46a, 46c,... That are turned on and off according to the auxiliary control voltage from the auxiliary MOS power supply line 45a (45b) provided for each power supply unit 44 without being constrained by the control voltage required for the operation. 46b, 46d, ).
- the auxiliary PMOS switches 46b, 46d,... are turned on by the non-selected power supply unit 44b to write to the unselected word lines 15b, 15d,. , And the PMOS switches 8b, 8d,... And the NMOS switches 9b, 9d,.
- the maximum voltage difference of the control voltage at which the PMOS switches 8a, 8c,... (8b, 8d,...) And the NMOS switches 9a, 9c in the power supply unit 44a, the PMOS switches 8a, 8c,... And the NMOS switches 9a, 9c,.
- the maximum voltage difference between the control voltages for turning on and off the PMOS switches 8a, 8c,... And the NMOS switches 9a, 9c,. V] or less, and the maximum voltage value of the control voltage for turning on / off the auxiliary PMOS switches 46a, 46c,... (46b, 46d,%) Can also be set to 6 [V] or less.
- PMOS switches 8a, 8c, ... (8b, 8d, ...), NMOS switches 9a, 9c, ... (9b, 9d, ...), and auxiliary NMOS switches 46a, 46c, ... (46b, 46d, ...) Can be used.
- the operation of the switching mechanism will be summarized.
- the selected power supply unit 44a to which the selected word line 15a having the selected memory cell C1 is connected the write-prohibited gate voltage from the second power supply line 6a to the source.
- the NMOS switch 9a to which the (charge accumulation prohibiting gate voltage) is applied and the auxiliary PMOS switch 46a to which the write gate voltage (charge accumulation gate voltage) is applied from the first power supply line 5a to the source are turned off.
- the PMOS switch 8a to which the write gate voltage (charge storage gate voltage) is applied from the first power supply line 5a to the source is turned on, the write gate voltage (charge) is applied from the drain of the PMOS switch 8a to the selected word line 15a. Apply the storage gate voltage).
- the write-inhibited gate voltage (charge) is applied to the unselected word line 15c in which only the unselected memory cell C2 is arranged.
- the PMOS switch 8c and the auxiliary PMOS switch 46c to which the write gate voltage (charge storage gate voltage) is applied from the first power supply line 5a to the source are turned off, and the second power supply line
- the NMOS switch 9c to which the write inhibit gate voltage (charge accumulation inhibit gate voltage) is applied from 6a to the source is turned on
- the write inhibit gate voltage (charge) from the drain of the NMOS switch 9c to the unselected word line 15c is turned on. Apply the storage inhibit gate voltage.
- the write gate voltage (charge) is applied to the selected word line 15a by the power supply unit 44 in the other column.
- the PMOS switch 8b and the auxiliary PMOS switch 46b are turned on and paired with the NMOS switch
- 9b is turned off, the write inhibit gate voltage (charge accumulation inhibit gate voltage) applied from the first power supply line 5b to the sources of the PMOS switch 8b and the auxiliary PMOS switch 46b is changed to the PMOS switch 8b and the auxiliary PMOS.
- the unselected word line 15b is applied from the drain of the switch 46b.
- the write prohibition gate voltage to the unselected word line 15c in the power supply unit 44 of the other column When there is an NMOS switch 9d sharing the common NMOS control line NGb with the NMOS switch 9c to which (charge accumulation inhibition gate voltage) is applied, the NMOS switch 9d and the PMOS switch 8d are turned off and paired with this.
- the write inhibit gate voltage charge accumulation inhibit gate voltage
- the write inhibit gate voltage charge accumulation inhibit gate voltage applied from the first power supply line 5b to the source of the auxiliary PMOS switch 46d is supplied from the drain of the auxiliary PMOS switch 46d. Applied to the unselected word line 15d. Thereby, in the nonvolatile semiconductor memory device 41, charges can be accumulated only in the memory cell C at a predetermined position.
- 51 is a nonvolatile semiconductor memory device according to the fifth embodiment
- This nonvolatile semiconductor memory device 51 is the same as the third embodiment described above in that it has a configuration in which auxiliary NMOS switches 36a, 36c,... (36b, 36d,...) Are provided.
- 4 [V] is applied to the P-type memory well PW2 in the non-selected unit column 32b, and the non-selected word lines 15b and 15d are connected to the 4 through the auxiliary NMOS switches 36b, 36d,.
- This is different from the third embodiment described above in that a write-inhibit gate voltage of [V] is applied.
- FIG. 7 shows that the memory cell C in the first row and the first column in the unit column 32 of the first column among the plurality of memory cells C is the same as in the third embodiment described above.
- the voltage values at the respective locations when the selected memory cell C1 to be written is set and all other memory cells C are set as non-selected memory cells C2 are shown.
- the selection unit row 32a each voltage value, the on / off operation of the PMOS switches 8a, 8c,..., The NMOS switches 9a, 9c,... And the auxiliary NMOS switches 36a, 36c,. Since the configuration is the same as that of the nonvolatile semiconductor memory device 31 according to the embodiment, the description thereof will be omitted, and only the non-selected unit row 32b will be described below.
- the PMOS switch 8b in the selected row 3a of the non-selected unit column 32b is applied with the second PMOS control voltage of 6 [V] from the common PMOS control line PGa to the gate, as in the third embodiment described above.
- an off voltage of 6 [V] is applied from the first power supply line 5b to the source to turn off, and the off voltage can be cut off.
- a 4 [V] write inhibit gate voltage is applied to the second power supply line 6b as a common voltage.
- the NMOS switch 9b arranged in the selected row 3a of the non-selected unit column 32b receives the second NMOS control voltage of 0 [V] from the common NMOS control line NGa to the gate and the source from the second power supply line 6b.
- 4 [V] write inhibit gate voltage is applied to turn off and the write inhibit gate voltage can be cut off.
- an auxiliary control voltage of 6 [V] is applied from the auxiliary MOS power line 7b to the gate, and from the second power line 6b. Since a 4 [V] write inhibit gate voltage is applied to the source, the source is turned on, and the write inhibit gate voltage can be applied from the drain to the non-selected word line 15b. Thus, a write inhibit gate voltage of 4 [V] can be applied to the unselected word line 15b in the selected row 3a of the third area AR3 via the auxiliary NMOS switch 36b.
- a write inhibit voltage of 6 [V] is applied to the non-selected first bit line L1c and the non-selected second bit line L2c in the non-selected unit column 32b.
- 4 [V] is applied to the type memory well PW2.
- the PMOS switch 8d arranged in the non-selected row 3b at the lower stage of the non-selected unit column 32b has a 12 [V] gate from the common PMOS control line PGb to the gate, as in the third embodiment described above. Since the 1 PMOS control voltage is applied and the off voltage of 6 [V] is applied from the first power supply line 5b to the source, the off state is established and the off voltage can be cut off.
- the NMOS switch 9d arranged in the non-selected row 3b of the non-selected unit column 32b the first NMOS control voltage of 6 [V] is applied from the common NMOS control line NGb to the gate, and the second power supply line 6b.
- a 4 [V] write inhibit gate voltage is applied from the source to the source to turn it on, and the write inhibit gate voltage can be applied from the drain to the non-selected word line 15d.
- the auxiliary NMOS switch 36d arranged in the non-selected row 3b of the non-selected unit column 32b is applied with the auxiliary control voltage of 6 [V] from the auxiliary MOS power line 7b to the gate, and the second power line.
- a write inhibit gate voltage of 4 [V] is applied from 6b to the source to turn it on, and the write inhibit gate voltage can be applied from the drain to the unselected word line 15d.
- a 4 [V] write inhibit gate voltage can be applied to the unselected word line 15d arranged in the unselected row 3b of the third area AR3 via the NMOS switch 9d and the auxiliary NMOS switch 36d. Has been made.
- the nonvolatile semiconductor memory device 51 can also obtain the same effect as that of the above-described third embodiment. Further, in the nonvolatile semiconductor memory device 51, when data is written, 0 [V] is applied to the P-type well PW1 of the non-selected unit column 32b, and the auxiliary NMOS switches 36b, 36d,. A 4 [V] write inhibit gate voltage is applied to each unselected word line 15b, 15d,... Of the unit row 32b.
- non-selected unit row 32b 12 V is applied to the N-type well NW1 in which the PMOS switches 8b, 8d,... Are formed when data is written, but the PMOS switches 8b, 8d,.
- a non-selected word line 15b, 15d,... Connected to the drain is applied with a 4 [V] write inhibit gate voltage having a slightly higher voltage value, and the drains of these PMOS switches 8b, 8d,. Since the voltage difference with the well NW1 is made relatively small as 8 [V], the voltage burden on the PMOS switches 8b, 8d,... Is reduced correspondingly, and the reliability of the PMOS switches 8b, 8d,. Can be improved.
- reference numeral 55 denotes a nonvolatile semiconductor memory device according to the sixth embodiment
- the nonvolatile semiconductor memory device 55 has the same circuit configuration as that of the fifth embodiment described above, but includes PMOS switches 8a, 8c,... (8b, 8d,%) And NMOS switches 9a, The voltage values at the gates 9c,... (9b, 9d,%) And the voltage values at the non-selected unit column 32b at the time of data writing are the same as the nonvolatile semiconductor memory device 51 according to the fifth embodiment described above. Is different.
- FIG. 8 shows the memory cell C in the first row and the first column in the unit column 32 of the first column among the plurality of memory cells C, as in the fifth embodiment described above.
- the voltage values at the respective locations when the selected memory cell C1 to be written is set and all other memory cells C are set as non-selected memory cells C2 are shown.
- the first PMOS control voltage of 12 [V] is applied to the first PMOS power supply line VL3, as in the fifth embodiment, but the second PMOS power supply line VL4 is applied to the fifth PMOS power supply line VL4.
- the second PMOS control voltage of 8 [V] higher than that of the embodiment is applied, and the voltage difference between the first PMOS control voltage and the second NMOS control voltage is smaller than that of the fifth embodiment described above 4 [ V] is set.
- the common PMOS control lines PGa to PGd connected to the first PMOS power line VL3 and the second PMOS power line VL4 via the first inverter circuit 24 are connected to the non-selected row 3b by the first inverter circuit 24.
- the first PMOS control voltage of 12 [V] may be applied, and the second PMOS control voltage of 8 [V] may be applied when the selected row 3a.
- the common PMOS control lines PGa to PGd have a voltage amplitude of 4 [V] (that is, 12 [V] ⁇ 8 [) between the voltage value in the selected row 3a and the voltage value in the non-selected row 3b. V]), the voltage amplitude is reduced.
- the gate insulating film can be made thinner by that amount.
- a second NMOS control voltage of 0 [V] is applied to the second NMOS power supply line VL6, as in the fifth embodiment, but the first NMOS power supply line VL5 has the fifth NMOS control line described above.
- the first NMOS control voltage of 4 [V] lower than that of the embodiment is applied, and the voltage difference between the first NMOS control voltage and the second NMOS control voltage is smaller than that of the fifth embodiment described above. [V] is set.
- the common NMOS control lines NGa to NGd connected to the first NMOS power line VL5 and the second NMOS power line VL6 via the second inverter circuit 25 are connected to the non-selected row 3b by the second inverter circuit 25.
- the first NMOS control voltage of 4 [V] may be applied, and the second NMOS control voltage of 0 [V] may be applied when the selected row 3a.
- the common NMOS control lines NGa to NGd have a voltage amplitude of 4 [V] (that is, 4 [V] ⁇ 0 [) between the voltage value in the selected row 3a and the voltage value in the non-selected row 3b. V]), the voltage amplitude is reduced.
- the voltage amplitude at the gates in the selected row 3a and the non-selected row 3b is reduced.
- the gate insulating film can be made thinner.
- the selected power supply unit 34a of the selected unit row 32a has the first area as in the fifth embodiment described above.
- a write gate voltage of 12 [V] is applied to one power supply line 5a, and a write inhibit gate voltage of 0 [V] is applied to the other second power supply line 6a.
- the first inverter circuit 24 applies the second PMOS control voltage of 8 [V] in the second PMOS power supply line VL4 to the common PMOS control line PGa. .
- the PMOS switch 8a arranged in the selection row 3a of the selection unit column 32a is applied with the second PMOS control voltage of 8 [V] from the common PMOS control line PGa to the gate, and from the first power supply line 5a to the source.
- the write gate voltage of 12 [V] is applied to turn on, and the write gate voltage of 12 [V] can be applied from the drain to the selected word line 15a.
- the selected memory cell C1 connected to the selected first bit line L1a and the selected second bit line L2a has one end and the other end from the selected first bit line L1a and the selected second bit line L2a.
- the first applied to the gate in the PMOS switch 8a when the PMOS switch 8a is turned on in the selected row 3a of the selected unit column 32a, the first applied to the gate in the PMOS switch 8a.
- the voltage difference between the 2PMOS control voltage (8 [V]) and the write gate voltage (12 [V]) applied to the source can be set to 4 [V], which is much lower than that of the fifth embodiment. Has been made.
- the non-selected first Since a write inhibit voltage of 6 [V] is applied to one end and the other end of the bit line L1b and the non-selected second bit line L2b, a write gate voltage of 12 [V] is applied to the control gate from the selected word line 15a. Even if this is done, the voltage difference between the control gate and the channel region becomes small. As a result, the quantum tunnel effect does not occur, and charge cannot be injected from the channel region into the charge storage layer.
- the second NMOS control voltage of 0 [V] in the second NMOS power supply line VL6 is applied to the common NMOS control line NGa by the second inverter circuit 25.
- the NMOS switch 9a arranged in the selected row 3a of the selected unit column 32a is applied with the second NMOS control voltage of 0 [V] from the common NMOS control line NGa to the gate, and from the second power supply line 6a to the source.
- a write inhibit gate voltage of 0 [V] is applied to turn off and the write inhibit gate voltage can be cut off.
- the auxiliary NMOS switch 36a arranged in the selected row 3a of the selection unit column 32a applies an auxiliary control voltage of 0 [V] from the auxiliary MOS power line 7a to the gate, as in the fifth embodiment described above.
- a write inhibit gate voltage of 0 [V] is applied to the source from the second power supply line 6a, so that the write inhibit gate voltage can be cut off.
- a write gate voltage of 12 [V] can be applied to the selected word line 15a in the first region AR1 via the PMOS switch 8a.
- the first inverter circuit 24 causes the first PMOS control voltage of 12 [V] in the first PMOS power supply line VL3 to be the common PMOS control lines PGb, PGc, Applied to PGd.
- the PMOS switch 8c arranged in the non-selected row 3b of the selected unit column 32a is supplied with the first PMOS control voltage of 12 [V] from the common PMOS control line PGb to the gate, and from the first power supply line 5a to the source.
- a write gate voltage of 12 [V] is applied to turn off and the write gate voltage can be cut off.
- the first NMOS control voltage of 4 [V] in the first NMOS power supply line VL5 is applied to the common NMOS control lines NGb, NGc, and NGd by the second inverter circuit 25.
- the NMOS switch 9c arranged in the non-selected row 3b of the selected unit column 32a is supplied with the first NMOS control voltage of 4 [V] from the common NMOS control line NGb to the gate and from the second power supply line 6a to the source.
- the write inhibit gate voltage of 0 [V] is applied to the ON state, and the write inhibit gate voltage of 0 [V] can be applied from the drain to the unselected word line 15c.
- the nonvolatile semiconductor memory device 55 As described above, when the NMOS switch 9c is turned on in the non-selected row 3b of the selected unit column 32a, the nonvolatile semiconductor memory device 55 according to the sixth embodiment is applied to the gate of the NMOS switch 9c.
- the voltage difference between the first NMOS control voltage (4 [V]) and the write inhibit gate voltage (0 [V]) applied to the source can be set to 4 [V], which is much lower than that of the fifth embodiment. It is made like that.
- the non-selected memory cell C2 connected to the selected first bit line L1a and the selected second bit line L2a is connected to the selected first bit line L1a and the selected second bit line L2a at one end and the other.
- a write voltage of 0 [V] is applied to the end
- a write inhibit gate voltage of 0 [V] is also applied to the control gate from the unselected word line 15c via the NMOS switch 9c.
- the channel region has the same voltage. As a result, the quantum tunnel effect does not occur, and charge cannot be injected from the channel region into the charge storage layer.
- the non-selected memory cell C2 connected to the non-selected first bit line L1b and the non-selected second bit line L2b is also connected to the non-selected first bit line L1b and the non-selected second bit line.
- a 6V write inhibit voltage is applied from L1b to one end and the other end, and a 0V write inhibit gate voltage is applied from the unselected word line 15c to the control gate, resulting in a quantum tunnel effect. Without charge, charge cannot be injected from the channel region into the charge storage layer.
- an auxiliary control voltage of 0 [V] is applied from the auxiliary MOS power line 7a to the gate, and from the second power line 6a to the source. Since the write gate voltage of 0 [V] is applied, it is turned off, and this write voltage can be cut off. Thus, a write inhibit gate voltage of 0 [V] can be applied to the unselected word line 15c in the second region AR2 via the NMOS switch 9c.
- the PMOS switch 8b arranged in the selected row 3a of the non-selected unit column 32b is applied with the second PMOS control voltage of 8 [V] from the common PMOS control line PGa to the gate, and the source from the first power supply line 5b.
- an off voltage of 8 [V] is applied to the off state, and the off voltage can be cut off.
- the second NMOS circuit 25 applies the second NMOS control voltage of 0 [V] in the second NMOS power supply line VL6 to the common NMOS control line NGa.
- the NMOS switch 9b arranged in the selected row 3a of the non-selected unit column 32b receives the second NMOS control voltage of 0 [V] from the common NMOS control line NGa to the gate and the source from the second power supply line 6b.
- 4 [V] write inhibit gate voltage is applied to turn off and the write inhibit gate voltage can be cut off.
- auxiliary NMOS switch 36b arranged in the selected row 3a of the non-selected unit column 32b is supplied with the auxiliary control voltage of 6 [V] from the auxiliary MOS power supply line 7b to the gate, and from the second power supply line 6b to the source.
- a 4 [V] write inhibit gate voltage is applied to turn on and the write inhibit gate voltage can be applied from the drain to the unselected word line 15b.
- a 4 [V] write inhibit gate voltage can be applied to the unselected word line 15b arranged in the selected row 3a of the third area AR3 via the auxiliary NMOS switch 36b.
- a write inhibit voltage of 6 [V] is applied to the non-selected first bit line L1c and the non-selected second bit line L2c in the non-selected unit column 32b, and the P-type memory well 4 [V] is applied to PW2.
- the first PMOS control voltage of 12 [V] in the first PMOS power supply line VL3 is applied to the common PMOS control lines PGb, PGc, and PGd by the first inverter circuit 24.
- the PMOS switch 8d arranged in the non-selected row 3b of the non-selected unit column 32b is applied with the first PMOS control voltage of 12 [V] from the common PMOS control line PGb to the gate, and from the first power supply line 5b.
- An off voltage of 8 [V] is applied to the source so that the source is turned off, and the off voltage can be cut off.
- the first NMOS control voltage of 4 [V] in the first NMOS power supply line VL5 is applied to the common NMOS control lines NGb, NGc, and NGd by the second inverter circuit 25.
- the NMOS switch 9d arranged in the non-selected row 3b of the non-selected unit column 32b is applied with the first NMOS control voltage of 4 [V] from the common NMOS control line NGb to the gate, and from the second power supply line 6b.
- a 4 [V] write inhibit gate voltage is applied to the source to turn it off so that the write inhibit gate voltage can be cut off.
- auxiliary control voltage of 6 [V] is applied from the auxiliary MOS power line 7b to the gate, and the second power line Since the write inhibit gate voltage of 4 [V] is applied from 6b to the source, it is turned on, and the write inhibit gate voltage can be applied from the drain to the unselected word line 15d.
- a 4 [V] write inhibit gate voltage can be applied to the non-selected word line 15d arranged in the non-selected row 3b of the third area AR3 via the auxiliary NMOS switch 36d.
- the non-selected memory cell C2 connected to the non-selected first bit line L1c and the non-selected second bit line L2c in the non-selected row 3b of the third area AR3, the non-selected first bit line L1c and the non-selected A write inhibit voltage of 6 [V] is applied from the second bit line L2c to one end and the other end, and a write inhibit gate voltage of 4 [V] is applied from the auxiliary NMOS switch 36d to the control gate via the non-selected word line 15d.
- the voltage difference between the control gate and the channel region is reduced.
- the quantum tunnel effect does not occur, and charge cannot be injected from the channel region into the charge storage layer.
- the voltage difference between the auxiliary control voltage (6 [V]) applied to the gate and the write inhibit gate voltage (4 [V]) applied to the source is set to the fifth embodiment. It can be set to 4 [V] or lower, which is much lower than the form.
- this nonvolatile semiconductor memory device 55 can also obtain the same effect as that of the third embodiment described above.
- the nonvolatile semiconductor memory device 55 according to the sixth embodiment it is not always necessary to turn on the PMOS switches 8b, 8d,... And the NMOS switches 9b, 9d,.
- the selection unit row 32a it is possible to freely set control voltage values for turning on / off the PMOS switches 8a, 8c,... And the NMOS switches 9a, 9c,.
- the maximum voltage difference for turning on / off the NMOS switches 9a, 9c,... And the auxiliary NMOS switches 36a, 36c,... (36b, 36d,...) Is, for example, 4 [V] or less, which is much lower than that of the third embodiment. Can be set.
- the PMOS switches 8a, 8c,... (8b, 8d,%) can be set to a voltage difference of 4 [V] or less when the on / off operation is performed. Therefore, the thickness of the gate insulating film is reduced to 8 [nm] accordingly.
- non-selected unit row 32b, 12 [V] is applied to the N-type well NW1 in which the PMOS switches 8b, 8d,... Are formed at the time of data writing, but the PMOS switches 8b, 8d,.
- a non-selected word line 15b, 15d,... Connected to the drain is applied with a 4 [V] write inhibit gate voltage having a slightly higher voltage value, and the drains of these PMOS switches 8b, 8d,. Since the voltage difference with the well NW1 is made relatively small as 8 [V], the voltage burden on the PMOS switches 8b, 8d,... Is reduced correspondingly, and the reliability of the PMOS switches 8b, 8d,. Can be improved.
- the operation of the switching mechanism of this embodiment is almost the same as that of “(3) Third Embodiment” described above, but only the non-selected memory cell C2 is arranged in the power supply unit.
- the NMOS switch 9c and the common NMOS control line for applying the write inhibit gate voltage (charge accumulation inhibit gate voltage) to the unselected word line 15c in the power supply unit 34 of the other column When there is an NMOS switch 9d sharing NGb, the NMOS switch 9d and the PMOS switch 8d are turned off, and the auxiliary NMOS switch 36d paired with the NMOS switch 9d is turned on, so that the second power supply
- the write inhibit gate voltage (charge accumulation inhibit gate voltage) applied from the line 6b to the source of the auxiliary NMOS switch 36d is set to the auxiliary NMOS switch 36d. Is applied to the unselected word line 15d.
- charges can be accumulated only
- 61 is a nonvolatile semiconductor memory device according to the seventh embodiment
- the nonvolatile semiconductor memory device 61 includes auxiliary NMOS switches 71a, 69c,... (69b, 69d,...) And NMOS switches 70a, 70c,. 71c,... (71b, 71d,...) Are provided, and a PMOS power supply line VPa (VPb) and an NMOS power supply line VNa (VNb) extending in the column direction are provided as unit wirings for each unit column 62.
- VPa PMOS power supply line
- VNb NMOS power supply line
- FIG. 9 shows that the memory cell C in the first row and the first column in the unit column 62 in the first column among the plurality of memory cells C is the same as in the third embodiment described above.
- the voltage values at the respective locations when the selected memory cell C1 to be written is set and all other memory cells C are set as non-selected memory cells C2 are shown.
- the nonvolatile semiconductor memory device 61 is arranged such that the first power supply line 65 and the second power supply line 66 run in parallel in the column direction, and the first power supply line 65 and the second power supply line 66 are connected to a plurality of power supply units. 64 is configured to be common. In practice, a plurality of inverter circuits 63 are commonly connected to the first power line 65 and the second power line 66, and common power lines 67a to 67d are connected to the output portions of the inverter circuits 63, respectively. . Each inverter circuit 63 has either a 12 [V] write gate voltage applied to the first power supply line 65 or a 0 [V] write inhibit gate voltage applied to the second power supply line 66. Is selected for each row and can be applied to the common power supply lines 67a to 67d.
- a PMOS power supply line VPa (VPb) extending in the column direction is formed in the N-type well NW1 of the power supply unit 64, and a plurality of PMOS switches 69a, 69c,... (69b) are formed along the PMOS power supply line VPa (VPb). , 69d, ...) are formed.
- the PMOS switch 69a has a gate connected to the PMOS power supply line VPa and a source connected to the common power supply line 67a. Further, for example, the PMOS switch 69a has a drain connected to the word line 15, and is turned on so that the write gate voltage applied to the common power supply line 67a can be applied from the drain to the word line 15. Yes.
- an NMOS power supply line VNa (VNb) extending in the column direction is formed in the P-type well PW1 of the power supply unit 64, and a plurality of NMOS switches 70a, 70c,... Along the NMOS power supply line VNa (VNb). (70b, 70d,...) are formed.
- the NMOS switch 70a has a gate connected to the NMOS power supply line VNa and a source connected to the common power supply line 67a.
- the NMOS switch 70c has a drain connected to the word line 15, and can be turned on so that the write inhibit gate voltage applied to the common power supply line 67b can be applied from the drain to the unselected word line 15c. Has been made.
- 12 [V] can be applied to the N-type well NW1 in both the selected unit column 62a and the non-selected unit column 62b.
- the P-type well PW1 of the power supply unit 64 is formed with a third power supply line 68a (68b) and an auxiliary MOS power supply line 7a (7b) so as to run in parallel with the NMOS power supply line VNa (VNb).
- a plurality of auxiliary NMOS switches 71a, 71c,... (71b, 71d,...) Are formed along the third power supply line 68a (68b) and the auxiliary MOS power supply line 7a (7b).
- the auxiliary NMOS switches 71a, 71c,... (71b, 71d,...) Have their gates connected to the auxiliary MOS power line 7a (7b) and their sources connected to the third power line 68a (68b).
- the drains of the auxiliary NMOS switches 71a, 71c,... (71b, 71d,...) are connected to the word line 15.
- the auxiliary NMOS switches 71b, 71d are turned on to operate the third power supply.
- the write inhibit gate voltage applied to the line 68b can be applied from the drain to the unselected word lines 15b and 15d.
- 0 [V] can be applied to the P-type well PW1 in both the selected unit column 62a and the non-selected unit column 62b.
- a plurality of word lines 15 extending in the row direction are arranged at predetermined intervals in the column direction, and the control gates of the memory cells C in the same row are provided.
- Each word line 15 is connected.
- the P-type memory well PW2 includes a first bit line L1 and a second bit line L2 extending in the column direction, and a first bit line L1 and a second bit line adjacent to the first bit line L1.
- the bit line L2 is paired, and a plurality of memory cells C are arranged in parallel between the first bit line L1 and the second bit line L2 that run in parallel.
- Each memory cell C has a first bit line L1 connected to one end and a second bit line L2 connected to the other end.
- the first bit line L1 and the second bit line L2 are connected to one end and the second bit line L2.
- a write voltage or a write inhibit voltage can be applied to the other end.
- the first area AR1 will be described first, and then the second area AR2 and the third area AR3 will be described in this order.
- the write gate voltage of 12 [V] in the first power supply line 65 by the inverter circuit 63 connected to the first power supply line 65 and the second power supply line 66. Is applied to the common power supply line 67a as a common voltage.
- the first PMOS control voltage of 6 [V] is applied as a unit voltage to the PMOS power supply line VPa, and the first PMOS control voltage is applied to the gates of the PMOS switches 69a, 69c,. Each can be applied.
- the PMOS switch 69a arranged in the selected row 3a of the selected unit column 62a is applied with the first PMOS control voltage of 6 [V] from the PMOS power supply line VPa to the gate and from the common power supply line 67a to the source 12 [
- the write gate voltage of V] is applied to turn on, and the write gate voltage of 12 [V] can be applied from the drain to the selected word line 15a.
- a write voltage of 0 [V] is applied to the selected first bit line L1a and the selected second bit line L2a.
- the first NMOS control voltage of 6 [V] is applied to the NMOS power supply line VNa as a unit voltage.
- the NMOS switch 70a arranged in the selection row 3a of the selection unit column 62a is applied with the first NMOS control voltage of 6 [V] from the NMOS power supply line VNa to the gate, and 12 [V] from the common power supply line 67a to the source. ] Is applied to turn off, and the write gate voltage can be cut off.
- an auxiliary control voltage of 0 [V] is applied as a unit voltage to the auxiliary MOS power line 7a.
- the auxiliary NMOS switch 71a arranged in the selected row 3a of the selection unit column 62a is applied with the auxiliary control voltage of 0 [V] from the auxiliary MOS power line 7a to the gate, and from the third power line 68a to the source.
- a write inhibit gate voltage of 0 [V] is applied to turn off and the write inhibit gate voltage can be cut off.
- a write gate voltage of 12 [V] can be applied to the selected word line 15a in the first region AR1 via the PMOS switch 69a.
- the inverter circuit 63 causes the 0 [V] write inhibit gate voltage in the second power line 66 to be the common power line 67b, 67c as a common voltage. , 67d.
- the PMOS switch 69c arranged in the non-selected row 3b of the selected unit column 62a receives the first PMOS control voltage of 6 [V] from the PMOS power supply line VPa to the gate, and 0 from the common power supply line 67b to the source.
- the write inhibit gate voltage of [V] is applied to turn off and the write inhibit gate voltage can be cut off.
- the first NMOS control voltage of 6 [V] is applied from the NMOS power supply line VNa to the gate, and 0 [ The V] write inhibit gate voltage is applied to turn on, and the 0 [V] write inhibit gate voltage can be applied from the drain to the unselected word line 15c.
- the non-selected memory cell C2 connected to the selected first bit line L1a and the selected second bit line L2a is connected to the selected first bit line L1a and the selected second bit line L2a at one end and Although the write voltage of 0 [V] is applied to the other end, the write gate voltage of 0 [V] is similarly applied to the control gate from the NMOS switch 70c via the non-selected word line 15c. As a result, the quantum voltage is not generated between the channel region and the channel region, and charge cannot be injected from the channel region to the charge storage layer.
- the non-selected memory cell C2 connected to the non-selected first bit line L1b and the non-selected second bit line L2b includes the non-selected first bit line L1b and the non-selected second bit line.
- a write inhibit voltage of 6 [V] is applied to one end and the other end from L2b, and a write inhibit gate voltage of 0 [V] is applied to the control gate from the NMOS switch 70c via the non-selected word line 15c. Therefore, the quantum tunnel effect does not occur, and charge cannot be injected from the channel region into the charge storage layer.
- the auxiliary NMOS switch 71c arranged in the non-selected row 3b of the selected unit column 62a is applied with an auxiliary control voltage of 0 [V] from the auxiliary MOS power line 7a to the gate, and from the third power line 68a to the source.
- An off voltage of 0 [V] is applied to enter an off state so that the off voltage can be cut off.
- a write inhibit gate voltage of 0 [V] can be applied to the unselected word line 15c in the second area AR2 via the NMOS switch 70c.
- the second PMOS control voltage of 12 [V] is applied to the PMOS power supply line VPb in the non-selected power supply unit 64b of the non-selected unit row 62b.
- the write gate voltage of 12 [V] in the first power supply line 65 is applied to the common power supply line 67a by the inverter circuit 63.
- the PMOS switch 69b arranged in the selected row 3a of the non-selected unit column 62b is supplied with the 12 [V] write gate voltage from the common power supply line 67a to the source, but has 12 to the gate from the PMOS power supply line VPb.
- the second PMOS control voltage of [V] is applied to turn off and the write gate voltage can be cut off.
- the second NMOS control voltage of 0 [V] is applied to the NMOS power supply line VNb.
- the NMOS switch 70b arranged in the selected row 3a of the non-selected unit column 62b has a write gate voltage of 12 [V] applied to one end from the common power supply line 67a, but 0 to the gate from the NMOS power supply line VNb.
- the second PMOS control voltage of [V] is applied to turn off and the write gate voltage can be cut off.
- an auxiliary control voltage of 8 [V] is applied to the auxiliary MOS power supply line 7b, and a write inhibit gate voltage of 6 [V] is applied to the third power supply line 68b.
- the auxiliary NMOS switch 71b arranged in the selected row 3a of the non-selected unit column 62b is supplied with the auxiliary control voltage of 8 [V] from the auxiliary MOS power supply line 7b to the gate, and from the third power supply line 68b to the source.
- a 6 [V] write inhibit gate voltage is applied to turn on, and the write inhibit gate voltage can be applied from the drain to the unselected word line 15b.
- a 6 [V] write inhibit gate voltage can be applied to the unselected word line 15b arranged in the selected row 3a of the third area AR3 via the auxiliary NMOS switch 71b.
- a write inhibit voltage of 6 [V] is applied to the non-selected first bit line L1c and the non-selected second bit line L2c in the non-selected unit column 62b.
- 6 [V] is also applied to the P-type memory well PW2.
- the second PMOS control voltage of 12 [V] is applied from the PMOS power supply line VPb to the gate, and from the common power supply line 67b. Since the 0 [V] write inhibit gate voltage is applied to the source, the source is turned off, and the 0 [V] write inhibit gate voltage can be cut off.
- the second NMOS control voltage of 0 [V] is applied from the NMOS power supply line VNb to the gate, and from the common power supply line 67b. Since the 0 [V] write inhibit gate voltage is applied to the source, the source is turned off, and the 0 [V] write inhibit gate voltage can be cut off.
- auxiliary control voltage of 8 [V] is applied from the auxiliary MOS power line 7b to the gate, and the third power line Since the write inhibit gate voltage of 6 [V] is applied from 68b to the source, it is turned on, and the 6 [V] write inhibit gate voltage can be applied from the drain to the unselected word line 15d. .
- the write inhibit gate voltage of 6 [V] can be applied to the non-selected word line 15d arranged in the non-selected row 3b of the third area AR3 via the auxiliary NMOS switch 71d.
- a plurality of word lines 15 formed in a matrix and a plurality of memory cells C connected to the word lines 15, Each word line includes a first bit line L1 and a second bit line L2 capable of applying a selective voltage to a plurality of memory cells C, and a plurality of power supply units 64 provided corresponding to the respective word line columns.
- the PMOS power supply line VPa (VPb) connected to the gates of the PMOS switches 69a, 69c,... (69b, 69d,...)
- NMOS power supply lines VNa VNb connected to the gates of the PMOS switches 69a, 69c,... (69b, 69d,...)
- NMOS switches 70a, 70c,. 70d,...) Are connected to the word line 15.
- each power supply unit 64 includes an auxiliary MOS power supply line 7a (7b) and a third power supply line 68a (68b) extending in the column direction, and the third power supply line 68a (68b) is connected to the auxiliary NMOS switches 71a and 71c. ,... (71b, 71d,...) Are connected to the word line 15.
- the selected power supply unit 64a applies the write gate voltage to the selected word line 15a by turning on the PMOS switch 69a by the voltage difference between the PMOS power supply line VPa and the common power supply line 67a in the selected row 3a.
- the NMOS switch 70c is turned on by the voltage difference between the NMOS power supply line VNa and the common power supply line 67a, thereby applying the write inhibit gate voltage to the unselected word line 15c.
- the auxiliary NMOS switches 71b, 71d, 71b, 71d, and 72b are selected by the voltage difference between the auxiliary MOS power line 7b and the third power line 68b. Are turned on to apply a write inhibit gate voltage to all the unselected word lines 15b, 15d,.
- the non-selected power supply unit 64b independently operates the auxiliary NMOS switches 71b, 71d,... Without being constrained by the selected power supply unit 64a, and separately from the selected power supply unit 64a, the third power supply line 68b. Can be applied to all the unselected word lines 15b, 15d,.
- the voltage value of the write inhibit gate voltage is not restricted by the selected power supply unit 64a of one word line column, and the non-selected power supply unit 64b of another word line column,
- the voltage value applied to the P-type memory well PW2 and the voltage values of the non-selected first bit line L1c and the non-selected second bit line L2c at that time can suppress the occurrence of disturbance in the non-selected memory cell C2, for example.
- Each voltage can be set freely.
- the write inhibit gate voltage applied to the unselected word lines 15b, 15d,... can be set to a low voltage of 6 [V]
- the P-type memory well PW2 Since the voltage value and the voltage values of the unselected first bit line L1c and the unselected second bit line L2c can all be set to 6 [V] of the same voltage, the data of the selected memory cell C1 is temporarily selected in the selected unit column 62a. Even if the write operation is repeated, it is possible to suppress the disturbance without affecting each non-selected memory cell C2 of the non-selected unit column 62b.
- control voltages applied to the PMOS power supply line VPa (VPb) and the NMOS power supply line VNa (VNb) are applied to the PMOS switches 69a, 69c,. , 70c,... Can be freely set as long as they can be appropriately turned on.
- the voltage difference between the control voltages applied to the PMOS power supply line VPa (VPb) and the NMOS power supply line VNa (VNb) when the selected power supply unit 64a and the non-selected power supply unit 64b are compared. Since the voltage can be set to a low 6 [V], it is possible to reduce the voltage load applied to the gates of the PMOS switches 69a, 69c,... And the NMOS switches 70a, 70c,. it can.
- the PMOS power supply line VPa (VPb) and the NMOS power supply line VNa (VNb) are individually provided for each power supply unit 64, a plurality of common power supplies are provided between the power supply units 64. These are connected by lines 67a to 67d, and by adjusting the voltage value applied to the common power supply lines 67a to 67d for each row, PMOS switches 69a, 69c,... (69b, 69d,...), NMOS switches 70a, 70c ,... (70b, 70d,...) And auxiliary NMOS switches 71a, 71c,...
- the write gate voltage (charge) is supplied from the common power supply line 67a to the source.
- the NMOS switch 70a to which the storage gate voltage is applied and the auxiliary NMOS switch 71a connected to the third power supply line 68a are turned off, and the write gate voltage (charge storage gate voltage) is written from the common power supply line 67a to the source.
- a write gate voltage charge storage gate voltage
- the selected power supply unit 64a to which the selected word line 15a having the selected memory cell C1 is connected is connected to the unselected word line 15c in which only the unselected memory cell C2 is arranged.
- a write inhibit gate voltage charge accumulation inhibit gate voltage
- the write gate voltage (charge) is written to the selected word line 15a in the power supply unit 64 of the other column.
- the write-inhibited gate voltage to the non-selected word line 15c in the power supply unit 64 in the other column when there is an NMOS switch 70d sharing the common power supply line 67b with the NMOS switch 70c to which (charge accumulation prohibition gate voltage) is applied, the NMOS switch 70d and the PMOS switch 69d are turned off, and the auxiliary switch is paired with the NMOS switch 70d.
- the write inhibit gate voltage charge accumulation inhibit gate voltage
- the write inhibit gate voltage charge accumulation inhibit gate voltage applied from the third power supply line 68b to the source of the auxiliary NMOS switch 71d is reduced from the drain of the auxiliary NMOS switch 71d.
- the selected word line 15d Applied to the selected word line 15d.
- the nonvolatile semiconductor memory device 21 As an example, the nonvolatile semiconductor memory device 21 according to the second embodiment shown in FIG.
- the breakdown voltage structure of the NMOS switches 9a, 9c,... (9b, 9d,%) Of the nonvolatile semiconductor memory device 21 will be described.
- the NMOS switch 9a, 9c,... (9b, 9d,%) Of each power supply unit 4 is connected to the second power supply line 6a (6b) at one end and the word line 15 to the other end.
- Common NMOS control lines NGa to NGd are connected to the gates.
- the NMOS switches 9a, 9c,... (9b, 9d,%) Have a control voltage of either 0 [V] or 8 [V] at the time of data writing and data erasing. Since the voltage applied to the gate via NGa to NGd and 0 [V] is applied to the P-type well PW1, the maximum voltage difference with the P-type well PW1 at the gate is relatively low 8 [V]. Can be set.
- the NMOS switches 9a, 9c,... (9b, 9d,...) At the time of data writing and data erasing, one voltage of 0 [V] or 6 [V] is applied to the second power supply line 6a. Since the voltage applied to the source via (6b) and 0 [V] is applied to the P-type well PW1, the maximum voltage difference with the P-type well PW1 on the source side is relatively low 6 [V] Can be set.
- the maximum voltage difference from the P-type well PW1 at the gate is 8 [V]
- the maximum voltage difference from the P-type well PW1 at the source side Therefore, it is sufficient to provide a withstand voltage structure of 8 [V] which is the maximum voltage difference, and the gate insulating film can be made thinner accordingly.
- the maximum voltage difference applied to the common NMOS control lines NGa to NGd and the common PMOS control lines PGa to PGd is 8 [V].
- the NMOS transistor can also have a transistor configuration in which the gate insulating film is thinned in accordance with the maximum voltage difference of 8 [V].
- the NMOS switches 9a, 9c,... (9b, 9d,%) The maximum voltage difference between the gate and the P-type well PW1 and the maximum voltage difference between the source and the P-type well PW1 are 8 [V].
- the maximum voltage difference from the P-type well PW1 on the drain side is 12 [V]. That is, the NMOS switches 9a, 9c,... (9b, 9d,%) Have 12 [V] write gates on the selected word line 15a connected to the drain when the selected unit column 2a becomes the selected row 3a. Since a voltage is applied, the drain side needs to have a high breakdown voltage structure in accordance with the high writing gate voltage of 12 [V].
- the drain side connected to the word line 15 uses NMOS switches 100, 115, 117, 120, 123, 131, 135 having a higher breakdown voltage structure than the source side. desirable.
- FIGS. 10 and 11 show the peripheral NMOS transistor 101 constituting the peripheral circuit and the NMOS switches 100, 115, 117, 120, 123, 131, 135 provided in the nonvolatile semiconductor memory device 21 (corresponding to the NMOS switches 9a, 9c (9b, 9d) shown in FIG. 2).
- FIG. 1 the drain side connected to the word line 15 has a higher withstand voltage structure than the source side, and the NMOS switches 100, 115, 117, 120, 123 having a left-right asymmetric withstand voltage structure on the drain side and the source side, and an NMOS with a low well concentration
- a switch 131 and an NMOS switch 135 in which the entire gate insulating film is thickened are shown. In this case, as shown in FIGS.
- the voltage difference between the common NMOS control lines NGa to NGd of the nonvolatile semiconductor memory device 21 is set to 8 [V] or less.
- the voltage difference between the applied voltages is 8 [V]
- the gate insulating film 105a can be made thin as much as the voltage burden is reduced.
- the peripheral NMOS transistor 101 is provided with a gate insulating film 105a on the P-type well 102 between the source 103a and the drain 103b, and a source-side extension 104a at the end of the source 103a and an end of the drain 103b.
- a channel region is formed between the drain side extension portion 104b.
- the peripheral NMOS transistor 101 has a configuration in which a gate 106a is formed on a channel region of a P-type well 102 as a semiconductor substrate via a gate insulating film 105a, and common NMOS control lines NGa, NGb, NGc,
- the gate insulating film 105a between the P-type well 102 and the gate 106a can be formed to 12 [nm] in accordance with the maximum voltage difference of 8 [V] or less in NGd so that the gate insulating film 105a can be thinned. Has been made.
- the NMOS switch 100 has a left-right asymmetric breakdown voltage structure in which the drain side connected to the word line 15 has a higher breakdown voltage structure than the source side, and is formed at the end of the drain 103d. This is different from the peripheral NMOS transistor 101 in that the impurity concentration of the drain-side extension portion 110 is lower than the impurity concentration of the source-side extension portion 104c.
- a source 103c and a drain 103d are formed at a predetermined interval in the P-type well 102, and a gate insulating film 105b is provided on the P-type well 102 between the source 103c and the drain 103d. I have.
- a source side extension portion 104c is formed at the end portion of the source 103c, and a drain side extension portion 110 is formed at the end portion of the drain 103d.
- a channel region is formed between the extension portion 104c and the drain side extension portion 110, and a gate 106b is provided on the channel region via a gate insulating film 105b.
- the NMOS switch 100 corresponds to the NMOS switch 9a, (9b, 9c, 9d,...) In FIG. 2, for example, 0 [V] or 8 [V] is applied to the gate 106b when writing data. 0 [V] or 6 [V] may be applied to the source, and 0 [V] may be further applied to the P-type well 102.
- the NMOS switch 100 is configured such that the maximum voltage difference between the gate and the P-type well 102 and the maximum voltage difference between the source and the P-type well 102 are suppressed to 8 [V] or less.
- the thickness of the gate insulating film 105b between the P-type wells 102 can be formed to 12 [nm], and the gate insulating film 105b can be thinned.
- the word line 15 is connected to the drain of the NMOS switch 100 as described above, the write gate voltage of 12 [V] and the write inhibit gate voltage of 0 [V] are used when writing data. As a result, it is necessary to provide a withstand voltage structure for the maximum voltage difference of 12 [V] on the drain side. Therefore, in the NMOS switch 100, by providing the drain side extension part 110 having a low impurity concentration, the drain side extension part 110 can drop the voltage. As a result, the NMOS switch 100 has a breakdown voltage structure with respect to a voltage difference of 12 [V] on the drain side, and the gate insulating film 105b is formed to a thickness of 12 [nm] in the same manner as the peripheral NMOS transistor 101. The insulating film 105b can be thinned.
- the NMOS switch 115 shown in FIG. 10B has a left-right asymmetric breakdown voltage structure in which the drain side connected to the word line 15 has a higher breakdown voltage structure than the source side, and the drain 103d is kept away from the gate 106b.
- the offset structure is formed.
- the NMOS switch 115 has a wider gap between the source 103c and the drain 103d than the NMOS switch 100 described above, and the drain-side extension portion 104d has a larger distance than the source-side extension portion 104c.
- the gate 106b is moved away from the drain 103d and the influence of the maximum voltage difference of 12 [V] generated on the drain 103d side is reduced.
- the gate insulating film 105b can be made thinner by forming the film thickness to 12 [nm].
- the NMOS switch 117 shown in FIG. 10C has an asymmetrical withstand voltage structure as described above, and has an offset structure in which the drain 103d is formed away from the gate 106b, and the side of the side of the gate insulating film 105b. This is different from the NMOS switch 115 described above in that the wall is formed so as to cover all the drain side extension portions 104d that are spread over a wide area. Similarly to the peripheral NMOS transistor 101, the NMOS switch 117 having such a configuration also reduces the influence of the maximum voltage difference of 12 [V] generated on the drain 103d side, as the drain 103d is kept away from the gate 106b.
- the gate insulating film 105b can be made thinner by forming the film thickness to 12 [nm].
- the NMOS switch 120 shown in FIG. 11A has a left-right asymmetric withstand voltage structure as described above.
- the NMOS switch 120 includes a gate insulating film 105b with a film thickness of 12 [nm], and more than the gate insulating film 105b.
- a thick gate insulating film (hereinafter referred to as a thick gate oxide film) 105f is formed.
- the NMOS switch 120 has a stepped portion that is recessed upward at the bottom end of the gate 106c located on the drain 103d side, and is recessed so that the bottom of the gate 106c is away from the P-type well 102.
- the gate 106c and the P-type well 102 are separated from each other, and the influence of the maximum voltage difference of 12 [V] generated on the drain 103d side can be alleviated.
- the film of the gate insulating film 105b on the one source 103c side The thickness can be reduced to 12 [nm].
- the source 103c and the drain 103e are spaced apart from each other in the P-type well 124 having a well concentration lower than that of the P-type well 102 of the peripheral NMOS transistor 101. Is formed. Inside the P-type well 124, a source-side extension part 104c is formed at the end of the source, and another extension part 125 having a different impurity concentration is formed so as to cover the source 103c and the source-side extension part 104c. ing.
- a buried oxide film 105g is formed at the end of the drain 103e inside the P-type well 124, and a drain-side extension part 126 is formed at the bottom of the drain 103e and the buried oxide film 105g.
- a channel region is formed between the extension portion 125 and the buried oxide 105g.
- a buried oxide film 105g is formed at a position facing the low end portion located on the drain 103e side of the gate 106d, and the gate 106d is provided by the provision of the buried oxide 105g.
- the gate insulating film 105b is formed to a thickness of 12 [nm] while reducing the influence of the maximum voltage difference of 12 [V] generated on the drain 103e side, away from the drain 103e and the drain side extension 126. It is made to become possible.
- the well concentration of the P-type well 132 is set to, for example, P of the peripheral NMOS transistor 101 as in the NMOS switch 131 shown in FIG.
- a lower concentration than the well concentration of the type well 102 is selected and the breakdown voltage itself between the source 103c and the drain 103d is increased, or a gate insulating film as in the NMOS switch 135 shown in FIG. 11D.
- a configuration may be adopted in which the film thickness of 105 h is selected to be large.
- FIG. 12 shows a mixed chip using a conventional non-volatile semiconductor memory device 212 (EEPRPM or Flash, expressed as “EEPRPM / Flash” in the figure).
- the chip 201 and the nonvolatile semiconductor memory device 255 according to the present invention (corresponding to the above-described nonvolatile semiconductor memory devices 1, 21, 27, 31, 38, 41, 51, 55, 61, “EEPRPM / Flash” in the figure) And the mixed chip 251 using the notation.
- a large number of external connection electrodes 203 such as bonding pads are arranged on the periphery of the substrate 202, and in the inner region surrounded by the external connection electrodes 203, the logic circuit power supply 207 and the CPU 208
- an analog circuit 209, a nonvolatile semiconductor memory device 212, and a RAM 210 are provided.
- the logic circuit power source 207, the CPU 208, the RAM 210, and the peripheral circuit 211 of the nonvolatile semiconductor memory device 212 are applied by the logic circuit power source 207, for example, 1.2 [V] logic.
- the region AR10 can be formed of a thin film transistor having a withstand voltage against the circuit voltage.
- the analog circuit 209 can be an area AR11 composed of a transistor having a withstand voltage against an interface voltage of, for example, 5.0 [V] or 3.3 [V].
- the nonvolatile semiconductor memory device 212 can be an area AR12 composed of a thick film transistor having a withstand voltage against a rewrite gate voltage of, for example, 12 [V] or 10 [V].
- the conventional mixed chip 201 as a breakdown voltage structure with respect to a logic circuit voltage of 1.2 [V], for example, a region AR10 in which a gate insulating film is formed of a low-voltage transistor of 3 [nm] and 5.0 [ As a breakdown voltage structure with respect to an interface voltage of V] or 3.3 [V], for example, an area AR11 composed of a 5 [V] transistor having a gate insulating film of 12 [nm] is provided.
- the gate insulating film can be thinned to about 12 [nm] by the low voltage transistor configuration in the area AR10 and the area AR11, but the nonvolatile semiconductor memory device 212 is incorporated.
- NMOS switches 9a, 9c,... (9b, 9d,%) Can be set to 8 [V] or less, so that PMOS switches 8a, 8c,. ), And the NMOS switches 9a, 9c,... (9b, 9d,...),
- a standard 5 [V] transistor is added to a circuit that handles the rewrite gate voltage and the like without changing the write gate voltage and the write inhibit gate voltage. It can be used, and a nonvolatile semiconductor memory device 255 such as a Flash memory or an EEPROM can be mounted without adding a dedicated high voltage transistor.
- the voltage values at the time of data writing and data erasing are specified in FIGS. 1 to 12, but the present invention is not limited to this.
- Various voltage values may be applied, and the voltage value may be appropriately changed as necessary, such as a write gate voltage of 10 [V], for example.
- PMOS switches 8a, 8c,... (8b, 8d,...) And NMOS switches 9a, 9c,. ,...) the switching mechanism is composed of two types of MOS switches.
- the present invention is not limited to this, and the switching mechanism is composed of only PMOS switches, or the switching mechanism is composed of only NMOS switches. It may be.
- the SONOS type memory cell C capable of storing charges in the silicon nitride film layer is applied as the memory cell capable of storing charges in the charge storage layer.
- the invention is not limited to this, and various other memory cells such as a stacked memory cell in which conductive polysilicon is formed on a tunnel oxide film and charges are accumulated in its floating gate may be applied.
- the non-selected word lines 15b, 15d,..., The P-type memory well PW2, the non-selected first bit line L1c, the non-selected second The voltage values of the bit lines L2c are all set to the same voltage.
- the voltage amplitude of the control voltage applied to the common PMOS control lines PGa to PGd and the common NMOS control lines NGa to NGd is set to 8 [V] or less
- the third embodiment In the embodiment, the voltage amplitude of the control voltage applied to the common PMOS control lines PGa to PGd and the common NMOS control lines NGa to NGd is set to 6 [V] or less.
- the common PMOS control line PGa is used.
- the voltage amplitude of the control voltage applied to PGd and the common NMOS control lines NGa to NGd is set to 6 [V] or less.
- the common PMOS control lines PGa to PGd and the common NMOS control lines NGa to The voltage amplitude of the control voltage applied to NGd may be set to 4 [V] or less.
- the write gate voltage for example, 12 [V]
- Minimum write inhibit gate voltage applied to C2 For example, if the voltage amplitude of the control voltage applied to the common PMOS control lines PGa to PGd and the common NMOS control lines NGa to NGd is selected between 0 [V]), various voltage amplitudes are selected. Also good.
- NMOS switch switching mechanism 15 Word line 36a, 36b, 36c, 36d, 71a, 71b, 71c, 71d
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Abstract
Description
(1-1)不揮発性半導体記憶装置の全体構成
図13との対応部分に同一符号を付して示す図1において、1は本発明による不揮発性半導体記憶装置を示し、同一構成でなる複数のユニット列2が行方向(左右方向)に並んで配置された構成を有する。ここで、複数のユニット列2は全て同一構成でなることから、以下、第1列目のユニット列2に着目して説明する。この場合、ユニット列2には、N型ウェルNW1、P型ウェルPW1及びP型メモリウェルPW2が順に配置されており、N型ウェルNW1及びP型ウェルPW1に電源ユニット4が形成され、メモリウェルとしてのP型メモリウェルPW2に複数のメモリセルCが行列状に形成されている。
ここで、図1は、不揮発性半導体記憶装置1において、複数のユニット列2のうち、第1列目のユニット列2の第1行1列目に配置したメモリセルCをデータが書き込まれる選択メモリセルC1とし、その他全てのユニット列2のメモリセルCを非選択メモリセルC2としたときの各箇所の電圧値を示している。なお、ここでは、説明の便宜上、選択メモリセルC1が配置されたユニット列2を選択ユニット列2aと呼び、非選択メモリセルC2だけが配置されたユニット列2を非選択ユニット列2bと呼ぶ。また、選択ユニット列2aの電源ユニット4を選択電源ユニット4aと呼び、非選択ユニット列2bの電源ユニット4を非選択電源ユニット4bと呼ぶ。
この場合、選択行3aでは、インバータ回路11によって、共通PMOS制御線PGa及び共通NMOS制御線NGaに、共通電圧として第2MOS電源線VL2における0[V]の第2制御電圧が印加されている。また、選択電源ユニット4aには、第1電源線5aにユニット電圧として12[V]の書き込みゲート電圧(電荷蓄積ゲート電圧)が印加され、一方、第2電源線6aにユニット電圧として0[V]の書き込み禁止ゲート電圧(電荷蓄積禁止ゲート電圧)が印加されている。なお、この選択ユニット列2aでは、第1電源線5aが形成されたN型ウェルNW1に、第1電源線5aの電圧値と同じ12[V]が印加され、一方、第2電源線6aが形成されたP型ウェルPW1に第2電源線6aの電圧値と同じ0[V]が印加されている。
次に、選択ユニット列2aと非選択行3bとが交わる第2領域AR2に着目して以下説明する。ここで非選択メモリセルC2だけが配置された非選択行3bでは、インバータ回路11によって、共通電圧として第1MOS電源線VL1における12[V]の第1制御電圧が、共通PMOS制御線PGb(PGc,PGd)及び共通NMOS制御線NGb(NGc,NGd)に印加されている。これにより、例えば、選択ユニット列2aの非選択行3bに配置されたPMOSスイッチ8cは、共通PMOS制御線PGbからゲートに12[V]の第1制御電圧が印加され、かつ第1電源線5aからソースに12[V]の書き込みゲート電圧が印加されてオフ状態となり、当該12[V]の書き込みゲート電圧を遮断し得るようになされている。
次に、非選択ユニット列2bの第3領域AR3に着目して以下説明する。この場合、非選択電源ユニット4bには、第1電源線5b及び第2電源線6bに6[V]の書き込み禁止ゲート電圧(電荷蓄積禁止ゲート電圧)が印加されている。また、この非選択ユニット列2bでは、第1電源線5bが形成されたN型ウェルNW1に12[V]が印加され、一方、第2電源線6bが形成されたP型ウェルPW1に0[V]が印加されている。ここで、非選択ユニット列2bの選択行3aでは、インバータ回路11によって、第2MOS電源線VL2における0[V]の第2制御電圧が、共通PMOS制御線PGaと共通NMOS制御線NGaとに印加されている。
以上の構成において、不揮発性半導体記憶装置1では、行列状に形成された複数のワード線15と、各ワード線15に連結された複数のメモリセルCと、複数のメモリセルCに選択的な電圧を印加し得る第1ビット線L1及び第2ビット線L2と、各ワード線列にそれぞれ対応して設けられた複数の電源ユニット4とを備え、ワード線15毎に一対のPMOSスイッチ8a(8b,8c,8d,…)及びNMOSスイッチ9a(9b,9c,9d,…)がそれぞれ各電源ユニット4に設けられている。
(2-1)データの書き込み動作
図1との対応部分に同一符号を付して示す図2において、21は第2の実施の形態による不揮発性半導体記憶装置を示し、図1に示した第1MOS電源線VL1及び第2MOS電源線VL2に替えて、第1PMOS電源線VL3及び第2PMOS電源線VL4と、第1NMOS電源線VL5及び第2NMOS電源線VL6とを設けた点で、上述した第1の実施の形態による不揮発性半導体記憶装置1とは相違している。実際上、この不揮発性半導体記憶装置21は、第1PMOS電源線VL3及び第2PMOS電源線VL4が列方向に延設されており、これら第1PMOS電源線VL3及び第2PMOS電源線VL4と並走するようにして第1NMOS電源線VL5及び第2NMOS電源線VL6も列方向に延設された構成を有する。
ここでは、先ず初めに第1領域AR1に着目して説明した後、第2領域AR2、第3領域AR3の順に説明する。この場合、選択ユニット列2aの選択電源ユニット4aには、第1電源線5aにユニット電圧として12[V]の書き込みゲート電圧が印加され、他方の第2電源線6aにユニット電圧として0[V]の書き込み禁止ゲート電圧が印加されている。この際、選択メモリセルC1が配置された選択行3aでは、第1PMOS電源線VL3及び第2PMOS電源線VL4に接続された第1インバータ回路24によって、共通電圧として第2PMOS電源線VL4における4[V]の第2PMOS制御電圧が共通PMOS制御線PGaに印加されている。
次に、選択ユニット列2aにおける非選択行3bの第2領域AR2について着目する。この場合、非選択メモリセルC2だけが配置された非選択行3bでは、第1インバータ回路24によって、共通電圧として第1PMOS電源線VL3における12[V]の第1PMOS制御電圧が、共通PMOS制御線PGb,PGc,PGdに印加されている。これにより、選択ユニット列2aの非選択行3bに配置されたPMOSスイッチ8cは、共通PMOS制御線PGbからゲートに12[V]の第1PMOS制御電圧が印加され、かつ第1電源線5aからソースに12[V]の書き込みゲート電圧が印加されてオフ状態となり、この書き込みゲート電圧を遮断し得るようになされている。
次に、非選択ユニット列2bにおける第3領域AR3について着目する。この場合、非選択ユニット列2bの非選択電源ユニット4bには、第1電源線5b及び第2電源線6bにそれぞれ6[V]の書き込み禁止ゲート電圧が印加されている。また、選択行3aでは、第1インバータ回路24によって、第2PMOS電源線VL4における4[V]の第2PMOS制御電圧が共通PMOS制御線PGaに印加されている。これにより、非選択ユニット列2bの選択行3aに配置されたPMOSスイッチ8bは、共通PMOS制御線PGaからゲートに4[V]の第2PMOS制御電圧が印加され、かつ第1電源線5bからソースに6[V]の書き込み禁止ゲート電圧が印加されてオン状態となり、当該書き込み禁止ゲート電圧をドレインから非選択ワード線15bへ印加し得るようになされている。
次に、この不揮発性半導体記憶装置21において、メモリセルCのデータを消去する際の電圧印加について以下説明する。図2との対応部分に同一符号を付して示す図3は、データの消去動作を行う第2の実施の形態による不揮発性半導体記憶装置27を示し、複数のメモリセルCのうち、第1領域AR1にある全てのメモリセルCのデータを消去し、それ以外の全てのメモリセルCについてはデータを消去しないときの各箇所の電圧値を示している。この場合、第1PMOS電源線VL3には、データ書き込み時と異なる10[V]の第1PMOS制御電圧が印加されているとともに、第2PMOS電源線VL4には、データ書き込み時と同じ4[V]の第2PMOS制御電圧が印加されている。また、第1NMOS電源線VL5には、データ書き込み時と同じ8[V]の第1NMOS制御電圧が印加されているとともに、第2NMOS電源線VL6にも、データ書き込み時と同じ0[V]の第2NMOS制御電圧が印加されている。
ここでは、先ず初めに第1領域AR1に着目して説明した後、第2領域AR2、第3領域AR3の順に説明する。この場合、データを消去するメモリセル(以下、これを消去メモリセルと呼ぶ)C3が配置された選択ユニット列2aの選択電源ユニット4aには、第1電源線5aに10[V]の非消去ゲート電圧が印加され、他方の第2電源線6aに0[V]の消去ゲート電圧が印加されている。この際、選択行3aでは、第1PMOS電源線VL3及び第2PMOS電源線VL4に接続された第1インバータ回路24によって、第1PMOS電源線VL3における10[V]の第1PMOS制御電圧が、共通PMOS制御線PGaに印加されている。これにより、選択ユニット列2aの選択行3aに配置されたPMOSスイッチ8aは、共通PMOS制御線PGaからゲートに10[V]の第1PMOS制御電圧が印加され、かつ第1電源線5aからソースに10[V]の非消去ゲート電圧が印加されてオフ状態となり、当該非消去ゲート電圧を遮断し得るようになされている。
次に、選択ユニット列2aにおける非選択行3bの第2領域AR2について着目する。この場合、データが消去されないメモリセル(以下、これを非消去メモリセルと呼ぶ)C4が配置された非選択行3bでは、第1インバータ回路24によって、第2PMOS電源線VL4における4[V]の第2PMOS制御電圧が、共通PMOS制御線PGb,PGc,PGdに印加されている。これにより、選択ユニット列2aの非選択行3bに配置されたPMOSスイッチ8cは、共通PMOS制御線PGbからゲートに4[V]の第2PMOS制御電圧が印加され、かつ第1電源線5aからソースに10[V]の非消去ゲート電圧が印加されてオン状態となり、この非消去ゲート電圧をドレインから非選択ワード線15cに印加し得るようになされている。
次に、非選択ユニット列2bにおける第3領域AR3について着目する。この場合、非選択ユニット列2bの非選択電源ユニット4bには、第1電源線5b及び第2電源線6bにそれぞれ6[V]の非消去ゲート電圧が印加されている。ここで、この選択行3aでは、第1インバータ回路24によって、第1PMOS電源線VL3における10[V]の第1PMOS制御電圧が共通PMOS制御線PGaに印加されている。これにより、非選択ユニット列2bの選択行3aに配置されたPMOSスイッチ8bは、共通PMOS制御線PGaからゲートに10[V]の第1PMOS制御電圧が印加され、かつ第1電源線5bからソースに6[V]の非消去ゲート電圧が印加されてオフ状態となり、当該非消去ゲート電圧を遮断し得るようになされている。
以上の構成において、この不揮発性半導体記憶装置21でも、上述した第1の実施の形態と同様の効果を得ることができる。すなわち、不揮発性半導体記憶装置21でも、例えば選択ユニット列2aの選択ワード線15aに印加される12[V]の書き込みゲート電圧に拘束されることなく、非選択ユニット列2bの非選択ワード線15b,15dに印加される書き込み禁止ゲート電圧を6[V]に設定し得、さらにP型メモリウェルPW2の電圧値や、非選択第1ビット線L1c、非選択第2ビット線L2cの電圧値を全て同電圧に設定できることから、仮に選択ユニット列2aにて選択メモリセルC1に対するデータの書き込み動作が繰り返されたとしても、非選択ユニット列2bの各非選択メモリセルC2におけるディスターブの発生を抑制し得る。
(3-1)データの書き込み動作
図2との対応部分に同一符号を付して示す図4において、31は第3の実施の形態による不揮発性半導体記憶装置を示し、この不揮発性半導体記憶装置31は、PMOSスイッチ8a,8c,…(8b,8d,…)及びNMOSスイッチ9a,9c,…(9b,9d,…)に加えて、各行毎に補助NMOSスイッチ36a,36c,…(36b,36d,…)を各電源ユニット34に設け、データの書き込み時、非選択ユニット列32bにて各非選択ワード線15b,15d,…に0[V]の書き込み禁止ゲート電圧を、補助NMOSスイッチ36b,36d,…により印加させるようにした点で、上述した第2の実施の形態による不揮発性半導体記憶装置21と相違している。
ここで、先ず初めに第1領域AR1に着目すると、選択ユニット列32aの選択電源ユニット34aには、第1電源線5aに12[V]の書き込みゲート電圧が印加され、他方の第2電源線6aに0[V]の書き込み禁止ゲート電圧が印加されている。この際、選択行3aでは、1インバータ回路24によって、共通電圧として第2PMOS電源線VL4における6[V]の第2PMOS制御電圧が、共通PMOS制御線PGaに印加されている。
次に、選択ユニット列32aにおける非選択行3bの第2領域AR2について着目する。この場合、非選択行3bでは、第1PMOS電源線VL3に印加されている12[V]の第1PMOS制御電圧を第1インバータ回路24によって選択し、当該第1PMOS制御電圧を共通PMOS制御線PGb,PGc,PGdに印加している。これにより、選択ユニット列32aの非選択行3bに配置されたPMOSスイッチ8cは、共通PMOS制御線PGbからゲートに12[V]の第1PMOS制御電圧が印加され、かつ第1電源線5aからソースに12[V]の書き込みゲート電圧が印加されてオフ状態となり、当該書き込みゲート電圧を遮断し得るようになされている。
次に、非選択ユニット列32bにおける第3領域AR3について着目する。この場合、非選択ユニット列32bの非選択電源ユニット34bには、第1電源線5bに6[V]のオフ電圧が印加され、他方の第2電源線6bに0[V]の書き込み禁止ゲート電圧が印加されている。この際、選択行3aでは、第1インバータ回路24によって、第2PMOS電源線VL4における6[V]の第2PMOS制御電圧が共通PMOS制御線PGaに印加されている。これにより、非選択ユニット列32bの選択行3aに配置されたPMOSスイッチ8bは、共通PMOS制御線PGaからゲートに6[V]の第2PMOS制御電圧が印加され、かつ第1電源線5bからソースに6[V]のオフ電圧が印加されてオフ状態となり、当該オフ電圧を遮断し得るようになされている。
次に、この不揮発性半導体記憶装置31において、メモリセルCのデータを消去する場合について以下説明する。図4との対応部分に同一符号を付して示す図5は、データの消去動作を行うときの第3の実施の形態による不揮発性半導体記憶装置38を示し、複数のメモリセルCのうち、第1領域AR1にある全てのメモリセルCのデータを消去し、それ以外の全てのメモリセルCについてはデータを消去しないときの各箇所の電圧値を示している。この場合、第1PMOS電源線VL3には10[V]の第1PMOS制御電圧が印加され、第2PMOS電源線VL4には8[V]の第2PMOS制御電圧が印加されている。また、第1NMOS電源線VL5には4[V]の第1NMOS制御電圧が印加され、第2NMOS電源線VL6には0[V]の第2NMOS制御電圧が印加されている。
ここでは、先ず初めに第1領域AR1に着目して説明した後、第2領域AR2、第3領域AR3の順に説明する。この場合、消去メモリセルC3が配置された選択ユニット列32aの選択電源ユニット34aには、第1電源線5aに10[V]の非消去ゲート電圧が印加され、他方の第2電源線6aに0[V]の消去ゲート電圧が印加されている。この際、選択行3aでは、第1PMOS電源線VL3及び第2PMOS電源線VL4に接続された第1インバータ回路24によって、第1PMOS電源線VL3における10[V]の第1PMOS制御電圧が、共通PMOS制御線PGaに印加されている。
次に、選択ユニット列32aにおける非選択行3bの第2領域AR2について着目する。この場合、非選択行3bでは、第1インバータ回路24によって、第2PMOS電源線VL4における8[V]の第2PMOS制御電圧が、共通PMOS制御線PGb,PGc,PGdに印加されている。これにより、選択ユニット列32aの非選択行3bに配置されたPMOSスイッチ8cは、共通PMOS制御線PGbからゲートに8[V]の第2PMOS制御電圧が印加され、かつ第1電源線5aからソースに10[V]の非消去ゲート電圧が印加されてオン状態となり、この非消去ゲート電圧をドレインから非選択ワード線15cに印加し得るようになされている。
次に、非選択ユニット列32bにおける第3領域AR3について着目する。この場合、非選択ユニット列32bの非選択電源ユニット34bには、第1電源線5bに8[V]のオフ電圧が印加され、第2電源線6bに4[V]の非消去ゲート電圧が印加されている。ここで、選択行3aでは、第1インバータ回路24によって、第1PMOS電源線VL3における10[V]の第1PMOS制御電圧が共通PMOS制御線PGaに印加されている。これにより、非選択ユニット列32bの選択行3aに配置されたPMOSスイッチ8bは、共通PMOS制御線PGaからゲートに10[V]の第1PMOS制御電圧が印加され、かつ第1電源線5bからソースに8[V]のオフ電圧が印加されてオフ状態となり、当該オフ電圧を遮断し得るようになされている。
(4-1)データの書き込み動作
図4との対応部分に同一符号を付して示す図6において、41は第4の実施の形態による不揮発性半導体記憶装置を示し、この不揮発性半導体記憶装置41は、上述した補助NMOSスイッチ36a,36c,…(36b,36d,…)(図4)に替えて補助PMOSスイッチ46a,46c,…(46b,46d,…)を設け、データの書き込み時、非選択ユニット列42bにて、この補助PMOSスイッチ46b,46d,…により各非選択ワード線15b,15d,…に12[V]の書き込み禁止ゲート電圧を印加するようにした点で、上述した第3の実施の形態による不揮発性半導体記憶装置31と相違している。ここで、図6は、上述した実施の形態と同様に、複数のメモリセルCのうち、第1列目のユニット列42における第1行1列目のメモリセルC、をデータが書き込まれる選択メモリセルC1とし、それ以外の全てのメモリセルCを非選択メモリセルC2としたときの各箇所の電圧値を示している。
ここで、先ず初めに第1領域AR1に着目すると、選択ユニット列42aの選択電源ユニット44aには、第1電源線5aに12[V]の書き込みゲート電圧が印加され、他方の第2電源線6aに0[V]の書き込み禁止ゲート電圧が印加されている。この際、選択メモリセルC1が配置された選択行3aでは、第1インバータ回路24によって、第2PMOS電源線VL4における6[V]の第2PMOS制御電圧が、共通PMOS制御線PGaに印加されている。
次に、選択ユニット列42aにおける非選択行3bの第2領域AR2について着目する。この場合、非選択メモリセルC2だけが配置された非選択行3bでは、第1インバータ回路24によって、第1PMOS電源線VL3における12[V]の第1PMOS制御電圧が、共通PMOS制御線PGb,PGc,PGdに印加されている。これにより、選択ユニット列42aの非選択行3bに配置されたPMOSスイッチ8cは、共通PMOS制御線PGbからゲートに12[V]の第1PMOS制御電圧が印加され、かつ第1電源線5aからソースに12[V]の書き込みゲート電圧が印加されてオフ状態となり、この書き込みゲート電圧を遮断し得るようになされている。
次に、非選択ユニット列42bにおける第3領域AR3について着目する。この場合、非選択ユニット列42bの非選択電源ユニット44bには、第1電源線5bに12[V]の書き込み禁止ゲート電圧が印加され、他方の第2電源線6bに6[V]のオフ電圧が印加されている。この際、選択行3aでは、第1インバータ回路24によって、第2PMOS電源線VL4における6[V]の第2PMOS制御電圧が、共通PMOS制御線PGaに印加されている。これにより、非選択ユニット列42bの選択行3aに配置されたPMOSスイッチ8bは、共通PMOS制御線PGaからゲートに6[V]の第2PMOS制御電圧が印加され、かつ第1電源線5bからソースに12[V]の書き込み禁止ゲート電圧が印加されてオン状態となり、当該12[V]の書き込み禁止ゲート電圧をドレインから非選択ワード線15bに印加し得るようになされている。
以上の構成において、不揮発性半導体記憶装置41でも、上述した第2の実施の形態と同様の効果を得ることができる。また、この第4の実施の形態による不揮発性半導体記憶装置41では、PMOSスイッチ8a,8c,…(8b,8d,…)及びNMOSスイッチ9a,9c,…(9b,9d,…)をオンオフ動作させるのに必要となる制御電圧に拘束されることなく、電源ユニット44毎に設けた補助MOS電源線45a(45b)からの補助制御電圧に応じてオンオフ動作する補助PMOSスイッチ46a,46c,…(46b,46d,…)を設けるようにした。
(5-1)データの書き込み動作
図4との対応部分に同一符号を付して示す図7において、51は第5の実施の形態による不揮発性半導体記憶装置を示し、この不揮発性半導体記憶装置51は、補助NMOSスイッチ36a,36c,…(36b,36d,…)を設けた構成を有している点で上述した第3の実施の形態と同じであるが、データの書き込み時、非選択ユニット列32bにおいて、P型メモリウェルPW2に4[V]を印加し、さらに各非選択ワード線15b,15dに補助NMOSスイッチ36b,36d,…を介して4[V]の書き込み禁止ゲート電圧を印加するようにした点で、上述した第3の実施の形態とは相違している。
以上の構成において、不揮発性半導体記憶装置51でも、上述した第3の実施の形態と同様の効果を得ることができる。また、この不揮発性半導体記憶装置51では、データ書き込み時、非選択ユニット列32bのP型ウェルPW1に0[V]を印加し、補助NMOSスイッチ36b,36d,…をオン動作させて、非選択ユニット列32bの各非選択ワード線15b,15d,…に4[V]の書き込み禁止ゲート電圧を印加するようにした。
(6-1)データの書き込み動作
図7との対応部分に同一符号を付して示す図8において、55は第6の実施の形態による不揮発性半導体記憶装置を示し、この不揮発性半導体記憶装置55は、上述した第5の実施の形態と同じ回路構成を有しているが、PMOSスイッチ8a,8c,…(8b,8d,…)及びNMOSスイッチ9a,9c,…(9b,9d,…)の各ゲートにおける電圧値と、データ書き込み時における非選択ユニット列32bにおける各電圧値とが、上述した第5の実施の形態による不揮発性半導体記憶装置51とは相違している。
ここで、先ず初めに第1領域AR1に着目すると、選択ユニット列32aの選択電源ユニット34aには、上述した第5の実施の形態と同様に、第1電源線5aに12[V]の書き込みゲート電圧が印加され、他方の第2電源線6aに0[V]の書き込み禁止ゲート電圧が印加されている。この際、選択メモリセルC1が配置された選択行3aでは、第1インバータ回路24によって、第2PMOS電源線VL4における8[V]の第2PMOS制御電圧が、共通PMOS制御線PGaに印加されている。
次に、選択ユニット列32aにおける非選択行3bの第2領域AR2について着目する。この場合、非選択メモリセルC2だけが配置された非選択行3bでは、第1インバータ回路24によって、第1PMOS電源線VL3における12[V]の第1PMOS制御電圧が共通PMOS制御線PGb,PGc,PGdに印加されている。これにより、選択ユニット列32aの非選択行3bに配置されたPMOSスイッチ8cは、共通PMOS制御線PGbからゲートに12[V]の第1PMOS制御電圧が印加され、かつ第1電源線5aからソースに12[V]の書き込みゲート電圧が印加されてオフ状態となり、この書き込みゲート電圧を遮断し得るようになされている。
次に、非選択ユニット列32bにおける第3領域AR3について着目する。この場合、非選択ユニット列32bの非選択電源ユニット34bには、第1電源線5bに8[V]のオフ電圧が印加され、他方の第2電源線6bに4[V]の書き込み禁止ゲート電圧が印加されている。この際、選択行3aでは、第1インバータ回路24によって、第2PMOS電源線VL4における8[V]の第2PMOS制御電圧が共通PMOS制御線PGaに印加されている。これにより、非選択ユニット列32bの選択行3aに配置されたPMOSスイッチ8bは、共通PMOS制御線PGaからゲートに8[V]の第2PMOS制御電圧が印加され、かつ第1電源線5bからソースに8[V]のオフ電圧が印加されてオフ状態となり、当該オフ電圧を遮断し得るようになされている。
以上の構成において、この不揮発性半導体記憶装置55でも、上述した第3の実施の形態と同様の効果を得ることができる。また、この第6の実施の形態による不揮発性半導体記憶装置55では、非選択ユニット列32bにて、PMOSスイッチ8b,8d,…及びNMOSスイッチ9b,9d,…を必ずしもオン動作させる必要がないため、選択ユニット列32aにて、PMOSスイッチ8a,8c,…及びNMOSスイッチ9a,9c,…をオンオフ動作させる制御電圧値を自由に設定することができ、かくして、PMOSスイッチ8a,8c,…や、NMOSスイッチ9a,9c,…、さらには補助NMOSスイッチ36a,36c,…(36b,36d,…)をオンオフ動作させる最大電圧差を、例えば第3の実施の形態よりも一段と低い4[V]以下に設定できる。
(7-1)データの書き込み動作
図4との対応部分に同一符号を付して示す図9において、61は第7の実施の形態による不揮発性半導体記憶装置を示し、この不揮発性半導体記憶装置61は、PMOSスイッチ69a,69c,…(69b,69d,…)及びNMOSスイッチ70a,70c,…(70b,70d,…)に加えて、補助NMOSスイッチ71a,71c,…(71b,71d,…)が設けられている他、列方向に延びるPMOS電源線VPa(VPb)及びNMOS電源線VNa(VNb)がユニット配線としてユニット列62毎に設けられている点と、行方向に延びる複数の共通電源線67a,67b,67c,67dが共通配線として設けられ、各電源ユニット64間が共通電源線67a~67dにより接続されている点とに特徴がある。ここで、図9は、上述した第3の実施の形態と同様に、複数のメモリセルCのうち、第1列目のユニット列62における第1行1列目のメモリセルCを、データが書き込まれる選択メモリセルC1とし、それ以外の全てのメモリセルCを非選択メモリセルC2としたときの各箇所の電圧値を示している。
ここでは、先ず初めに第1領域AR1に着目して説明した後、第2領域AR2、第3領域AR3の順に説明する。この場合、選択メモリセルC1が配置された選択行3aでは、第1電源線65及び第2電源線66に接続されたインバータ回路63によって、第1電源線65における12[V]の書き込みゲート電圧が、共通電圧として共通電源線67aに印加されている。この際、選択ユニット列62aでは、PMOS電源線VPaに6[V]の第1PMOS制御電圧がユニット電圧として印加されており、各PMOSスイッチ69a,69c,…のゲートに、当該第1PMOS制御電圧をそれぞれ印加し得るようになされている。
次に、選択ユニット列62aにおける非選択行3bの第2領域AR2について着目する。この場合、非選択メモリセルC2だけが配置された非選択行3bでは、インバータ回路63によって、第2電源線66における0[V]の書き込み禁止ゲート電圧が、共通電圧として共通電源線67b,67c,67dに印加されている。これにより、選択ユニット列62aの非選択行3bに配置されたPMOSスイッチ69cは、PMOS電源線VPaからゲートに6[V]の第1PMOS制御電圧が印加され、かつ共通電源線67bからソースに0[V]の書き込み禁止ゲート電圧が印加されてオフ状態となり、この書き込み禁止ゲート電圧を遮断し得るようになされている。
次に、非選択ユニット列62bにおける第3領域AR3について着目する。この場合、非選択ユニット列62bの非選択電源ユニット64bには、PMOS電源線VPbに12[V]の第2PMOS制御電圧が印加されている。また、この際、選択行3aでは、インバータ回路63によって、第1電源線65における12[V]の書き込みゲート電圧が共通電源線67aに印加されている。これにより、非選択ユニット列62bの選択行3aに配置されたPMOSスイッチ69bは、共通電源線67aからソースに12[V]の書き込みゲート電圧が印加されるものの、PMOS電源線VPbからゲートに12[V]の第2PMOS制御電圧が印加されてオフ状態となり、当該書き込みゲート電圧を遮断し得るようになされている。
以上の構成において、この不揮発性半導体記憶装置61では、行列状に形成された複数のワード線15と、各ワード線15に連結された複数のメモリセルCと、複数のメモリセルCに選択的な電圧を印加し得る第1ビット線L1及び第2ビット線L2と、ワード線列にそれぞれ対応して設けられた複数の電源ユニット64とを備え、各ワード線15に対応させてPMOSスイッチ69a,69c,…(69b,69d,…)とNMOSスイッチ70a,70c,…(70b,70d,…)と補助NMOSスイッチ71a,71c,…(71b,71d,…)とを各電源ユニット64に設け、電源ユニット64の同一行のPMOSスイッチ69a,69c,…(69b,69d,…)及びNMOSスイッチ70a,70c,…(70b,70d,…)の各ソース間を共通電源線67a~67dにて接続するようにした。
ここでは、一例として、上述した第1~第7の実施の形態のうち、図2に示す第2の実施の形態による不揮発性半導体記憶装置21に着目し、この不揮発性半導体記憶装置21のNMOSスイッチ9a,9c,…(9b,9d,…)の耐圧構造について説明する。この場合、各電源ユニット4のNMOSスイッチ9a,9c,…(9b,9d,…)には、一端に第2電源線6a(6b)が接続され、他端にワード線15が接続され、さらにゲートに共通NMOS制御線NGa~NGdが接続されている。
ここで、図12は、従来の不揮発性半導体記憶装置212(EEPRPM又はFlashであり、図中、「EEPRPM/Flash」と表記)を用いた混載チップ201と、本発明による不揮発性半導体記憶装置255(上述した不揮発性半導体記憶装置1,21,27,31,38,41,51,55,61に相当し、図中、「EEPRPM/Flash」と表記)を用いた混載チップ251とを示している。この場合、従来の混載チップに201は、基板202の周縁に多数のボンディングパッド等の外部接続電極203が配置され、それら外部接続電極203で囲まれた内側領域に、ロジック回路電源207と、CPU208と、アナログ回路209と、不揮発性半導体記憶装置212と、RAM210とが設けられている。
なお、上述した実施の形態では、図1~図12において、データ書き込み時や、データ消去時における電圧値をそれぞれ明記しているが、本発明はこれに限らず、種々の電圧値を適用してもよく、例えば10[V]の書き込みゲート電圧等、必要に応じて電圧値を適宜変更してもよい。また、例えば、第2の実施の形態や第3の実施の形態等では、切替機構として、PMOSスイッチ8a,8c,…(8b,8d,…)とNMOSスイッチ9a,9c,…(9b,9d,…)の2種類のMOSスイッチで切替機構を構成した場合について述べたが、本発明はこれに限らず、PMOSスイッチだけで切替機構を構成したり、NMOSスイッチだけで切替機構を構成するようにしてもよい。
2 ユニット列
4、34、44、64、78 電源ユニット
5a、5b 第1電源線(ユニット配線)
6a、6b 第2電源線(ユニット配線)
7a、7b、45a、45b 補助MOS電源線(補助切替電源線)
8a、8b、8c、8d、69a、69b、69c、69d PMOSスイッチ(切替機構)
9a、9b、9c、9d、70a、70b、70c、70d NMOSスイッチ(切替機構)
15 ワード線
36a、36b、36c、36d、71a、71b、71c、71d 補助NMOSスイッチ(補助スイッチ)
46a、46b、46c、46d 補助PMOSスイッチ(補助スイッチ)
C メモリセル
C1、C3 選択メモリセル
C2、C4 非選択メモリセル
L1 第1ビット線(ビット線)
L2 第2ビット線(ビット線)
PGa、PGb、PGc、PGd 共通PMOS制御線(共通配線)
NGa、NGb、NGc、NGd 共通NMOS制御線(共通配線)
67a、67b、67c、67d 共通電源線(共通配線)
VPa、VPb PMOS電源線(ユニット配線)
VNa、VNb NMOS電源線(ユニット配線)
PW2 P型メモリウェル(メモリセル)
NW2 N型メモリウェル(メモリウェル)
Claims (12)
- 電荷蓄積ゲート電圧又は電荷蓄積禁止ゲート電圧のいずれか一方が印加される行列状に形成された複数のワード線と、前記各ワード線に連結された複数のメモリセルと、前記複数のメモリセルに選択的な電圧を印加するビット線とを備え、前記ワード線に印加された前記電荷蓄積ゲート電圧と、前記ビット線に印加された電圧との電圧差により、前記複数のメモリセルのうち選択メモリセルに電荷を蓄積させる不揮発性半導体記憶装置であって、
ワード線列毎に設けられた電源ユニットと、ワード線行毎に設けられた共通配線とを備え、各前記共通配線は、所定の共通電圧を前記ワード線行単位で各前記電源ユニットに印加し、
各前記電源ユニットには、
前記ワード線毎に設けられ、前記ワード線を前記共通配線に接続する切替機構と、
前記ワード線列に前記選択メモリセルがあるか否かに応じて、異なるユニット電圧を前記電源ユニット内の各前記切替機構に一律に印加するユニット配線とが設けられており、
各前記電源ユニット毎に印加される前記ユニット電圧と、前記共通電圧との電圧差を基に、各前記電源ユニットの前記切替機構をオンオフ動作させることで、前記電源ユニットを介して各前記ワード線に前記電荷蓄積ゲート電圧又は前記電荷蓄積禁止ゲート電圧を個別に印加する
ことを特徴とする不揮発性半導体記憶装置。 - 前記切替機構は、少なくともPMOSスイッチとNMOSスイッチとを備えており、
前記PMOSスイッチ及び前記NMOSスイッチは、前記共通電圧と前記ユニット電圧とがそれぞれ印加されることにより生じる前記共通電圧と前記ユニット電圧との電圧差を基に個別にオンオフ動作する
ことを特徴する請求項1記載の不揮発性半導体記憶装置。 - 前記共通配線は、
前記PMOSスイッチの制御ゲートに接続された共通PMOS制御線と、前記NMOSスイッチの制御ゲートに接続された共通NMOS制御線とであり、
前記ユニット配線は、
前記PMOSスイッチのソースに接続された第1電源線と、前記NMOSスイッチのソースに接続された第2電源線とであり、
前記PMOSスイッチ及び前記NMOSスイッチの各ドレインには前記ワード線が接続されている
ことを特徴とする請求項2記載の不揮発性半導体記憶装置。 - 前記電源ユニットのうち、前記選択メモリセルがある選択ワード線が接続された選択電源ユニットでは、
前記NMOSスイッチがオフ状態になり、ソースに前記電荷蓄積ゲート電圧が印加されている前記PMOSスイッチがオン状態になることで、該PMOSスイッチのドレインから前記選択ワード線に前記電荷蓄積ゲート電圧を印加する
ことを特徴とする請求項2または3記載の不揮発性半導体記憶装置。 - 前記共通PMOS制御線には、第1PMOS電源線及び第2PMOS電源線が第1選択手段を介して接続されており、
前記共通PMOS制御線は、前記第1選択手段によって、前記第1PMOS電源線又は前記第2PMOS電源線のいずれか一方の制御電圧を、各電源ユニットの前記PMOSスイッチに印加し、
前記共通NMOS制御線には、第1NMOS電源線及び第2NMOS電源線が第2選択手段を介して接続されており、
前記共通NMOS制御線は、前記第2選択手段によって、前記第1NMOS電源線又は前記第2NMOS電源線のいずれか一方の制御電圧を、各前記電源ユニットの前記NMOSスイッチに印加する
ことを特徴とする請求項3記載の不揮発性半導体記憶装置。 - 前記共通配線は、
前記PMOSスイッチ及び前記NMOSスイッチの各ソースに接続された共通電源線であり、
前記ユニット配線は、
前記PMOSスイッチの制御ゲートに接続されたPMOS電源線と、前記NMOSスイッチの制御ゲートに接続されたNMOS電源線とであり、
前記PMOSスイッチ及びNMOSスイッチの各ドレインには前記ワード線が接続されている
ことを特徴とする請求項2記載の不揮発性半導体記憶装置。 - 前記電源ユニットには、
前記切替機構毎に設けられ、前記ユニット配線と接続された補助スイッチと、
前記ワード線列に前記選択メモリセルがあるか否かに応じて、異なる補助制御電圧を前記電源ユニット内の各前記補助スイッチに一律に印加する補助切替電源線とが設けられており、
前記ワード線列内に前記非選択メモリセルだけを有するとき、前記ユニット電圧と前記補助制御電圧との電圧差を基に前記補助スイッチをオン動作させ、前記ユニット電圧を前記電荷蓄積禁止ゲート電圧として、前記選択メモリセル以外の非選択メモリセルだけが接続された非選択ワード線に印加する
ことを特徴とする請求項1~6のうちいずれか1項記載の不揮発性半導体記憶装置。 - 前記選択メモリセルが接続された選択ワード線の行の前記共通配線に前記共通電圧として印加される一の制御電圧と、前記選択メモリセル以外の非選択メモリセルだけが接続された非選択ワード線の行の前記共通配線に前記共通電圧として印加される他の制御電圧との制御電圧差が、
前記電荷蓄積ゲート電圧と、前記電荷蓄積禁止ゲート電圧との間の電圧値に選定されている
ことを特徴とする請求項1~7のうちいずれか1項記載の不揮発性半導体記憶装置。 - 前記制御電圧差が6[V]以下である
ことを特徴とする請求項8記載の不揮発性半導体記憶装置。 - 前記制御電圧差が4[V]以下である
ことを特徴とする請求項8記載の不揮発性半導体記憶装置。 - 前記切替機構の形成されるウェルが、各電源ユニット毎に電気的に分離して形成されている
ことを特徴とする請求項1~10のうちいずれか1項記載の不揮発性半導体記憶装置。 - 各前記ワード線列は各々電気的に離間したP型メモリウェルで構成され、前記メモリセルがNチャネル型の構成を有しており、
前記切替機構は、前記選択メモリセルが接続された選択ワード線に対して、前記ビット線に印加される電圧よりも高い電圧値の前記ユニット電圧を、前記電荷蓄積ゲート電圧として印加する
ことを特徴とする請求項1~11のうちいずれか1項記載の不揮発性半導体記憶装置。
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US9335775B2 (en) * | 2014-06-23 | 2016-05-10 | International Business Machines Corporation | Integrated circuit having regulated voltage island power system |
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US9837130B2 (en) * | 2015-12-31 | 2017-12-05 | Taiwan Semiconductor Manufacturing Company Ltd. | Digtial circuit structures to control leakage current |
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US11733763B2 (en) * | 2020-08-06 | 2023-08-22 | Micron Technology, Inc. | Intelligent low power modes for deep learning accelerator and random access memory |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6095794A (ja) | 1983-10-28 | 1985-05-29 | Hitachi Ltd | 半導体集積回路 |
JPH1173791A (ja) * | 1997-08-28 | 1999-03-16 | Sharp Corp | 不揮発性半導体記憶装置 |
JPH11177069A (ja) * | 1997-12-10 | 1999-07-02 | Matsushita Electron Corp | 不揮発性半導体記憶装置およびその書き換え方法 |
JP2000215683A (ja) * | 1999-01-20 | 2000-08-04 | Matsushita Electronics Industry Corp | 不揮発性半導体記憶装置 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5896340A (en) * | 1997-07-07 | 1999-04-20 | Invox Technology | Multiple array architecture for analog or multi-bit-cell memory |
US5886923A (en) * | 1997-10-27 | 1999-03-23 | Integrated Silicon Solution Inc. | Local row decoder for sector-erase fowler-nordheim tunneling based flash memory |
EP1028433B1 (en) * | 1999-02-10 | 2004-04-28 | SGS-THOMSON MICROELECTRONICS s.r.l. | Nonvolatile memory and reading method therefor |
EP1061525B1 (en) * | 1999-06-17 | 2006-03-08 | STMicroelectronics S.r.l. | Row decoder for a nonvolatile memory with possibility of selectively biasing word lines to positive or negative voltages |
ITMI20022240A1 (it) | 2002-10-22 | 2004-04-23 | Atmel Corp | Architettura di memoria flash con cancellazione di modo |
JP4088143B2 (ja) * | 2002-11-28 | 2008-05-21 | シャープ株式会社 | 不揮発性半導体記憶装置及び行線短絡不良検出方法 |
US7272052B2 (en) * | 2005-03-31 | 2007-09-18 | Sandisk 3D Llc | Decoding circuit for non-binary groups of memory line drivers |
JP2011138579A (ja) * | 2009-12-28 | 2011-07-14 | Toshiba Corp | 不揮発性半導体記憶装置 |
DE102011056141A1 (de) * | 2010-12-20 | 2012-06-21 | Samsung Electronics Co., Ltd. | Negativspannungsgenerator, Dekoder, nicht-flüchtige Speichervorrichtung und Speichersystem, das eine negative Spannung verwendet |
US8456914B2 (en) * | 2011-03-07 | 2013-06-04 | Elpida Memory, Inc. | Memory device with multiple planes |
JP2013125576A (ja) * | 2011-12-16 | 2013-06-24 | Samsung Electronics Co Ltd | 不揮発性半導体記憶装置 |
-
2012
- 2012-06-29 JP JP2012146954A patent/JP5908803B2/ja active Active
-
2013
- 2013-06-21 SG SG11201408686QA patent/SG11201408686QA/en unknown
- 2013-06-21 US US14/410,380 patent/US9343166B2/en active Active
- 2013-06-21 CN CN201380033347.XA patent/CN104380387B/zh active Active
- 2013-06-21 WO PCT/JP2013/067146 patent/WO2014002913A1/ja active Application Filing
- 2013-06-21 KR KR1020157002203A patent/KR101643108B1/ko active IP Right Grant
- 2013-06-21 EP EP13810694.3A patent/EP2869303B1/en active Active
- 2013-06-27 TW TW102122903A patent/TWI616883B/zh active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6095794A (ja) | 1983-10-28 | 1985-05-29 | Hitachi Ltd | 半導体集積回路 |
JPH1173791A (ja) * | 1997-08-28 | 1999-03-16 | Sharp Corp | 不揮発性半導体記憶装置 |
JPH11177069A (ja) * | 1997-12-10 | 1999-07-02 | Matsushita Electron Corp | 不揮発性半導体記憶装置およびその書き換え方法 |
JP2000215683A (ja) * | 1999-01-20 | 2000-08-04 | Matsushita Electronics Industry Corp | 不揮発性半導体記憶装置 |
Non-Patent Citations (2)
Title |
---|
IEICE TRANS, ELECTRON., vol. E84-C, no. 6, 2001 |
See also references of EP2869303A4 |
Also Published As
Publication number | Publication date |
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TW201415466A (zh) | 2014-04-16 |
EP2869303B1 (en) | 2021-03-03 |
SG11201408686QA (en) | 2015-03-30 |
KR101643108B1 (ko) | 2016-07-26 |
CN104380387B (zh) | 2017-06-13 |
US9343166B2 (en) | 2016-05-17 |
EP2869303A4 (en) | 2015-12-02 |
TWI616883B (zh) | 2018-03-01 |
EP2869303A1 (en) | 2015-05-06 |
US20150318048A1 (en) | 2015-11-05 |
JP2014010866A (ja) | 2014-01-20 |
JP5908803B2 (ja) | 2016-04-26 |
CN104380387A (zh) | 2015-02-25 |
KR20150027261A (ko) | 2015-03-11 |
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