WO2013159542A1 - 薄膜晶体管阵列基板及其制造方法和显示装置 - Google Patents

薄膜晶体管阵列基板及其制造方法和显示装置 Download PDF

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Publication number
WO2013159542A1
WO2013159542A1 PCT/CN2012/086503 CN2012086503W WO2013159542A1 WO 2013159542 A1 WO2013159542 A1 WO 2013159542A1 CN 2012086503 W CN2012086503 W CN 2012086503W WO 2013159542 A1 WO2013159542 A1 WO 2013159542A1
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Prior art keywords
contact hole
thin film
film transistor
array substrate
transistor array
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PCT/CN2012/086503
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English (en)
French (fr)
Inventor
崔贤植
徐智强
李会
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US13/991,724 priority Critical patent/US8877649B2/en
Publication of WO2013159542A1 publication Critical patent/WO2013159542A1/zh
Priority to US14/503,761 priority patent/US9177920B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133711—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by organic films, e.g. polymeric films
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Thin film transistor array substrate manufacturing method thereof and display device
  • Embodiments of the present invention relate to a thin film transistor array substrate, a method of fabricating the same, and a display device. Background technique
  • an insulating layer is formed on a thin film transistor (TFT) array substrate by using a conventional silicon nitride process (SiNx PA), and there is no problem of contact holes, as shown in FIG.
  • an insulating layer is formed on the TFT array substrate by a resin process (Resin PA).
  • Resin PA resin process
  • a plurality of pixel-like contact holes 1 appear, which are applied in a subsequent alignment liquid such as PI liquid 2
  • the PI liquid 2 flows into these contact holes, causing a decrease in the thickness of the alignment film after curing.
  • the size and the number of contact hole capacities are proportional to the decrease in the thickness of the polyimide (PI) film, that is, the more contact holes, the larger the contact holes, the more the thickness of the PI film is reduced, and the contact holes are
  • the number is proportional to the number of pixels.
  • the reduction in the thickness of the PI film caused by the contact holes is not significant and does not cause significant disadvantages; however, at high resolutions greater than 1700 PPI, for example A contact hole of 1.5 ⁇ m deep causes a large decrease in the thickness of the PI film, such as from 800 ⁇ to 450 ⁇ , and an excessively thin ruthenium film causes an afterimage of an image displayed by the liquid crystal device, and a problem of reduced image contrast.
  • the prior art method In order to avoid the problem of the reduction of the thickness of the ruthenium film, the prior art method generally increases the proportion of ruthenium in the mash, for example, the proportion of ruthenium in the sputum coated in the FFS TFT substrate is generally 5%-6.5%, slightly Higher than the proportion of the sputum coated in the TN TFT substrate, however, the ratio of sputum is generally difficult to be higher than 6.5%. If the proportion of bismuth in the mash is too high, the sputum is too viscous, causing sputum The problem of uneven coating. Therefore, the conventional method for the high-resolution TFT substrate cannot effectively avoid the problem caused by the reduction of the thickness of the ruthenium layer. Summary of the invention
  • the embodiment of the invention provides a thin film transistor array substrate, a manufacturing method thereof and a display device, which are used to solve the problem that the thickness of the alignment film is reduced by the contact hole in the prior art, and the residual image of the image is caused. And the problem of reduced image contrast.
  • the resin layer is patterned by a patterning process to form a spacer and a contact hole filling layer; the contact hole filling layer is used to fill a contact hole on the thin film transistor array substrate;
  • An alignment film is formed on the substrate on which the spacer and the contact hole filling layer are formed.
  • the embodiment of the invention further provides a thin film transistor array substrate, including a thin film transistor array and an alignment film, further comprising:
  • the alignment film is formed on the contact hole filling layer and the thin film transistor array.
  • the embodiment of the invention further provides a display device comprising the thin film transistor array substrate provided by the implementation of the invention.
  • FIG. 1 is a schematic view showing a structure in which an alignment film is formed by using SiNx PA to form an insulating layer on a TFT array substrate in the prior art
  • FIG. 2 is a schematic view showing a structure in which an alignment film is formed when an insulating layer is formed on a TFT array substrate by using Resin PA;
  • FIG. 3 is a flow chart of a method for fabricating a TFT array substrate according to an embodiment of the present invention
  • FIG. 4 is a schematic structural view showing a resin layer formed on a TFT array substrate according to an embodiment of the present invention
  • FIG. 5 is a schematic view showing exposure processing of a resin layer using a two-tone mask according to an embodiment of the present invention
  • FIG. 6 is a schematic structural diagram of a TFT array substrate after development according to an embodiment of the present invention
  • FIG. 7 is a schematic structural diagram of a TFT array substrate according to an embodiment of the present invention. detailed description
  • a method for fabricating a thin film transistor array substrate provided by an embodiment of the present invention, as shown in FIG. 3, includes the following steps:
  • Step S301 forming a resin layer on the substrate on which the thin film transistor array is formed.
  • the thickness of the formed resin layer 3 is greater than the hole depth of the contact hole 4 on the thin film transistor array substrate, that is, the resin layer 3 will fill the contact hole 4;
  • the resin layer 3 formed on the array substrate on which the thin film transistor is formed is a photosensitive material layer.
  • the material of the resin layer 3 may be a positive photosensitive material or a negative photosensitive material.
  • the formation of the resin layer 3 belongs to the prior art and will not be described herein.
  • Step S302 patterning the resin layer by using a patterning process to form a spacer and a contact hole filling layer
  • the contact hole filling layer is used to fill a contact hole on the thin film transistor array substrate
  • the thickness of the contact hole filling layer formed is the same as the depth of the contact hole.
  • the resin layer is patterned by a patterning process, and the process of forming the spacer and the contact hole filling layer includes:
  • the resin layer 3 is subjected to exposure treatment using a two-tone mask 5 as shown in FIG. 5; wherein the completely light-transmitting region of the two-tone mask 5 corresponds to the resin layer 3 for formation. a region 6 of the spacer, a portion of the light-transmitting region of the two-tone mask 5 corresponds to the region 7 of the resin layer 3 for forming the contact hole filling layer, and the completely opaque region of the two-tone mask 5 corresponds to the resin layer 5 except for Further, the area of the spacer and the contact hole filling layer is formed; further, the two-tone mask 5 may be a Half Tone Mask or a Gray Tone Mask.
  • the resin layer 3 is a negative photosensitive material layer, after exposure to light (indicated by an arrow in FIG. 5), the resin layer 3 corresponding to the completely light-transmitting region of the two-tone mask 5 is used to form a spacer.
  • the region 6 of the object will produce a photochemical reaction to form the desired spacer (PS); the portion of the resin layer 3 corresponding to the partially transparent region of the two-tone mask 5 for forming the contact hole filling layer will have a part of the resin.
  • Photochemical reaction forming a contact hole filling layer to fill the contact hole on the thin film transistor array substrate; and the region of the resin layer 3 corresponding to the completely opaque region of the two-tone mask has no photochemical reaction, and is removed in subsequent operations. Drop it.
  • the resin layer is subjected to development treatment to remove the resin layer which does not undergo photochemical reaction, and the spacer 8 and the contact hole filling layer 9 are formed. As shown in FIG. 6, the spacer 8 is formed on the thin film transistor array substrate. It will play the role of liquid crystal gap during the process of bonding with the color film substrate.
  • the exposure amount for the region 6 of the resin layer 3 for forming the spacer may be 100%; the exposure amount for the region 7 of the resin layer 3 for forming the contact hole filling layer may be less than 50% .
  • the exposure time is generally controlled at 3-8 seconds, which can prevent overexposure to ensure that the height of the contact hole filling layer 9 formed in the contact hole coincides with the depth of the contact hole, so that the surface of the contact hole is flush with other regions. level.
  • an alignment film 10 on the substrate on which the spacers 8 and the contact hole filling layer 9 are formed.
  • an alignment film PI film
  • FIG. 7 an alignment film
  • the uniform alignment liquid is solidified to form the alignment film 10 having a uniform thickness, thereby preventing the afterimage and the contrast unevenness caused by the thickness reduction, since the formation process of the alignment film 10 is present
  • it can be a printing process or a coating process, no longer here. Said.
  • the thickness of the formed alignment film 10 is generally from 0.6 to 0.8 ⁇ m.
  • a process of printing an alignment liquid a plurality of times may be employed to ensure the thickness of the formed alignment film.
  • the embodiment of the invention further provides a thin film transistor array substrate, as shown in FIG. 7, comprising a thin film transistor array 11 and an alignment film 10, further comprising:
  • the alignment film 10 is formed on the contact hole filling layer 9 and the thin film transistor array 11.
  • the material of the spacer 8 and the contact hole filling layer 9 in the above-described thin film transistor array substrate is a resin material, and may be, for example, a negative photosensitive material and a positive photosensitive material.
  • the thickness of the contact hole filling layer 9 in the above-described thin film transistor array substrate coincides with the depth of the contact hole.
  • the thickness of the alignment film 10 in the thin film transistor array substrate is 0.6 to 0.8 ⁇ m.
  • the embodiment of the invention further provides a display device comprising the above-mentioned thin film transistor array substrate provided by the embodiment of the invention.
  • the display device may be: a product or a component having any display function such as a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, a tablet computer, or the like.
  • a thin film transistor array substrate, a manufacturing method thereof and a display device a resin layer is formed on a substrate on which a thin film transistor array is formed; a resin layer is patterned by a patterning process to form a spacer and a contact hole filling
  • the contact hole filling layer is for filling a contact hole on the thin film transistor array substrate; and an alignment film is formed on the substrate on which the spacer and the contact hole filling layer are formed. Since the contact hole filling layer is used to fill the contact hole on the array substrate, the alignment liquid does not flow into the contact hole when the subsequent alignment liquid is applied, thereby causing a decrease in the thickness of the formed alignment film, thereby avoiding image afterimage and The problem of reduced image contrast.

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Spectroscopy & Molecular Physics (AREA)
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Abstract

提供了一种薄膜晶体管阵列基板及其制造方法和显示装置，所述薄膜晶体管阵列基板的制作方法包括：在形成有薄膜晶体管阵列的基板上形成树脂层（3）；利用构图工艺对树脂层（3）进行构图，形成隔垫物（8）和接触孔填充层（9）；所述接触孔填充层（9）用于填充薄膜晶体管阵列基板上的接触孔（4）；在形成有隔垫物（8）和接触孔填充层（9）的基板上形成取向膜（10）。由于使用接触孔填充层（9）填平阵列基板上的接触孔（4），在后续取向液涂覆时，取向液就不会流到接触孔（4）内，而引起取向液固化后形成的取向膜（10）厚度减少，避免了图像出现残像以及图像对比度减少的问题。

Description

薄膜晶体管阵列基板及其制造方法和显示装置 技术领域
本发明的实施例涉及一种薄膜晶体管阵列基板及其制造方法和显示装 置。 背景技术
目前，在薄膜晶体管（ TFT )阵列基板上使用传统的氮化硅工艺（ SiNx PA ) 制作绝缘层， 不会出现接触孔的问题， 如图 1所示。 但是， 在 TFT阵列基板 上使用树脂工艺 （Resin PA )制作绝缘层， 如图 2所示， 就会出现许多像像 素点一样的接触孔 1 , 在后续的取向液例如 PI液 2涂覆时， PI液 2会流到这 些接触孔中， 引起固化后的取向膜厚度减少。
一般地， 接触孔容量的大小以及数量的多少和聚酰亚胺 (PI)膜厚度的减 少成正比， 即， 接触孔越多， 接触孔越大， PI膜厚度减少的越多， 而接触孔 的数量正比于像素的数量， 在 60-120PPI的普通分辨率下， 接触孔引起的 PI 膜厚度的减少还不明显， 不会造成明显的缺点； 但是， 在大于 1700PPI的高 分辨率下， 例如 1.5μπι深的接触孔会引起 PI膜厚度较大的减少， 如从 800Α 减少到 450Α, 过薄的 ΡΙ膜会引起液晶器件显示的图像出现残像， 以及图像 对比度减少问题。
为了避免 ΡΙ膜厚度减少的问题， 现有技术中的方法一般为增加 ΡΙ液中 ΡΙ的比例 ,例如：在 FFS TFT基板中涂覆的 ΡΙ液中 ΡΙ的比例一般在 5%-6.5%, 稍高于在 TN TFT基板中涂覆的 ΡΙ液中的比例， 但是， 一般 ΡΙ液的比例很 难高于 6.5%, 如果 ΡΙ液中 ΡΙ的比例太高， ΡΙ液过于粘稠， 会引起 ΡΙ液涂 覆不均匀的问题。 因此， 现有的这种做法对于高分辨率的 TFT基板， 并不能 有效地避免 ΡΙ层厚度的减少而带来的问题。 发明内容
本发明实施例提供了一种薄膜晶体管阵列基板及其制造方法和显示装 置， 用以解决现有技术中接触孔引起取向膜厚度减少， 引起图像出现残像以 及图像对比度减少的问题。
本发明实施例提供的薄膜晶体管阵列基板的制作方法， 包括：
在形成有薄膜晶体管阵列的基板上形成树脂层；
利用构图工艺对所述树脂层进行构图， 形成隔垫物和接触孔填充层； 所 述接触孔填充层用于填充所述薄膜晶体管阵列基板上的接触孔；
在形成有所述隔垫物和所述接触孔填充层的基板上形成取向膜。
本发明实施例还提供了一种薄膜晶体管阵列基板， 包括薄膜晶体管阵列 和取向膜， 还包括：
位于所述薄膜晶体管阵列上的隔垫物； 以及
填充在所述薄膜晶体管阵列基板上的接触孔内的接触孔填充层； 所述取向膜形成在所述接触孔填充层和所述薄膜晶体管阵列上。
本发明实施例还提供了一种显示装置， 包括本发明实施提供的薄膜晶体 管阵列基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为现有技术中在 TFT阵列基板上使用 SiNx PA制作绝缘层时形成取 向膜后的结构示意图；
图 2为现有技术中在 TFT阵列基板上使用 Resin PA制作绝缘层时形成 取向膜后的结构示意图；
图 3为本发明实施例提供的 TFT阵列基板的制造方法的流程图； 图 4为本发明实施例提供的 TFT阵列基板上形成树脂层后的结构示意 图；
图 5为本发明实施例提供的使用双色调掩膜板对树脂层进行曝光处理的 示意图；
图 6为本发明实施例提供的显影后的 TFT阵列基板的的结构示意图； 图 7为本发明实施例提供的 TFT阵列基板的结构示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一" 、 "第二" 以及类似的词语并不表示任何顺序、 数量或者重要性，而只是用来区分不同的组成部分。同样， "一个 "或者 "一" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "连接" 或者 "相 连" 等类似的词语并非限定于物理的或者机械的连接， 而是可以包括电性的 连接， 不管是直接的还是间接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用 于表示相对位置关系， 当被描述对象的绝对位置改变后， 则该相对位置关系 也相应地改变。
本发明实施例提供的一种薄膜晶体管阵列基板的制作方法，如图 3所示， 包括以下几个步骤：
步骤 S301、 在形成有薄膜晶体管阵列的基板上形成树脂层。
如图 4所示， 形成的树脂层 3的厚度会大于薄膜晶体管阵列基板上的接 触孔 4的孔深， 即树脂层 3将会填满接触孔 4;
具体地， 在形成有薄膜晶体管的阵列基板上形成的树脂层 3为感光材料 层。
其中， 树脂层 3的材料可以是正性感光材料， 也可是负性感光材料， 树 脂层 3的形成属于现有技术， 在此不再赘述。
以下步骤， 以负性感光材料为例进行说明， 但本发明并不局限于负性感 光材料。
步骤 S302、 利用构图工艺对树脂层进行构图， 形成隔垫物和接触孔填充 层；
所述接触孔填充层用于填充薄膜晶体管阵列基板上的接触孔；
例如， 形成的接触孔填充层的厚度和接触孔的深度一致。 例如， 步骤 S302利用构图工艺对树脂层进行构图， 形成隔垫物和接触 孔填充层的过程包括：
在形成有树脂层 3的阵列基板上， 利用双色调掩模板 5对树脂层 3进行 曝光处理， 如图 5所示； 其中， 双色调掩模板 5的完全透光区域对应树脂层 3用于形成隔垫物的区域 6, 双色调掩模板 5的部分透光区域对应树脂层 3 用于形成接触孔填充层的区域 7 , 双色调掩模板 5的完全不透光区域对应树 脂层 5除用于形成隔垫物和接触孔填充层以外的区域； 进一步的， 双色调掩 模板 5可以是半色调掩模板 ( Half Tone Mask ) , 也可以是灰色调掩模板 ( Gray Tone Mask ) 。
由于树脂层 3为负性感光材料层， 因此， 在经过光照射（图 5中的箭头 所示） 即曝光后， 双色调掩模板 5的完全透光区域对应的树脂层 3用于形成 隔垫物的区域 6会产生光化学反应， 形成所需的隔垫物（PS )； 双色调掩模 板 5的部分透光区域对应的树脂层 3用于形成接触孔填充层的区域 7会有部 分树脂发生光化学反应， 形成接触孔填充层， 填平薄膜晶体管阵列基板上的 接触孔； 而双色调掩模板的完全不透光区域对应的树脂层 3的区域没有发生 光化学反应， 在后续操作中会被去除掉。
曝光处理后， 对树脂层进行显影处理， 去除掉没有发生光化学反应的树 脂层， 形成隔垫物 8和接触孔填充层 9, 如图 6所示， 形成的隔垫物 8在薄 膜晶体管阵列基板和彩膜基板的对合过程中将会起到液晶间隙的作用。
例如， 在曝光过程中， 对于树脂层 3用于形成隔垫物的区域 6的曝光量 可以为 100%; 对于树脂层 3用于形成接触孔填充层的区域 7的曝光量可以 为小于 50%。 并且， 曝光时间一般控制在 3-8秒， 这样能够防止过度曝光， 以确保形成在接触孔内的接触孔填充层 9的高度与接触孔的深度一致， 这样 使得接触孔的表面与其他区域齐平。
S303、 在形成有隔垫物 8和接触孔填充层 9的基板上形成取向膜 10。 例如取向膜（PI膜） ， 如图 7所示， 在图中可以看出， 由于接触孔已经 被接触孔填充层 9填平， 因此， 形成在薄膜晶体管阵列基板上的取向液不会 因为流到接触孔中而引起不均匀的情况， 均匀的取向液固化后形成厚度均匀 的取向膜 10, 从而防止了因厚度减少引起的残像及对比度不均的情况， 由于 取向膜 10的形成工艺为现有技术，可以是印刷工艺或涂覆工艺，在此不再赘 述。
例如， 形成的取向膜 10的厚度一般在 0.6-0.8μπι。
例如，还可以釆用多次印刷取向液的工艺，来保证形成的取向膜的厚度。 本发明实施例还提供了一种薄膜晶体管阵列基板， 如图 7所示， 包括薄 膜晶体管阵列 11和取向膜 10, 还包括：
位于薄膜晶体管阵列 11上的隔垫物 8; 以及
填充在薄膜晶体管阵列 11基板上的接触孔内的接触孔填充层 9;
其中， 取向膜 10形成在接触孔填充层 9和薄膜晶体管阵列 11上。
例如， 上述薄膜晶体管阵列基板中的隔垫物 8和接触孔填充层 9的材料 为树脂材料， 例如可以为负性感光材料和正性感光材料。
例如， 上述薄膜晶体管阵列基板中的接触孔填充层 9的厚度与接触孔的 深度一致。
例如， 上述薄膜晶体管阵列基板中的取向膜 10的厚度为 0.6~0.8μπι。 本发明实施例还提供了一种显示装置， 包括本发明实施例提供的上述薄 膜晶体管阵列基板。 所述显示装置可以为： 液晶面板、 电子纸、 OLED面板、 液晶电视、 液晶显示器、 数码相框、 手机、 平板电脑等具有任何显示功能的 产品或部件。
本发明实施例提供的一种薄膜晶体管阵列基板及其制造方法和显示装 置， 在形成有薄膜晶体管阵列的基板上形成树脂层； 利用构图工艺对树脂层 进行构图， 形成隔垫物和接触孔填充层； 该接触孔填充层用于填充薄膜晶体 管阵列基板上的接触孔； 在形成有隔垫物和接触孔填充层的基板上形成取向 膜。 由于使用接触孔填充层填平阵列基板上的接触孔，在后续取向液涂覆时， 取向液就不会流到接触孔内， 而引起生成的取向膜厚度的减少， 避免了图像 出现残像以及图像对比度减少的问题。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1、 一种薄膜晶体管阵列基板的制作方法， 包括：
在形成有薄膜晶体管阵列的基板上形成树脂层；
利用构图工艺对所述树脂层进行构图， 形成隔垫物和接触孔填充层； 所 述接触孔填充层用于填充所述薄膜晶体管阵列基板上的接触孔；
在形成有所述隔垫物和所述接触孔填充层的基板上形成取向膜。
2、 如权利要求 1所述的方法， 其中， 在形成有薄膜晶体管阵列的基板上 形成的树脂层为负性感光材料层。
3、 如权利要求 2所述的方法， 其中， 所述利用构图工艺对所述树脂层进 行构图， 形成隔垫物和接触孔填充层， 包括：
在形成有所述树脂层的阵列基板上， 利用双色调掩模板对所述树脂层进 行曝光处理， 其中， 所述双色调掩模板的完全透光区域对应所述树脂层用于 形成所述隔垫物的区域， 所述双色调掩模板的部分透光区域对应所述树脂层 用于形成所述接触孔填充层的区域， 所述双色调掩模板的完全不透光区域对 应所述树脂层除用于形成所述隔垫物和所述接触孔填充层以外的区域；
曝光处理后对所述树脂层进行显影处理， 形成所述隔垫物和所述接触孔 填充层。
4、 如权利要求 1-3任一项所述的方法， 其中， 形成的所述接触孔填充层 的厚度和所述接触孔的深度一致。
5、 如权利要求 1-4 任一项所述的方法， 其中， 所述取向膜的厚度为
0.6~0.8μπι。
6、 一种薄膜晶体管阵列基板， 包括
薄膜晶体管阵列；
取向膜；
位于所述薄膜晶体管阵列上的隔垫物； 以及
填充在所述薄膜晶体管阵列基板上的接触孔内的接触孔填充层； 其中所述取向膜形成在所述接触孔填充层和所述薄膜晶体管阵列上。
7、 如权利要求 6所述的阵列基板， 其中， 所述隔垫物和所述接触孔填充 层的材料为树脂材料。
8、 如权利要求 6-7任一项所述的阵列基板， 其中， 所述隔垫物和所述接 触孔填充层的材料为负性感光材料。
9、 如权利要求 6-8任一项所述的阵列基板， 其中， 所述接触孔填充层的 厚度与所述接触孔的深度一致。
10、如权利要求 6-9任一项所述的阵列基板， 其中， 所述取向膜的厚度为 0.6~0.8μπι。
11、 一种显示装置， 其中， 包括如权利要求 6-10任一项所述的薄膜晶体 管阵列基板。
PCT/CN2012/086503 2012-04-27 2012-12-13 薄膜晶体管阵列基板及其制造方法和显示装置 WO2013159542A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113552753A (zh) * 2021-07-23 2021-10-26 南京京东方显示技术有限公司 阵列基板的制造方法、阵列基板、显示面板及电子设备

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI624878B (zh) 2011-03-11 2018-05-21 半導體能源研究所股份有限公司 半導體裝置的製造方法
CN102650786B (zh) * 2012-04-27 2014-04-02 京东方科技集团股份有限公司 一种薄膜晶体管阵列基板及其制造方法和显示装置
CN103500731B (zh) * 2013-10-18 2015-07-01 京东方科技集团股份有限公司 Oled背板及其制作方法
CN104407224A (zh) * 2014-11-27 2015-03-11 合肥京东方光电科技有限公司 半导体-金属接触电阻率检测方法、阵列基板
KR20160086521A (ko) * 2015-01-09 2016-07-20 삼성디스플레이 주식회사 액정 표시 장치 및 그 제조 방법
CN104656315B (zh) * 2015-03-17 2017-08-25 合肥鑫晟光电科技有限公司 液晶显示基板及其制备方法
CN104880865B (zh) * 2015-06-19 2019-03-19 武汉华星光电技术有限公司 阵列基板及其制作方法、液晶面板
CN105159000B (zh) * 2015-09-25 2018-07-06 昆山龙腾光电有限公司 薄膜晶体管阵列基板及液晶显示面板
CN105304647B (zh) * 2015-10-22 2018-10-12 重庆京东方光电科技有限公司 一种阵列基板、其制作方法、及显示装置
CN105304649B (zh) * 2015-10-28 2019-01-18 京东方科技集团股份有限公司 阵列基板及其制作方法、显示面板、显示装置
KR102515002B1 (ko) * 2015-12-28 2023-03-28 엘지디스플레이 주식회사 어레이 기판 및 이를 갖는 디스플레이 패널
CN107422543B (zh) * 2017-07-04 2020-07-28 京东方科技集团股份有限公司 一种显示面板及其制备方法、显示装置
CN111225947B (zh) * 2017-10-18 2022-07-26 奥升德功能材料运营有限公司 含卤素的阻燃性聚酰胺组合物
CN111370496B (zh) * 2020-03-18 2021-10-26 京东方科技集团股份有限公司 薄膜晶体管及其制作方法、显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11111995A (ja) * 1997-10-03 1999-04-23 Matsushita Electric Ind Co Ltd 表示装置の製造方法
CN1447153A (zh) * 2002-03-22 2003-10-08 精工爱普生株式会社 电光装置及其制造方法以及电子机器
CN1499277A (zh) * 2002-10-31 2004-05-26 ������������ʽ���� 电光装置及电子设备
CN1599080A (zh) * 2003-06-25 2005-03-23 三星Sdi株式会社 薄膜晶体管及平板显示装置
CN101051160A (zh) * 2007-05-17 2007-10-10 友达光电股份有限公司 液晶面板及其制造方法
CN102650786A (zh) * 2012-04-27 2012-08-29 京东方科技集团股份有限公司 一种薄膜晶体管阵列基板及其制造方法和显示装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4717392B2 (ja) * 2004-08-13 2011-07-06 富士通株式会社 液晶表示装置用基板及びそれを備えた液晶表示装置
CN101387799B (zh) * 2007-09-13 2011-04-13 北京京东方光电科技有限公司 液晶显示器基板、液晶显示器及制造方法
CN101398570A (zh) * 2007-09-26 2009-04-01 北京京东方光电科技有限公司 液晶显示装置及制造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11111995A (ja) * 1997-10-03 1999-04-23 Matsushita Electric Ind Co Ltd 表示装置の製造方法
CN1447153A (zh) * 2002-03-22 2003-10-08 精工爱普生株式会社 电光装置及其制造方法以及电子机器
CN1499277A (zh) * 2002-10-31 2004-05-26 ������������ʽ���� 电光装置及电子设备
CN1599080A (zh) * 2003-06-25 2005-03-23 三星Sdi株式会社 薄膜晶体管及平板显示装置
CN101051160A (zh) * 2007-05-17 2007-10-10 友达光电股份有限公司 液晶面板及其制造方法
CN102650786A (zh) * 2012-04-27 2012-08-29 京东方科技集团股份有限公司 一种薄膜晶体管阵列基板及其制造方法和显示装置

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CN113552753A (zh) * 2021-07-23 2021-10-26 南京京东方显示技术有限公司 阵列基板的制造方法、阵列基板、显示面板及电子设备
CN113552753B (zh) * 2021-07-23 2024-01-23 南京京东方显示技术有限公司 阵列基板的制造方法、阵列基板、显示面板及电子设备

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