Classifications

• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/26—Testing of individual semiconductor devices
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
  • G01R1/02—General constructional details
  • G01R1/04—Housings; Supporting members; Arrangements of terminals
  • G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
  • G01R1/0416—Connectors, terminals
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
  • G01R1/02—General constructional details
  • G01R1/06—Measuring leads; Measuring probes
  • G01R1/067—Measuring probes
  • G01R1/073—Multiple probes
  • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
  • G01R1/07364—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch
  • G01R1/07378—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch using an intermediate adapter, e.g. space transformers
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
  • G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/2851—Testing of integrated circuits [IC]
  • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/2851—Testing of integrated circuits [IC]
  • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
  • G01R31/2887—Features relating to contacting the IC under test, e.g. probe heads; chucks involving moving the probe head or the IC under test; docking stations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
  • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

• the present disclosure relates generally to translators coupleable to opposing surfaces of microelectronic substrates for testing, and associated systems and methods.
• Integrated circuits are typically manufactured in batches. Individual batches typically contain multiple semiconductor wafers or other substrates, within and upon which integrated circuits are formed. Forming the integrated circuits requires a wide variety of semiconductor manufacturing steps, including, for example, depositing, masking, patterning, implanting, etching, planarizing, and other processes.
• Each wafer typically includes hundreds of individual dies which are later separated or singulated and packaged for use. Before the dies are singulated, completed wafers are tested to determine which dies on the wafer are capable of operating according to predetermined specifications. In this manner, integrated circuits that cannot perform as desired are not packaged or otherwise incorporated into finished products.
• Figures 1A-1C illustrate a representative substrate (e.g., a wafer) having two opposing surfaces, and corresponding translators for eiectrically accessing the substrate from both surfaces in accordance with an embodiment of the present technology.
• a representative substrate e.g., a wafer
• translators for eiectrically accessing the substrate from both surfaces in accordance with an embodiment of the present technology.
• Figure 1 D is a scanning electron micrograph of a portion of a substrate of the type shown in Figures 1A-1C.
• Figure 1 E is a partially schematic enlarged illustration of the substrate and two translators shown in Figure 1C.
• Figure 2 is a partially schematic, cross-sectional illustration of a substrate and two translators coupled to a tester assembly in accordance with an embodiment of the present disclosure.
• Figures 3A and 3B are partially schematic, cross-sectional illustrations of a substrate coupled to two translators that access unpowered dies in accordance with an embodiment of the present technology.
• Figures 4A and 4B illustrate a substrate and two translators configured to direct test signals in a radiaily outward direction in accordance with an embodiment of the present technology.
• Figures 5A and 5B illustrate a substrate and two translators positioned to simulate stacked dies of an unsingulated substrate in accordance with an embodiment of the present technology.
• Figures 6A and 6B illustrate a substrate and two translators positioned to use the through-substrate vias of incomplete dies in accordance with an embodiment of the present technology.
• Figures 7A and 7B illustrate a substrate and two flexible translators configured in accordance with an embodiment of the present technology.
• Figures 8A and 8B illustrate a substrate with one rigid translator and one flexible translator configured in accordance with an embodiment of the present technology.
• Figures 9A and 9B illustrate a substrate and two rigid translators configured in accordance with an embodiment of the present technology.
• Figures 10A and 10B illustrate a substrate and two flexible translators configured in accordance with another embodiment of the present technology.
• the present technology is directed generally to translators coupleable to opposing surfaces of microelectronic substrates, e.g., for testing, and associated systems and methods.
• these techniques can take advantage of through-substrate (e.g., through-wafer or through-silicon) vias to access the microeiectronic substrate from both sides and thereby increase the efficiency with which dies of the substrate are tested.
• through-substrate e.g., through-wafer or through-silicon
• FIG. 1A is a partially schematic, cross-sectional illustration of a microelectronic substrate 100 (e.g., a semiconductor wafer) suitable for testing with devices and methods in accordance with the present technology.
• the representative microelectronic substrate 100 includes multiple dies or die sites 101 having corresponding die edges 107. After testing, the substrate 100 is singulated or diced along the die edges 107 to produce individual dies 101 that are encapsulated or otherwise packaged prior to use.
• Each die 101 can include one or more active areas 102. Dies pads 103 are accessible from a first side (e.g., a first major surface) 106a of the substrate 100.
• Through-substrate vias (e.g., through-silicon vias) 104 can provide electrical access to structures within the substrate 100 from both the first side 106a of the substrate 100 and an oppositely-facing second side (e.g., a second major surface) 106b.
• Through-substrate via pads 105 provide electrical access to the vias 104.
• Figure 1 B illustrates a representative substrate 100 positioned between two translators 110, shown as a first translator 110a and a second translator 110b.
• the first translator 1 10a is positioned proximate to and facing toward the first side 106a of the substrate 100
• the second translator 110b is positioned proximate to and facing toward the second side 106b of the substrate 100.
• the term "translator” refers generally to a structure having one or more conductive (e.g., metal) layers, with the translator being temporarily affixed to attached to or engaged
• the translator is configured to move with the substrate 100, e.g., from one station (e.g., a testing or processing station) to another.
• the translator includes one set of contacts having spacings therebetween that match the spacings between the die pads 103 and/or the vias 104.
• This first set of contacts sometimes referred to generally as wafer contacts or substrate contacts, are engaged with the substrate 100 during testing, and are located on a "wafer side" or "substrate side" of the translator.
• the translator also typically includes a second set of contacts e.g.
• the translator can provide an interface between the die pads, which are typically very closely spaced together, and the corresponding tester pads, which are typically spaced further apart.
• the translators can be temporarily attached to the substrate via vacuum forces, clamps, and/or other techniques so as to move with the substrate 100 from one station to another during testing, pre-testing and/or post-testing procedures.
• the substrate or wafer contacts of the first translator 110a can include first conductors 111 positioned to contact the die pads 103 of the associated substrate 100, and second conductors 1 12 positioned to contact the through-substrate vias 104 (e.g., the via pads 105) at the first side 106a of the substrate 100.
• the second translator 110b can also include second conductors 112 positioned to contact the through-substrate vias 104 from the second side 106b of the substrate 100. Accordingly, the first translator 110a can access the through-substrate vias 104 from the first side 106a, and the second translator 110b can access the same or different through-substrate vias 104 from the second side 106b.
• Figure 1C illustrates the substrate 100 with the first and second translators 110a, 110b releasabiy attached to it. With the substrate 100 and the translators 1 10a, 1 10b in this configuration, the substrate 100 can be tested with electrical signals that access both the first and second sides 106a, 106b of the substrate 100. Accordingly, the first translator 110a is positioned in a first region 108a that extends outwardly from the first major surface 106a of the substrate 100, and the second translator 110b is positioned in a second region 108b that extends outwardly from the second major surface 106b of the substrate 100.
• Figure 1 D is a scanning electron micrograph illustrating a portion of the substrate 100 shown in Figure 1C. Accordingly, Figure 1 D illustrates individual dies 101 and associated through-substrate vias 104.
• Figure 1 E is an enlarged illustration of a portion of the substrate 100 and the translators 110a, 110b shown in Figure 1 C.
• FIG. 2 is a partially schematic, cross-sectional illustration of a representative substrate 100 and representative translators 110a, 110b arranged for testing in accordance with an embodiment of the present technology.
• the arrangement can include a tester assembly 120 that in turn includes multiple testers or test modules 121.
• the testers 121 can include first testers 121a positioned to access the first translator 110a, and second testers 121 b positioned to access the substrate 100 via the second translator 1 10b. Accordingly, the first testers 121a can communicate electrically with first tester contacts 113a carried by the first translator 1 10a, and the second testers 121 b can access the second translator 110b through second tester contacts 113b.
• Tester signal paths 122 connect or provide communication between the first testers 121a and the second testers 121 b. Accordingly, tests performed by the first testers 121a can be coordinated with tests performed by the second testers 121 b. This function can be particularly useful for testing certain microelectronic devices, e.g., NAND devices, for which results from one test can direct which of multiple possible follow-on tests are conducted. Another advantage of the foregoing arrangement is that it can be used to test a die that ultimately is incorporated into a stack of dies.
• Such dies may use the through- substrate vias 104 to transmit different signals to pads located at the first side 106a than to pads located at the second side 106b.
• the first and second testers 121a, 121b can be programmed/configured to deliver and/or respond to the different signals that the dies 101 may generate.
• the second testers 121b can simulate a lower die, and the first testers 121a can simulate an upper die.
• signals transmitted to and/or from the dies 101 through the through-substrate vias 104 can, in operation, travel in only one direction (e.g., toward only the first translator 110a or toward only the second translator 110b).
• Representative devices include diodes and tri-state devices. Accordingly, the ability to access both ends of individual through-substrate vias 104 can increase the versatility of the overall testing operation.
• the through-substrate via of one die can be used to facilitate testing of another die, as will be described further below, in further embodiments, signals are transmitted in both directions along one or more vias. For example, such signals can be used to test the integrity of unidirectional devices (which should transmit signals in only one direction) and/or test the ability of multi-directional devices to transmit signals in multiple directions.
• Figures 3A and 3B illustrate a representative substrate 100 with representative first and second translators 1 10a, 110b configured in accordance with a particular embodiment of the present technology.
• the translators 110a, 110b and a set of first testers 121 a are shown schematically in position for engaging the substrate 100.
• the first and second translators 110a, 110b have been engaged with the substrate 100, and the first testers 121a have been engaged with the first translator 110a.
• the second translator 110b includes circuitry that allows the through-substrate vias of an unpowered or untested die to facilitate testing of a powered or test die (e.g., a die or device under test, or "DUT").
• a powered or test die e.g., a die or device under test, or "DUT"
• Figure 3B illustrates a first die 101a (also identified as “Die 4 Test”) that is powered and under test, and is located between two second die 101 b (also identified as “Unpowered Die 3" and "Unpowered Die 5") that are unpowered.
• a corresponding first tester 121 a accesses the first die 101a by first through-substrate vias 104a of the first die 101a.
• the second translator 110b includes second signal paths 114b that connect the first through-substrate vias 104a of the first die with second through-substrate vias 104b of the second dies 101 b.
• the first tester 121a can communicate with the first die 101a by first signal paths 1 14a that pass through both the first through-substrate vias 104a of the first die 101a, and the second through-substrate vias 104b of the second dies 101 b.
• This arrangement can be used to increase the access available to each die that is currently under test by using adjacent (and/or other) dies that are not currently under test.
• this arrangement can allow the first testers 121a to evaluate signals from the first die 101 a that are typically transmitted unidirectionally "down" through the first through-substrate vias 104a toward the second translator 1 10b by using the second translator 1 10b to redirect such signals back up through the second vias 104b of the second dies 101 b to the first testers 121a.
• the dies can be tested by sequentiaily shifting the first testers 121a and/or connections between the testers and the dies 101a, 101 b.
• the second vias 104b can be used to send instructions between the first and second translators 110a, 110b.
• Figures 4A and 4B illustrate another arrangement in which a second translator 110b is used to convey signals that may be conveyed to and/or received from components not shown in Figures 4A and 4B.
• the first testers 121a can communicate with the dies 101 as indicated by the first signal paths 114a
• a second translator 110b can convey signals away, for example to/from additional iesters (offsite or distributed testers) that are not visible in Figures 4A and 4B, as indicated by second signal paths 1 14b.
• the signals can be routed along paths that extend beyond the outer periphery of the substrate 100, as wiil be described further below with reference to Figures 7A and 7B.
• Figures 5A and 5B illustrate an arrangement in which the first and second translators 110a, 110b include signal paths that are used to test multiple unsingulated dies in a manner that emulates a stacked die arrangement.
• a total of six dies 101a-101f are involved in a particular test that simulates three stacked dies.
• the first, third and fifth dies 101a, 101c, 101e are powered and tested.
• the second, fourth, and sixth dies 101 b, 101d, 101f are unpowered, but provide pathways to connect the powered dies.
• each of the translators 110a, 110b are configured to use the unpowered dies to route signals from the bottom of one tested die to the top of the other, thus emulating a stacked die arrangement.
• first signal paths 114a at the first translator 110a provide communication between a first tester 121a and the first die 101a.
• Second signal paths 114b at the second translator 110b connect the through- substrate vias 104 of the first die 101a to the through-substrate vias 104 of the second die 101 b.
• Third signal paths 1 14c at the first translator 101a connect the through- substrate vias 104 of the second, unpowered die 101 b with the through-substrate vias 104 of the third, powered die 101 c.
• a similar arrangement is used to connect the third die 101 c with the fifth die 101e, and route signals to a second tester 121 b.
• aspects of the operation of the dies that are typically evident only when the dies are in a stacked arrangement can be tested before the dies are singulated and actually placed in a stacked arrangement.
• individual dies may be tested together in a simulated stacked arrangement, once singulated, the dies do not necessarily need to be stacked with the same dies used during the simulation.
• Figures 6A and 6B illustrate an arrangement for testing dies (e.g., complete, intact dies) by using the through-substrate vias of incomplete dies carried by the substrate 100.
• the substrate 100 is typically circular and complete or whole dies 101a are typically rectangular, the outer periphery of the substrate 100 can include portions of incomplete or partial dies 101 b.
• These incomplete dies 101 b may have undergone at least some of the manufacturing processes associated with complete dies 101a, for example, the formation of through- substrate vias.
• the complete dies 101a can have first through-substrate vias 104a and the incomplete dies 101 b can have second through-substrate vias 104b.
• the second through-substrate vias 104b can be used to provide access to first dies 101a by using the second translator 110b to convey signals along signal paths 1 14 between the second through-substrate vias 104b of partial or incomplete dies 101b and the first through-substrate vias 104a of complete dies 101a. Accordingly, the second vias 104b can provide a "pass-through" function.
• Figures 7A and 7B illustrate a configuration in which a representative substrate 100 is tested by relatively thin first and second translators 110a, 110b.
• the second translator 110b can have an "edge extended" configuration that includes edge extensions 1 15 extending beyond the periphery of the substrate 100.
• the edge extensions 1 15 can provide additional functional areas e.g., for coupling to testers and/or other external devices.
• the translators 110a, 110b can be formed from thin, flexible layered metal/dieiectric materials to provide for low clearance in a vertical direction. Accordingly, this arrangement is particularly suitable where the vertical clearance requirements during testing are tight.
• Figures 8A and 8B illustrate another arrangement in which a representative substrate 100 is positioned between a first translator 810a having a relatively thick configuration, and a second translator 810b having a thin configuration generally similar to that described above with reference to Figures 7A and 7B. This arrangement can be used where vertical clearance above the substrate 100 is not as tight or critical as the vertical clearance below the substrate 100.
• Figures 9A and 9B illustrate another arrangement in which a substrate 100 is positioned between two translators 910a, 910b, both of which have a relatively thick configuration. This arrangement can be used in installations for which vertical clearance both above and below the substrate 100 is not as tight or critical.
• Figures 10A and 10B illustrate a substrate 100 positioned between first and second translators 1010a, 1010b, both of which are relatively thin, and neither of which include the edge extender arrangement described above with reference to Figures 7A and 7B. Accordingly, this arrangement can be used in instances for which the communications to and from the substrate 100 do not require a density of signal paths and/or other features that necessitate or otherwise require an edge extender.
• a representative method includes positioning a first translator in a first region proximate to a microelectronic substrate.
• the microelectronic substrate has a first major surface and a second major surface facing away from the first major surface, and has electrically conductive through-substrate vias extending through the substrate, with a first region extending outwardly from the first major surface of the microelectronic substrate and a second region extending outwardly from the second major surface.
• the method can further include reieasably fixing the first translator relative to the microelectronic substrate at the first region, reieasably fixing a second translator relative to the microelectronic substrate at the second region while the first translator is fixed relative to the microelectronic substrate at the first region, electrically accessing a first through-substrate via of the microelectronic substrate with the first translator while the first translator is positioned in the first region, and electrically accessing the first through-substrate via or a second through-substrate via of the microelectronic substrate with the second translator while both the first and second translators are fixed relative to the microelectronic substrate.
• the method further includes simultaneously electrically accessing the microelectronic substrate with both the first and second translators.
• the method further includes receiving a first signal from the first translator at the second translator, and in response, directing the first signal or a second signal to the microelectronic substrate or the first translator.
• the first via is part of a first die
• the method further includes simulating stacked dies by routing a signal from the first translator through the first via of the first die to the second translator, using the second translator to route the signal from the first via to a second via, receiving the signal from the second via at the first translator, and using first translator to route the signal from the second via to a third via of the microeiectronic substrate, the third via being part of a second die different than the first die.
• the methods disclosed herein include and encompass, in addition to methods of making and using the disclosed devices and systems, methods of instructing others to make and use the disclosed devices and systems. Accordingly, any and ail methods of use and manufacture disclosed herein also fully disclose and enable corresponding methods of instructing such methods of use and manufacture. Methods of instructing such use and manufacture may take the form of computer- readabie-medium-based executable programs or processes.
• translators having configurations other than those expressly described above can be used to provide access to substrates from opposing surfaces of the substrates.
• Substrates can be tested in a generally horizontal orientation, as shown in the Figures, or in a vertical or other orientation in other embodiments.
• the same signal received by one translator from another is transmitted directly to another site, e.g., back to the first translator, or to a die under test.
• the received signal is altered before further transmission, or provides a basis for transmission of a different signal.

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• Physics & Mathematics (AREA)
• General Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• General Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Testing Or Measuring Of Semiconductors Or The Like (AREA)
• Tests Of Electronic Circuits (AREA)

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• 2013
  • 2013-03-15 US US13/840,937 patent/US8779789B2/en active Active
  • 2013-04-04 EP EP13776186.2A patent/EP2837023A4/en not_active Withdrawn
  • 2013-04-04 KR KR1020147031469A patent/KR20150007305A/ko not_active Ceased
  • 2013-04-04 CN CN201380030314.XA patent/CN104350588B/zh active Active
  • 2013-04-04 JP JP2015505804A patent/JP6058119B2/ja active Active
  • 2013-04-04 WO PCT/US2013/035286 patent/WO2013154909A1/en not_active Ceased
  • 2013-04-04 SG SG11201406383RA patent/SG11201406383RA/en unknown
  • 2013-04-08 TW TW102112402A patent/TWI551869B/zh active
• 2014
  • 2014-06-19 US US14/309,672 patent/US9222965B2/en active Active

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