WO2013153717A1 - Appareil électronique et procédé de fabrication de celui-ci - Google Patents

Appareil électronique et procédé de fabrication de celui-ci Download PDF

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Publication number
WO2013153717A1
WO2013153717A1 PCT/JP2013/000356 JP2013000356W WO2013153717A1 WO 2013153717 A1 WO2013153717 A1 WO 2013153717A1 JP 2013000356 W JP2013000356 W JP 2013000356W WO 2013153717 A1 WO2013153717 A1 WO 2013153717A1
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WIPO (PCT)
Prior art keywords
substrate
electronic component
electrode
semiconductor device
surface electrode
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PCT/JP2013/000356
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English (en)
Japanese (ja)
Inventor
和之 川嶋
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日本電気株式会社
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Publication of WO2013153717A1 publication Critical patent/WO2013153717A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
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    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
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    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2036—Permanent spacer or stand-off in a printed circuit or printed circuit assembly
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
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    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
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    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to an electronic device and a manufacturing method thereof, and more particularly to an electronic device in which an electronic component is mounted on a substrate and a manufacturing method thereof.
  • eMMC embedded Multi Media Card
  • eMMC an interface including terminal arrangement is defined by JEDEC (Joint Electron Device Engineering Council).
  • JEDEC Joint Electron Device Engineering Council
  • MMC Multi Media Card
  • Patent Documents 1 to 6 are known as techniques related to mounting of semiconductor devices.
  • a semiconductor device such as eMMC has been mounted on various devices as the memory size increases and the outer shape of the package increases and the standardization of the interface of the semiconductor device advances.
  • first electronic component such as eMMC
  • second electronic component such as a bypass capacitor
  • peripheral components are arranged in the peripheral region (land region) of the semiconductor device. Therefore, there is a problem that the mounting area increases when peripheral components are arranged and mounted around the semiconductor device as in the related art.
  • peripheral components are arranged around the package of a large-sized semiconductor device, a mounting area for mounting peripheral components in addition to a large package outer shape is required on the mounting substrate, which increases the mounting area. .
  • a mounting area for mounting peripheral components in addition to a large package outer shape is required on the mounting substrate, which increases the mounting area.
  • a portable electronic device such as a mobile phone that often uses a small mounting board, it is difficult to increase the mounting area, and an increase in the mounting area becomes a big problem.
  • An object of the present invention is to provide an electronic device that solves such a problem and a manufacturing method thereof.
  • An electronic apparatus includes a substrate, a first electronic component mounted on the substrate, and the substrate and the first electronic component between the substrate and the first electronic component.
  • a method for manufacturing an electronic device is a method for manufacturing an electronic device in which a first electronic component is mounted on a substrate, wherein the substrate, the first electronic component, And a connection support portion for supporting the first electronic component on the substrate is disposed via a conductive connection material, and the second region on the substrate is electrically conductive.
  • a second electronic component is disposed via a connection material, and the first electron is disposed on the connection support portion via a conductive connection material in a region including the connection support portion and the upper side of the second electronic component. Parts are arranged.
  • an electronic device capable of preventing an increase in mounting area and a manufacturing method thereof.
  • FIG. 1 is a schematic cross-sectional view showing a configuration of a mounting structure according to a first embodiment.
  • 2 is an enlarged cross-sectional view showing a configuration of a mounting structure according to Embodiment 1.
  • FIG. FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the sub board according to the first embodiment.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the sub board according to the first embodiment.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the sub board according to the first embodiment.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the sub board according to the first embodiment.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the sub board according to the first embodiment.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the sub board according to the first embodiment.
  • 5 is a schematic cross-sectional view showing the method for manufacturing the mounting structure according to Embodiment 1.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the mounting structure according to Embodiment 1.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the mounting structure according to Embodiment 1.
  • FIG. 5 is a schematic cross-sectional view showing the method for manufacturing the mounting structure according to Embodiment 1.
  • FIG. FIG. 3 is an enlarged cross-sectional view illustrating a configuration of a daughter board according to the first embodiment.
  • 6 is a schematic cross-sectional view showing a configuration of a mounting structure according to Embodiment 2.
  • FIG. 6 is an enlarged cross-sectional view illustrating a configuration of a mounting structure according to a second embodiment.
  • FIG. 10 is a schematic cross-sectional view showing a method for manufacturing a daughter board according to Embodiment 2.
  • FIG. 10 is a schematic cross-sectional view showing a method for manufacturing a daughter board according to Embodiment 2.
  • FIG. 10 is a schematic cross-sectional view showing a method for manufacturing a daughter board according to Embodiment 2.
  • FIG. 10 is a schematic cross-sectional view showing a method for manufacturing a daughter board according to Embodiment 2.
  • FIG. 10 is a schematic cross-sectional view showing the method for manufacturing the mounting structure according to the second embodiment.
  • FIG. 10 is a schematic cross-sectional view showing a method for manufacturing a daughter board according to Embodiment 2.
  • FIG. 10 is a schematic cross-sectional view showing the method for manufacturing the mounting structure according to the second embodiment.
  • FIG. 10 is a schematic cross-sectional view showing the method for manufacturing the mounting structure according to the second embodiment.
  • FIG. 10 is a schematic cross-sectional view showing the method for manufacturing the mounting structure according to the second embodiment.
  • FIG. 5 is an enlarged cross-sectional view showing a configuration of a daughter board according to a second embodiment.
  • FIG. 6 is a schematic cross-sectional view showing a configuration of a mounting structure according to a third embodiment.
  • FIG. 6 is an enlarged cross-sectional view illustrating a configuration of a mounting structure according to a third embodiment.
  • FIG. 9 is a schematic cross-sectional view showing a method for manufacturing the mounting structure according to the third embodiment.
  • FIG. 10 is a schematic cross-sectional view showing the method for manufacturing the mounting structure according to the second embodiment.
  • FIG. 10 is a schematic cross-sectional view showing the method for manufacturing the mounting structure according to
  • FIG. 9 is a schematic cross-sectional view showing a method for manufacturing the mounting structure according to the third embodiment.
  • FIG. 9 is a schematic cross-sectional view showing a method for manufacturing the mounting structure according to the third embodiment.
  • FIG. 9 is a schematic cross-sectional view showing a method for manufacturing the mounting structure according to the third embodiment.
  • FIG. 6 is a schematic cross-sectional view showing a configuration of a mounting structure according to a fourth embodiment.
  • an electronic device (corresponding to a mounting structure) 100 according to the present invention includes a connection support portion (corresponding to a sub board and a soldering spacer) 101, a first electronic component (a semiconductor device such as eMMC). Equivalent) 102, a substrate (corresponding to a parent substrate) 103, and a second electronic component (corresponding to a peripheral component) 104 such as a bypass capacitor.
  • a connection support portion corresponding to a sub board and a soldering spacer
  • a first electronic component a semiconductor device such as eMMC). Equivalent
  • a substrate corresponding to a parent substrate
  • a second electronic component corresponding to a peripheral component
  • the substrate 103 has a mounting surface 103a, the first electronic component 102 is mounted above the mounting surface 103a, and the connection support portion 101 is an area between the substrate 103 and the first electronic component 102.
  • the substrate 103 and the first electronic component 102 are electrically connected, the first electronic component 102 is supported at a predetermined position from the substrate 103, and the second electronic component 104 is connected to the substrate 103 and the first electronic component 102.
  • the mounting area 103b is mounted on the mounting surface 103a in an area 105b from which the connection support area 105a is removed. That is, the electronic device 100 according to the present invention includes the substrate 103, the first electronic component 102 mounted on the substrate 103, and the substrate 103 and the first electronic component 102.
  • the electronic component 102 is electrically connected and mounted on the substrate 103 between the substrate 103 and the first electronic component 102, and the connection support unit 101 that supports the first electronic component 102 on the substrate 103. It is a main feature of the present invention that the second electronic component 104 is provided.
  • the first electronic component such as a semiconductor device mounted on the substrate is connected and supported by the connection support portion, and the space (region) formed by the connection support portion connecting and supporting the space (region).
  • a second electronic component such as a peripheral component is mounted on 105b).
  • the outer shape of the package increases, and the arrangement of terminals is defined by standards such as JEDEC, and thus has certain limitations.
  • a semiconductor device such as a BGA package
  • since terminals are arranged in the central portion of the semiconductor device the distance between the terminal in the central portion of the semiconductor device and the package outer edge increases as the package outer shape increases.
  • peripheral components are arranged and mounted around a large-sized semiconductor device such as eMMC, the wiring length of the wiring connecting the terminal of the semiconductor device and the peripheral component becomes long. For this reason, when peripheral components are mounted side by side on the periphery of the semiconductor device, there is a problem that the mounting area increases and the effect of noise reduction by the peripheral components decreases, leading to deterioration of characteristics.
  • the second electronic component 104, the first electronic component 102 can be electrically connected via the connection support portion 101.
  • the wiring length connecting the second electronic component and the first electronic component is shortened as compared with the case where the second electronic component is arranged and connected around the first electronic component. Can be prevented.
  • Patent Documents 1 to 6 since a dedicated semiconductor package is required as a semiconductor package (including a module) to be mounted, it is difficult to use a general-purpose semiconductor device. On the other hand, in the present invention, it is possible to apply a semiconductor device standardized by JEDEC or the like. As a result, significant cost reduction can be achieved.
  • the layout area of peripheral components decreases or disappears as the number of terminals of the semiconductor device increases, whereas the present invention uses a semiconductor device in which the number of terminals is determined. The layout area does not decrease.
  • Patent Documents 2 and 3 describe that peripheral components can be mounted on both sides of the sub board.
  • a child board on which peripheral components are mounted is mounted on a parent board, and a semiconductor device is mounted on the child board. Then, in addition to the mounting height of the semiconductor device, the total value of the thickness of the child board and the mounting height of the peripheral components, and the clearance between the parent substrate and the peripheral components is the total height, making it difficult to reduce the thickness. .
  • the total thickness of the body thickness of the semiconductor device, the mounting height of the peripheral components, and the clearance between them is the total height, so that it can be made thinner than Patent Documents 2 and 3. is there.
  • Patent Documents 4 and 5 describe that a plurality of substrates on which a semiconductor package is mounted are connected to each other via a relay substrate.
  • the relay substrate is arranged around the semiconductor package, the substrate on which the semiconductor package is mounted needs to be enlarged depending on the size of the semiconductor package and the number of terminals (for example, Patent Document 4). 1 and the like in FIG.
  • Patent Documents 4 and 5 a plurality of dedicated module substrates and a plurality of relay substrates are used, which causes a problem in cost.
  • the child substrate (spacer substrate) can be arranged without affecting the projected area of the semiconductor device 2, and the size can be reduced without restriction. Further, since it is composed of a single sub-substrate (spacer substrate), it is superior to Patent Documents 4 and 5 in terms of cost.
  • Patent Document 6 describes that a plurality of semiconductor elements having different sizes are stacked to reduce the mounting area.
  • Patent Document 6 in order to realize the proposed structure, in an actual manufacturing process, after applying the adhesive material, mounting the chip, and heating and curing the adhesive material several times, the chips are stacked, and then the electrical connection is made by wire. Bonding is performed one by one, and the manufacturing process is complicated.
  • the spacer chip does not involve electrical connection and does not contribute to shortening the wiring length.
  • the present invention is a simple manufacturing process in which solder connection is performed by batch reflow using SMT (Surface Mount Technology), which is advantageous in terms of manufacturing cost. Also, the wiring length can be shortened by connecting the connection support portion and the electronic component.
  • SMT Surface Mount Technology
  • FIG. 2 is a schematic cross-sectional view showing the configuration of the mounting structure 100 according to the present embodiment
  • FIG. 3 is an enlarged cross-sectional view of the mounting structure 100 of FIG.
  • the mounting structure 100 is a mounting structure 100 built in a portable electronic device that is required to be reduced in size or thickness, such as a smartphone, a tablet terminal, or a mobile phone.
  • the mounting structure 100 mainly includes a child substrate 1, a semiconductor device 2, a parent substrate 5, and peripheral components 7.
  • the peripheral component 7 is mounted on the upper surface (mounting surface) of the parent substrate 5, and the semiconductor device 2 is mounted via the child substrate 1 constituted by a double-sided wiring board.
  • the position of the semiconductor device 2 is higher than the position of the parent substrate 5, and conversely, the position of the semiconductor device 2.
  • the position of the parent substrate 5 is lower.
  • the semiconductor device 2 is a semiconductor device such as eMMC.
  • the semiconductor device 2 has a package structure such as a BGA (Ball grid array) or an LGA (Land grid array) (FIG. 2 is an example of a BGA), and a face-down mounting type semiconductor having a plurality of lower electrodes 3 on the lower surface.
  • the plurality of lower electrodes 3 are arranged in accordance with the shape, size, number of arrangements, and pitch specified in standards such as JEDEC.
  • the semiconductor device 2 is a large package device incorporating a large-capacity memory, and the lower electrode 3 is arranged in the arrangement region 5 a at the substantially central portion of the lower surface of the semiconductor device 2.
  • region 5a of the lower electrode 3 and the package external end are spaced apart.
  • the arrangement region 5 a of the lower electrode 3 and the outer edge of the semiconductor device 2 are separated by the same size or more than the size of the peripheral component 7.
  • the peripheral component 7 is a bypass capacitor or the like, and is a component necessary for electrical characteristics for reducing noise of the semiconductor device 2.
  • the peripheral component 7 is provided with connection electrodes 7a at both ends so as to be connected to and mounted on the parent substrate 5.
  • the peripheral component 7 is electrically connected to the semiconductor device 2 via the parent substrate 5 and the child substrate 1.
  • the parent substrate 5 is a mounting substrate for mounting the semiconductor device 2 and the peripheral components 7 on the upper surface (mounting surface).
  • the outer shape of the parent substrate 5 is larger than at least the outer shape of the semiconductor device 2 in order to mount the semiconductor device 2.
  • the parent substrate 5 is a single-sided or multilayer printed wiring board having two or more layers, and has a plurality of connection pads (connection wirings) 9 on the upper surface.
  • the connection pad 9 is a pad for electrical connection with the semiconductor device 2 and the peripheral component 7 to be mounted, and is formed to have a necessary wiring pattern.
  • the connection pad 9 a is wired so as to connect the peripheral component 7 and the semiconductor device 2.
  • connection pads 9 are formed at positions corresponding to the lower electrode 3 (arrangement region 5a) of the semiconductor device 2 in the region overlapping the semiconductor device 2. Alternatively, it can be said that the plurality of connection pads 9 are arranged and formed at positions corresponding to the lower surface electrodes 4 b of the daughter board 1. Further, the connection pad 9 is also formed at a position corresponding to the connection electrode 7 a (arrangement region 5 b) of the peripheral component 7 in the region overlapping with the semiconductor device 2.
  • connection pad 9 and the connection electrode 7a of the peripheral component 7 are soldered.
  • the connection pad 9a connected to the peripheral component 7 is formed to extend from a position corresponding to the connection electrode 7a of the peripheral component 7 to a position corresponding to the lower electrode 3 of the semiconductor device 2 (the lower surface electrode 4b of the child substrate 1).
  • the peripheral component 7 and the semiconductor device 2 (child board 1) are electrically connected.
  • the child substrate 1 is a connection support substrate for connecting and mounting the semiconductor device 2 to the parent substrate 5 and supporting the semiconductor device 2 at a predetermined position (height).
  • the sub board 1 can also be said to be a board that forms the arrangement region (space) 5b for arranging the peripheral component 7 by supporting the semiconductor device 2.
  • the base material of the daughter board 1 is not particularly limited as long as it can form a wiring pattern and has a reflow heat resistance such as polyimide film, ceramics, and glass.
  • the wiring material is not particularly limited as long as it is a material having high conductivity.
  • the daughter board 1 is a double-sided printed wiring board, and has a plurality of upper surface electrodes 4a on the upper surface (front surface) and a plurality of lower surface electrodes 4b on the lower surface (back surface).
  • the plurality of upper surface electrodes 4 a and lower surface electrodes 4 b are arranged in positions corresponding to the lower electrodes 3 (arrangement regions 5 a) of the semiconductor device 2. Note that the upper electrode 4a and the lower electrode 4b that correspond to the electrodes that do not require electrical connection due to characteristics among the lower electrodes 3 do not have to be disposed.
  • the lower surface electrode 4b is formed on the lower surface (back surface) immediately below the upper surface electrode 4a.
  • the upper surface electrode 4a and the lower surface electrode 4b have the same shape or a shape close to that so that the front and back of the substrate are substantially symmetrical, and are provided with a countermeasure against warping during reflow.
  • an interstitial via hole (also referred to as “Interstitial Via Hole” or via hole) 8 is formed between the upper surface electrode 4a and the lower surface electrode 4b.
  • the via hole 8 is formed so as to penetrate from the upper surface to the lower surface of the daughter board 1, that is, from the lower surface (back surface) of the upper electrode 4a to the upper surface (back surface) of the lower electrode 4b.
  • a copper plating 15 is buried inside the via hole 8, and the upper surface electrode 4 a and the lower surface electrode 4 b are electrically connected by the copper plating 15.
  • the upper surface electrode 4a is connected to the lower electrode 3 of the semiconductor device 2 by soldering, and the lower surface electrode 4b is connected to a connection pad (soldering pad) 9 of the parent substrate 5 via a conductive connection material 6 such as solder. .
  • a connection pad 9 of the parent substrate 5 via a conductive connection material 6 such as solder.
  • the outer end of the daughter board 1 is cut so as to be in the vicinity of the upper surface electrode 4a and the lower surface electrode 4b.
  • the sub-substrate 1 has an outer shape that can form an upper surface electrode 4 a and a lower surface electrode 4 b corresponding to the lower electrode 3 of the semiconductor device 2, and is, for example, as large as the arrangement region 5 a of the lower electrode 3 of the semiconductor device 2. That's it.
  • a resist may be formed.
  • the sub board 1 is arranged on the main board 5, and the semiconductor device 2 is arranged on the sub board 1.
  • the lower electrode 3 is formed in the arrangement region 5a at the center of the lower surface of the semiconductor device 2, and the child substrate 1 is arranged under the arrangement region 5a.
  • the sub substrate 1 has a shape corresponding to the arrangement region 5 a of the lower electrode 3 of the semiconductor device 2 and is smaller than the outer shape of the semiconductor device 2.
  • the peripheral component 7 is arranged below the arrangement region 5 b in the lower peripheral portion of the semiconductor device 2. That is, the peripheral component 7 is arranged in the arrangement region 5 b from the outer edge of the sub board 1 to the outer edge of the semiconductor device 2.
  • the arrangement region 5b is a space formed by the child substrate 1 supporting the semiconductor device at a predetermined height so as to be surrounded by the lower surface of the semiconductor device 2, the side surface of the child substrate 1, and the upper surface of the parent substrate 5. . That is, the peripheral component 7 is accommodated and arranged in the arrangement area 5b, and the arrangement area 5b is an area in which at least all or a part of the peripheral component 7 can be accommodated.
  • each member has a relationship of height (length in the vertical direction) as shown in FIG. That is, the thickness (distance between the upper and lower electrodes) of the sub board 1 in the present embodiment is designed in advance so as to satisfy the following formula 1 so that the semiconductor device 2 and the peripheral component 7 do not contact in the height direction.
  • the stand-off L1 of the sub-board 1 is the height when the conductive connection material 6 (solder paste) of the sub-board 1 is mounted, and the stand-off L3 of the semiconductor device 2 is when the lower electrode 3 of the semiconductor device 2 is mounted. Of height.
  • the peripheral component 7 can be arranged directly below the semiconductor device 2 as shown in FIG. The effect of improving the electrical characteristics and reducing the mounting area by shortening the wiring length with the electrode 3 is brought about.
  • the printed wiring board design tool (CAD) prohibits duplication that is one size larger than the part outline, taking into consideration the outline tolerance of the parts and the mounting position accuracy of the mounting machine so that adjacent parts do not interfere with each other when mounting the parts.
  • An area is provided, and when the printed wiring board is designed, the overlap prohibition area of each part is restricted so as not to overlap. For this reason, when designing the mounting structure of the present embodiment, the restriction is released in advance and the parent board is designed. That is, the designer changes the design rule of the printed board wiring design tool, and places the child board 1 and the peripheral component 7 between the parent board 5 and the semiconductor device 2.
  • FIGS. 4A to 4E and FIGS. 5A to 5D a method for manufacturing the mounting structure 100 according to the present embodiment will be described.
  • the manufacturing method of the previous process will be described with reference to FIGS. 4A to 4E. 4A to 4E, the child substrate 1 having the upper surface electrode 4a and the lower surface electrode 4b on both surfaces is formed.
  • a double-sided copper clad laminate 11 having an upper surface conductor 12 formed on the upper surface and a lower surface conductor 13 formed on the lower surface is prepared.
  • the upper surface electrode 4a and the lower surface electrode 4b are formed by chemically etching the upper surface conductor 12 and the lower surface conductor 13 on both surfaces of the double-sided copper-clad laminate 11 by a photolithography method.
  • the upper surface electrode 4 a and the lower surface electrode 4 b are formed so as to correspond to the arrangement of the lower electrode 3.
  • the shape of the upper surface electrode 4a and the lower surface electrode 4b is a shape close to the electrode of the substrate to which the lower electrode 3 of the semiconductor device 2 mounted on the upper surface electrode 4a in a later step is connected.
  • the double-sided copper-clad wires are positioned as close as possible to the upper surface electrode 4a and the lower surface electrode 4b.
  • the daughter board 1 is completed.
  • the completed sub-substrate 1 is stored in a package that can be mounted by an automatic mounting machine, such as a tray or embossed tape, for a subsequent process.
  • the thickness of the sub board 1 is adjusted by selecting the base material thickness, the copper foil thickness, and the plating thickness so as to satisfy the above-described formula 1.
  • the child substrate 1 is formed using a double-sided copper-clad laminate, but other substrates other than the double-sided copper-clad laminate may be used.
  • the child board 1 is formed using the double-sided board on which the pattern is formed. Also good. Further, the child substrate 1 may be formed using a multilayer board having three or more layers.
  • copper plating is buried in the via hole 8 reaching the lower surface electrode 4b from the upper surface electrode 4a of the daughter board 1, and the upper surface electrode 4a and the lower surface electrode 4b are electrically connected by other methods. It may be.
  • the upper surface electrode 4a and the lower surface electrode 4b are formed. May be connected.
  • a through hole may be formed with a mechanical drill instead of a laser, and the hole may be filled with an insulating paste, and then the lid may be formed by copper plating.
  • the peripheral component 7 is mounted on the parent substrate 5 and the semiconductor device 2 is mounted via the child substrate 1 formed in FIG. 4A to FIG. 4E. Form.
  • connection pad 9 is formed on the upper surface of the parent substrate 5, and the conductive connection material 6 such as solder paste is supplied on the connection pad 9 by printing or dispensing.
  • the lower substrate electrode 4b of the child substrate 1 formed in FIGS. 4A to 4E is aligned with the position of the conductive connection material 6 on the predetermined connection pad 9, and the child substrate 1 is attached.
  • the peripheral component 7 is mounted by aligning the connection electrode 7 a of the peripheral component 7 at the position of the conductive connection material 6 on the predetermined connection pad 9.
  • the conductive connecting material 16 such as flux or solder paste is transferred to the lower electrode 3 of the semiconductor device 2
  • the conductive connecting material is placed at the position of the upper surface electrode 4a of the daughter board 1. 16 is aligned and the semiconductor device 2 is mounted on the daughter board 1.
  • connection pads 9 of the parent substrate 5 and the lower surface of the child substrate 1 are obtained.
  • the mounting structure 100 is completed by bonding the electrode 4b, the connection pad 9 of the parent substrate 5 and the connection electrode 7a of the peripheral component 7, and the upper electrode 4a of the child substrate 1 and the lower electrode 3 of the semiconductor device 2, respectively.
  • the peripheral component 7 can be disposed in the vicinity of the lower electrode 3 of the semiconductor device 2 (immediately below the semiconductor device 2).
  • the front and back electrodes having the upper surface electrode at the same position as the semiconductor device having the lower electrode and the connection electrode with the parent substrate immediately below the upper surface electrode are symmetrical child substrates. It cut
  • a peripheral component such as a bypass capacitor is mounted below the semiconductor device, the distance between the peripheral component and the electrode of the semiconductor device can be shortened, and a mounting structure realizing improved electrical characteristics is provided. be able to.
  • the mounting structure can be realized by using the sub board composed of the double-sided copper-clad laminate, the first and second effects can be provided at a low cost.
  • the cost is low.
  • improvements in electrical characteristics and mounting density can be realized.
  • the slave board is configured by a double-sided printed wiring board (double-sided copper-clad laminate), whereas in this embodiment, the secondary board 1 is configured by a single-sided printed wiring board.
  • the slave board is configured by a double-sided printed wiring board (double-sided copper-clad laminate)
  • the secondary board 1 is configured by a single-sided printed wiring board.
  • Other configurations are the same as those in the first embodiment.
  • FIG. 7 is a schematic cross-sectional view showing the configuration of the mounting structure 100 according to the present embodiment
  • FIG. 8 is an enlarged cross-sectional view of the mounting structure 100 of FIG.
  • the mounting structure 100 includes the semiconductor device 2, the parent substrate 5, and peripheral components 7 as in FIG. 2, and also includes the single-sided wiring board child substrate 1. That is, in the mounting structure 100 of the present embodiment, the peripheral component 7 is mounted on the upper surface (mounting surface) of the parent substrate 5 and the semiconductor device 2 is mounted via the child substrate 1 composed of a single-sided wiring board.
  • the lower surface (front surface) of the lower surface conductor in the sub-board 1 is a plurality of lower surface electrodes 4b
  • the upper surface (back surface) of the lower surface conductor (lower surface electrode 4b) is the upper surface electrode 4a.
  • the upper surface (front surface) of the upper surface conductor may be the upper surface electrode 4a
  • the lower surface (back surface) of the upper surface conductor may be the lower surface electrode 4b instead of the lower surface conductor of the child substrate 1.
  • the sub-substrate 1 is formed with via holes 8 so as to penetrate from the upper surface to the lower surface. That is, the via hole 8 is formed so as to reach the upper surface (back surface) of the lower surface electrode 4b from the upper surface of the daughter board 1, and the upper surface of the lower surface electrode 4b becomes the upper surface electrode 4a.
  • the lower electrode 3 is embedded in the via hole 8 at the time of mounting, and the upper surface electrode 4 a is solder-connected to the lower electrode 3 via the via hole 8.
  • the sub board 1 is mounted in the arrangement area 5 a between the semiconductor device 2 and the parent board 5, and the arrangement area 5 b between the semiconductor device 2 and the parent board 5 is peripheral.
  • the component 7 is mounted.
  • each member has a height (vertical length) relationship as shown in FIG. That is, the thickness of the daughter board 1 in this embodiment (electrode conductor thickness + substrate thickness) is designed in advance so as to satisfy the following expression 2 so that the semiconductor device 2 and the peripheral component 7 do not contact in the height direction. Is done.
  • the peripheral component 7 can be arranged directly below the semiconductor device 2 as in the first embodiment as shown in FIG.
  • L2 is the distance between the upper and lower electrodes of the child substrate 1 (the thickness of two conductors + the thickness of the base material), so it may be difficult to reduce L2.
  • L2 is only the sum of the thickness of the lower surface conductor of the child substrate 1 and the thickness of the substrate (conductor thickness + substrate thickness). For this reason, L2 can be easily reduced. Therefore, when it is necessary to increase the thickness of L2, it is preferable to adopt the first embodiment, and when it is necessary to reduce the thickness of L2, it is possible to adopt the second embodiment. preferable.
  • FIGS. 9A to 9D and FIGS. 10A to 10D a method for manufacturing the mounting structure 100 according to the present embodiment will be described. First, the manufacturing method of the previous process will be described with reference to FIGS. 9A to 9D. 9A to 9D, the child substrate 1 having the lower surface electrode 4b on one side is formed.
  • a single-sided copper-clad laminate (conductor layer) 11 having a lower surface conductor 13 formed only on the lower surface is prepared.
  • the lower surface electrode 4b is formed by chemically etching the lower surface conductor 13 of the single-sided copper clad laminate 11 by a photolithography method. Using the mask pattern corresponding to the arrangement pattern of the lower electrode 3 in the semiconductor device 2, the lower surface electrode 4 b is formed so as to correspond to the arrangement of the lower electrode 3.
  • vias are used so that the insulating layer is removed from the upper surface side of the single-sided copper clad laminate 11 to partially expose the back surface (upper surface) of the lower electrode 4b. Open hole 8. This exposed portion becomes the upper surface electrode 4a.
  • a via hole 8 reaching the lower surface electrode 4b from the upper surface of the daughter board 1 is formed and connected to the upper surface electrode 4a and the lower electrode 3 of the semiconductor device 2, but the upper surface is formed by other methods.
  • the electrode 4a and the lower electrode 3 may be electrically connected.
  • a conductive layer 15a such as copper plating or nickel plating may be formed on the conductor of the lower surface electrode 4b at the bottom of the via hole 8, and the upper surface of the conductive layer 15a may be used as the upper surface electrode 4a. Since the height of the upper surface electrode 4a is raised by the conductive layer 15a, fine adjustment of L2 in Expression 2 can be easily performed.
  • a reinforcing plate having an opening around the upper surface electrode 4a may be pasted on the upper surface of the child substrate 1 in advance.
  • the peripheral component 7 is mounted on the parent substrate 5 and the semiconductor device 2 is mounted via the child substrate 1 formed in FIGS. 9A to 9D, and the mounting structure according to this embodiment is performed. Form.
  • connection pad 9 is formed on the upper surface of the parent substrate 5, and the conductive connection material 6 such as solder paste is supplied on the connection pad 9 by printing or dispensing.
  • the lower substrate electrode 4b of the child substrate 1 formed in FIGS. 9A to 9D is aligned with the position of the conductive connection material 6 on the predetermined connection pad 9, and the child substrate 1 is attached.
  • the peripheral component 7 is mounted by aligning the connection electrode 7 a of the peripheral component 7 at the position of the conductive connection material 6 on the predetermined connection pad 9.
  • the conductive connection material 16 such as flux or solder paste is transferred to the lower electrode 3 of the semiconductor device 2, it is placed at the position of the via hole 8 (upper surface electrode 4a) of the child substrate 1. Then, the conductive connecting material 16 is aligned, and the semiconductor device 2 is mounted on the daughter board 1.
  • connection pads 9 of the parent substrate 5 and the lower surface of the child substrate 1 are obtained.
  • the mounting structure 100 is completed by bonding the electrode 4b, the connection pad 9 of the parent substrate 5, the connection electrode 7a of the peripheral component 7, and the upper electrode 4a of the child substrate 1 via the via hole 8 and the lower electrode 3 of the semiconductor device 2, respectively.
  • the peripheral component 7 in the vicinity of the lower electrode 3 of the semiconductor device 2 (directly below the semiconductor device 2).
  • the semiconductor device is mounted on the parent substrate via the child substrate of the single-sided wiring board, and the peripheral components are mounted on the region formed by the child substrate.
  • peripheral components can be arranged at a distance close to the semiconductor device, so that electrical characteristics can be improved and a mounting area including peripheral components can be reduced. .
  • the material price can be reduced compared to the first embodiment using the double-sided wiring board. Further, when it is desired to reduce the thickness L2 of the daughter board 1 as in the above-described formula 2, L2 is only one conductor thickness, so that L2 can be easily reduced.
  • Embodiment 3 of the present invention will be described below with reference to the drawings.
  • the semiconductor device is mounted via a child substrate, whereas in this embodiment, the semiconductor device is mounted via a soldering type spacer instead of the child substrate.
  • Other configurations are the same as those in the first embodiment.
  • FIG. 12 is a schematic cross-sectional view showing the configuration of the mounting structure 100 according to the present embodiment
  • FIG. 13 is an enlarged cross-sectional view of the mounting structure 100 of FIG.
  • the mounting structure 100 includes the semiconductor device 2, the parent substrate 5, peripheral components 7, and also includes a soldering spacer 17, as in FIG. 2. That is, in the mounting structure 100 of the present embodiment, the peripheral component 7 is mounted on the upper surface (mounting surface) of the parent substrate 5 and the semiconductor device 2 is mounted via the soldering spacer 17.
  • the soldering spacer 17 is a connection support member for supporting the semiconductor device 2 at a predetermined position (height) while connecting and mounting the semiconductor device 2 to the parent substrate 5 in the same manner as the child substrate 1.
  • the soldering spacer 17 can be said to be a substrate that supports the semiconductor device 2 and forms an arrangement region (space) 5 b for arranging the peripheral component 7.
  • the soldering spacers 17 are conductive spacers and are arranged separately for each lower electrode 3 of the semiconductor device 2.
  • the soldering spacer 17 has an upper surface connected to the lower electrode 3 of the semiconductor device 2 by soldering, and a lower surface connected to a connection pad (soldering pad) 9 of the parent substrate 5 and a conductive connection such as solder. It is connected via material 6. Thus, the lower electrode 3 of the semiconductor device 2 and the connection pad 9 of the parent substrate 5 are electrically connected.
  • the soldering spacers 17 are arranged in the arrangement region 5 a between the semiconductor device 2 and the parent substrate 5, and the arrangement region 5 b between the semiconductor device 2 and the parent substrate 5 is arranged.
  • a peripheral component 7 is mounted.
  • the members have a height (vertical length) relationship as shown in FIG. That is, the thickness (distance between the upper and lower ends) of the soldering spacer 17 in the present embodiment is designed in advance so as to satisfy the following expression 3 so that the semiconductor device 2 and the peripheral component 7 do not contact in the height direction. .
  • the peripheral component 7 can be disposed directly below the semiconductor device 2 as in the first embodiment, as shown in FIG.
  • connection pad 9 is formed on the upper surface of the parent substrate 5, and a conductive connection material 6 such as a solder paste is supplied onto the connection pad 9 by printing or dispensing.
  • a surface treatment capable of soldering is performed on both surfaces of a metal material such as copper or SUS, and this is used as a soldering spacer 17 to conduct on a predetermined connection pad 9 of the parent substrate 5. It is mounted on the conductive connecting material 6. Further, the peripheral component 7 is mounted by aligning the connection electrode 7 a of the peripheral component 7 at the position of the conductive connection material 6 on the predetermined connection pad 9.
  • the conductive connection material 16 such as flux or solder paste is transferred to the lower electrode 3 of the semiconductor device 2
  • the conductive connection material 16 is positioned at the position of the soldering spacer 17.
  • the semiconductor device 2 is mounted on the soldering spacer 17.
  • connection pads 9 of the parent substrate 5 and the soldering spacers 17 The mounting structure 100 is completed by bonding the lower surface, the connection pad 9 of the parent substrate 5 and the connection electrode 7a of the peripheral component 7, the upper surface of the soldering spacer 17 and the lower electrode 3 of the semiconductor device 2, respectively.
  • the peripheral component 7 similarly to the first embodiment, it is possible to arrange the peripheral component 7 in the vicinity of the lower electrode 3 of the semiconductor device 2 (directly below the semiconductor device 2).
  • the semiconductor device is mounted on the parent substrate via the soldering spacer, and the peripheral components are mounted on the region formed by the soldering spacer.
  • peripheral components can be arranged at a distance close to the semiconductor device, so that electrical characteristics can be improved and a mounting area including peripheral components can be reduced. .
  • Embodiment 4 of the present invention will be described below with reference to the drawings.
  • the sub board in the first embodiment is configured by a chip component built-in board.
  • Other configurations are the same as those in the first embodiment.
  • FIG. 15 is a schematic cross-sectional view showing the configuration of the mounting structure 100 according to the present embodiment.
  • the mounting structure 100 includes the semiconductor device 2, the parent substrate 5, and peripheral components 7, and also includes a chip component built-in substrate 18, as in FIG. 2. That is, in the mounting structure 100 of the present embodiment, the peripheral component 7 is mounted on the upper surface (mounting surface) of the parent substrate 5 and the semiconductor device 2 is mounted via the chip component built-in substrate 18.
  • the chip component built-in substrate 18 is a connection support substrate for connecting and mounting the semiconductor device 2 to the parent substrate 5 and supporting the semiconductor device 2 at a predetermined position (height), similarly to the child substrate 1.
  • the chip component built-in substrate 18 can also be said to be a substrate that forms the arrangement region (space) 5b for arranging the peripheral component 7 by supporting the semiconductor device 2.
  • the chip component built-in substrate 18 has a chip component 18a formed therein in advance.
  • the chip component 18a is a circuit element, and is, for example, a bypass capacitor or the like, similar to the peripheral component 7.
  • the chip component built-in substrate 18 is a double-sided printed wiring board, and has a plurality of upper surface electrodes 4a on the upper surface (front surface) and a plurality of lower surface electrodes 4b on the lower surface (back surface).
  • the plurality of upper surface electrodes 4a are arranged and formed at positions corresponding to the lower electrode 3 of the semiconductor device 2, and the plurality of lower surface electrodes 4b are formed immediately below the lower surface (back surface) of the upper surface electrode 4a.
  • An interstitial via hole 8 is formed from the upper surface electrode 4a and the lower surface electrode 4b to the chip component 18a.
  • the via hole 8 is embedded with copper plating or the like, and the upper surface electrode 4a and the lower surface electrode 4b are connected to the chip component 18a.
  • the chip component 18a can be connected to both the upper surface electrode 4a and the lower surface electrode 4b through the via hole 8, or can be connected to only one of the upper surface electrode 4a and the lower surface electrode 4b.
  • the upper surface electrode 4a is connected to the lower electrode 3 of the semiconductor device 2 by soldering, and the lower surface electrode 4b is connected to a connection pad (soldering pad) 9 of the parent substrate 5 via a conductive connection material 6 such as solder. .
  • a connection pad 9 of the parent substrate 5 such as solder.
  • the lower electrode 3 of the semiconductor device 2 and the chip component 18a are electrically connected, and the connection pad 9 of the parent substrate 5 and the chip component 18a are electrically connected.
  • the lower electrode 3 of the semiconductor device 2 and the connection pad 9 of the parent substrate 5 are electrically connected via the chip component 18a connected to both the upper surface electrode 4a and the lower surface electrode 4b.
  • chip parts similar to the peripheral parts 7 are built in the chip part built-in substrate 18. For this reason, the connection pad 9 under the peripheral component 7 and the connection pad 9 under the semiconductor device 2 are not connected, and the peripheral component 7 and the semiconductor device 2 are not electrically connected. That is, as shown in FIG. 15, peripheral components 7 that are not connected to the semiconductor device 2 may be mounted below the semiconductor device 2.
  • the semiconductor device is mounted on the parent substrate via the chip component built-in substrate, and the peripheral components are mounted in the region formed by the chip component built-in substrate.
  • peripheral components can be arranged at a distance close to the semiconductor device, so that electrical characteristics can be improved and a mounting area including peripheral components can be reduced. .
  • the peripheral component is built in the substrate connecting the semiconductor device and the parent substrate, the distance between the peripheral component and the lower electrode 3 of the semiconductor device 2 can be further shortened, and the electrical characteristics can be improved. Further, since a space is created around the child substrate 1 because the components are built in the child substrate 1, more components can be arranged directly below the semiconductor device 2 and high-density mounting becomes possible.
  • a solder resist may be formed when the sub-substrate 1 is formed. 4A to 4E, 9A to 9D, etc., after forming the upper surface electrode 4a and the lower surface electrode 4b, a solder resist may be formed in a region between the upper surface electrode 4a and a region between the lower surface electrode 4b. .
  • the solder resist is formed so as to be symmetric with respect to the front and back of the substrate in accordance with the upper surface electrode 4a and the lower surface electrode 4b. If solder leakage can be prevented, the solder resist may not be formed so as to be symmetrical with respect to the front and back of the substrate.
  • solder bumps may be formed on the child substrate 1 before the child substrate 1 is mounted on the parent substrate 5.
  • solder bumps are formed in advance on the lower electrode 4b of the sub board 1, and the sub board 1 on which the solder bumps are formed is placed on the connection pads 9 of the main board 5. It may be mounted and the lower surface electrode 4b and the connection pad 9 may be connected.
  • solder bumps may be formed in advance on the peripheral component 7 and mounted on the parent substrate 5.
  • the semiconductor device 2 may be mounted on the sub board 1 before mounting the sub board 1 on the main board 5.
  • the semiconductor device 2 is connected (prestacked) on the child substrate 1 in advance, and the child substrate 1 and the semiconductor device 2 are used as one component (module). 5 may be mounted.
  • the semiconductor device 2 may be mounted on the sub-board 1 after cutting (divided) as shown in FIG. 4E or FIG. 9D, or a plurality of semiconductor devices 2 may be mounted on the sub-board 1 before cutting.
  • a blade of a cutting device (dividing device) may be inserted and cut (divided) from the surface of the electrode 4b.
  • the peripheral component 7 is mainly connected to the semiconductor device 2.
  • the peripheral component 7 is not necessarily electrically connected to the semiconductor device 2. It does not have to be connected. In this case, the characteristics of the semiconductor device 2 are not affected, but at least the effect of realizing high-density mounting can be obtained.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Combinations Of Printed Boards (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

L'invention concerne un appareil électronique (100) rendant superflue l'augmentation d'une surface de montage et qui, pour ce faire, comporte : un substrat (103) ; un premier composant électronique (102) monté sur le substrat (103) ; une partie de connexion/support (101), qui connecte électriquement entre eux le substrat (103) et le premier composant électronique (102), est prévue entre le substrat (103) et le premier composant électronique (102) et maintient le premier composant électronique (102) sur le substrat (103) ; et un second composant électronique (104), monté sur le substrat (103) entre le substrat (103) et le premier composant électronique (102).
PCT/JP2013/000356 2012-04-12 2013-01-24 Appareil électronique et procédé de fabrication de celui-ci WO2013153717A1 (fr)

Applications Claiming Priority (2)

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JP2012-090812 2012-04-12
JP2012090812 2012-04-12

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WO2013153717A1 true WO2013153717A1 (fr) 2013-10-17

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Cited By (2)

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CN104952614A (zh) * 2014-03-24 2015-09-30 株式会社村田制作所 电子部件
CN111034374A (zh) * 2017-08-23 2020-04-17 斯天克有限公司 柔性电路板及其制造方法

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JP2002368373A (ja) * 2001-06-06 2002-12-20 Toyo Commun Equip Co Ltd 電子デバイス
JP2005136380A (ja) * 2003-10-06 2005-05-26 Elpida Memory Inc 半導体部品の実装構造及び半導体装置
JP2006012897A (ja) * 2004-06-22 2006-01-12 Matsushita Electric Ind Co Ltd 実装構造および電子部品
JP2007221133A (ja) * 2006-02-14 2007-08-30 Integrant Technologies Inc 集積回路パッケージ
JP2007324354A (ja) * 2006-05-31 2007-12-13 Sony Corp 半導体装置
JP2009289977A (ja) * 2008-05-29 2009-12-10 Fujitsu Media Device Kk 電子部品モジュール
JP2011155169A (ja) * 2010-01-28 2011-08-11 Nec Corp 電子部品の実装構造およびキャビティ基板の製造方法

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JP2002368373A (ja) * 2001-06-06 2002-12-20 Toyo Commun Equip Co Ltd 電子デバイス
JP2005136380A (ja) * 2003-10-06 2005-05-26 Elpida Memory Inc 半導体部品の実装構造及び半導体装置
JP2006012897A (ja) * 2004-06-22 2006-01-12 Matsushita Electric Ind Co Ltd 実装構造および電子部品
JP2007221133A (ja) * 2006-02-14 2007-08-30 Integrant Technologies Inc 集積回路パッケージ
JP2007324354A (ja) * 2006-05-31 2007-12-13 Sony Corp 半導体装置
JP2009289977A (ja) * 2008-05-29 2009-12-10 Fujitsu Media Device Kk 電子部品モジュール
JP2011155169A (ja) * 2010-01-28 2011-08-11 Nec Corp 電子部品の実装構造およびキャビティ基板の製造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104952614A (zh) * 2014-03-24 2015-09-30 株式会社村田制作所 电子部件
JP2015185652A (ja) * 2014-03-24 2015-10-22 株式会社村田製作所 電子部品
US10014111B2 (en) 2014-03-24 2018-07-03 Murata Manufacturing Co., Ltd. Substrate terminal mounted electronic element
CN111034374A (zh) * 2017-08-23 2020-04-17 斯天克有限公司 柔性电路板及其制造方法

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