WO2013145412A1 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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WO2013145412A1
WO2013145412A1 PCT/JP2012/078882 JP2012078882W WO2013145412A1 WO 2013145412 A1 WO2013145412 A1 WO 2013145412A1 JP 2012078882 W JP2012078882 W JP 2012078882W WO 2013145412 A1 WO2013145412 A1 WO 2013145412A1
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semiconductor layer
type impurity
layer
semiconductor device
impurities
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French (fr)
Japanese (ja)
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小池　正浩
雄一 上牟田
手塚　勉
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National Institute of Advanced Industrial Science and Technology AIST
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National Institute of Advanced Industrial Science and Technology AIST
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28255—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC

Definitions

  • Embodiments described herein relate generally to a semiconductor device having an impurity diffusion region and a method for manufacturing the same.
  • an impurity diffusion region such as an n + -Ge layer is usually formed by introducing an n-type impurity into a Ge substrate by ion implantation. At this time, heat treatment is required to reduce defects generated by ion implantation and to electrically activate the impurities.
  • high-temperature heat treatment (> 450 ° C.) is necessary to sufficiently activate the impurities.
  • the level at the interface of the gate insulating film / Ge substrate is increased, which may cause deterioration in device characteristics.
  • An object of the present invention is to provide a semiconductor device that can activate impurities introduced into a semiconductor layer at a low temperature and contribute to improvement of element characteristics, and a method for manufacturing the same.
  • a semiconductor device includes a first conductivity type semiconductor layer, a pair of second conductivity type impurity diffusion regions provided apart from a surface portion of the semiconductor layer, and the semiconductor layer of the semiconductor layer.
  • a gate insulating film provided on a region sandwiched between the pair of impurity diffusion regions; and a gate electrode provided on the gate insulating film.
  • the impurity diffusion region has two or more types of impurities, one of the two or more types of impurities is an element selected from the group of chalcogens, and another type is an impurity of the second conductivity type. is there.
  • an impurity of a necessary conductivity type is introduced as an impurity to be introduced into a semiconductor layer for forming an impurity diffusion region, and an element selected from chalcogen is introduced, so that the impurity can be sufficiently removed even at a low temperature. Can be activated. Thereby, the device characteristics can be improved.
  • FIG. It is a figure which shows the impurity concentration profile of the Ge layer which ion-implanted P.
  • FIG. It is a figure which shows the electron concentration profile of the Ge layer which ion-implanted P.
  • FIG. It is a figure which shows the impurity concentration profile of the Ge layer which ion-implanted S.
  • FIG. It is a figure which shows the electron concentration profile of the Ge layer which ion-implanted S.
  • FIG. It is a figure which shows the impurity concentration profile of Ge layer which ion-implanted Se.
  • FIG. 1 is a cross-sectional view showing a schematic configuration of a Ge-MOSFET according to a first embodiment.
  • FIG. 7 is a cross-sectional view showing a Ge-MOSFET manufacturing process according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a Ge-MOSFET manufacturing process according to the first embodiment.
  • FIG. 7 is a cross-sectional view showing a Ge-MOSFET manufacturing process according to the first embodiment.
  • FIG. 3 is a schematic diagram illustrating a configuration of a nonvolatile semiconductor memory device according to a second embodiment, and is a cross-sectional view along a channel length direction.
  • FIG. 3 is a schematic diagram illustrating a configuration of a nonvolatile semiconductor memory device according to a second embodiment, and is a cross-sectional view along a channel length direction.
  • FIG. 3 is a schematic diagram illustrating a configuration of a nonvolatile semiconductor memory device according to a second embodiment, and is a cross-sectional view along a channel width direction. It is sectional drawing which shows schematic structure of the junctionless transistor concerning 3rd Embodiment. It is sectional drawing which shows the modification of 3rd Embodiment.
  • the present inventors have made various experiments and studies on the formation of an n-type impurity diffusion region for a Ge substrate. As a result, it has been found that when chalcogen (S, Se, Te) is introduced into Ge together with P as an n-type impurity, an n + -Ge layer having a higher electron concentration than that of P alone is formed.
  • chalcogen S, Se, Te
  • FIG. 1A shows an impurity concentration profile and FIG. 1B shows an electron concentration profile when only P as an n-type impurity is implanted into a Ge substrate.
  • the P dose was 1 ⁇ 10 15 cm ⁇ 2 and the acceleration energy was 10 keV.
  • the impurity concentration profile hardly changes depending on the temperature except near the surface. That is, it is understood that it hardly diffuses except near the surface.
  • the electron concentration profile increases near the surface as the temperature increases. That is, it can be seen that the electron concentration increases near the surface.
  • the maximum concentration when the heat treatment temperature is 450 ° C. is 5.6 ⁇ 10 18 cm ⁇ 3 .
  • FIG. 2A shows an impurity concentration profile and FIG. 2B shows an electron concentration profile when only S as chalcogen is implanted into a Ge substrate.
  • the S dose was set to 5 ⁇ 10 14 cm ⁇ 2 .
  • an acceleration energy of 10 keV was selected so that the P injection and the projection range were aligned.
  • FIG. 3A shows the impurity concentration profile and FIG. 3B shows the carrier concentration profile when only Se as chalcogen is implanted into the Ge substrate.
  • FIG. 4A shows an impurity concentration profile and FIG. 4B shows a carrier concentration profile when only Te as a chalcogen is implanted into a Ge substrate.
  • the impurity profile hardly changes depending on the temperature as in the case of P and S. Furthermore, it was found that generation of electrons was not recognized even when the temperature was increased.
  • the impurity concentration profile is near the surface at each temperature as shown in FIG. 5A. Except for the change. However, as shown in FIG. 5B, it was found that the electron concentration profile changes with temperature and also with depth. Moreover, as can be seen from comparison with FIG. 1B, it was confirmed that the electron concentration increased even at a low temperature of 350 ° C. or 250 ° C.
  • FIGS. 6A and 6B and FIGS. 7A and 7B show the electron concentration increased even at a low temperature.
  • 6A and 6B show the case where Se is implanted together with P into the Ge substrate
  • FIG. 6A shows the impurity concentration profile
  • FIG. 6B shows the electron concentration profile
  • 7A and 7B show the case where Te is implanted into the Ge substrate together with P
  • FIG. 7A shows the impurity concentration profile
  • FIG. 7B shows the electron concentration profile.
  • the acceleration energy of Se and Te was 17 and 20 keV, respectively, and the dose amount was 5 ⁇ 10 14 cm ⁇ 2 , which was the same as S, so that the P implantation and the projection range were aligned.
  • any one of chalcogens (S, Se, Te) is introduced together with P, so that n at a temperature lower than 450 ° C. (for example, 250 ° C.).
  • the electron concentration in the type impurity diffusion region can be sufficiently increased. Therefore, by applying this to MOSFETs and other semiconductor devices, it is possible to contribute to improvement of element characteristics.
  • the chalcogen impurity concentration is preferably lower than the n-type impurity concentration.
  • the present inventors have a high concentration n + -Ge layer without introducing a general n-type impurity such as P. Was found to be formed.
  • FIGS. 8A to 8C are diagrams showing impurity profiles at respective heat treatment temperatures in S, Se, and Te.
  • 8A is 250 ° C.
  • FIG. 8B is 350 ° C.
  • FIG. 8C is 450 ° C. From these figures, as in the case where S, Se, and Te are introduced alone, the impurity profile at each heat treatment temperature hardly changes except near the surface. That is, it can be seen that it is not diffused except near the surface.
  • FIG. 9 is a diagram showing an electron concentration profile of a Ge substrate into which three kinds of ions of S, Se, and Te are implanted.
  • a significant increase in electron concentration is seen up to a depth of about 20 nm from the surface. That is, with each chalcogen alone, an increase in the electron concentration due to the heat treatment was not visible, or only a low concentration n + -Ge layer was formed.
  • the higher the heat treatment temperature after ion implantation It can be seen that the electron concentration increases. In particular, it can be seen that the electron concentration greatly increases at 350 ° C. or higher.
  • the maximum concentration at 350 ° C. is 8.1 ⁇ 10 17 cm ⁇ 3
  • the maximum concentration at 450 ° C. is 9.35 ⁇ 10 16 cm ⁇ 3 .
  • the electron concentration in the n-type impurity diffusion region can be sufficiently increased at a temperature lower than 450 ° C. (eg, 350 ° C.). Therefore, by applying this to MOSFETs and other semiconductor devices, it is possible to contribute to improvement of element characteristics.
  • n-type impurity As and Sb.
  • the present invention can be applied not only to the formation of an n + layer but also to the formation of a p + layer.
  • a semiconductor containing Ge as a main component has been described as an example. It is possible to apply.
  • GaAs for example, Zn is used as a p-type impurity, and Si is used as an n-type impurity.
  • chalcogen when introduced together with one or more types of chalcogen, a high concentration layer of each conductivity type can be formed.
  • the dose amount of each chalcogen is 5 ⁇ 10 14 cm ⁇ 2
  • the effect of the present invention is obtained if the chalcogen dose exceeds the solid solubility limit of the semiconductor layer.
  • the chalcogen dose exceeds the solid solubility limit of the semiconductor layer.
  • it may be 1 ⁇ 10 16 cm ⁇ 3 or more.
  • the temperature used for the electrical activation of impurities varies from semiconductor to semiconductor, using the present invention can lower the temperature or shorten the time. Diffusion of impurities may be caused by heat treatment for electrical activation, but diffusion can be suppressed by reducing the heat treatment temperature or the heat treatment time.
  • FIG. 11 is a cross-sectional view showing a schematic configuration of the Ge-MOSFET according to the first embodiment.
  • reference numeral 10 denotes a p-Ge substrate
  • a gate electrode 12 such as polycrystalline silicon is formed on the surface of the substrate 10 via a gate insulating film 11 such as a silicon oxide film.
  • Sidewall insulating films 13 are formed on both side surfaces of the gate electrode 12.
  • a source / drain region (S / D region) 14 composed of an n + diffusion region is formed on the surface portion of the substrate 10 with the gate structure portion interposed therebetween.
  • P as an n-type impurity and Te as a chalcogen are introduced into the S / D region 14 by ion implantation. Then, the impurity is activated by annealing after ion implantation, and an n + -type impurity diffusion region having a high electron concentration is formed.
  • the thickness of the S / D region 14 in the substrate direction is about 1/3 (10 to 20 nm) of the gate length
  • the maximum impurity concentration of P is 3 ⁇ 10 19 cm ⁇ 3
  • Te The maximum impurity concentration is 2 ⁇ 10 19 cm ⁇ 3 lower than that.
  • Each impurity concentration may be higher than Te as long as Te does not exceed the concentration of P.
  • the heat treatment temperature is 350 ° C. which can increase the carrier concentration without deteriorating the gate insulating film / substrate structure. Even at such a temperature, impurities can be sufficiently activated, and good device characteristics can be obtained.
  • 12A to 12C are cross-sectional views showing the manufacturing process of the Ge-MOSFET of this embodiment.
  • the gate electrode 12 is formed on the surface of the p-Ge substrate 10 via the gate insulating film 11. Specifically, after a silicon oxide film is formed on the surface of the substrate 10, a polysilicon film is deposited and processed into a gate pattern.
  • sidewall insulating films 13 are formed on both side surfaces of the gate electrode 12.
  • the sidewall insulating film 13 may be formed by, for example, etching back so that the silicon oxide film on the surface of the substrate and the gate electrode 12 is removed after a silicon oxide film is deposited on the entire surface.
  • the gate electrode 12 and the sidewall insulating film 13 are used as a mask, and P and Te are introduced into the surface portion of the substrate 10 by ion implantation, thereby forming the S / D region 14.
  • the order of ion implantation of P and Te may be any first.
  • the depth of ion implantation is about 1/3 (10 to 20 nm) of the gate length for a MOSFET having a gate length of 50 nm, the maximum impurity concentration of P is 3 ⁇ 10 19 cm ⁇ 3 , and the maximum of Te The impurity concentration of 2 ⁇ 10 19 cm ⁇ 3 was lower than that.
  • the carrier concentration of the n + -type diffusion layer (S / D region) 14 could be increased without degrading the gate insulating film / substrate structure.
  • the carrier concentration of the polysilicon layer can be increased.
  • an example of a polysilicon film is shown as the gate electrode, but another polycrystalline semiconductor or metal may be used. In the case of a polycrystalline semiconductor, the carrier concentration can be increased by the effect of this research.
  • the Ge-MOSFET is completed by depositing an interlayer insulating film or the like (not shown) and forming a contact plug.
  • the annealing temperature for impurity activation can be lowered as compared with the case where P is introduced alone, and an increase in the level of the gate insulating film / Ge substrate interface accompanying the annealing can be suppressed. Therefore, the device characteristics of the Ge-MOSFET can be improved.
  • FIG. 13A and 13B are cross-sectional views showing a schematic configuration of the nonvolatile semiconductor memory device according to the second embodiment, and FIG. 13A corresponds to the AA ′ cross section of FIG. 13B.
  • a floating gate (charge storage layer) 22 is formed on the Si substrate 20 via a tunnel insulating film 21.
  • a control gate 24 is formed on the floating gate 22 via an interelectrode insulating film 23.
  • a groove is formed in the substrate 20 along the word line direction, and an element isolation insulating film 25 is formed in the groove. The upper surface of the element isolation insulating film 25 is higher than the lower surface of the floating gate 22 and lower than the upper surface of the floating gate 22.
  • chalcogen S, Se, or Te is introduced into the floating gate 22 and the control gate 24 in addition to P, thereby annealing at a low temperature. Impurity activation can be performed. Thereby, the resistance of the floating gate 22 and the control gate 23 can be reduced, and the device characteristics can be improved.
  • FIG. 14 is a schematic configuration diagram illustrating a junctionless transistor according to the third embodiment.
  • n + -Ge layer 31 is formed on a support substrate 40 in which an insulating film 42 is formed on a Si substrate 41.
  • a gate electrode 33 is formed on the n + -Ge layer 31 via a gate insulating film 32.
  • Source / drain electrodes 34 and 35 are formed on the surface of the n + -Ge layer 31 with the gate electrode 33 interposed therebetween.
  • Such a junctionless transistor is a nano-scale MOS transistor configured as a MOS transistor without using a pn junction. Since all the source, channel, and drain regions are composed of semiconductor layers having the same polarity, a device structure with extremely high gate electrostatic control power is required to realize the OFF state. Therefore, it is desirable that the n + -Ge layer 31 is formed in a fin shape on the insulating film 42 and the gate electrode 33 is formed so as to surround the periphery of the n + -Ge layer 31.
  • the source / drain regions do not necessarily have to be the same n + -Ge layer 31 as the channel. As shown in FIG. 15, all of the source / drain regions or the upper portion of the n + -Ge layer 31 is made of NiGe or the like.
  • the metal layers 36 and 37 may be used.
  • the n + -Ge layer 31 is formed by annealing at a temperature of 350 ° C.
  • the n + -Ge layer 31 is formed by introducing P and S and performing epitaxial growth. Thereby, the impurity of Ge layer 31 can be made into a high electron concentration, and the device characteristic can be improved.
  • the present invention is not necessarily limited to the formation of the n + layer, but can be applied to the formation of the p + layer.
  • the impurity introduction method is not limited to ion implantation, and for example, epitaxial growth, solid phase diffusion, vapor phase diffusion, or the like may be used.
  • the semiconductor is not limited to a semiconductor layer or Si layer mainly composed of Ge, but can be applied to a compound semiconductor.
  • the present invention is not limited to MOSFET source / drain regions and extension layers, control gate electrodes and floating gate electrodes of nonvolatile semiconductor devices, and junctionless transistor substrates. It is possible.

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WO2015029270A1 (ja) * 2013-08-28 2015-03-05 株式会社 東芝 半導体装置及びその製造方法

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US10224402B2 (en) * 2014-11-13 2019-03-05 Texas Instruments Incorporated Method of improving lateral BJT characteristics in BCD technology
DE102014119088A1 (de) * 2014-12-18 2016-06-23 Infineon Technologies Ag Ein Verfahren zum Bilden eines Halbleiterbauelements und eines Halbleitersubstrats
JP7672901B2 (ja) 2021-07-06 2025-05-08 キヤノン株式会社 電子写真用ベルト及びそれを用いた電子写真画像形成装置

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