WO2013104289A1 - 发光二极管及制作方法 - Google Patents

发光二极管及制作方法 Download PDF

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Publication number
WO2013104289A1
WO2013104289A1 PCT/CN2013/070141 CN2013070141W WO2013104289A1 WO 2013104289 A1 WO2013104289 A1 WO 2013104289A1 CN 2013070141 W CN2013070141 W CN 2013070141W WO 2013104289 A1 WO2013104289 A1 WO 2013104289A1
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ohmic contact
layer
buffer layer
contact buffer
type
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PCT/CN2013/070141
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English (en)
French (fr)
Inventor
叶孟欣
吴志强
黄少华
周启伦
Original Assignee
林秀成
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Priority claimed from CN201210003578.3A external-priority patent/CN102569556B/zh
Priority claimed from CN201210003576.4A external-priority patent/CN102522468B/zh
Application filed by 林秀成 filed Critical 林秀成
Priority to US14/369,930 priority Critical patent/US9397253B2/en
Publication of WO2013104289A1 publication Critical patent/WO2013104289A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/0004—Devices characterised by their operation
    • H01L33/002—Devices characterised by their operation having heterojunctions or graded gap
    • H01L33/0025—Devices characterised by their operation having heterojunctions or graded gap comprising only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
    • H01L33/325—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen characterised by the doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0075—Processes relating to semiconductor body packages relating to heat extraction or cooling elements

Definitions

  • the invention relates to a light emitting diode and a manufacturing method thereof, in particular to a method with high doping n Light-emitting diode of type ohmic contact buffer layer and method of manufacturing the same.
  • substrate transfer techniques have been developed, such as deposition by MOCVD on sapphire substrates.
  • a GaN-based film which is then bonded to a semiconductor or metal substrate by wafer bonding or electroplating, and then the sapphire substrate is removed by laser lift-off; or in SiC or Si Depositing a GaN-based film on the substrate, and then bonding the GaN-based film to a semiconductor or metal substrate by wafer bonding or electroplating, and then SiC or Si The substrate is removed by chemical etching.
  • the above two aspects make the thin film GaN chip have higher light-emitting efficiency, and the transferred substrate has excellent thermal conductivity, so the GaN transferred to the heat-dissipating substrate is transferred.
  • the base film chip has a great advantage in high current applications.
  • the exposed GaN after removal of the growth substrate The surface of the film is generally a nitrogen polar surface, and the ohmic contact characteristics of the nitrogen polar surface are different from those of the gallium polar surface.
  • the ohmic contact electrode of the N-type GaN of the gallium polar plane generally adopts a Ti/Al ohmic contact electrode, and the nitrogen pole Sexual If the contact electrode of N-type GaN still uses a Ti/Al electrode, Ti/Al and N-type GaN exhibit better ohmic contact characteristics than the gallium polarity plane at the initial time, but after 150 After the temperature is around, the contact characteristics are degraded to Schottky contact, which is manifested by the increase of the forward working voltage, which seriously restricts the light efficiency of the thin film GaN chip.
  • Hyunsoo Kim et al. (APPLIED PHYSICS LETTERS 93, 192106, 2008) considers nitrogen vacancies and surface gallium vacancies as well as C, O Atomic reactions lead to a reduction in surface nitrogen vacancies; Ho Won Jang et al. (APPLIED PHYSICS LETTERS 94, 182108, 2009) It is believed that the diffusion of nitrogen atoms into the surface compensates for the reduction of surface nitrogen vacancies due to nitrogen vacancies. So far, the two research teams have not proposed an effective method for making N-type GaN ohmic contact electrodes on the nitrogen polar surface.
  • TFFC thin film flip-chip LED from Philips Lumileds Lighting Company, whose N-type ohmic contact electrode is still fabricated on a gallium polar surface N-type On GaN, the Ti/Al ohmic contact electrode can continue to be used, so a significant advantage of TFFC is that it can completely avoid the above discussion of the polar face of the nitrogen, but because of the P, N on the film.
  • the electrodes need to be bonded to the corresponding positive and negative electrode regions on the substrate respectively, so the flip chip technology is required to be high; in addition, in order to avoid film breakage when the laser is peeled off from the sapphire substrate, it is necessary to ensure that the film surface receives a uniform impact force in the laser stripping sapphire moment. Therefore, it is necessary to fill the medium between the film and the flip-chip bonding substrate before laser stripping the sapphire substrate, the consistency of filling is difficult to control, and the device yield may be affected.
  • the invention proposes a doping n Light-emitting diode of ohmic contact buffer layer and manufacturing method thereof to overcome the existing vertical GaN-based vertical light-emitting diode, and the ohmic contact electrode on the n-type GaN-based semiconductor layer is susceptible to temperature cracking GaN-based light-emitting device voltage reliability issues.
  • a method of fabricating an epitaxial structure of an LED includes the steps of: providing a growth substrate; forming a doped n-type ohmic contact buffer layer on the growth substrate, the electron concentration being greater than or equal to 1 ⁇ 10 18 cm ⁇ 3 ; epitaxially growing a light-emitting epitaxial layer on the n-type ohmic contact buffer layer, which includes at least an n-type semiconductor layer, an active layer, and a p-type semiconductor layer.
  • the n-type ohmic contact buffer layer is formed by epitaxial growth, and the material is Al c In d Ga 1-cd N (where 0 ⁇ c ⁇ 1 , 0 ⁇ d ⁇ 1 , c+d ⁇ 1 ),
  • the energy gap is less than or equal to 3.4 eV and the thickness is 10 angstroms to 5000 angstroms.
  • ions may be implanted by ion implantation to form a high doping having a doping concentration greater than or equal to 1 ⁇ 10 20 cm -3 .
  • an LED epitaxial structure includes: a growth substrate; a doped n-type ohmic contact buffer layer on the growth substrate, the electron concentration of which is greater than or equal to 1 ⁇ 10 18 cm
  • a light-emitting epitaxial layer is formed over the n-type ohmic contact buffer layer, and includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer from bottom to top.
  • the n-type ohmic contact buffer layer is a silicon-doped nitride having a doping concentration greater than or equal to 1 ⁇ 10 18 cm ⁇ 3 and is composed of Al c In d Ga 1-cd N (where 0 ⁇ c ⁇ 1 , 0 ⁇ d ⁇ 1 , c+d ⁇ 1 ), the energy gap is less than or equal to 3.4 eV, and the thickness is 10 angstroms to 5000 angstroms.
  • ions may be implanted by ion implantation to form a high doping having a doping concentration greater than or equal to 1 ⁇ 10 20 cm -3 .
  • the LED epitaxial structure may further include a gradation silicon doped n-type nitride semiconductor layer, which is located at n Between the ohmic contact buffer layer and the luminescent epitaxial layer.
  • a method of fabricating an LED chip includes the steps of: providing a growth substrate; forming a doped n-type ohmic contact buffer layer on the growth substrate, the electron concentration being greater than or equal to 1 ⁇ 10 18 cm ⁇ 3 ; epitaxially growing an illuminating epitaxial layer on the n-type ohmic contact buffer layer, the bottom portion including at least: an n-type semiconductor layer, an active layer, and a p-type semiconductor layer; providing a conductive substrate to emit light The epitaxial layer is bonded to the conductive substrate; the growth substrate is peeled off to expose the surface of the n-type ohmic contact buffer layer; the p-electrode is formed on the conductive substrate, and the n-electrode is formed on the surface of the n-type ohmic contact buffer layer.
  • the n-type ohmic contact buffer layer is formed by epitaxial growth, and the material is Al c In d Ga 1-cd N (where 0 ⁇ c ⁇ 1 , 0 ⁇ d ⁇ 1 , c+d ⁇ 1 ), and the doping thereof
  • the impurity concentration is greater than or equal to 1 ⁇ 10 18 cm -3
  • the energy gap is less than or equal to 3.4 eV
  • the thickness is 10 angstroms to 5000 angstroms.
  • ions may be implanted by ion implantation to form a high doping having a doping concentration greater than or equal to 1 ⁇ 10 20 cm -3 .
  • a light emitting diode chip includes: a conductive substrate having positive and negative surfaces; and a light emitting epitaxial layer on a front surface of the conductive substrate, wherein the top and bottom layers comprise an n-type semiconductor layer, Active layer, p-type semiconductor layer; doped n-type ohmic contact buffer layer, located on the n-type semiconductor layer, having an electron concentration greater than or equal to 1 ⁇ 10 18 cm ⁇ 3 ; second electrode located in the n-type ohmic contact buffer layer Above; the first electrode is located above the reverse surface of the conductive substrate.
  • the n-type ohmic contact buffer layer is a silicon-doped nitride having a doping concentration greater than or equal to 1 ⁇ 10 18 cm ⁇ 3 and is composed of Al c In d Ga 1-cd N (where 0 ⁇ c ⁇ 1 , 0 ⁇ d ⁇ 1 , c+d ⁇ 1 ), the energy gap is less than or equal to 3.4 eV, and the thickness is 10 angstroms to 5000 angstroms.
  • ions may be implanted by ion implantation to form a high doping having a doping concentration greater than or equal to 1 ⁇ 10 20 cm -3 .
  • the surface in contact with the growth substrate is made to have a non-nitrogen polarity by doping a high concentration of n-type ions.
  • a gallium nitride based light emitting diode an epitaxial layer is epitaxially grown on a high electron concentration n-type ohmic contact buffer layer, and when the growth substrate is removed, an n-type ohmic contact buffer layer of the surface is exposed, which is a low energy gap
  • Non-nitrogen polar n-type GaN-based material, n-type ohmic contact electrode is fabricated on the n-type ohmic contact buffer layer, and the Ti/Al ohmic contact electrode is used to avoid the problem of ohmic contact of the nitrogen polar surface, and is guaranteed Thin film GaN light emitting devices have a lower operating voltage.
  • the ohmic contact buffer layer is used as the initial nucleation layer, and is doped with high silicon and grown at a low temperature. Therefore, the crystal lattice is loose and the bond strength between atoms is weak, so that the laser stripping process or the wet etching process is significantly reduced. Due to the laser lift-off process on the growth substrate and The transient high temperature generated by the LED film interface and the large stress and impact generated during the mechanical separation process do not increase the structural defects of the LED epitaxial layer, and the negative impact on the internal quantum efficiency is greatly reduced.
  • the doping concentration needs to be at least 1 ⁇ 10 20 cm ⁇ 3 , generally only by epitaxial growth, It is easy to form such a high impurity concentration, and the present invention can easily achieve the impurity concentration or higher by ion implantation.
  • FIG. 1 is a schematic view showing an epitaxial structure of a light emitting diode having a doped n-type ohmic contact buffer layer according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic cross-sectional view of an LED chip prepared according to the epitaxial structure of the LED shown in FIG.
  • Figure 3 is a graph showing the forward operating voltage of Embodiment 1 of the present invention.
  • Fig. 4 is a graph showing the forward working voltage after aging in the first embodiment of the present invention.
  • Fig. 5 is a graph showing the luminous output power of the embodiment 1 of the present invention.
  • FIG. 6 is a schematic diagram showing an epitaxial structure of a light emitting diode having a doped n-type ohmic contact buffer layer according to Embodiment 2 of the present invention.
  • FIG. 7 is a schematic cross-sectional view of an LED chip prepared according to the epitaxial structure of the LED shown in FIG. 6.
  • Figure 8 is a graph showing the forward operating voltage of Embodiment 2 of the present invention.
  • Fig. 9 is a graph showing the forward working voltage after aging in the second embodiment of the present invention.
  • Figure 10 is a graph showing the luminous output power of Embodiment 2 of the present invention.
  • LEDs proposed by the present invention in specific device design and manufacture The structure will be modified according to the application field and process process requirements, and some of its structure and size can be modified within a certain range, and the material selection can be modified.
  • FIG. 1 is a schematic diagram of an epitaxial structure of an LED of Embodiment 1.
  • an LED epitaxial structure includes: an epitaxial growth substrate 101, and an n-type ohmic contact buffer layer 102. Formed on the epitaxial growth substrate 101, an n-type GaN-based semiconductor layer 103 is formed over the n-type ohmic contact buffer layer 102, and an active layer 104 is formed on the n-type GaN. Above the base semiconductor layer 103, a p-type GaN-based semiconductor layer 106 is formed over the active layer 104.
  • the epitaxial growth substrate 101 includes, but is not limited to, sapphire, aluminum nitride, gallium nitride, silicon, silicon carbide, and the crystal orientation thereof includes but is not limited to 0001 Equally polarized, semi-polarized, and non-polarized, the surface structure of which may be a planar structure or a specially treated patterned surface.
  • the n-type ohmic contact buffer layer 102 is composed of a layer of aluminum indium gallium nitride Al c In d Ga 1-cd N having a specific composition and an energy gap of less than or equal to 3.4 eV, and 0 ⁇ c ⁇ 1 , 0 ⁇ d ⁇ 1 , c +d ⁇ 1, film thickness between 10 angstroms and 5000 angstroms.
  • the n-type ohmic contact buffer layer 102 is doped with silicon impurities, and the concentration of silicon is greater than or equal to 1 ⁇ 10 18 cm -3 , so that the electron concentration of the n-type ohmic contact buffer layer 102 is greater than or equal to 1 ⁇ 10 18 cm -3 .
  • Its outer surface is a non-nitrogen polar surface.
  • the film thickness of the n-type GaN-based semiconductor layer 103 is 20,000 angstroms to 40,000 angstroms; the active layer 104
  • the multi-quantum well structure has an InGaN layer as a well layer and a GaN layer as a barrier layer, wherein the well layer has a film thickness of 18 ⁇ to 30 ⁇ , and the barrier layer has a film thickness of 80 ⁇ to 200 ⁇ ;
  • p-type The film thickness of the GaN-based semiconductor layer 106 is between 1000 ⁇ and 3000 ⁇ ; a Mg-doped Mg can be interposed between the p-type GaN-based semiconductor layer 106 and the active layer 104.
  • the aluminum indium gallium nitride layer serves as an electron blocking layer 105 having a film thickness of 100 angstroms to 600 angstroms.
  • FIG. 2 is a vertical LED chip fabricated according to the epitaxial structure of the LED shown in FIG. 1.
  • an LED chip having a good n-type ohmic contact includes: a conductive substrate 203
  • the light-emitting epitaxial layer is flip-chip soldered on the front surface of the conductive substrate through the metal bonding layer 202, and the light-emitting epitaxial layer is a structure in which the light-emitting diode epitaxial structure shown in FIG.
  • the top-down structure is p-type GaN-based semiconductor layer, electron blocking layer 105, active layer 104, n-type GaN-based semiconductor layer 103, n-type ohmic contact buffer layer 102; second electrode metal layer 204 Formed on the n-type ohmic contact buffer layer 102, a first electrode metal layer 205 is formed on the back surface of the conductive substrate 203.
  • a p-plane mirror and an ohmic electrode layer 201 are interposed between the base semiconductor layer and the conductive substrate, and a p-plane metal diffusion barrier layer is added to the metal bonding layer 202.
  • the second electrode metal layer 204 Fabricated on a highly doped n-type ohmic contact buffer layer 102, avoiding the formation of Ti/Al on the nitrogen polar surface of an n-type GaN-based semiconductor layer in a conventional vertical gallium nitride-based light-emitting diode chip.
  • the ohmic contact electrode encounters 150 ° C, its contact characteristics deteriorate into a problem of Schottky contact.
  • Step 1 providing an epitaxial growth substrate 101, and epitaxially growing a doped n-type ohmic contact buffer layer 102 on the surface of the growth substrate. , whose electron concentration is greater than or equal to 1 ⁇ 10 18 Cm -3 The energy gap is less than or equal to 3.4 eV.
  • N-type ohmic contact buffer layer 102 Silicon-doped Al can be used c In d Ga 1-cd N , ( 0 ⁇ c ⁇ 1 , 0 ⁇ d ⁇ 1 , c+d ⁇ 1 ), thickness 10 angstroms to 5000 angstroms, and doping concentration of silicon greater than or equal to 1 ⁇ 10 18 Cm -3 .
  • the electron concentration can be appropriately increased, for example, the concentration can be higher than or equal to 1 ⁇ 10 20 Cm -3 .
  • the concentration can be higher than or equal to 1 ⁇ 10 20 Cm -3 .
  • its growth temperature can be 500 ⁇ 600 °C. .
  • Step 2 epitaxially growing a light-emitting epitaxial layer on the n-type ohmic contact buffer layer 102 to form an epitaxial structure.
  • the luminescent epitaxial layer includes at least: The n-type GaN-based semiconductor layer 103, the active layer 104, and the p-type semiconductor layer 106.
  • the film thickness of the n-type GaN-based semiconductor layer 103 is 20,000 ⁇ .
  • the active layer 104 is a multi-quantum well structure with an InGaN layer as a well layer and a GaN layer as a barrier layer, wherein the well layer has a film thickness of 18 ⁇ to 30 ⁇ , and the film thickness of the barrier layer is 80 ⁇ to 200 ⁇ ;
  • the p-type GaN-based semiconductor layer 106 has a film thickness of 1000 ⁇ to 3000 ⁇ ; in order to improve the internal effect of the luminescent layer, p-type GaN can be used.
  • an aluminum nitride indium gallium nitride layer doped with Mg is inserted as an electron blocking layer 105 having a film thickness of 100 ⁇ to 600 ⁇ .
  • Step 3 Defining the size of the chip, performing mesa etching on the completed epitaxial wafer by a dry etching process to complete chip-level separation of the epitaxial wafer.
  • the etching depth is at least transmitted through the epitaxial film to the epitaxial growth substrate 101 Surface.
  • Step 4 A conductive substrate 203 is provided to connect the light-emitting epitaxial layer to the conductive substrate 203.
  • P-type GaN-based semiconductor layer 106 P-type GaN-based semiconductor layer 106.
  • a metal bonding layer 202 is formed on the conductive substrate 203, and the light emitting epitaxial layer and the conductive substrate 203 are connected by a metal bonding process.
  • it can be in p type A p-plane mirror and an ohmic electrode layer 201 are formed on the GaN-based semiconductor layer 106, and a p-plane metal diffusion barrier layer is added to the metal bonding layer 202.
  • Step 5 Peel the growth substrate 101.
  • the epitaxial growth substrate 101 is removed by epitaxy, grinding or wet etching, and the substrate is epitaxially grown and The LED films are separated and the LED film remains on the inversion substrate to expose the surface of the n-type ohmic contact buffer layer 102.
  • Step 6 forming a lower electrode metal layer 205 on the conductive substrate, and forming an n-side electrode metal layer on the surface of the n-type ohmic contact buffer layer 204. Complete the fabrication of the vertical structure LED.
  • the process of the present embodiment (the buffer layer has n-type doping), the conventional process (ie, the buffer layer is not doped), and the fabrication 2
  • the samples were evaluated for their luminous output power, forward voltage and aging characteristics.
  • the thick layers of the respective semiconductor layers were set as shown in Table 1.
  • Table I Semiconductor layer Film thickness ⁇ and structure of each layer of the process of the present invention Film thickness ( and structure of various layers of the traditional process Buffer layer 102 N-type doped ohmic contact buffer 600 Undoped buffer layer 600 N-type GaN-based semiconductor layer 103 25000 25000 Active layer 104 GaN(140)/InGaN(25) X10 cycle (last GaN layer) GaN(140)/InGaN(25) X10 cycle (last GaN layer) Electronic barrier layer 105 600 600 P-type GaN-based semiconductor layer 106 2000 2000 2000 2000
  • Figure 3, Figure 4, and Figure 5 show the results of its evaluation.
  • FIG. 3 A graph of the forward operating voltage of each sample of this example is shown. As can be seen from the figure, the forward working voltage of the nitride vertical structure light emitting diode sample of the present embodiment is lower than that of the conventional nitride vertical structure light emitting diode sample.
  • Fig. 4 is a graph showing the forward working voltage after aging of each sample of the present example. As can be seen from the figure, the reliability of the forward working voltage of the nitride vertical structure light-emitting diode sample of the present embodiment is significantly better than that of the conventional nitride vertical structure light-emitting diode sample.
  • Fig. 5 is a graph showing the luminous output power of each sample of the present embodiment.
  • the nitride vertical structure light emitting diode sample of the present embodiment has a higher light output output than the conventional nitride vertical structure light emitting diode sample.
  • FIG. 6 is a schematic diagram of an epitaxial structure of an LED for Embodiment 2, which is distinguished from Embodiment 1.
  • the n-type ohmic contact buffer layer 102 of the present embodiment is grown by using an ion implantation method to grow n-type ohms in order to obtain a higher electron concentration. After the buffer layer is contacted, ions are implanted so that the co-doping concentration can reach 1 ⁇ 10 20 cm ⁇ 3 or more, and then the other semiconductor material layers are further grown by the secondary epitaxial growth method.
  • n-type nitride semiconductor layer is formed on the n-type ohmic contact buffer layer 102, and the specific structure thereof will be described in detail below with reference to the drawings.
  • an LED epitaxial structure includes: an epitaxial growth substrate 101, an n-type ohmic contact buffer layer 102. Formed on the epitaxial growth substrate 101, a graded silicon doped n-type nitride semiconductor layer 107 is formed on the n-type ohmic contact buffer layer 102 by secondary epitaxial growth, n-type GaN
  • the base semiconductor layer 103 is formed over the graded silicon doped n-type nitride semiconductor layer 107, and the active layer 104 is formed over the n-type GaN-based semiconductor layer 103, p-type GaN
  • a base semiconductor layer 106 is formed over the active layer 104.
  • the epitaxial growth substrate 101 can be selected according to the first embodiment, and the description is not repeated here.
  • the n-type ohmic contact buffer layer 102 is composed of a layer of aluminum indium gallium nitride Al c In d Ga 1-cd N having a specific composition and an energy gap of less than or equal to 3.4 eV, and 0 ⁇ c ⁇ 1 , 0 ⁇ d ⁇ 1 , c +d ⁇ 1; film thickness is between 10 angstroms and 5000 angstroms.
  • the silicon impurity is doped by ion implantation in the n-type ohmic contact buffer layer 102, and the concentration of silicon is greater than or equal to 1 ⁇ 10 20 cm -3 so that the electron concentration of the n-type ohmic contact buffer layer 102 is greater than or equal to 1 ⁇ 10 20 cm. -3 , its outer surface is non-nitrogen polarity.
  • the graded silicon-doped n-type nitride semiconductor layer 107 has a film thickness of 100 ⁇ to 20,000 angstroms and is formed by secondary growth epitaxy, wherein the silicon doping concentration is from 1 ⁇ 10 17 cm -3 to 5 ⁇ 10 18 cm - 3 Gradient to 1 ⁇ 10 18 cm -3 -5 ⁇ 10 19 cm -3 , in this embodiment, the gradient silicon doping n-type nitride semiconductor layer is preferably selected to have a film thickness of 4000 ⁇ to 6000 ⁇ , and the silicon doping concentration is 1 ⁇ .
  • the film thickness of the n-type GaN-based semiconductor layer 103 is 20,000 angstroms to 40,000 angstroms; the active layer 104
  • the multi-quantum well structure has an InGaN layer as a well layer and a GaN layer as a barrier layer, wherein the well layer has a film thickness of 18 ⁇ to 30 ⁇ , and the barrier layer has a film thickness of 80 ⁇ to 200 ⁇ ; p-type
  • the film thickness of the GaN-based semiconductor layer 106 is between 1000 ⁇ and 3000 ⁇ ; a Mg-doped Mg can be interposed between the p-type GaN-based semiconductor layer 107 and the active layer 104.
  • the aluminum indium gallium nitride layer serves as an electron blocking layer 105 having a film thickness of 100 angstroms to 600 angstroms.
  • FIG. 7 is a vertical LED chip fabricated according to the epitaxial structure of the LED shown in FIG. 6.
  • an LED chip having an n-type ohmic contact includes: a conductive substrate 203; and a light-emitting epitaxial layer through a metal bonding layer 202 is flip-chip soldered on the front surface of the conductive substrate, and the light-emitting epitaxial layer is a structure in which the light-emitting diode epitaxial structure shown in FIG. 6 is used to remove the growth substrate, and the p-type GaN-based semiconductor layer is top-down.
  • n-side electrode metal layer 204 is formed over the n-type ohmic contact buffer layer 102, and the lower electrode metal layer 205 is formed on the back surface of the conductive substrate 203.
  • a p-plane mirror and an ohmic electrode layer 201 are interposed between the GaN-based semiconductor layer and the conductive substrate, and a p-plane metal diffusion barrier layer is added to the metal bonding layer 202.
  • n-side electrode metal layer 204 is connected to the n-type n-type GaN-based semiconductor layer 104 through the doped n-type ohmic contact buffer layer 102, avoiding the conventional vertical gallium nitride-based light-emitting diode chip, in the n-type
  • the Ti/Al ohmic contact electrode formed on the nitrogen surface of the GaN-based semiconductor layer has a contact characteristic of 150 ° C, it deteriorates into a problem of Schottky contact.
  • the light-emitting diode epitaxial structure shown in FIG. 6 and the light-emitting diode chip shown in FIG. 7 can be completed by the following process.
  • Step one providing an epitaxial growth substrate 101, and epitaxially growing a doped n-type ohmic contact buffer layer 102 on the surface of the growth substrate, the electron concentration of which is greater than or equal to 1 ⁇ 10 20 cm ⁇ 3 , and the energy gap is less than Or equal to 3.4eV.
  • the n-type ohmic contact buffer layer 102 may be selected from silicon-doped Al c In d Ga 1-cd N ( 0 ⁇ c ⁇ 1 , 0 ⁇ d ⁇ 1 , c+d ⁇ 1 ), and implanted with silicon ions by ion implantation.
  • the doping concentration of silicon is greater than or equal to 1 x 10 20 cm -3 and the thickness is from 10 angstroms to 5000 angstroms. If the n-type ohmic contact buffer layer 102 selects GaN, its growth temperature may be 500 to 600 °C.
  • Step 2 The n-type ohmic contact buffer layer 102 is doped with a graded silicon doped n-type nitride semiconductor layer 107 by a second epitaxial growth, and the graded silicon-doped n-type nitride semiconductor layer 107 has a film thickness of 100 ⁇ to 20,000. A, wherein the silicon doping concentration is changed from 1 ⁇ 10 17 cm -3 to 5 ⁇ 10 18 cm -3 to 1 ⁇ 10 18 cm -3 - 5 ⁇ 10 19 cm -3 .
  • the gradient silicon doping n-type nitride semiconductor layer has a film thickness of 4000 ⁇ to 6000 ⁇ , and the silicon doping concentration is changed from 1 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 19 cm ⁇ 3 by a gradual change.
  • the silicon-doped n-type nitride semiconductor layer repairs the n-type ohmic contact buffer layer 102 which causes surface defects due to ion implantation, thereby maintaining the lattice quality of the gallium nitride-based semiconductor layer after the secondary epitaxy.
  • Step 3 epitaxially growing a light-emitting epitaxial layer on the n-type ohmic contact buffer layer 107 to form an epitaxial structure.
  • the luminescent epitaxial layer includes at least: The n-type GaN-based semiconductor layer 103, the active layer 104, and the p-type semiconductor layer 106.
  • the film thickness of the n-type GaN-based semiconductor layer 103 is 20,000 ⁇ .
  • the active layer 104 is a multi-quantum well structure with an InGaN layer as a well layer and a GaN layer as a barrier layer, wherein the well layer has a film thickness of 18 ⁇ to 30 ⁇ , and the film thickness of the barrier layer is 80 ⁇ to 200 ⁇ ;
  • the p-type GaN-based semiconductor layer 106 has a film thickness of 1000 ⁇ to 3000 ⁇ ; and can be in the p-type GaN-based semiconductor layer 106 and the active layer 104 is interposed between a Mg-doped aluminum indium gallium nitride layer as an electron blocking layer 105 having a film thickness of 100 ⁇ to 600 ⁇ .
  • Step 4 Defining the size of the chip, performing mesa etching on the completed epitaxial wafer by a dry etching process to complete chip-level separation of the epitaxial wafer.
  • the etching depth is at least transmitted through the epitaxial film to the epitaxial growth substrate 101 Surface.
  • Step 5 providing a conductive substrate 203 to connect the light emitting epitaxial layer to the conductive substrate 203.
  • a metal bonding layer 202 is formed on the conductive substrate 203, and the light emitting epitaxial layer and the conductive substrate 203 are connected by a metal bonding process.
  • it can be in p type A P-plane mirror and an ohmic electrode layer 201 are formed on the GaN-based semiconductor layer 106, and a p-plane metal diffusion barrier layer is added to the metal bonding layer 202.
  • Step 6 Peel the growth substrate 101.
  • the epitaxial growth substrate 101 is removed by epitaxy, grinding or wet etching, and the substrate is epitaxially grown and The LED films are separated and the LED film remains on the inversion substrate to expose the surface of the n-type ohmic contact buffer layer 102.
  • Step 7 forming a lower electrode metal layer 205 on the conductive substrate, and forming an n-side electrode metal layer on the surface of the n-type ohmic contact buffer layer 204. Complete the fabrication of the vertical structure LED.
  • the process of the present embodiment ie, the buffer layer is obtained by implanting silicon ions to obtain high n-type doping
  • the conventional process That is, the buffer layer was not doped, and two kinds of samples were prepared, and the light-emitting output power, forward voltage, and aging characteristics were evaluated.
  • the thick layers of the respective semiconductor layers were set in Table 2.
  • Table 2 Semiconductor layer Film thickness ⁇ and structure of each layer of the process of the present invention Film thickness ( and structure of various layers of the traditional process Buffer layer 102 N-type doped ohmic contact buffer 600 Undoped buffer layer 600 Gradient silicon doped N-type nitride semiconductor layer 107 5000 no N-type GaN-based semiconductor layer 103 25000 25000 Active layer 104 GaN(140)/InGaN(25) X10 cycle (last GaN layer) GaN(140)/InGaN(25) X10 cycle (last GaN layer) Electronic barrier layer 105 600 600 P-type GaN-based semiconductor layer 106 2000 2000 2000 2000 2000
  • Figure 8 Figure 9, and Figure 10 show its evaluation results.
  • Figure 8 A graph of the forward operating voltage of each sample of this example is shown. As can be seen from the figure, the forward working voltage of the nitride vertical structure light emitting diode sample of the present embodiment is lower than that of the conventional nitride vertical structure light emitting diode sample.
  • Fig. 9 is a graph showing the forward working voltage of each sample of the present embodiment after aging. As can be seen from the figure, the reliability of the forward working voltage of the nitride vertical structure light-emitting diode sample of the present embodiment is significantly better than that of the conventional nitride vertical structure light-emitting diode sample.
  • Fig. 10 is a graph showing the luminous output power of each sample of the present embodiment.
  • the nitride vertical structure light emitting diode sample of the present embodiment has a higher light output output than the conventional nitride vertical structure light emitting diode sample.

Abstract

本发明公开了一种具有掺杂n型欧姆接触缓冲层的发光二极管其及制作方法。在本发明中，在发光外延层的n侧上形成一电子浓度达1×1018cm-3以上高掺杂n型欧姆接触缓冲层，当去除生长衬底时，露出表面的n型欧姆接触缓冲层，其为低能隙、非氮极性面n型GaN基材料，n型欧姆接触电极制作在该n型欧姆接触缓冲层上，沿用Ti/Al欧姆接触电极，可克服现有垂直式氮化镓基垂直发光二极管存在的因氮面n型GaN基半导体层上欧姆接触电极易受温度裂化导致薄膜GaN基发光器件电压可靠性问题。

Description

发光二极管及制作方法 相关申请
本申请主张如下优先权：中国发明专利申请号 CN201210003578.3 ，题为'具有高导通 n 型欧姆接触的发光二极管及制作方法'，于 2012 年 1 月 9 日提交；中国发明专利申请号 CN 201210003576.4 ，题为'具有良好 n 型欧姆接触的发光二极管及制作方法'，于 2012 年 1 月 9 日提交。上述申请的全部内容通过引用结合在本申请中。
技术领域
本发明涉及一种发光二极管其及制作方法，特别是涉及一种具有高掺杂 n 型欧姆接触缓冲层的发光二极管及其制造方法。
背景技术
近年来，为了提高氮化镓基发光二极管的发光效率，发展了衬底转移技术，例如在蓝宝石衬底上通过 MOCVD 沉积 GaN 基薄膜，然后把 GaN 基薄膜通过晶圆键合技术或电镀技术黏结到半导体或金属基板上，再把蓝宝石衬底用激光剥离方法去除；或者在 SiC 或者 Si 衬底上沉积 GaN 基薄膜，然后把 GaN 基薄膜通过晶圆键合技术或电镀技术黏结到半导体或金属基板上，再把 SiC 或者 Si 衬底用化学腐蚀方法去除。这样一方面可以通过在外延薄膜和基板之间加一个反射层，另一方面由于氮极性面的 GaN 上容易通过光化学腐蚀方法获取粗糙的出光面，以上两方面使薄膜 GaN 芯片具有更高的出光效率，同时转移后的基板具有优良的导热特性，因此转移到散热基板上的 GaN 基薄膜芯片在大电流应用上具有较大的优势。
然而，去除生长衬底后暴露的 GaN 薄膜表面一般为氮极性面，而氮极性面的欧姆接触特性与镓极性面不同，例如镓极性面的 N 型 GaN 的欧姆接触电极一般采用 Ti/Al 欧姆接触电极，而氮极性面的 N 型 GaN 的接触电极若仍然采用 Ti/Al 电极，则在初始时间， Ti/Al 与 N 型 GaN 呈现出比镓极性面更优的欧姆接触特性，但经过 150 度左右的温度后，其接触特性即劣化为肖特基接触，表现为其正向工作电压升高，严重制约了薄膜 GaN 芯片的光效。关于其形成原因的探讨较具有代表性的有： Hyunsoo Kim 等人 (APPLIED PHYSICS LETTERS 93, 192106, 2008) 认为是氮空位与表面镓空位以及 C 、 O 原子反应导致表面氮空位减少； Ho Won Jang 等人 (APPLIED PHYSICS LETTERS 94, 182108, 2009) 认为是体内的氮原子向表面扩散补偿了氮空位导致表面氮空位减少。目前为止，此两个研究团队亦未提出在氮极性面上制作 N 型 GaN 欧姆接触电极的有效方法。 Philips Lumileds Lighting Company 推出的薄膜倒装 (TFFC) 发光二极管，其 N 型欧姆接触电极仍然制作在镓极性面 N 型 GaN 上，即可以继续沿用 Ti/Al 欧姆接触电极，因此 TFFC 的一个显着优点是可以完全避开上述讨论氮极性面的问题，但因薄膜上 P 、 N 电极需要分别黏结在基板上对应的正负电极区域，因此对芯片倒装技术要求较高；另外为了避免激光剥离蓝宝石衬底时薄膜破裂，需要保证薄膜表面在激光剥离蓝宝石瞬间承受均匀的冲击力，因此在激光剥离蓝宝石衬底前需要在薄膜与倒装粘结基板之间填充介质，填充的一致性难控制，器件成品率可能因此受影响。
发明内容
本发明提出了一种具有掺杂 n 型欧姆接触缓冲层的发光二极管其及制作方法，以克服现有垂直式氮化镓基垂直发光二极管存在的因氮面 n 型 GaN 基半导体层上欧姆接触电极易受温度裂化导致薄膜 GaN 基发光器件电压可靠性问题。
根据本发明的第一方面，一种发光二极管外延结构的制造方法，包括以下步骤：提供一生长衬底；在生长衬底上形成一掺杂 n 型欧姆接触缓冲层，其电子浓度大于或等于 1×1018cm-3 ；在 n 型欧姆接触缓冲层上外延生长发光外延层，其至下而上至少包括： n 型半导体层 、活性层、 p 型半导体层。
更具体地，所述 n 型欧姆接触缓冲层通过外延生长形成，材料为 AlcIndGa1-c-dN （其中 0 ≦ c<1 ， 0 ≦ d<1 ， c+d<1 ），其能隙小于或等于 3.4eV ，厚度为 10 埃～ 5000 埃。在本发明的一些优选实施例中，为了达到较高的电子浓度，可以通过离子注入法注入离子形成高掺杂，其掺杂浓度大于或等于 1×1020cm-3 。
根据本发明的第二个方面，一种发光二极管外延结构，包括：生长衬底；掺杂 n 型欧姆接触缓冲层，位于该生长衬底之上，其电子浓度大于或等于 1×1018cm-3 ；发光外延层，形成于 n 型欧姆接触缓冲层之上，其自下而上包含 n 型半导体层、活性层、 p 型半导体层。
具体地，所述 n 型欧姆接触缓冲层为硅掺杂氮化物，其掺杂浓度大于或等于 1×1018cm-3 ，由 AlcIndGa1-c-dN 构成（其中 0 ≦ c<1 ， 0 ≦ d<1 ， c+d<1 ），其能隙小于或等于 3.4eV ，厚度为 10 埃～ 5000 埃。在本发明的一些优选实施例中，为了达到较高的电子浓度，可以通过离子注入法注入离子形成高掺杂，其掺杂浓度大于或等于 1×1020cm-3 。
进一步地，所述发光二极管外延结构还可以包括一渐变式硅掺杂 n 型氮化物半导体层，其位于 n 型欧姆接触缓冲层与发光外延层之间。
根据本发明的第三个方面，一种发光二极管芯片的制作方法，包括以下步骤：提供一生长衬底；在生长衬底上形成一掺杂 n 型欧姆接触缓冲层，其电子浓度大于或等于 1×1018cm-3 ；在 n 型欧姆接触缓冲层上外延生长发光外延层，其至下而上至少包括： n 型半导体层 、活性层、 p 型半导体层；提供一导电基板，将发光外延层与导电基板连结；剥离生长衬底，露出 n 型欧姆接触缓冲层表面；在导电基板上形成 p 电极，在 n 型欧姆接触缓冲层表面之上形成 n 电极。
具体地，所述 n 型欧姆接触缓冲层通过外延生长形成，材料为 AlcIndGa1-c-dN （其中 0 ≦ c<1 ， 0 ≦ d<1 ， c+d<1 ），其掺杂浓度大于或等于 1×1018cm-3 ，能隙小于或等于 3.4eV ，厚度为 10 埃～ 5000 埃。在本发明的一些优选实施例中，为了达到较高的电子浓度，可以通过离子注入法注入离子形成高掺杂，其掺杂浓度大于或等于 1×1020cm-3 。
根据本发明的第四个方面，一种发光二极管芯片，包括：导电基板，其具有正、反两表面；发光外延层，位于导电基板正表面之上，其至上而下包含 n 型半导体层，活性层， p 型半导体层 ; 掺杂 n 型欧姆接触缓冲层，位于 n 型半导体层之上，其电子浓度大于或等于 1×1018cm-3 ；第二电极，位于 n 型欧姆接触缓冲层之上；第一电极，位于导电基板反表面之上。
具体地，所述 n 型欧姆接触缓冲层为硅掺杂氮化物，其掺杂浓度大于或等于 1×1018cm-3 ，由 AlcIndGa1-c-dN 构成（其中 0 ≦ c<1 ， 0 ≦ d<1 ， c+d<1 ），其能隙小于或等于 3.4eV ，厚度为 10 埃～ 5000 埃。在本发明的一些优选实施例中，为了达到较高的电子浓度，可以通过离子注入法注入离子形成高掺杂，其掺杂浓度大于或等于 1×1020cm-3 。
在 AlcIndGa1-c-dN 层中，通过掺入高浓度的 n 型离子，使得其与生长衬底接触的表面呈非氮极性。在氮化镓基发光二极管中，将发外延层外延生长在高电子浓度的 n 型欧姆接触缓冲层上，当去除生长衬底时，露出表面的 n 型欧姆接触缓冲层，其为低能隙、非氮极性面 n 型 GaN 基材料， n 型欧姆接触电极制作在该 n 型欧姆接触缓冲层上，沿用 Ti/Al 欧姆接触电极，可以避开氮极性面欧姆接触的问题，且可保证薄膜 GaN 发光器件具有较低的工作电压。
进一步地， n 型欧姆接触缓冲层作为初始的成核层，且高硅掺杂、低温成长，故其晶格松散、原子间的键结强度较弱，因此利于激光剥离工艺或湿法腐蚀工艺，明显地减少因激光剥离工艺在生长衬底和 LED 薄膜界面产生的瞬态高温和机械分离过程中产生的巨大应力和冲击力，不会增加 LED 外延层的结构缺陷，对内量子效率的负面影响大大的减低。
在本发明的一些实施例中，当 n 型欧姆接触缓冲层的电子浓度达到 1×1020cm-3 ，其掺杂浓度需至少达到 1×1020cm-3 ，一般仅通过外延生长，不容易形成如此高的杂质浓度，本发明采用离子注入法可以简单地实现该杂质浓度或更高。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
虽然在下文中将结合一些示例性实施及使用方法来描述本发明，但本领 域技术人员应当理解，并不旨在将本发明限制于这些实施例。反之，旨在覆盖包含在所附的权利要求书所定义的本发明的精神与范围内的所有替代品、修正及等效物。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例一起用于解释本发明，并不构成对本发明的限制。此外，附图数据是描述概要，不是按比例绘制。
图 1 是本发明实施例 1 之一种具有掺杂 n 型欧姆接触缓冲层的发光二极管外延结构示意图。
图 2 是根据图 1 所示的发光二极管外延结构制备而成的发光二极管芯片的剖面示意图。
图 3 是本发明实施例 1 的正向工作电压的曲线图。
图 4 是本发明实施例 1 的老化后的正向工作电压的曲线图。
图 5 是本发明实施例 1 的发光输出功率的曲线图。
图 6 是本发明实施例 2 之一种具有掺杂 n 型欧姆接触缓冲层的发光二极管外延结构示意图。
图 7 是根据图 6 所示的发光二极管外延结构制备而成的发光二极管芯片的剖面示意图。
图 8 是本发明实施例 2 的正向工作电压的曲线图。
图 9 是本发明实施例 2 的老化后的正向工作电压的曲线图。
图 10 是本发明实施例 2 的发光输出功率的曲线图。
主要组件符号说明：
101. 外延生长衬底； 102. n 型欧姆接触缓冲层； 103. n 型 GaN 层； 104 . 活性层； 105. 电子阻挡层； 106. p 型 GaN 层； 107. 渐变式硅掺杂 n 型氮化物半导体层； 201. p 面反光镜和欧姆电极层； 202. p 面金属扩散阻挡层和键合层； 203. 导电基板； 204. 第二电极金属层； 205. 第一电极金属层。
具体实施方式
下面结合附图和优选的具体实施例对本发明做进一步说明。在具体的器件设计和制造中，本发明提出的 LED 结构将根据应用领域和工艺制程实施的需要，可对其部分结构和尺寸在一定范围内做出修改，对材料的选取进行变通。
实施例一
图 1 是实施 1 之一种发光二极管外延结构示意图。
如图 1 所示，一种发光二极管外延结构，包括：外延生长衬底 101 ， n 型欧姆接触缓冲层 102 形成于外延生长衬底 101 之上， n 型 GaN 基半导体层 103 形成于 n 型欧姆接触缓冲层 102 之上，活性层 104 形成于 n 型 GaN 基半导体层 103 之上， p 型 GaN 基半导体层 106 形成于活性层 104 之上。
其中，外延生长衬底 101 的选取包括但不限于蓝宝石、氮化铝、氮化镓、硅、碳化硅，其晶向包括但不限于 0001 等极化、半极化和非极化方向，其表面结构可为平面结构或经特别处理的图形化表面。
n 型欧姆接触缓冲层 102 由特定组成、能隙小于或等于 3.4eV 的氮化铝铟镓 AlcIndGa1-c-dN 层所构成其 0 ≦ c<1 ， 0 ≦ d<1 ， c+d<1 ，膜厚介于 10 埃～ 5000 埃之间。在 n 型欧姆接触缓冲层 102 中掺有硅杂质，硅的浓度大于或等于 1×1018cm-3 ，使得 n 型欧姆接触缓冲层 102 的电子浓度大于或等于 1×1018cm-3 ，其外表面为非氮极性面。在允许的范围内， n 型欧姆接触缓冲层 102 的电子浓度的越高，对于后续形成垂直结构的发光二极管芯片时，越有利于在该 n 型欧姆接触缓冲层 102 外侧表面制作电极结构。
n 型 GaN 基半导体层 103 的膜厚为 20000 埃～ 40000 埃；活性层 104 为多量子阱结构，以 InGaN 层作为阱层、 GaN 层作为势垒层，其中阱层的膜厚为 18 埃～ 30 埃，势垒层的膜厚为 80 埃～ 200 埃； p 型 GaN 基半导体层 106 的膜厚为 1000 埃～ 3000 埃间；可在 p 型 GaN 基半导体层 106 与活性层 104 间插入一由掺杂了 Mg 的氮化铝铟镓层作为电子阻挡层 105 ，其膜厚为 100 埃～ 600 埃。
图 2 为根据图 1 所示的发光二极管外延结构制作而成的垂直式发光二极管芯片。
如图 2 所示，具有良好 n 型欧姆接触的发光二极管芯片，包括：导电基板 203 ；发光外延层通过金属键合层 202 倒装焊接在导电基板的正面上，发光外延层为图 1 中所示的发光二极管外延结构去除生长衬底后的结构，其至上而下为 p 型 GaN 基半导体层、电子阻挡层 105 、活性层 104 、 n 型 GaN 基半导体层 103 、 n 型欧姆接触缓冲层 102 ；第二电极金属层 204 形成于 n 型欧姆接触缓冲层 102 之上，第一电极金属层 205 形成于导电基板 203 的背面上。为了提高取光效率，可在 p 型 GaN 基半导体层与导电基板之间加入 p 面反光镜和欧姆电极层 201 ，在金属键合层 202 中加入 p 面金属扩散阻挡层。由于第二电极金属层 204 制作在高掺杂的 n 型欧姆接触缓冲层 102 上，避免了传统的垂直式氮化镓基发光二极管芯片中，在 n 型 GaN 基半导体层的氮极性面上制作的 Ti/Al 欧姆接触电极遇 150℃ 后其接触特性即劣化为肖特基接触的问题。
前述图 1 所示的发光二极管的外延结构和图 2 所示的发光二极管芯片通过下面工艺完成。
步骤一：提供外延生长衬底 101 ，在生长衬底的表面上低温外延生长一掺杂的 n 型欧姆接触缓冲层 102 ，其电子浓度为大于或等于 1×1018cm-3 ，能隙小于或等于 3.4eV 。 n 型欧姆接触缓冲层 102 可选用掺硅的 AlcIndGa1-c-dN ，（ 0 ≦ c<1 ， 0 ≦ d<1 ， c+d<1 ），厚度为 10 埃～ 5000 埃，其硅的掺杂浓度大于或等于 1×10 18cm-3 。为了取得更佳的 n 型欧姆接触，可适当提高电子浓度，如其浓度可高于或等于 1×1020cm-3 。当 n 型欧姆接触缓冲层 102 选择 GaN ，其生长温度可为 500~600℃ 。
步骤二：在 n 型欧姆接触缓冲层 102 上外延生长发光外延层，形成外延结构。发光外延层至下而上至少包括： n 型 GaN 基半导体层 103 、活性层 104 、 p 型半导体层 106 。 n 型 GaN 基半导体层 103 的膜厚为 20000 埃～ 40000 埃；活性层 104 为多量子阱结构，以 InGaN 层作为阱层、 GaN 层作为势垒层，其中阱层的膜厚为 18 埃～ 30 埃，势垒层的膜厚为 80 埃～ 200 埃； p 型 GaN 基半导体层 106 的膜厚为 1000 埃～ 3000 埃间；为了提高发光层的内部效应，可在 p 型 GaN 基半导体层 106 与活性层 104 间插入一由掺杂了 Mg 的氮化铝铟镓层作为电子阻挡层 105 ，其膜厚为 100 埃～ 600 埃。
步骤三：定义芯片的尺寸，通过干法蚀刻工艺对上述完成外延片进行台面蚀刻，完成外延片的芯片级分离。蚀刻深度至少透过外延层薄膜，至外延生长衬底 101 表面。
步骤四：提供一导电基板 203 ，将发光外延层与导电基板 203 连结。分别在 p 型 GaN 基半导体层 106 、导电基板 203 上形成金属键合层 202 ，采用金属键合工艺将发光外延层与导电基板 203 连结在一起。为了提高芯片的取光效率，可在 p 型 GaN 基半导体层 106 上制作 p 面反光镜和欧姆电极层 201 ，在金属键合层 202 中加入 p 面金属扩散阻挡层。
步骤五：剥离生长衬底 101 。采用剥离、研磨或湿法腐蚀，将外延生长衬底 101 去除，外延生长衬底和 LED 薄膜分开， LED 薄膜留在反转基板上，露出 n 型欧姆接触缓冲层 102 表面。
步骤六：在导电基板上形成下电极金属层 205 ，在 n 型欧姆接触缓冲层表面之上形成 n 面电极金属层 204 ，完成垂直结构 LED 的制作。
在本实施例中，针对本实施例的工艺（缓冲层具有 n 型掺杂）、传统的工艺 ( 即缓冲层未掺杂 ) ，制作 2 种样品，分别评价其发光输出功率、正向电压与老化特性。其中，各半导体层的厚层按表 1 进行设定。
表一
半导体层 本发明工艺的各层
膜厚埃（ À ）及结构		 传统工艺的各层
膜厚埃（ À ）及结构
缓冲层 102 n 型掺杂欧姆接触缓冲 600 未掺杂缓冲层
600
n 型 GaN 基半导体层 103 25000 25000
活性层 104 GaN(140)/InGaN(25)
X10 周期 ( 最后是 GaN 层 )		 GaN(140)/InGaN(25)
X10 周期 ( 最后是 GaN 层 )
电子阻挡层 105 600 600
p 型 GaN 基半导体层 106 2000 2000
图 3 、图 4 、图 5 示出了它的评价结果。
如图 3 展示了本实施例的各样品的正向工作电压的曲线图。从图中可看出，本实施例的氮化物垂直结构发光二极管样品的正向工作电压低于传统工艺的氮化物垂直结构发光二极管样品。
如图 4 展示了本实施例的各样品的老化后的正向工作电压的曲线图。 从图中可看出，本实施例的氮化物垂直结构发光二极管样品的老化后的正向工作电压的可靠性明显优于传统工艺的氮化物垂直结构发光二极管样品。
如图 5 展示了本实施例的各样品的发光输出功率的曲线图。 从图中可看出，本实施例的氮化物垂直结构发光二极管样品的发光输出功率高于传统工艺的氮化物垂直结构发光二极管样品。
实施例二
图 6 是为实施 2 之一种发光二极管外延结构示意图，区别以实施例 1 ，本实施例的 n 型欧姆接触缓冲层 102 为了获得更高的电子浓度，通过采用离子注入法在生长 n 型欧姆接触缓冲层后注入离子，使共掺杂浓度可以达到 1×1020cm-3 以上，然后通过二次外延生长法继续生长其他半导体材料层。为了保证二次外延的质量，在 n 型欧姆接触缓冲层 102 上先生长一层渐变式硅掺杂 n 型氮化物半导体层，下面结合附图对其具体结构进行详细说明。
如图 6 所示，一种发光二极管外延结构，包括：外延生长衬底 101 ， n 型欧姆接触缓冲层 102 形成于外延生长衬底 101 之上，渐变式硅掺杂 n 型氮化物半导体层 107 通过二次外延生长形成于 n 型欧姆接触缓冲层 102 之上， n 型 GaN 基半导体层 103 形成于渐变式硅掺杂 n 型氮化物半导体层 107 之上，活性层 104 形成于 n 型 GaN 基半导体层 103 之上， p 型 GaN 基半导体层 106 形成于活性层 104 之上。
其中，外延生长衬底 101 可按照实施例一进行选取，在此不再重复表述。
n 型欧姆接触缓冲层 102 由特定组成、能隙小于或等于 3.4eV 的氮化铝铟镓 AlcIndGa1-c-dN 层所构成其 0 ≦ c<1 ， 0 ≦ d<1 ， c+d<1 ；膜厚介于 10 埃～ 5000 埃之间。在 n 型欧姆接触缓冲层 102 中通过离子注入法掺硅杂质，硅的浓度大于或等于 1×1020cm-3 ，使得 n 型欧姆接触缓冲层 102 的电子浓度大于或等于 1×1020cm-3 ，其外表面呈非氮极性。
渐变式硅掺杂 n 型氮化物半导体层 107 的膜厚为 100 埃～ 20000 埃，由二次成长外延所形成，其中硅掺杂浓度由 1×1017cm-3 -5×1018cm-3 渐变至 1×1018cm-3 -5×1019cm-3 ，本实施例优先选择渐变式硅掺杂 n 型氮化物半导体层膜厚 4000 埃～ 6000 埃，硅掺杂浓度由 1×1017cm-3 渐变至 1×1019cm-3 ，借由渐变式硅掺杂的 n 型氮化物半导体层修复改善因离子注入造成表层缺陷的 n 型欧姆接触缓冲层 102 ，进而维持二次外延后氮化镓基半导体层的晶格质量。
n 型 GaN 基半导体层 103 的膜厚为 20000 埃～ 40000 埃；活性层 104 为多量子阱结构，以 InGaN 层作为阱层、 GaN 层作为势垒层，其中阱层的膜厚为 18 埃～ 30 埃，势垒层的膜厚为 80 埃～ 200 埃； p 型 GaN 基半导体层 106 的膜厚为 1000 埃～ 3000 埃间；可在 p 型 GaN 基半导体层 107 与活性层 104 间插入一由掺杂了 Mg 的氮化铝铟镓层作为电子阻挡层 105 ，其膜厚为 100 埃～ 600 埃。
图 7 为根据图 6 所示的发光二极管外延结构制作而成的垂直式发光二极管芯片。
如图 7 所示，具有 n 型欧姆接触的发光二极管芯片，包括：导电基板 203 ；发光外延层通过金属键合层 202 倒装焊接在导电基板的正面上，发光外延层为图 6 中所示的发光二极管外延结构去除生长衬底后的结构，其至上而下为 p 型 GaN 基半导体层 106 、电子阻挡层 105 、活性层 104 、 n 型 GaN 基半导体层 103 、渐变式硅掺杂 n 型氮化物半导体层 107 、 n 型欧姆接触缓冲层 102 ； n 面电极金属层 204 形成于 n 型欧姆接触缓冲层 102 之上，下电极金属层 205 形成于导电基板 203 的背面上。为了提高取光效率，可在 p 型 GaN 基半导体层与导电基板之间加入 p 面反光镜和欧姆电极层 201 ，在金属键合层 202 中加入 p 面金属扩散阻挡层。由于 n 面电极金属层 204 通过掺杂的 n 型欧姆接触缓冲层 102 与 n 型 n 型 GaN 基半导体层 104 连接，避免了传统的垂直式氮化镓基发光二极管芯片中，在 n 型 GaN 基半导体层的氮性面上制作的 Ti/Al 欧姆接触电极遇 150℃ 后其接触特性即劣化为肖特基接触的问题。
前述图 6 所示的发光二极管外延结构和图 7 所示的发光二极管芯片可以通过下面工艺完成。
步骤一，提供外延生长衬底 101 ，在生长衬底的表面上低温外延生长一掺杂的 n 型欧姆接触缓冲层 102 ，其电子浓度为大于或等于 1×1020cm-3 ，能隙小于或等于 3.4eV 。 n 型欧姆接触缓冲层 102 可选用掺硅的 AlcIndGa1-c-dN （ 0 ≦ c<1 ， 0 ≦ d<1 ， c+d<1 ），采用离子注入法注入硅离子，其硅的掺杂浓度为大于或等于 1×1020cm-3 ，厚度为 10 埃～ 5000 埃。如果 n 型欧姆接触缓冲层 102 选择 GaN ，其生长温度可为 500~600℃ 。
步骤二：在 n 型欧姆接触缓冲层 102 上通过二次外延生长渐变式硅掺杂 n 型氮化物半导体层 107 ，渐变式硅掺杂 n 型氮化物半导体层 107 的膜厚为 100 埃～ 20000 埃，其中硅掺杂浓度由 1×1017cm-3 -5×1018cm-3 渐变至 1×1018cm-3 -5×1019cm-3 。本实施例优先选择渐变式硅掺杂 n 型氮化物半导体层膜厚 4000 埃～ 6000 埃，硅掺杂浓度由 1×1017cm-3 渐变至 1×1019cm-3 ，借由渐变式硅掺杂的 n 型氮化物半导体层修复改善因离子注入造成表层缺陷的 n 型欧姆接触缓冲层 102 ，进而维持二次外延后氮化镓基半导体层的晶格质量。
步骤三：在 n 型欧姆接触缓冲层 107 上外延生长发光外延层，形成外延结构。发光外延层至下而上至少包括： n 型 GaN 基半导体层 103 、活性层 104 、 p 型半导体层 106 。 n 型 GaN 基半导体层 103 的膜厚为 20000 埃～ 40000 埃；活性层 104 为多量子阱结构，以 InGaN 层作为阱层、 GaN 层作为势垒层，其中阱层的膜厚为 18 埃～ 30 埃，势垒层的膜厚为 80 埃～ 200 埃； p 型 GaN 基半导体层 106 的膜厚为 1000 埃～ 3000 埃间；可在 p 型 GaN 基半导体层 106 与活性层 104 间插入一由掺杂了 Mg 的氮化铝铟镓层作为电子阻挡层 105 ，其膜厚为 100 埃～ 600 埃。
步骤四：定义芯片的尺寸，通过干法蚀刻工艺对上述完成外延片进行台面蚀刻，完成外延片的芯片级分离。蚀刻深度至少透过外延层薄膜，至外延生长衬底 101 表面。
步骤五：提供一导电基板 203 ，将发光外延层与导电基板 203 连结。分别在 p 型 GaN 基半导体层 107 、导电基板 203 上形成金属键合层 202 ，采用金属键合工艺将发光外延层与导电基板 203 连结在一起。为了提高芯片的取光效率，可在 p 型 GaN 基半导体层 106 上制作 P- 面反光镜和欧姆电极层 201 ，在金属键合层 202 中加入 p 面金属扩散阻挡层。
步骤六：剥离生长衬底 101 。采用剥离、研磨或湿法腐蚀，将外延生长衬底 101 去除，外延生长衬底和 LED 薄膜分开， LED 薄膜留在反转基板上，露出 n 型欧姆接触缓冲层 102 表面。
步骤七：在导电基板上形成下电极金属层 205 ，在 n 型欧姆接触缓冲层表面之上形成 n 面电极金属层 204 ，完成垂直结构 LED 的制作。
在本实施例中，针对本实施例的工艺（即缓冲层通过注入硅离子获得高 n 型掺杂）、传统的工艺 ( 即缓冲层未掺杂 ) ，制作 2 种样品，分别评价其发光输出功率、正向电压与老化特性。其中，各半导体层的厚层按表 2 进行设定。
表 2
半导体层 本发明工艺的各层
膜厚埃（ À ）及结构		 传统工艺的各层
膜厚埃（ À ）及结构
缓冲层 102 n 型掺杂欧姆接触缓冲 600 未掺杂缓冲层
600
渐变式硅掺杂 N 型氮化物半导体层 107 5000 无
n 型 GaN 基半导体层 103 25000 25000
活性层 104 GaN(140)/InGaN(25)
X10 周期 ( 最后是 GaN 层 )		 GaN(140)/InGaN(25)
X10 周期 ( 最后是 GaN 层 )
电子阻挡层 105 600 600
p 型 GaN 基半导体层 106 2000 2000
图 8 、图 9 、图 10 示出了它的评价结果。
如图 8 展示了本实施例的各样品的正向工作电压的曲线图。从图中可看出，本实施例的氮化物垂直结构发光二极管样品的正向工作电压低于传统工艺的氮化物垂直结构发光二极管样品。
如图 9 展示了本实施例的各样品的老化后的正向工作电压的曲线图。 从图中可看出，本实施例的氮化物垂直结构发光二极管样品的老化后的正向工作电压的可靠性明显优于传统工艺的氮化物垂直结构发光二极管样品。
如图 10 展示了本实施例的各样品的发光输出功率的曲线图。 从图中可看出，本实施例的氮化物垂直结构发光二极管样品的发光输出功率高于传统工艺的氮化物垂直结构发光二极管样品。

Claims (22)

  1. 发光二极管外延结构的制造方法，包括以下步骤：
    提供一生长衬底；
    在生长衬底上形成一掺杂 n 型欧姆接触缓冲层，其电子浓度大于或等于 1×1018cm-3 ；
    在 n 型欧姆接触缓冲层上外延生长发光外延层，其至下而上至少包括： n 型半导体层 、活性层、 p 型半导体层。
  2. 根据权利要求 1 所述的发光二极管外延结构的制造方法，其特征在于：所述 n 型欧姆接触缓冲层通过外延生长形成，其材料为
    AlcIndGa1-c-dN ，其中 0 ≦ c<1 ， 0 ≦ d<1 ， c+d<1 。
  3. 根据权利要求 1 所述的发光二极管外延结构的制造方法，其特征在于：通过离子注入法注入离子形成所述掺杂 n 型欧姆接触缓冲层，其掺杂浓度大于或等于 1×1020cm-3 。
  4. 根据权利要求 1 所述的发光二极管外延结构的制造方法，其特征在于：所述 n 型欧姆接触缓冲层的能隙小于或等于 3.4eV 。
  5. 根据权利要求 1 所述的发光二极管外延结构的制造方法，其特征在于：所述 n 型欧姆接触缓冲层的厚度为 10 埃～ 5000 埃。
  6. 发光二极管外延结构，包括：
    一生长衬底；
    一掺杂 n 型欧姆接触缓冲层，位于该生长衬底之上，其电子浓度大于或等于 1×1018cm-3 ；
    一发光外延层，形成于 n 型欧姆接触缓冲层之上，其自下而上包含 n 型半导体层、活性层、 P 型半导体层。
  7. 根据权利要求 6 所述的发光二极管外延结构，其特征在于：所述 n 型欧姆接触缓冲层由 AlcIndGa1-c-dN 构成，其中 0 ≦ c<1 ， 0 ≦ d<1 ， c+d<1 。
  8. 根据权利要求 6 所述的发光二极管外延结构，其特征在于：所述 n 型欧姆接触缓冲层的能隙小于或等于 3.4eV 。
  9. 根据权利要求 6 所述的发光二极管外延结构，其特征在于：所述 n 型欧姆接触缓冲层的厚度为 10 埃～ 5000 埃。
  10. 根据权利要求 6 所述的发光二极管外延结构，其特征在于：所述 n 型欧姆接触缓冲层为硅掺杂氮化物，其掺杂浓度大于或等于
    　　 　　　　1×1018cm-3 。
  11. 根据权利要求 6 所述的发光二极管外延结构，其特征在于：所述 n 型欧姆接触缓冲层为硅掺杂氮化物，其掺杂浓度大于或等于
    1×1020cm-3 。
  12. 根据权利要求 11 所述的发光二极管外延结构，其特征在于：还包括渐变式硅掺杂 n 型氮化物半导体层，其位于 n 型欧姆接触缓冲层与发光外延层之间。
  13. 发光二极管芯片的制作方法，包括以下步骤：
    提供一生长衬底；
    在生长衬底上形成一掺杂 n 型欧姆接触缓冲层，其电子浓度大于或等于 　　　1×1018cm-3 ；
    在 n 型欧姆接触缓冲层上外延生长发光外延层，其至下而上至少包括： n 型半导体层 、活性层、 p 型半导体层；
    提供一导电基板，将发光外延层与导电基板连结；
    剥离生长衬底，露出 n 型欧姆接触缓冲层表面；
    在导电基板上形成第一电极，在 n 型欧姆接触缓冲层表面之上形成第二电极。
  14. 根据权利要求 13 所述的发光二极管芯片的制作方法，其特征在于：所述 n 型欧姆接触缓冲层通过外延生长形成，其材料为
    AlcIndGa1-c-dN ，其中 0 ≦ c<1 ， 0 ≦ d<1 ， c+d<1 。
  15. 根据权利要求 13 所述的发光二极管芯片的制造方法，其特征在于：所述 n 型欧姆接触缓冲层的能隙小于或等于 3.4eV 。
  16. 根据权利要求 13 所述的发光二极管芯片的制造方法，其特征在于：通过离子注入法注入离子形成所述掺杂 n 型欧姆接触缓冲层，其掺杂浓度大于或等于 1×1020cm-3 。
  17. 发光二极管芯片，包括：
    一导电基板，其具有正、反两表面；
    一发光外延层，位于导电基板正表面之上，其至上而下包含 n 型半导体层，活性层， p 型半导体层 ;
    一掺杂 n 型欧姆接触缓冲层，位于 n 型半导体层之上，其电子浓度大于或等于 1×1018cm-3 ；
    一第一电极，位于导电基板反表面之上；
    一第二电极，位于 n 型欧姆接触缓冲层之上。
  18. 根据权利要求 17 所述的发光二极管芯片，其特征在于：所述 n 型欧姆接触缓冲层由 AlcIndGa1-c-dN 构成，其中 0 ≦ c<1 ， 0 ≦ d<1 ， c+d<1 。
  19. 根据权利要求 17 所述的发光二极管芯片，其特征在于：所述 n 型欧姆接触缓冲层的能隙小于或等于 3.4eV 。
  20. 根据权利要求 17 所述的发光二极管外芯片，其特征在于：所述 n 型欧姆接触缓冲层的厚度为 10 埃～ 5000 埃。
  21. 根据权利要求 17 所述的发光二极管芯片，其特征在于：所述 n 型欧姆接触缓冲层为硅掺杂氮化物，其掺杂浓度大于或等于 1×1018cm-3 。
  22. 根据权利要求 21 所述的发光二极管芯片，其特征在于：所述 n 型欧姆接触缓冲层为硅掺杂氮化物，其掺杂浓度大于或等于 1×1020cm-3 。
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