WO2013097749A1 - 一种提高亚阈值sram存储单元工艺鲁棒性的电路 - Google Patents

一种提高亚阈值sram存储单元工艺鲁棒性的电路 Download PDF

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Publication number
WO2013097749A1
WO2013097749A1 PCT/CN2012/087719 CN2012087719W WO2013097749A1 WO 2013097749 A1 WO2013097749 A1 WO 2013097749A1 CN 2012087719 W CN2012087719 W CN 2012087719W WO 2013097749 A1 WO2013097749 A1 WO 2013097749A1
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Prior art keywords
nmos transistor
pmos transistor
transistor
circuit
pmos
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PCT/CN2012/087719
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English (en)
French (fr)
Inventor
柏娜
朱贾峰
冯越
龚才
潘非
常红
邓一峰
陈愿
夏迎成
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东南大学
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Priority to US14/369,651 priority Critical patent/US9236115B2/en
Publication of WO2013097749A1 publication Critical patent/WO2013097749A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element

Definitions

  • the invention relates to a circuit for improving the process robustness of a subthreshold SRAM (Static Random Access Memory) memory cell, and belongs to the technical field of integrated circuit design.
  • SRAM Static Random Access Memory
  • Subthreshold design is gradually being widely used due to its ultra-low power consumption characteristics.
  • the MOS tube threshold voltage in the memory cell is more significantly affected by process fluctuations.
  • process fluctuations result in reduced performance or even errors in the memory cells. This poses new challenges to the stability design of the entire system. Therefore, it is necessary to adopt process fluctuation compensation measures to improve the stability of SRAM memory cells.
  • the threshold voltage of the MOS transistor is related to the driving capability index. Therefore, changing the threshold voltage of the subthreshold MOS transistor can effectively change the driving capability of the MOS transistor.
  • Changing the MOS tube substrate voltage is one of the most effective ways to change the MOS tube threshold voltage.
  • the substrate voltage of the NMOS transistor is limited to the power supply ground under the single well process. Therefore, changing the PMOS substrate voltage becomes one of the effective paths for implementing the method.
  • the object of the present invention is to solve the problem that the threshold voltage of the sub-threshold region MOS is degraded or even functionally disabled due to process fluctuations, and a circuit for improving the robustness of the sub-threshold SRAM memory cell is provided.
  • the circuit adjusts the threshold voltage of the PMOS transistor in the sub-threshold memory cell by detecting the threshold voltage fluctuation of the PMOS transistor and the NMOS transistor caused by the process fluctuation, so that the threshold voltage of the PMOS in the sub-threshold memory cell and the threshold of the NMOS are controlled.
  • the voltage matching improves the noise margin of the memory cell and effectively improves the process robustness of the sub-threshold SRAM memory cell.
  • a circuit for improving the robustness of a subthreshold SRAM memory cell as an auxiliary circuit of a subthreshold SRAM memory cell connecting the output of the circuit ( ) to a substrate of a PMOS transistor in a subthreshold SRAM memory cell
  • the circuit includes a PMOS transistor threshold voltage detection circuit and a differential input single-ended output amplifier.
  • the PMOS transistor threshold voltage detecting circuit comprises a PMOS transistor P1 and an NMOS transistor N1.
  • the source end of the PMOS transistor PI is connected to the power supply voltage VDD, and the drain terminal and the gate terminal of the PMOS transistor P1 are respectively connected to the drain terminal and the gate terminal of the NMOS transistor N1.
  • the source end of the NMOS transistor N1 is connected to the substrate and connected to the power ground VSS;
  • the differential input single-ended output amplifier includes a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, and a fifth NMOS transistor N5.
  • the drain terminal and the gate terminal of the second PMOS transistor P2 are connected and connected to the gate terminal of the third PMOS transistor P3 and the drain terminal of the second NMOS transistor N2, the source terminal of the second PMOS transistor P2 and the third PMOS transistor P3.
  • the source terminals are connected together and connected to the power supply voltage VDD, and the gate terminal of the second NMOS transistor N2 is connected to the gate terminal of the fourth NMOS transistor N4 and connected to the peripheral bias voltage ( ), and the source of the second NMOS transistor N2 Terminal and source of the third NMOS transistor N3 And the drain terminals of the fourth NMOS transistor N4 are connected together, the source terminal of the fourth NMOS transistor N4 is connected to the power supply ground VSS; the gate terminal of the third NMOS transistor N3 and the drain of the first NMOS transistor N1 in the PMOS transistor threshold voltage detecting circuit The terminal and the gate terminal are connected together, and the drain terminal of the third NMOS transistor N3 is connected to the drain terminal of the third PMOS transistor P3 and the gate terminal of the fourth PMOS transistor P4 and the gate terminal of the fifth NMOS transistor N5, the fourth PMOS.
  • the source end of the pipe P4 is connected to the power supply voltage VDD, and the source end of the fifth NM0S pipe N5
  • the substrates of the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, and the fifth NMOS transistor N5 are all connected to the power ground VSS, the drain terminal of the fourth PMOS transistor P4 and the drain terminal of the fifth NMOS transistor N5. Connected together and connected to the substrates of the first PMOS pipe P1 to the fourth PMOS pipe P4 as the output terminal ( ) of the auxiliary circuit.
  • the circuit for improving the robustness of the sub-threshold SRAM process provided by the present invention is applied in the ultra-wide supply voltage range of the sub-threshold region under the single-well process, by changing the sub-threshold SRAM memory cell.
  • the substrate voltage of the PMOS transistor changes the threshold voltage of the PMOS transistor to match the threshold voltage of the NMOS under different processes, thereby improving the noise margin of the subthreshold SRAM memory cell, and effectively improving the subthreshold SRAM memory cell.
  • the circuit operates over an ultra-wide supply voltage range (0.2V-0.7V) in the subthreshold region.
  • FIG. 1 is a circuit diagram of the present invention
  • FIG. 2 is a circuit structural diagram of the present invention connected to a sub-threshold SRAM six-tube memory unit;
  • FIG. 3 is a gain diagram of a differential input single-ended output amplifier used in the present invention.
  • Figure 5 shows the read noise margin of a subthreshold SRAM six-cell memory cell at a supply voltage of 300 mV for 500 Monte Carlo analysis
  • Figure 6 shows the read operation noise margin of a subthreshold SRAM six-cell memory cell with a designed power supply voltage of 300 mV for 500 Monte Carlo analysis
  • Figure 7 is a comparison of write noise margins at the worst process corners of sub-threshold sub-threshold regions with different supply voltages for sub-threshold SRAM six-cell memory cells with and without the circuit of the present invention
  • Figure 8 is an embodiment of the application of the present invention in a sub-threshold SRAM.
  • a circuit for improving the process robustness of a sub-threshold SRAM memory cell includes a PMOS threshold voltage detection circuit. At the same time, a peripheral bias voltage V bias is required .
  • the PMOS threshold voltage detecting circuit includes a first PMOS transistor P1 and a first NMOS transistor N1; the source end of the first PMOS transistor P1 is connected to the power supply voltage VDD, and the drain terminal and the gate terminal thereof are respectively connected to the drain terminal and the gate terminal of the first NMOS transistor N1. Connected together; the source end of the first NMOS transistor N1 and the substrate are connected together and connected to the power supply ground VSS;
  • the differential input single-ended output amplifier includes a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, and a fifth NMOS transistor N5.
  • the drain terminal and the gate terminal of the second PMOS transistor P2 are connected and connected to the gate terminal of the third PMOS transistor P3 and the drain terminal of the second NMOS transistor N2, the source terminal of the second PMOS transistor P2 and the source of the third PMOS transistor P3.
  • the terminals are connected together and connected to the power supply voltage VDD, and the gate end of the second NMOS transistor N2 is connected to the gate terminal of the fourth NMOS transistor N4 and connected to the peripheral bias voltage (V bms ), and the second NMOS transistor N2
  • the source end is connected to the source end of the third NMOS transistor N3 and the drain end of the fourth NMOS transistor N4, the source end of the fourth NMOS transistor N4 is connected to the power supply ground VSS; the gate end of the third NMOS transistor N3 and the PMOS transistor threshold
  • the drain terminal and the gate terminal of the first NMOS transistor N1 are connected together in the voltage detecting circuit, the drain terminal of the third NMOS transistor N3 and the drain terminal of the third PMOS transistor P3, and the gate terminal and the fifth NMOS transistor of the fourth PMOS transistor P4.
  • the gate ends of N5 are connected together, the source end of the fourth PMOS transistor P4 is connected to the power supply voltage VDD, and the source end of the fifth NM
  • the substrates of the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, and the fifth NMOS transistor N5 are all connected to the power ground VSS, the drain terminal of the fourth PMOS transistor P4 and the drain terminal of the fifth NMOS transistor N5. Connected together and connected to the substrates of the first PMOS transistor P1 to the fourth PMOS transistor P4 as the output terminal ( ) of the auxiliary circuit.
  • the output of the sub-threshold SRAM memory cell process robustness improving circuit is connected to the substrate of the fifth PMOS transistor P5 and the sixth PMOS transistor P6 in the sub-threshold SRAM six-tube memory cell. To verify the robustness of the design to sub-threshold SRAM memory cells.
  • a PMOS transistor P1 and a first NMOS transistor N1 form a PMOS threshold voltage detecting circuit.
  • the expression of the subthreshold MOS transistor drive current I sub is as follows:
  • ⁇ is the width-to-length ratio of the MOS tube, which is the subthreshold amplitude coefficient
  • V is the thermal voltage. Its value is approximately equal to 26 mV at room temperature.
  • V i is the threshold voltage of the MOS tube.
  • ⁇ is affected by the power supply voltages VDD, V thn , V thp , u n , and p . At a certain supply voltage, it does not change. When process fluctuations occur, the influence of u n and p pairs is much smaller than ⁇ cron, V thp , so assume / i ⁇ ln ⁇
  • V A is a fixed value. Therefore, at a certain power supply voltage, the level of V A has a linear relationship withiller, ⁇ ⁇ 3 ⁇ 4 ⁇ .
  • V A is set to a fixed value under a power supply voltage in the sub-threshold region, and ⁇ and ⁇ are maintained in a fixed linear relationship.
  • ⁇ and ⁇ are maintained in a fixed linear relationship.
  • the differential amplifier used is a two-stage amplifier.
  • the first stage is the amplifier of the differential input single-ended output, and the second stage is mainly to increase the driving capability of this design, and the output swing of the amplifier is (0-VDD).
  • Figure 3 and Figure 4 show the gain and phase plots of the sub-threshold amplifiers at different supply voltages. It can be seen from the figure that the amplifier has a gain of more than 10 db and a sufficient phase margin (> 50°) at different supply voltages. Assuming the amplifier has a gain of G at different supply voltages, then:
  • V bp G(V A -V bi
  • G is the gain of the differential input single-ended output amplifier
  • ⁇ is! 5 ⁇
  • the output of the threshold voltage detection circuit is the peripheral bias voltage.
  • ⁇ is the threshold voltage of the MOS tube. Is the threshold voltage when the substrate bias is "0", V ss is the source bias, and 2 is the surface potential.
  • the threshold voltages of the MOS transistors P1 and N1 fluctuate such that V changes, and the differential input single-ended output amplifier amplifies the difference from V 4 and changes the PMOS transistor PI substrate voltage through the output terminal.
  • the threshold voltage of the PMOS transistor PI is matched with the threshold voltage of the NMOS transistor N1.
  • the gain of the amplifier is G.
  • the design can adaptively adjust the substrate voltage of the PMOS according to the process variation.
  • the NMOS and PMOS threshold voltages are balanced.
  • V Was bias voltage
  • the PMOS substrate of the sub-threshold SRAM six-tube memory cell is connected to the output ( ) of the amplifier.
  • Set ⁇ The process robustness of the sub-threshold SRAM six-tube memory cell can be improved.
  • Figure 5 shows the 500-Monte Carlo simulated read noise margin for a SRAM six-cell memory cell at a supply voltage of 300mV.
  • Figure 6 shows the read noise margin of a 500-Monte Carlo simulation using the six-tube memory cell of this design at a supply voltage of 300mV. It can be seen from the comparison that the design can effectively improve the process robustness of the sub-threshold storage unit.
  • this design can improve the robustness of SRAM memory cells in the ultra-wide operating supply voltage in the sub-threshold region.
  • ⁇ In order to adapt to the needs of different supply voltages in the subthreshold region, only ⁇ needs to be changed.
  • the voltage value can be.
  • Table 1 shows the comparison of read noise margins for subthreshold SRAM six-cell memory cells at different supply voltages without or without this design.
  • Table 2 gives a comparison of the sub-threshold SRAM six-tube memory cells with different noise tolerances after using and using this design at different supply voltages.
  • Figure 7 shows the noise tolerance of the write operation at the worst process angle after loading this compensation circuit. It is limited to the case of a conventional SRAM six-tube memory unit. It can be seen that the write operation noise margin at the worst process corner after loading this circuit is slightly worse than the conventional SRAM six-tube memory cell.
  • Figure 8 shows an application of this paper in subthreshold SRAM.
  • the read noise margin and the noise tolerance of the sub-threshold SRAM six-cell memory cell are significantly higher than those of the conventional SRAM six-cell memory cell.
  • the write noise margin is only slightly worse.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明公开一种提高亚阈值SRAM存储单元工艺鲁棒性的电路，该电路作为亚阈值SRAM存储单元的辅助电路，将该电路的输出连接到亚阈值SRAM存储单元内PMOS管及自身电路中PMOS管的衬底。该电路包括SRAM存储单元内PMOS管阈值电压检测电路及差分输入单端输出放大器，通过检测工艺波动引起的PMOS管与NMOS管阈值电压波动，自适应改变亚阈值SRAM存储单元内PMOS管及自身电路中PMOS管的衬底电压进而调节其阈值电压，使得PMOS的阈值电压与NMOS的阈值电压相匹配。提高了亚阈值SRAM存储单元的噪声容限，有效地提高了亚阈值SRAM存储单元的工艺鲁棒性。

Description

一种提高亚阈值 SRAM存储单元工艺鲁棒性的电路 技术领域
本发明涉及一种提高亚阈值 SRAM (静态随机存储器)存储单元工艺鲁棒性的电路， 属于集成电路设计技术领域。
背景技术
亚阈值设计因其超低能耗的特性而逐渐被广泛应用。 然而， 随着系统电源电压进入 亚阈值区域， 存储单元内 MOS管阈值电压受工艺波动影响更为显著。 针对于 SRAM等 存储电路而言， 工艺波动导致存储单元的性能降低甚至出现错误。 这对整个系统的稳定 性设计提出新的挑战。 因此， 采取工艺波动补偿措施提高 SRAM存储单元的稳定性成为 必须。
亚阈值区域， MOS管阈值电压与驱动能力指数关系， 因此改变亚阈值 MOS管的阈 值电压可有效的改变 MOS管的驱动能力。 改变 MOS管衬底电压是改变 MOS管阈值电 压最有效的方式之一。 然而， 受限于单阱工艺下 NMOS管的衬底电压为电源地， 因此， 改变 PMOS衬底电压成为实现该方法的有效路径之一。
发明内容
发明目的：本发明的目的是为了解决亚阈值区域 MOS的阈值电压受工艺波动影响导 致 SRAM存储单元的性能降低甚至出现功能失效的问题，提供一种提高亚阈值 SRAM存 储单元工艺鲁棒性的电路，本电路通过检测工艺波动引起的 PMOS管与 NMOS管阈值电 压波动， 改变亚阈值存储单元中 PMOS管的衬底电压而调节其阈值电压， 使得亚阈值存 储单元内 PMOS的阈值电压与 NMOS的阈值电压相匹配， 提高了存储单元的噪声容限， 有效地提高了亚阈值 SRAM存储单元的工艺鲁棒性。
技术方案： 一种提高亚阈值 SRAM存储单元工艺鲁棒性的电路， 该电路作为亚阈值 SRAM存储单元的辅助电路， 将该电路的输出 （ ） 连接到亚阈值 SRAM存储单元中 PMOS管的衬底； 该电路包括 PMOS管阈值电压检测电路及差分输入单端输出放大器， 其巾：
所述 PMOS管阈值电压检测电路包括一个 PMOS管 P1及一个 NMOS管 Nl， PMOS 管 PI的源端连电源电压 VDD， PMOS管 P1的漏端和栅端分别与 NMOS管 N1的漏端和 栅端链接在一起， NMOS管 N1的源端与衬底连接在一起并连接至电源地 VSS ;
差分输入单端输出放大器包括第二 PMOS管 P2第三 PM0S管 P3、 第四 PM0S管 P、 第二 NMOS管 N2、 第三 NMOS管 N3、 第四 NMOS管 N4、 第五 NMOS管 N5 ; 所述第 二 PMOS管 P2的漏端和栅端连接并与第三 PMOS管 P3的栅端以及第二 NMOS管 N2 的漏端连接在一起，第二 PMOS管 P2的源端和第三 PMOS管 P3的源端连接在一起并与 电源电压 VDD连接， 第二 NMOS管 N2的栅端与第四 NMOS管 N4的栅端连接在一起 并与外设偏置电压 （ ) 连接， 第二 NMOS管 N2的源端与第三 NMOS管 N3的源端 以及第四 NMOS管 N4的漏端连接在一起，第四 NM0S管 N4的源端连接至电源地 VSS ; 第三 NM0S管 N3的栅端与 PM0S管阈值电压检测电路中第一 NM0S管 N1的漏端和栅 端连接在一起， 第三 NM0S管 N3的漏端与第三 PM0S管 P3的漏端以及第四 PM0S管 P4的栅端和第五 NM0S管 N5的栅端连接在一起， 第四 PM0S管 P4的源端连电源电压 VDD, 第五 NM0S管 N5的源端连接至电源地 VSS ;
第二 NM0S管 N2、第三 NM0S管 N3、第四 NM0S管 N4、第五 NM0S管 N5的衬 底均连接至电源地 VSS , 第四 PMOS管 P4的漏端与第五 NMOS管 N5的漏端连接在一 起且与第一 PM0S管 P1〜第四 PM0S管 P4的衬底连接作为本辅助电路的输出端 （ ）。
有益效果：与现有技术相比，本方明所提供的提高亚阈值 SRAM工艺鲁棒性的电路， 应用在单阱工艺下亚阈值区域超宽电源电压范围内， 通过改变亚阈值 SRAM存储单元内 的 PMOS管的衬底电压， 改变 PMOS管阈值电压使其在不同工艺下均与 NMOS的阈值 电压相匹配，提高亚阈值 SRAM存储单元的噪声容限，有效地提高了亚阈值 SRAM存储 单元的工艺鲁棒性。 该电路可工作在亚阈值区域超宽电源电压范围内 （0.2V-0.7V)。 附图说明
图 1 是本发明电路结构图；
图 2 是本发明与亚阈值 SRAM六管存储单元连接在一起的电路结构图；
图 3 是本发明中使用的差分输入单端输出放大器的增益图；
图 4 是本发明中使用的差分输入单端输出放大器的相位图；
图 5 是亚阈值 SRAM六管存储单元在电源电压为 300mV时的读噪声容限 500次蒙 特卡洛分析；
图 6 是采用了本设计后的亚阈值 SRAM六管存储单元在电源电压为 300mV时的读 操作噪声容限 500次蒙特卡洛分析；
图 7 是亚阈值区域不同电源电压下亚阈值 SRAM六管存储单元在采用及没有采用 本发明电路时最坏工艺角下的写噪声容限比较；
图 8 是本发明在亚阈值 SRAM中应用的一个实施例。
具体实施方式
下面结合附图和具体的实施例， 进一步阐明本发明， 应理解这些实施例仅用于说明 本发明而不用于限制本发明的范围， 在阅读了本发明之后， 本领域技术人员对本发明的 各种等价形式的修改均落于本申请所附权利要求所限定的范围。
参看图 1， 提高亚阈值 SRAM存储单元工艺鲁棒性的电路包含一个 PMOS阈值电压 检测电路。 同时， 需要一个外设偏置电压 Vbias 。
PMOS阈值电压检测电路包括第一 PMOS管 P1及第一 NMOS管 N1 ; 第一 PMOS 管 P1的源端连电源电压 VDD, 其漏端和栅端分别与第一 NMOS管 N1的漏端和栅端连 在一起； 第一 NMOS管 N1的源端和衬底连接在一起并连接至电源地 VSS ; 差分输入单端输出放大器包括第二 PMOS管 P2第三 PM0S管 P3、 第四 PM0S管 P 第二 NMOS管 N2、 第三 NMOS管 N3、 第四 NMOS管 N4、 第五 NMOS管 N5 ; 所述第 二 PMOS管 P2的漏端和栅端连接并与第三 PMOS管 P3的栅端以及第二 NMOS管 N2 的漏端连接在一起，第二 PMOS管 P2的源端和第三 PMOS管 P3的源端连接在一起并与 电源电压 VDD连接， 第二 NMOS管 N2的栅端与第四 NMOS管 N4的栅端连接在一起 并与外设偏置电压 （ Vbms ) 连接， 第二 NMOS管 N2的源端与第三 NMOS管 N3的源端 以及第四 NMOS管 N4的漏端连接在一起，第四 NMOS管 N4的源端连接至电源地 VSS ; 第三 NMOS管 N3的栅端与 PMOS管阈值电压检测电路中第一 NMOS管 N1的漏端和栅 端连接在一起， 第三 NMOS管 N3的漏端与第三 PMOS管 P3的漏端以及第四 PMOS管 P4的栅端和第五 NMOS管 N5的栅端连接在一起， 第四 PMOS管 P4的源端连电源电压 VDD, 第五 NMOS管 N5的源端连接至电源地 VSS ;
第二 NMOS管 N2、第三 NMOS管 N3、第四 NMOS管 N4、第五 NMOS管 N5的衬 底均连接至电源地 VSS , 第四 PMOS管 P4的漏端与第五 NMOS管 N5的漏端连接在一 起且与第一 PMOS管 P1〜第四 PM0S管 P4的衬底连接作为本辅助电路的输出端 （ ）。
参看图 2， 该电路模型中， 将亚阈值 SRAM存储单元工艺鲁棒性提高电路的输出端 与亚阈值 SRAM六管存储单元中第五 PMOS管 P5、第六 PMOS管 P6的衬底连接在一起， 用以验证本设计对亚阈值 SRAM存储单元的工艺鲁棒性的提高。
本发明提高亚阈值 SRAM存储单元工艺鲁棒性的工作原理如下：
PMOS管阈值电压检测电路
如图 1中所示： 一地 PMOS管 P1与第一 NMOS管 N1组成 PMOS阈值电压检测电 路。 亚阈值 MOS管驱动电流 Isub ) 的表达式如下：
Figure imgf000005_0001
(1)
其中， /分别为 MOS的迁移率， "^为 MOS管的宽长比， 为亚阈值幅度系数， V 为热电压 其值在室温下大约等于 26 mV Vi 为 MOS管阈值电压。
的电流分别为 i iD,N1 , iDiP1 )： ,m = nCox (―) N1 ( - l)VT 2e πΥτ (2)
- W
iD,pi = PC0X (―) Pl (n - l)VT 2e "Vt
(3)
其中， μη、 分别为 NMOS PMOS的迁移率， n为亚阈值幅度系数， V为热电压 kTlq, VZ)Z)是电源电压， Vihn、 Vthp分别为 NMOS、 PMOS的阈值电压 （绝对值）。 由图中可知： iDN1=iD. 假设 （ )„= ( ) Ρ1。 此可得 Α点电平 （VA):
Figure imgf000006_0001
(4)
从公式 (4)可知， ^受电源电压 VDD、 Vthn、 Vthp、 un、 p的影响。 在某一电源电压 下， 不变。出现工艺波动时， un、 p对 的影响远小于^„、 Vthp, 因此假设/ i^ln^
un 为定值。 由此可得， 在某一电源电压下， VA的电平与 „、 νί¾ρ存在一线性关系。
综上可得， 设置 VA在亚阈值区域某电源电压下为一固定值， 则^„与 ^维持在一个 固定的线性关系上。 合理的设置 PMOS与 NMOS的宽长比即可实现在出现工艺波动时 NMOS与 PMOS的驱动能力均衡。
差分输入单端输出放大器
在本设计中， 采用的差分放大器为两级放大器。 第一级为差分输入单端输出的放大 器， 第二级主要为了增加本设计的驱动能力， 同时使得放大器的输出摆幅为 （0-VDD)。 图 3及图 4分别显示的是亚阈值放大器在不同电源电压的增益及相位图。 从图中可以看 出，在不同的电源电压下，该放大器的增益均大于 10db，且具有足够的相位裕度（> 50°)。 假设该放大器在不同的电源电压下的增益为 G， 那么：
Vbp =G(VA-Vbi
(5)
其中， 为本辅助电路的输出端， G为差分输入单端输出放大器的增益， ^为！5^^^ 阈值电压检测电路的输出， 为外设偏置电压。
PMOS管阈值电压调节过程
Figure imgf000006_0002
(6)
其中， ^为 MOS管阈值电压， 。是衬底偏压为 "0"时的阈值电压， Vss为源体偏 置， 2 为表面势。
当 MOS管受工艺波动时， MOS管 Pl、 N1的阈值电压发生波动使得 V变化， 差分 输入单端输出放大器会将 与 V4的差值放大，并通过输出端改变 PMOS管 PI衬底电压， 使得 PMOS管 PI的阈值电压和 NMOS管 N1的阈值电压相匹配。 放大器的增益为 G。 当受工艺波动影响导致 ^上升时， 由公式 (5)可知 上升。 由公式 (6)知， PMOS 的衬底 电压上升导致 V 上升。 最终 VA下降， 直至 VA = Vfc∞s。 同理， 当 ^因工艺波动而下降时， 下降，进而 νί¾ρ下降， 最终使得^上升， 直至 VA = V^。因此在不同的工艺波动情况下， ^ = ^ 。 进而， 使得工艺波动的情况下 NMOS与 PMOS的阈值电压平衡。
综上所述，本设计可以根据工艺的变化自适应的调节 PMOS的衬底电压。致使 NMOS 与 PMOS的阈值电压平衡。 通过改变偏置电压（VWas )， 该设计即可工作在亚阈值超宽电 源电压区域内。
本设计提高亚阈值 SRAM六管存储单元工艺鲁棒性
参见图 3，将亚阈值 SRAM六管存储单元的 PMOS衬底接至放大器的输出端（ ）。 设置^。即可实现提高亚阈值 SRAM六管存储单元的工艺鲁棒性。
图 5显示在电源电压为 300mV时 SRAM六管存储单元的 500次蒙特卡洛仿真出的 读噪声容限。图 6显示在电源电压为 300mV时采用了本设计后的六管存储单元的 500次 蒙特卡洛仿真出的读噪声容限。 通过对比可以看出， 本设计可以有效的提高亚阈值存储 单元的工艺鲁棒性。
此外， 本设计在亚阈值区域超宽工作电源电压内均可以提高 SRAM存储单元的鲁棒 性。 为了适应亚阈值区域不同电源电压的需要， 只需要改变^。的电压值即可。 表一给 出了在不同的电源电压下， 亚阈值 SRAM六管存储单元在没有采用和采用本设计后的读 噪声容限比较结果。 表
Figure imgf000007_0001
从表一中可以看出， 加入补偿电路后， 不同电源电压下的亚阈值存储单元最坏情况 下的读噪声容限、 读噪声容限的 Mean及 Std均得到很好的提升。
表二给出了不同的电源电压下， 亚阈值 SRAM六管存储单元在没有采用和采用本设 计后的保持噪声容限的比较。
表 二 没有补偿电路 有补偿电路 性能提升 电源电
Worst mean std Worst mean std Worst mean std 压（mV)
Case (mV) (mV) (mV) Case (mV) (mV) (mV) Case (mV) (mV) (mV)
200 7. 5 56. 4 5. 1 13. 7 57. 9 3. 5 82. 7% 2. 7% 31. 4%
300 53. 8 103. 3 5. 1 63. 5 104 3. 6 18. 0% 0. 7% 29. 4%
400 100. 5 150. 2 5. 2 113. 9 152. 6 3. 1 13. 3% 1. 6% 40. 4%
500 146. 7 196. 6 5. 1 161. 8 199 3 10. 3% 1. 2% 41. 2%
600 191. 5 241. 7 5. 1 205. 4 243. 7 3. 2 7. 3% 0. 8% 37. 3%
700 236 284. 2 5. 4 246. 8 285. 4 4. 3 4. 6% 0. 4% 20. 4% 图 7中给出了加载此补偿电路后， 最坏工艺角下写操作噪声容限与常规 SRAM六管 存储单元的情况比较。 图中看出， 加载此电路后的最坏工艺角下的写操作噪声容限较常 规 SRAM六管存储单元有稍许恶化。
值得注意的是， 当将本设计应用于亚阈值 SRAM中时， 多个 bitcell可共用一个本文 设计。 图 8给出了本文设计在亚阈值 SRAM中的一种应用方案。 综上所述， 加载本文设计后， 亚阈值 SRAM六管存储单元的读噪声容限和保持噪声 容限性能较常规 SRAM六管存储单元在亚阈值不同电源电压均有大幅度提升。 而写噪声 容限仅有稍许恶化。

Claims

权利要求书
1、 一种提高亚阈值 SRAM存储单元工艺鲁棒性的电路， 其特征在于： 该电路作为亚 阈值 SRAM存储单元的辅助电路， 将该电路的输出 （ Vbp )连接到亚阈值 SRAM存储单元 中 PMOS管及自身电路中 PMOS管的衬底； 该电路包括 PMOS管阈值电压检测电路及差 分输入单端输出放大器， 其中：
所述 PMOS管阈值电压检测电路包括第一 PMOS管 P1及第一 NMOS管 N1 ; 所述 第一 PMOS管 P1的源端连电源电压 VDD， 其漏端和栅端分别与第一 NMOS管 N1的漏 端和栅端链接在一起； 所述第一 NMOS管 N1的源端与衬底均连接至电源地 VSS ;
所述差分输入单端输出放大器包括第二 PMOS 管 P2、 第三 PMOS 管 P3、 第四 PMOS管 P4、 第二 NMOS管 N2、 第三 NMOS管 N3、 第四 NMOS管 N4和第五 NMOS 管 N5 ; 所述第二 PMOS管 P2的漏端和栅端连接并与第三 PMOS管 P3的栅端以及第二 NMOS管 N2的漏端连接在一起， 第二 PMOS管 P2的源端和第三 PMOS管 P3的源端连 接在一起并与电源电压 VDD连接； 所述第二 NMOS管 N2的栅端与第四 NMOS管 N4的 栅端连接在一起并与外设偏置电压 （V^ ) 连接， 第二 NMOS 管 N2 的源端与第三 NMOS管 N3的源端以及第四 NMOS管 N4的漏端连接在一起， 所述第四 NMOS管 N4 的源端连接至电源地 VSS， 第三 NMOS管 N3的栅端与 PMOS管阈值电压检测电路中第 一 NMOS管 N1的漏端和栅端连接在一起， 第三 NMOS管 N3的漏端与第三 PMOS管 P3 的漏端以及第四 PMOS管 P4的栅端和第五 NMOS管 N5的栅端连接在一起， 第四 PMOS 管 P4的源端连电源电压 VDD, 第五 NMOS管 N5的源端连接至电源地 VSS ;
第二 NMOS管 N2、 第三 NMOS管 N3、 第四 NMOS管 N4、 第五 NMOS管 N5的衬 底均连接至电源地 VSS , 第四 PMOS管 P4的漏端与第五 NMOS管 N5的漏端连接在一 起且与第一 PMOS管 P1〜第四 PM0S管 P4的衬底连接作为本辅助电路的输出端 （ Vfc„ )。
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