WO2013086912A1 - 只读存储器及其制作方法 - Google Patents

只读存储器及其制作方法 Download PDF

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Publication number
WO2013086912A1
WO2013086912A1 PCT/CN2012/084284 CN2012084284W WO2013086912A1 WO 2013086912 A1 WO2013086912 A1 WO 2013086912A1 CN 2012084284 W CN2012084284 W CN 2012084284W WO 2013086912 A1 WO2013086912 A1 WO 2013086912A1
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Prior art keywords
lightly doped
mos transistor
doped drain
source
drain region
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English (en)
French (fr)
Inventor
周玮
蔡建祥
王锴
李付军
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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Priority claimed from CN201110422511.9A external-priority patent/CN103165611B/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38—Doping programmed, e.g. mask ROM
    • H10B20/387—Source region or drain region doping programmed

Definitions

  • the present invention relates to a semiconductor memory, and more particularly to a read only memory and a method of fabricating the same.
  • Read only memory is a type of semiconductor memory. As the name suggests, read-only memory can only read information that it has deposited, and cannot erase or re-write the saved information. The ROM stores data stable, and the stored data will not be lost even without power support.
  • a read-only memory contains a number of memory cells arranged in an array for storing information.
  • the more common read-only memory on the market is a mask read-only memory.
  • the mask read-only memory requires an additional mask to create a memory cell for storing information.
  • This additional reticle ion implantation is used to form two different turn-on voltage memory cells.
  • the memory cell information is read using an operating voltage between the two turn-on voltages. For example, when reading, a memory cell lower than the turn-on voltage of the operating voltage is turned on to obtain a corresponding electrical signal; a memory cell higher than the turn-on voltage of the operating voltage is turned off, and no electrical signal is obtained. Therefore, the information stored in the mask read-only memory can be efficiently read by the above method.
  • the present invention provides a read-only memory and a manufacturing method thereof, which can save an extra mask in the conventional mask read-only memory, shorten the manufacturing cycle of the read-only memory, and the manufacturing cost.
  • a read only memory comprising a plurality of memory cells arranged in an array.
  • a read-only memory contains two different types of memory cells.
  • the two storage units are a first MOS tube and a second MOS tube, respectively.
  • the source and the drain of the first MOS transistor are each provided with a lightly doped drain region, and one of the source and the drain of the second MOS transistor has a lightly doped drain region or no lightly doped drain region.
  • the source and the drain of the first MOS transistor are both provided with a P-type lightly doped drain region, and the source and drain of the second MOS transistor.
  • One of the poles has a P-type lightly doped drain region or none of the P-type lightly doped drain regions.
  • the source and the drain of the first MOS transistor are both provided with an N-type lightly doped drain region, and the source and drain of the second MOS transistor are One of them has an N-type lightly doped drain region or none of the N-type lightly doped drain regions.
  • a method for manufacturing the above read-only memory comprising the following steps:
  • Step 1 providing a silicon substrate, simultaneously forming an active region of two different structures of memory cells on the silicon substrate;
  • Step 2 forming a gate oxide medium and a control gate of two different structure memory cells on the surface of the active region;
  • Step 3 forming lightly doped drain regions of the drain and the source on both sides of the first MOS transistor control gate, and forming a lightly doped drain region or source of the drain on one side of the second MOS transistor control gate a lightly doped drain region; or a lightly doped drain region of each of the drain and source is formed only on both sides of the first MOS transistor control gate;
  • Step 4 forming sidewalls on both sides of the control gates of the first MOS transistor and the second MOS transistor;
  • Step 5 simultaneously forming an ion doping region of each of the drain and source of the first MOS transistor and an ion doping region of the drain and source of the second MOS transistor on both sides of the control gate having the sidewall.
  • step 3 includes the following sub-steps:
  • Step 31 coating a photoresist on a surface of a silicon substrate on which a control gate is formed;
  • Step 32 removing the photoresist portion on the region where the lightly doped drain region is to be formed in the two different structure memory cells;
  • Step 33 performing ion implantation on the region where the photoresist is removed to form a lightly doped drain region
  • Step 34 Remove the photoresist remaining on the surface of the silicon substrate after ion implantation.
  • step 32 includes the following steps:
  • Providing a lightly doped drain mask defining a lightly doped drain region of the drain and source of the first MOS transistor and a lightly doped drain region of the drain or source of the second MOS transistor in the lightly doped drain mask Or; only the lightly doped drain region of the drain and source of the first MOS transistor is defined on the lightly doped drain mask;
  • the read-only memory uses only the drain and the source of the second MOS transistor having a lightly doped drain region with respect to the first MOS transistor, and the drain and the source have only one of the lightly doped drain regions or both have no doped drain regions. Therefore, when the two MOS tubes read information, the difference between the currents can be used to judge the stored "0" or "1" information.
  • the position of the lightly doped drain region to be formed can be directly defined on the mask plate of the lightly doped drain region, and an additional mask is not required, so that the conventional mask read-only memory can be omitted. Additional reticle.
  • FIG. 1 is a schematic structural diagram of a first MOS transistor in an embodiment of a read only memory of the present invention
  • FIG. 2 is a schematic structural diagram of a second MOS transistor in an embodiment of a read only memory of the present invention
  • FIG. 3 is another schematic structural diagram of a second MOS transistor in the embodiment of the read only memory of the present invention.
  • FIG. 4 is a schematic diagram of driving currents of three MOS tube outputs shown in FIG. 1, FIG. 2, and FIG.
  • FIG. 5 is a schematic diagram of a partial layout of a read-only memory storage unit according to an embodiment of the present invention.
  • the embodiment provides a read-only memory and a manufacturing method thereof, which can save the additional mask of the conventional mask read-only memory, and shorten the manufacturing cycle and cost of the read-only memory.
  • the read-only memory of this embodiment includes a plurality of memory cells arranged in an array.
  • a read-only memory contains two different types of memory cells.
  • the two types of memory cells are the first MOS transistor 101 shown in FIG. 1, and the second MOS transistor 102 or 102' shown in FIG. 2 or FIG.
  • the source 14 and the drain 16 of the first MOS transistor 101 are each provided with a lightly doped drain region 12 (LDD, Lightly Doped Drain).
  • LDD lightly doped Drain
  • FIG. 2 only the drain 20 of the source 18 and the drain 20 of the second MOS transistor 102 is provided with a lightly doped drain region 12, or only the source electrode 18 is provided with a lightly doped drain region 12.
  • one of the source 18 or the drain 20 of the second MOS transistor 102 may have a lightly doped drain region 12.
  • the second MOS transistor 102' drain 20' and source 18' have no lightly doped drain regions.
  • the first MOS transistor 101 and the second MOS transistor 102 are provided with a lightly doped drain region 12, and the second MOS transistor 102 has a source 18 and a drain 20 A lightly doped drain region 12 is provided. Therefore, when the first MOS transistor 101 and the second MOS transistor 102 are loaded with the same voltage condition, the amplitude of the output driving current Id is largely different. Only one of the source 18 and the drain 20 of the second MOS transistor 102 has a lightly doped drain region 12, so the effective channel length of the second MOS transistor 102 is greater than the effective channel length of the first MOS transistor 101, thereby The drive current Id output from the second MOS transistor 102 is smaller than the drive current Id output from the first MOS transistor 101.
  • the second MOS transistor 102' shown in FIG. 3 has no lightly doped drain region for both the drain 20' and the source 18'. Therefore, in the active state, the second MOS transistor 102' has an effective channel length. It is larger than the effective length of the channel of the second MOS transistor 102 shown in FIG. 2, so that the driving current outputted by the second MOS transistor 102' is smaller than the driving current of the output of the second MOS transistor 102.
  • the solid line curve in FIG. 4 corresponds to the driving current outputted by the second MOS transistor 102' shown in FIG. 3.
  • the dotted line curve corresponds to the driving current outputted by the second MOS transistor 102 shown in FIG.
  • the second MOS transistor in the memory cell adopts the structure shown in FIG. 2 or the structure shown in FIG. 3, and the read-only memory can distinguish the signal by the difference of the driving current outputted by the second MOS transistor and the first MOS transistor. 0" or "1".
  • the second MOS transistor preferably selects the structure shown in FIG. 3, since the driving current outputted by the second MOS transistor 102' and the first MOS transistor shown in FIG. 3 is the largest, which is advantageous for the information reading device to clearly distinguish the read only memory.
  • the stored signal is "0" or "1".
  • P-type memory cells two different types are P-type memory cells.
  • the source and the drain of the first MOS transistor are both provided with a P-type lightly doped drain region (PLDD), and one of the source and the drain of the second MOS transistor has a P-type lightly doped drain region or none of the P-type Lightly doped drain area.
  • PLDD P-type lightly doped drain region
  • N-type memory cells two different types of memory cells are N-type memory cells.
  • the source and the drain of the first MOS transistor are each provided with an N-type lightly doped drain region, and one of the source and the drain of the second MOS transistor has an N-type lightly doped drain region or none of the N-type lightly doped regions. Drain zone.
  • Step 1 A silicon substrate is provided, and active regions of memory cells of two different structures are simultaneously formed on the silicon substrate. Referring to FIGS. 1 to 3 and FIG. 5, the active regions 10 of the first MOS transistor and the second MOS transistor shown in FIGS. 1 and 2 or 3 are formed on a silicon substrate.
  • the active region 10 shown in FIG. 5 is a schematic diagram of a portion of a read-only memory memory cell on the active area mask.
  • Step 2 Forming a gate oxide medium and a control gate of two different structure memory cells on the surface of the active region 10. Referring to FIG. 1 to FIG. 3 and FIG. 5, a gate oxide medium 17 and a control gate 11 of a MOS transistor stacked in sequence are simultaneously formed on the surface of the active region 10.
  • Step 3 Referring to FIG. 1 and FIG. 2, the lightly doped drain regions 12 of the drain 16 and the source 14 are formed on both sides of the control gate 11 of the first MOS transistor 101, and the gate 11 is controlled in the second MOS transistor 102.
  • One side forms a lightly doped drain region 12 of the drain 20 or a lightly doped drain region 12 of the source 18.
  • FIG. 1 and FIG. 3 only the lightly doped drain regions 12 of the drain 20 and the source 18 are formed on both sides of the control gate 11 of the first MOS transistor 101, and the control gates 11 of the second MOS transistor 102' are respectively There is no need to form a lightly doped region on the side.
  • Step 3 specifically includes the following sub-steps:
  • Step 31 coating a photoresist on a surface of the silicon substrate on which the control gate 11 is formed;
  • Step 32 removing the photoresist portion on the region where the lightly doped drain region is to be formed in the memory cells of the two different structures, so as to perform ion implantation in a subsequent step;
  • Step 33 performing ion implantation on the region where the photoresist is removed to form a lightly doped drain region
  • Step 34 Remove the photoresist remaining on the surface of the silicon substrate after ion implantation.
  • step 32 includes the following steps:
  • a lightly doped drain mask is provided to define the lightly doped drain region 12 of the drain 16 and source 14 of the first MOS transistor 101 and the lightly doped drain region 12 of the drain 20 or source 18 of the second MOS transistor 102 On a lightly doped drain mask.
  • a preferred solution is selected: only the first MOS transistor 101 needs to form the lightly doped drain region 12. Therefore, only the lightly doped drain regions 12 of the drain 20 and the source 18 of the first MOS transistor 101 are defined on the lightly doped drain mask.
  • the region 20 illustrated in FIG. 5 is the lightly doped drain region 12 of the drain 16 and the source 14 of the first MOS transistor 101 shown in FIG. 1 defined on the lightly doped drain region mask.
  • Figure 5 illustrates only a partial layout of a memory cell in a read-only memory.
  • the read only memory includes a plurality of first MOS transistors 101 as shown in FIG. 1 and a plurality of second MOS transistors 102' as shown in FIG. Therefore, a plurality of regions 20 corresponding to the lightly doped drain regions 12 of the drains 16 and 14 of the first MOS transistors 101 are actually defined on the mask of the lightly doped drain region.
  • the photoresist formed on the surface of the silicon substrate on which the control gate 11 is formed is exposed by a lightly doped drain mask, and the surface of the silicon substrate is removed to correspond to the lightly doped drain region 20 defined on the lightly doped drain mask.
  • the type of ions injected in step 33 is determined according to the type of the storage unit in the read only memory. If the memory cell is P-type, the first MOS transistor and the second MOS transistor are both PMOS transistors, the lightly doped drain region corresponds to a P-type lightly doped drain region, and the ion type injected in step 33 is a P-type. If the memory cell is N-type, the first MOS transistor and the second MOS transistor are both NMOS transistors, the lightly doped drain region corresponds to the N-type lightly doped drain region, and the ion type injected in step 33 is N-type.
  • Step 4 Forming sidewalls on both sides of the control gate 11 of the first MOS transistor and the second MOS transistor.
  • the sidewalls 13 on both sides of the formed control gate 11 can be formed by the following exemplary implementation method: after the light doping drain region ion implantation is completed, the surface of the control gate 11 is grown with insulation. The dielectric layer is then etched to form sidewalls 13 of insulating dielectric material.
  • Step 5 simultaneously forming an ion doping region of each of the drain 16 and the source 14 of the first MOS transistor 101 shown in FIG. 1 on both sides of the control gate 11 having the sidewall 13 and the second portion shown in FIG. 2 or FIG. IO tube 102 or 102' drain 20 or 20' and source 18 or 18' respective ion doped regions.
  • the ion doping region of the drain and source of the MOS transistor is mainly completed by applying a photoresist on the surface of the silicon substrate forming the control gate with the sidewall, exposing through the drain and the source mask, and removing the drain. And the photoresist on the source region.
  • the dashed box 21 is the ion doped region of the drain and source illustrated on the drain and source reticle. Ion implantation of the drain and source is then performed to form ion-doped regions of the drain and source, namely the drain and source. Finally, the photoresist that remains on the surface of the silicon substrate is removed by ion implantation.
  • the manufacturing method of the entire read-only memory that, compared with the conventional read-only memory, the entire process does not require an additional mask, and is compatible with the manufacturing process of the conventional MOS transistor. Therefore, the manufacturing cycle of the read-only memory of the embodiment is shortened, and the cost thereof is also reduced.

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Abstract

一种只读存储器，包含若干个阵列排布的存储单元。只读存储器包含两种不同结构的存储单元；两种存储单元分别为第一MOS管和第二MOS管；第一MOS管的源极和漏极均设有轻掺杂漏区，第二MOS管的源极和漏极其中之一具有轻掺杂漏区或者均无轻掺杂漏区。因此，这两种不同结构的MOS管输出的驱动电流差别可用于区别只读存储器存储单元存储的"0"或"1"信号。且只读存储器的存储单元的制作与传统MOS管制作工艺，可以省去传统掩模只读存储器额外的掩模板，缩短只读存储器的制作周期与成本。

Description

只读存储器及其制作方法
【技术领域】
本发明涉及半导体存储器，尤其是涉及一种只读存储器及其制作方法。
【背景技术】
只读存储器(ROM，read only memory)是半导体存储器的一种。顾名思义，只读存储器只可以读取其已存入的信息，而无法对已存入的信息进行擦除或重新写入。ROM存储数据稳定，即使在没有电源支持的情况下，所存的数据也不会丢失。
只读存储器包含若干个呈阵列排布，用于储存信息的存储单元。目前，市面上较为常见的只读存储器为掩模只读存储器。该掩模只读存储器制作时需要额外的掩模板来形成用于存储信息的存储单元。利用此额外的掩模板离子注入形成两种不同开启电压的存储单元。在读取信息时，利用介于两种开启电压之间的操作电压读取存储单元信息。例如，读取时，低于操作电压的开启电压的存储单元就会开启有相应的电信号获得；高于操作电压的开启电压的存储单元就会处于关闭状态，没有电信号获得。因此，掩模只读存储器存储的信息采用上述方法就可进行有效地读取。
然而，此种掩模只读存储器需要利用到额外的掩模板来形成两种不同开启电压的存储单元，增加了只读存储器的制作成本。
【发明内容】
基于此，本发明提供一种只读存储器及其制作方法，可省去传统掩模只读存储器中额外的掩模板，缩短只读存储器的制作周期以及制作成本。
一种只读存储器，包含若干个阵列排布的存储单元。只读存储器包含两种不同结构的存储单元。两种存储单元分别为第一MOS管和第二MOS管。第一MOS管的源极和漏极均设有轻掺杂漏区，第二MOS管的源极和漏极其中之一具有轻掺杂漏区或者均无轻掺杂漏区。
进一步地，以两种不同结构的存储单元均为P型存储单元为例，第一MOS管的源极和漏极均设有P型轻掺杂漏区，第二MOS管的源极和漏极其中之一具有P型轻掺杂漏区或者均无P型轻掺杂漏区。
进一步地，以两种不同结构的存储单元为N型存储单元为例，第一MOS管的源极和漏极均设有N型轻掺杂漏区，第二MOS管的源极和漏极其中之一具有N型轻掺杂漏区或者均无N型轻掺杂漏区。
一种上述只读存储器的制作方法，包括以下步骤：
步骤1：提供硅衬底，在硅衬底同时形成两种不同结构的存储单元的有源区；
步骤2：在有源区表面形成两种不同结构存储单元的栅氧介质及控制栅；
步骤3：在第一MOS管控制栅的两侧形成漏极及源极各自的轻掺杂漏区，同时在第二MOS管控制栅的一侧形成漏极的轻掺杂漏区或源极的轻掺杂漏区；或者仅在第一MOS管控制栅的两侧形成漏极及源极各自的轻掺杂漏区；
步骤4：在第一MOS管和第二MOS管的控制栅两侧形成侧壁；
步骤5：在具有侧壁的控制栅两侧同时形成第一MOS管漏极及源极各自的离子掺杂区和第二MOS管漏极及源极各自的离子掺杂区。
进一步地，步骤3包括以下分步骤：
步骤31：在形成有控制栅的硅衬底表面涂覆光阻；
步骤32：去除两种不同结构存储单元中即将形成轻掺杂漏区的区域上的光阻部分；
步骤33：向去除了光阻的区域进行离子注入，形成轻掺杂漏区；
步骤34：去除离子注入后残留在硅衬底表面的光阻。
进一步地，步骤32包括以下步骤：
提供轻掺杂漏区掩模板，将第一MOS管漏极和源极的轻掺杂漏区和第二MOS管漏极或源极的轻掺杂漏区定义在轻掺杂漏区掩模板上；或者仅将第一MOS管漏极和源极的轻掺杂漏区定义在轻掺杂漏区掩模板上；
通过轻掺杂漏区的掩模板，曝光形成有控制栅的硅衬底表面的光阻，显影去除硅衬底表面对应于轻掺杂漏区掩模板上定义的轻掺杂漏区区域上的光阻部分。
上述只读存储器，利用第二MOS管漏极和源极相对第一MOS管具有轻掺杂漏区的漏极和源极只有其一具有轻掺杂漏区或者两者均无掺杂漏区，使得两种MOS管在读取信息时，电流之间的差别可用于判断其存储的“0”或“1”信息。在只读存储器的制作方法中，直接在轻掺杂漏区的掩模板上定义出要形成的轻掺杂漏区位置即可，无需额外的掩模板，因此可以省去传统掩模只读存储器额外的掩模板。
【附图说明】
图1为本发明只读存储器实施例中第一MOS管结构示意图；
图2为本发明只读存储器实施例中第二MOS管结构示意图；
图3为本发明只读存储器实施例中第二MOS管另一种结构示意图；
图4为图1、图2和图3所示的三种MOS管输出的驱动电流示意图；
图5为本发明实施例中只读存储器存储单元部分版图示意图。
【具体实施方式】
本实施例提出了只读存储器及其制作方法，可省去传统掩模只读存储器额外的掩模板，缩短只读存储器的制作周期及成本。
本实施例的只读存储器，包含若干个阵列排布的存储单元。只读存储器包含两种不同结构的存储单元。两种存储单元分别为图1所示的第一MOS管101、图2或图3所示的第二MOS管102或102＇。第一MOS管101的源极14和漏极16均设有轻掺杂漏区12（LDD，Lightly Doped Drain）。如图2所示第二MOS管102的源极18和漏极20中仅漏极20设有轻掺杂漏区12，或者仅源极18设有轻掺杂漏区12。总之，第二MOS管102的源极18或者漏极20之一具有轻掺杂漏区12即可。或者如图3所示，第二MOS管102＇漏极20＇和源极18＇均无轻掺杂漏区。
存储单元中第一MOS管101与第二MOS管102相比，漏极16及源极14均设有轻掺杂漏区12，而第二MOS管102源极18和漏极20只有其一设有轻掺杂漏区12。因此当第一MOS管101和第二MOS管102，加载相同的电压条件时，输出的驱动电流Id幅度是有较大差别的。第二MOS管102的源极18和漏极20只有两者之一具有轻掺杂漏区12，因此第二MOS管102有效沟道长度大于第一MOS管101的有效沟道长度，从而第二MOS管102输出的驱动电流Id则小于第一MOS管101输出的驱动电流Id。同理，图3所示的第二MOS管102＇由于漏极20＇和源极18＇两者均无轻掺杂漏区，因此在工作状态时，第二MOS管102＇有效沟道长度大于图2所示第二MOS管102的沟道有效长度，从而第二MOS管102＇输出的驱动电流小于第二MOS管102的输出的驱动电流。
请参阅图4，图4中的实线曲线对应图3所示第二MOS管102＇输出的驱动电流，点划线曲线对应图2所示第二MOS管102输出的驱动电流，虚线曲线则对应图1所示的第一MOS管101输出的驱动电流。因此，存储单元中第二MOS管无论采用图2所示的结构或者图3所示的结构，只读存储器都能依靠第二MOS管与第一MOS管输出的驱动电流的差别来辨别信号“0”或“1”。第二MOS管优选地选择图3所示的结构，由于图3所示的第二MOS管102＇与第一MOS管输出的驱动电流是最大的，更利于信息读取装置清楚分辨只读存储器存储的信号“0”或“1”。
以P型存储单元为例，两种不同结构的存储单元均为P型存储单元。第一MOS管的源极和漏极均设有P型轻掺杂漏区（PLDD），第二MOS管的源极和漏极其中之一具有P型轻掺杂漏区或者均无P型轻掺杂漏区。
以N型存储单元为例，两种不同结构的存储单元为N型存储单元。第一MOS管的源极和漏极均设有N型轻掺杂漏区，第二MOS管的源极和漏极其中之一具有N型轻掺杂漏区或者均无N型轻掺杂漏区。
一种上述只读存储器实施例的制作方法，包括以下步骤：
步骤1：提供硅衬底，在硅衬底同时形成两种不同结构的存储单元的有源区。请参阅图1至图3以及图5，同时在硅衬底上形成图1和图2或图3所示的第一MOS管和第二MOS管的有源区10。图5所示有源区10为有源区掩模板上只读存储器存储单元部分版图示意图。
步骤2：在有源区10表面形成两种不同结构存储单元的栅氧介质及控制栅。请参阅图1至图3以及图5，在有源区10表面同时形成依次堆叠的MOS管的栅氧介质17及控制栅11。
步骤3：请参阅图1和图2，在第一MOS管101控制栅11的两侧形成漏极16及源极14各自的轻掺杂漏区12，同时在第二MOS管102控制栅11的一侧形成漏极20的轻掺杂漏区12或源极18的轻掺杂漏区12。或者，请参阅图1和图3仅在第一MOS管101控制栅11的两侧形成漏极20及源极18各自的轻掺杂漏区12，第二MOS管102＇的控制栅11两侧无需形成轻掺杂区。
步骤3具体包括以下分步骤：
步骤31：在形成有控制栅11的硅衬底表面涂覆光阻；
步骤32：去除两种不同结构存储单元中即将形成轻掺杂漏区的区域上的光阻部分，以便后序步骤进行离子注入；
步骤33：向去除了光阻的区域进行离子注入，形成轻掺杂漏区；
步骤34：去除离子注入后残留在硅衬底表面的光阻。
其中，步骤32包括以下步骤：
提供轻掺杂漏区掩模板，将第一MOS管101漏极16和源极14的轻掺杂漏区12和第二MOS管102漏极20或源极18的轻掺杂漏区12定义在轻掺杂漏区掩模板上。或者，选择优选方案：仅第一MOS管101需要形成轻掺杂漏区12。因此，仅将第一MOS管101漏极20和源极18的轻掺杂漏区12定义在轻掺杂漏区掩模板上。如图5示例的区域20为轻掺杂漏区掩模板上定义的两个图1所示的第一MOS管101漏极16及源极14的轻掺杂漏区12。图5例举的仅为只读存储器中存储单元部分版图示意图。实际上，只读存储器中包含了若干个如图1所示的第一MOS管101和若干图3所示的第二MOS管102＇。因此在轻掺杂漏区的掩模板上实际上定义有若干个区域20对应于若干个第一MOS管101漏极16和源极14的轻掺杂漏区12。
通过轻掺杂漏区的掩模板，曝光形成有控制栅11的硅衬底表面的光阻，显影去除硅衬底表面对应于轻掺杂漏区掩模板上定义的轻掺杂漏区区域20上的光阻部分。
其中，步骤33注入的离子类型是依据只读存储器中存储单元的类型而定。若存储单元为P型，第一MOS管和第二MOS管则均为PMOS管，轻掺杂漏区对应为P型轻掺杂漏区，步骤33注入的离子类型则为P型。若存储单元为N型，第一MOS管和第二MOS管则均为NMOS管，轻掺杂漏区对应为N型轻掺杂漏区，步骤33注入的离子类型则为N型。
步骤4：在第一MOS管和第二MOS管的控制栅11两侧形成侧壁。请参阅图1、图2或图3，形成的控制栅11两侧的侧壁13可以通过以下例举的实现方法形成：在完成轻掺杂漏区离子注入后，在控制栅11表面生长绝缘介质层，然后进行刻蚀形成绝缘介质材料的侧壁13。
步骤5：在具有侧壁13的控制栅11两侧同时形成图1所示的第一MOS管101漏极16及源极14各自的离子掺杂区和图2或图3所示的第二MOS管102或102＇漏极20或20＇及源极18或18＇各自的离子掺杂区。MOS管漏极和源极的离子掺杂区主要通过以下步骤完成：在形成带有侧壁的控制栅的硅衬底表面涂敷光阻，通过漏极和源极掩模板曝光，去除漏极和源极区域上的光阻。请参阅图5，虚线框21为漏极和源极掩模板上示意的漏极和源极的离子掺杂区。然后进行漏极和源极的离子注入，形成漏极和源极的离子掺杂区，即漏极和源极。最后去除离子注入残留在硅衬底表面的光阻。
因此，从整个只读存储器的制作方法中可以看出，相对传统的只读存储器，整个过程无需额外的掩模板，和传统MOS管的制作工艺兼容。因此，本实施例的只读存储器的制作周期会缩短，其成本也有所降低。
以上实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (6)

  1. 一种只读存储器，包含若干个阵列排布的存储单元，其特征在于，所述只读存储器包含两种不同结构的存储单元；所述两种存储单元分别为第一MOS管和第二MOS管；所述第一MOS管的源极和漏极均设有轻掺杂漏区，所述第二MOS管的源极和漏极其中之一具有轻掺杂漏区或者均无轻掺杂漏区。
  2. 根据权利要求1所述的只读存储器，其特征在于，所述两种不同结构的存储单元均为P型存储单元，所述第一MOS管的源极和漏极均设有P型轻掺杂漏区，所述第二MOS管的源极和漏极其中之一具有P型轻掺杂漏区或者均无P型轻掺杂漏区。
  3. 根据权利要求1所述的只读存储器，其特征在于，所述两中不同结构的存储单元均为N型存储单元，所述第一MOS管的源极和漏极均设有N型轻掺杂漏区，所述第二MOS管的源极和漏极其中之一具有N型轻掺杂漏区或者均无N型轻掺杂漏区。
  4. 一种如权利要求1所述的只读存储器的制作方法，其特征在于，包括以下步骤：
    步骤1：提供硅衬底，在所述硅衬底同时形成所述两种不同结构的存储单元的有源区；
    步骤2：在所述有源区表面形成所述两种不同结构存储单元的栅氧介质及控制栅；
    步骤3：在所述第一MOS管控制栅的两侧形成漏极及源极各自的轻掺杂漏区，同时在第二MOS管控制栅的一侧形成漏极的轻掺杂漏区或源极的轻掺杂漏区；或者仅在第一MOS管控制栅的两侧形成漏极及源极各自的轻掺杂漏区；
    步骤4：在所述第一MOS管和第二MOS管的控制栅两侧形成侧壁；
    步骤5：在具有所述侧壁的控制栅两侧同时形成所述第一MOS管漏极及源极各自的离子掺杂区和第二MOS管漏极及源极各自的离子掺杂区。
  5. 根据权利要求4所述的只读存储器的制作方法，其特征在于，所述步骤3包括以下分步骤：
    步骤31：在形成有控制栅的硅衬底表面涂覆光阻；
    步骤32：去除所述两种不同结构存储单元中即将形成所述轻掺杂漏区的区域上的光阻部分；
    步骤33：向所述去除了光阻的区域进行离子注入，形成轻掺杂漏区；
    步骤34：去除离子注入后残留在所述硅衬底表面的光阻。
  6. 根据权利要求5所述的只读存储器的制作方法，其特征在于，去除即将形成所述轻掺杂漏区的区域上的光阻部分包括以下步骤：
    提供轻掺杂漏区掩模板，将所述第一MOS管漏极和源极的轻掺杂漏区和所述第二MOS管漏极或源极的轻掺杂漏区定义在所述轻掺杂漏区掩模板上；或者仅将所述第一MOS管漏极和源极的轻掺杂漏区定义在所述轻掺杂漏区掩模板上；
    通过所述轻掺杂漏区的掩模板，曝光所述形成有控制栅的硅衬底表面的光阻，显影去除所述硅衬底表面对应于所述轻掺杂漏区掩模板上定义的轻掺杂漏区区域上的光阻部分。
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