WO2013047847A1 - Feuille de cuivre pour carte de circuits imprimés et plaque stratifiée l'utilisant - Google Patents

Feuille de cuivre pour carte de circuits imprimés et plaque stratifiée l'utilisant Download PDF

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Publication number
WO2013047847A1
WO2013047847A1 PCT/JP2012/075266 JP2012075266W WO2013047847A1 WO 2013047847 A1 WO2013047847 A1 WO 2013047847A1 JP 2012075266 W JP2012075266 W JP 2012075266W WO 2013047847 A1 WO2013047847 A1 WO 2013047847A1
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Prior art keywords
copper foil
etching
circuit
coating layer
less
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PCT/JP2012/075266
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English (en)
Japanese (ja)
Inventor
秀樹 古澤
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Jx日鉱日石金属株式会社
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Priority to KR1020147011456A priority Critical patent/KR20140071463A/ko
Publication of WO2013047847A1 publication Critical patent/WO2013047847A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/01—Layered products comprising a layer of metal all layers being exclusively metallic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/04—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material
    • B32B15/08—Layered products comprising a layer of metal comprising metal as the main or only constituent of a layer, which is next to another layer of the same or of a different material of synthetic resin
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C9/00—Alloys based on copper
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C9/00—Alloys based on copper
    • C22C9/01—Alloys based on copper with aluminium as the next major constituent
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C9/00—Alloys based on copper
    • C22C9/02—Alloys based on copper with tin as the next major constituent
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C9/00—Alloys based on copper
    • C22C9/04—Alloys based on copper with zinc as the next major constituent
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C9/00—Alloys based on copper
    • C22C9/05—Alloys based on copper with manganese as the next major constituent
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C9/00—Alloys based on copper
    • C22C9/06—Alloys based on copper with nickel or cobalt as the next major constituent
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D1/00—Electroforming
    • C25D1/04—Wires; Strips; Foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/098—Special shape of the cross-section of conductors, e.g. very thick plated conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process

Definitions

  • the present invention relates to a copper foil for a printed wiring board and a laminated board using the same, and more particularly to a copper foil for a flexible printed wiring board and a laminated board using the copper foil.
  • a printed wiring board is made by bonding an insulating substrate to a copper foil, or depositing a Ni alloy or the like on the insulating substrate and then forming a copper layer by electroplating to form a copper-clad laminate, and then etching the copper foil or copper layer surface.
  • it is manufactured through a process of forming a conductor pattern. Therefore, good etching properties are required for the copper foil or copper layer for printed wiring boards.
  • Patent Document 1 includes a silver-based coating layer made of silver or a silver-palladium alloy on a bonding surface with an insulating base material that is a constituent material of a copper-clad laminate.
  • An invention relating to a copper foil with a silver-based coating layer is disclosed.
  • the etching property of the copper foil is simply good. That is, the etching property required in recent years means that the metal derived from the surface treatment does not remain in the insulating part between the circuits and that the circuit is less skirted. If metal remains in the insulating part between the circuits, a short circuit occurs between the circuits.
  • the circuit is etched from the upper surface to the lower side (insulating substrate side), and the cross section of the circuit becomes a trapezoid.
  • the space between circuits can be narrowed, and a high-density wiring board can be obtained. If the skirting is large, the circuit is short-circuited if the space between the circuits is narrowed, so that a high-density mounting substrate cannot be manufactured.
  • Patent Document 1 forms a coating layer made of a noble metal on the roughened surface of the copper foil, so it does not suppress side etch, and a circuit with a small tail is provided. It may be difficult to produce well.
  • Etching proceeds in the thickness direction and the planar direction of the copper base material. At this time, if the etching time is long, the etching proceeds in the planar direction of the copper base material, so that the circuit cross-sectional area is reduced. There's a problem.
  • an object of the present invention is to provide a copper foil for a printed wiring board and a laminated board using the copper foil, which can be used to produce a circuit having a cross-sectional shape with a small tailing suitable for fine pitch.
  • the present inventor has performed anisotropic etching with priority in the thickness direction in order to suppress etching in the planar direction, and widened the circuit top width by suppressing side etching at a position corresponding to the upper part of the circuit.
  • anisotropic etching with priority in the thickness direction in order to suppress etching in the planar direction, and widened the circuit top width by suppressing side etching at a position corresponding to the upper part of the circuit.
  • etching is performed in the vicinity of the back side of the resist when a predetermined coating layer is formed on the copper base material to be formed in the circuit. It has been found that the oxidant in the liquid may be reduced, that is, it may be controlled so that electrons flow from the copper base toward the coating layer.
  • the present invention completed on the basis of the above knowledge, in one aspect, includes a copper foil base material and a coating layer that covers at least a part of the surface of the copper foil base material, and a coating in which electrons flow from the copper foil side during etching
  • the layer is a copper foil for a printed wiring board formed on a surface on which a resist pattern at the time of etching is formed.
  • the coating layer is made of Pd, Ir, Pt, Au, Mo, Mn, In, Ag, Sn, Ti, Ta, Nb, Cr, Ru, Rh. 1 or more types of W are included.
  • the coating layer is 600 [mu] g / dm 2 or less of Pd, 1100 ⁇ g / dm 2 or less of Ir, 1050 ⁇ g / dm 2 or less of Pt, 1000 [mu] g / dm 2 following Au, 1000 [mu] g / dm 2 or less Mo, 1000 ⁇ g / dm 2 or less of Mn, 1000 [mu] g / dm 2 or less an in, 400 of ⁇ 10000 ⁇ g / dm 2 Ag, 1000 ⁇ 50000 ⁇ g / dm 2 of Sn, 400 [mu] g / dm Any one or more of 2 or less W is included.
  • the coating layer has 20 to 250 ⁇ g / dm 2 of Pd, 30 to 500 ⁇ g / dm 2 of Ir, and 20 to 400 ⁇ g / dm 2 of Pt. , of 20 ⁇ 400 ⁇ g / dm 2 Au, 10 ⁇ 800 ⁇ g / dm 2 of Mo, 10 ⁇ 500 ⁇ g / dm 2 of Mn, 10 ⁇ 500 ⁇ g / dm 2 of in, 700 ⁇ 2000 ⁇ g / dm 2 of Ag, 10000 ⁇ 50000 ⁇ g / One or more of Sn of dm 2 and 70 to 300 ⁇ g / dm 2 of W are included.
  • the present invention is a laminate including a copper layer and a resin substrate, the laminate including the coating layer of the present invention that covers at least a part of the surface of the copper layer.
  • the present invention is a laminate of the copper foil of the present invention and a resin substrate.
  • the present invention is a printed wiring board made from the laminate of the present invention.
  • a copper foil for a printed wiring board that can produce a circuit having a cross-sectional shape with a small skirt suitable for fine pitching and a laminate using the copper foil.
  • FIG. 49 is a diagram showing the definitions of elements c and d used in the calculation of etching factors (EF) in Examples 42 to 47.
  • the electrolytic copper foil is produced by electrolytic deposition of copper from a copper sulfate plating bath onto a drum of titanium or stainless steel, and the rolled copper foil is produced by repeating plastic working and heat treatment with a rolling roll.
  • Rolled copper foil is often used for applications that require flexibility.
  • high-purity copper such as tough pitch copper and oxygen-free copper, which are usually used as conductor patterns for printed wiring boards, for example, Sn-containing copper, Ag-containing copper, Cr, Zr or Mg are added as the copper foil base material.
  • a copper alloy such as a copper alloy, a Corson copper alloy to which Ni, Si and the like are added.
  • a copper alloy foil is also included.
  • the thickness of the copper foil base material that can be used in the present invention is not particularly limited, and may be appropriately adjusted to a thickness suitable for a printed wiring board.
  • the thickness can be about 5 to 100 ⁇ m.
  • it is 30 ⁇ m or less, preferably 20 ⁇ m or less, and typically about 5 to 20 ⁇ m.
  • the copper foil base material used in the present invention is not particularly limited, but for example, a material not subjected to roughening treatment may be used.
  • the surface is generally roughened by special plating with irregularities on the order of ⁇ m, and the physical anchor effect provides adhesion to the resin.
  • a smooth foil is considered to have good characteristics, and a roughened foil may work in a disadvantageous direction.
  • the roughening process process is abbreviate
  • the coating layer is formed in at least one part of the surface on the opposite side (circuit formation plan side) of the copper foil base material with the insulating substrate.
  • the oxidant in the etching solution is reduced at a position corresponding to the upper part of the circuit, that is, on the back side of the resist. That's fine.
  • a copper foil base material is preferable as an electron supply source used for the reduction of the oxidizing agent. That is, in order for the oxidant to be reduced on the back side of the resist, it may be controlled so that electrons flow from the copper foil base toward the coating layer.
  • cupric chloride aqueous solution or a ferric chloride aqueous solution is used as an etchant
  • a coating layer in which electrons flow from the copper foil side at the time of etching is formed on a surface on which a resist pattern at the time of etching is formed.
  • the thickness of the coating layer is preferably 5 nm or less for Pd, Ir, Pt and Au, 10 nm or less for Mo, 15 nm or less for Mn and In, 100 nm or less for Ag, and 1000 nm or less for Sn.
  • 0.1 to 2 nm is preferable, for Mo, Mn, and In, 0.1 to 8 nm, for Ag, 7 to 20 nm, and for Sn, 100 to 1000 nm are more preferable. If the thickness of the coating layer is less than the above-mentioned thickness, the side etch suppression effect is not sufficient, and if it exceeds the thickness, the initial etching property may be deteriorated.
  • the coating layer can be identified by the presence of each detected peak by performing argon sputtering from the surface layer with a surface analyzer such as XPS or AES and performing chemical analysis in the depth direction.
  • a surface analyzer such as XPS or AES
  • any of Pd, Ir, Pt, Au, Mo, Mn, In, Ag, Sn, Ti, Ta, Nb, Cr, Ru, Rh, and W are preferred.
  • the adhesion amount of Pd is preferably 600 ⁇ g / dm 2 or less, more preferably 20 to 250 ⁇ g / dm 2 .
  • the amount of Ir deposited is preferably 1100 ⁇ g / dm 2 or less, more preferably 30 to 500 ⁇ g / dm 2 .
  • the adhesion amount of Pt is preferably 1050 ⁇ g / dm 2 or less, more preferably 20 to 400 ⁇ g / dm 2 .
  • the adhesion amount of Au is preferably 1000 ⁇ g / dm 2 or less, more preferably 20 to 400 ⁇ g / dm 2 .
  • the deposition amount is preferably 1000 [mu] g / dm 2 or less of Mo, and more preferably 10 ⁇ 800 ⁇ g / dm 2.
  • the adhesion amount of Mn is preferably 1000 ⁇ g / dm 2 or less, more preferably 10 to 500 ⁇ g / dm 2 .
  • the adhesion amount of In is preferably 1000 ⁇ g / dm 2 or less, more preferably 10 to 500 ⁇ g / dm 2 .
  • the amount of deposition of Ag is preferably 400 ⁇ 10000 ⁇ g / dm 2, more preferably 700 ⁇ 2000 ⁇ g / dm 2.
  • the coating layer including a Sn atom is preferably 1000 ⁇ 50000 ⁇ g / dm 2 amount of deposition of Sn, and more preferably 10000 ⁇ 50000 ⁇ g / dm 2.
  • the adhesion amount of W is preferably 400 ⁇ g / dm 2 or less, more preferably 70 to 300 ⁇ g / dm 2 .
  • Adhesion amount of Pd coating layer is 600 [mu] g / dm 2 greater, the adhesion amount of Ir is 1100 ⁇ g / dm 2 greater, the adhesion amount of Pt 1050 ⁇ g / dm 2 greater, Au of adhesion amount 1000 [mu] g / dm 2 greater than the adhesion of Mo amount 1000 [mu] g / dm 2 greater, the adhesion amount of Mn is 1000 [mu] g / dm 2 greater, the adhesion amount of in is 1000 [mu] g / dm 2 greater, the adhesion amount of Ag is 10000 / dm 2 greater, the adhesion amount of Sn is 50000 ⁇ g / dm 2 If the adhesion amount of W and W is more than 400 ⁇ g / dm 2 , the initial etching property may be adversely affected. Further, when the adhesion amount of Ag is less than 400 ⁇ g / dm 2 and
  • An antirust treatment layer can be further formed on the outermost layer on the coating layer in order to enhance the antirust effect. Moreover, in order to suppress the oxidation by heat processing further between the coating layer and copper foil, you may form the base layer which has oxidation resistance.
  • the copper foil for printed wiring boards according to the present invention can be formed by a sputtering method. That is, at least a part of the surface of the copper foil base material is coated with the coating layer by a sputtering method. Specifically, a coating layer in which electrons flow from the copper foil side during etching is formed on the etching surface side of the copper foil by sputtering.
  • the coating layer is not limited to the sputtering method, and may be formed by, for example, a wet plating method such as electroplating or electroless plating.
  • the metal of the coating layer may be formed of a single layer or an alloy layer.
  • a Mo single layer is obtained when formed by a dry process such as sputtering.
  • an Mo single layer cannot be obtained, so an alloy layer such as Ni may be used.
  • the metal which cannot form a fine pitch pattern with bad initial etching property can solve this problem by using an alloy layer with a metal which is more easily corroded than itself rather than a single layer.
  • an initial etching property can be improved by forming an alloy layer with Ni by electroplating as compared with a W single layer.
  • the copper foil for printed wiring boards which concerns on this invention removes an oxide film etc. by a well-known means as a pretreatment before performing a sputtering process.
  • a printed wiring board (PWB) can be manufactured according to a conventional method using the copper foil according to the present invention. Below, the example of the manufacturing method of a printed wiring board is shown.
  • a laminated body is manufactured by bonding a copper foil and an insulating substrate.
  • the insulating substrate on which the copper foil is laminated is not particularly limited as long as it has characteristics applicable to a printed wiring board.
  • paper base phenolic resin, paper base epoxy resin, synthetic fiber for rigid PWB Use cloth base epoxy resin, glass cloth / paper composite base epoxy resin, glass cloth / glass non-woven composite base epoxy resin, glass cloth base epoxy resin, etc., use polyester film, polyimide film, etc. for FPC I can do things.
  • a prepreg in which a base material such as glass cloth is impregnated with a resin and the resin is cured to a semi-cured state is prepared. It can be carried out by superposing a copper foil on the prepreg from the opposite surface of the coating layer and heating and pressing.
  • a polyimide film or a polyester film and a copper foil can be bonded using an epoxy or acrylic adhesive (three-layer structure).
  • a polyimide varnish (polyamic acid varnish), which is a polyimide precursor, is applied to a copper foil and heated to form an imidization or on a polyimide film.
  • a laminating method in which a thermoplastic polyimide is applied to the substrate, a copper foil is overlaid thereon, and heated and pressed.
  • an anchor coating material such as thermoplastic polyimide in advance before applying the polyimide varnish.
  • the laminate according to the present invention can be used for various printed wiring boards (PWB) and is not particularly limited.
  • PWB printed wiring boards
  • the laminate according to the present invention is not limited to the above-described copper-clad laminate obtained by attaching a copper foil to a resin, and is a metalizing material in which a copper layer is formed on the resin by sputtering or plating. Also good.
  • a resist is applied to the surface of the coating layer formed on the copper foil of the laminate produced as described above, the pattern is exposed with a mask, and developed to form a resist pattern. Subsequently, the coating layer exposed at the opening of the resist pattern is removed using a reagent.
  • a reagent one containing hydrochloric acid, sulfuric acid or nitric acid as a main component is preferably used for reasons such as availability.
  • the laminate is immersed in an etching solution composed of a cupric chloride aqueous solution or a ferric chloride aqueous solution.
  • the oxidant in the etching solution is reduced at a position corresponding to the upper part of the circuit, that is, the back side of the resist pattern, and side etching at the upper part of the circuit is suppressed.
  • the etching of the copper circuit pattern proceeds substantially vertically.
  • unnecessary portions of copper are removed, and then the etching resist is removed and removed to expose the circuit pattern.
  • a heat-resistant layer may be formed in advance on the surface of the copper foil base before forming the coating layer.
  • the circuit on the copper foil surface of the printed wiring board formed by etching from the coating layer side is not usually formed with two long side surfaces perpendicular to the insulating substrate. From the surface of the foil downward, that is, toward the resin layer, it is formed so as to spread toward the end (generation of sagging).
  • the two long side surfaces each have an inclination angle ⁇ with respect to the surface of the insulating substrate. It is important to reduce the circuit pitch as much as possible for miniaturization (fine pitch) of the circuit pattern that is currently required. However, if this inclination angle ⁇ is small, the sagging increases accordingly, The pitch becomes wider.
  • the inclination angle ⁇ is usually not completely constant in each circuit and circuit. If the variation in the inclination angle ⁇ is large, the circuit quality may be adversely affected. Therefore, in the circuit on the copper foil surface of the printed wiring board formed by etching from the coating layer side, the two long side surfaces each have an inclination angle ⁇ of 65 to 90 ° with respect to the insulating substrate surface, In addition, it is desirable that the standard deviation of tan ⁇ in the same circuit is 1.0 or less.
  • the etching factor is preferably 1.5 or more, and more preferably 2.5 or more when the circuit pitch is 50 ⁇ m or less.
  • the coating layer on the back side of the resist and the copper foil base [17 ⁇ m thick copper foil (JX Nippon Mining & Metals C1100) were regarded as electrodes, respectively, immersed in an etching solution, and the current was measured.
  • the coating layer was formed on the copper foil by sputtering to a thickness of 200 nm, and the back side of the copper foil was covered with an acid-resistant tape so that the area exposed to the etching solution was 23 cm 2 (hereinafter referred to as surface treatment electrode) ).
  • the copper foil side of the counter electrode was also covered with an acid-resistant tape so that the area of the exposed portion was 23 cm 2 (hereinafter, copper foil electrode).
  • a digital multimeter (ADC Corporation, 7351A / E) was connected to the copper foil electrode and the surface treatment electrode with a lead wire so that the current would be positive when electrons flowed from the copper foil electrode to the surface treatment electrode.
  • the conditions of the electrolytic solution in which both electrodes are immersed are as follows.
  • the composition of the etching solution was a general one. Composition: CuCl 2 2.0M + HCl 2.3M Liquid temperature: 50 ° C Rotation speed: 200rpm
  • the simple substance of the various metals used for sputtering used the thing of purity 3N. The amount of adhesion was adjusted by changing the output.
  • the surface-treated copper foil surface of the laminate was degreased with acetone and immersed in dilute sulfuric acid for 30 seconds to remove surface dirt and an oxidized layer.
  • a liquid resist manufactured by Tokyo Ohka Kogyo Co., Ltd., OFPR-800LB
  • the resist thickness after drying was adjusted to 1 ⁇ m.
  • 10 circuits were printed by exposure, and etching was performed under the following conditions to form circuits. After the etching, the resist was peeled off by being immersed in an aqueous NaOH solution (100 g / L) at 45 ° C. for 1 minute.
  • the adhesion amount of the coating layer is measured by applying about 50% of the copper layer to a solution of HNO 3 (2% by weight) and HCl (5% by weight). After dissolution, the metal concentration in the solution was quantified with an ICP emission spectroscopic analyzer (SFC-3100, manufactured by SII Nanotechnology Inc.), and the amount of metal per unit area ( ⁇ g / dm 2 ) was calculated. The measurement results are shown in Table 2.
  • Etching factor Table 3 shows the average value and deviation of the etching factor.
  • Example 48 Coating layer containing W: sputtering
  • a W target purity 3N
  • a current flowing between the copper foil and the W layer in the same procedure as in Examples 1 to 47 The direction of was measured.
  • a W layer was formed on the S surface of the copper foil by sputtering using a W target (purity 3N).
  • a resist pattern with a pitch of 40 ⁇ m or 200 ⁇ m was formed by the same procedure as in Examples 1 to 47, and a circuit was formed by etching.
  • Experimental conditions and results are shown in Tables 1-3.
  • Example 48 is considered to suggest that electrons flow from the copper foil side to the W side even when oxides and metals coexist, and that the oxidizing agent is reduced.
  • Example 49 in order to form the Mo layer by electroplating, an alloy layer with Ni was formed under the following conditions.
  • Bath composition Nickel sulfate hexahydrate 0.1M Sodium molybdate dihydrate 0.2M Trisodium citrate dihydrate 0.2M Temperature: 30 ° C Current density: 2A / dm2 Time: 12 seconds
  • a resist pattern with a pitch of 40 ⁇ m was formed on the surface on which this alloy layer was formed by the same procedure as in Examples 1 to 48, and a circuit was formed by etching.
  • Experimental conditions and results are shown in Tables 2 and 3. According to the experimental results, the Mo adhesion amount was 433 ⁇ g / dm 2 .
  • the etching factor of the circuit was as high as 5.9.
  • a resist pattern with a pitch of 40 ⁇ m was formed on the surface on which the W layer was formed by the same procedure as in Examples 1 to 49, and a circuit was formed by etching. Experimental conditions and results are shown in Tables 2 and 3. According to the experimental results, since the initial etching property was improved as compared with the single layer because of the alloy with Ni, a circuit with a pitch of 40 ⁇ m could be formed.

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Laminated Bodies (AREA)

Abstract

La présente invention concerne une feuille de cuivre pour une carte de circuits imprimés et une plaque stratifiée l'utilisant, qui permettent la formation d'un circuit possédant une coupe transversale trapézoïdale très compacte, ce qui convient à la fabrication de pas fins. La feuille de cuivre pour carte de circuits imprimés possède un matériau de feuille de cuivre et une couche de recouvrement permettant de recouvrir au moins une partie de la surface du matériau de feuille de cuivre. La couche de recouvrement vers laquelle des électrons circulent depuis la feuille de cuivre pendant la gravure est formée sur la surface où un motif de réserve est formé pendant la gravure.
PCT/JP2012/075266 2011-09-30 2012-09-28 Feuille de cuivre pour carte de circuits imprimés et plaque stratifiée l'utilisant WO2013047847A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020147011456A KR20140071463A (ko) 2011-09-30 2012-09-28 프린트 배선판용 구리박 및 그것을 사용한 적층판

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JP2011-218559 2011-09-30
JP2011218559 2011-09-30

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WO2013047847A1 true WO2013047847A1 (fr) 2013-04-04

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002176242A (ja) * 2000-12-05 2002-06-21 Nikko Materials Co Ltd 電子回路用銅箔及び電子回路の形成方法
JP2007243043A (ja) * 2006-03-10 2007-09-20 Sumitomo Metal Mining Co Ltd フレキシブル配線基板およびその製造方法
JP2011166018A (ja) * 2010-02-12 2011-08-25 Jx Nippon Mining & Metals Corp プリント配線板用銅箔
JP2011171621A (ja) * 2010-02-22 2011-09-01 Jx Nippon Mining & Metals Corp 抵抗層付き銅箔並びに銅張積層板及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002176242A (ja) * 2000-12-05 2002-06-21 Nikko Materials Co Ltd 電子回路用銅箔及び電子回路の形成方法
JP2007243043A (ja) * 2006-03-10 2007-09-20 Sumitomo Metal Mining Co Ltd フレキシブル配線基板およびその製造方法
JP2011166018A (ja) * 2010-02-12 2011-08-25 Jx Nippon Mining & Metals Corp プリント配線板用銅箔
JP2011171621A (ja) * 2010-02-22 2011-09-01 Jx Nippon Mining & Metals Corp 抵抗層付き銅箔並びに銅張積層板及びその製造方法

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JPWO2013047847A1 (ja) 2015-03-30
TW201519712A (zh) 2015-05-16

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