WO2013018357A1 - 半導体パワーモジュール、半導体パワーモジュールの製造方法、回路基板 - Google Patents
半導体パワーモジュール、半導体パワーモジュールの製造方法、回路基板 Download PDFInfo
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- WO2013018357A1 WO2013018357A1 PCT/JP2012/004865 JP2012004865W WO2013018357A1 WO 2013018357 A1 WO2013018357 A1 WO 2013018357A1 JP 2012004865 W JP2012004865 W JP 2012004865W WO 2013018357 A1 WO2013018357 A1 WO 2013018357A1
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- bonding
- semiconductor element
- multilayer substrate
- insulating
- power module
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Definitions
- the present invention relates to a semiconductor power module in which a semiconductor element is mounted on a circuit board, a method for manufacturing the semiconductor power module, and a circuit board.
- an inorganic material is used in addition to a conventional organic material used as a sealing material in the gap between the bumps between the ceramic multilayer substrate and the semiconductor element.
- a conventional organic material used as a sealing material in the gap between the bumps between the ceramic multilayer substrate and the semiconductor element.
- the heat dissipation performance of the semiconductor element is decreased due to the decrease in the thermal diffusion performance from the semiconductor element to the ceramic multilayer substrate, the bonding strength between the ceramic multilayer substrate and the semiconductor element is decreased, and the reliability There was a problem of deterioration of characteristics.
- the present invention has been made to solve at least a part of the problems described above, and can be realized as the following forms.
- a semiconductor power module is provided.
- the semiconductor power module is formed on the first surface of the multilayer substrate; a multilayer substrate on which vias and wiring patterns are formed; a semiconductor element disposed on the first surface side of the multilayer substrate; A bonding layer for bonding the multilayer substrate and the semiconductor element; and the bonding layer is a planar conductive bonding portion disposed at a first portion corresponding to the via, and the semiconductor element A conductive joint formed by a conductive protrusion formed on the conductive member, and a conductive connection portion that electrically connects the protrusion and the multilayer substrate; and a second part different from the first part And a planar insulating bonding portion mainly composed of an inorganic material.
- the bonding layer is formed in a planar shape, generation of voids between the multilayer substrate and the semiconductor element can be suppressed when the multilayer substrate and the semiconductor element are bonded. Therefore, the thermal diffusion performance from the semiconductor element to the multilayer substrate and the bonding strength between the multilayer substrate and the semiconductor element can be improved.
- the multilayer substrate and the bonding layer, and the semiconductor element and the bonding layer are bonded by diffusion bonding; and the semiconductor power module is further bonded to the multilayer substrate and the bonding
- a diffusion layer formed at the time of the diffusion bonding may be provided between the layer and the semiconductor element and the bonding layer.
- the semiconductor power module of this embodiment at the time of diffusion bonding between the multilayer substrate and the bonding layer, and the bonding layer and the semiconductor element, the bonding surface between the multilayer substrate and the bonding layer, and the bonding surface between the bonding layer and the semiconductor element.
- a diffusion layer is formed by the diffusion of the generated atoms. Therefore, the bonding strength between the multilayer substrate and the bonding layer and between the bonding layer and the semiconductor element can be improved.
- the first joining start temperature which is the joining start temperature of the material constituting the conductive joint portion
- the second joining start temperature of the material constituting the insulating joint portion It may be lower than the joining start temperature.
- the conductive joint is joined before the insulating joint. Therefore, the conductive connection portion and the projecting portion of the semiconductor element, and the conductive junction portion and the wiring substrate are joined, that is, between the conductive connection portion and the projecting portion of the semiconductor element, and the conductive junction portion and the wiring.
- Softening deformation of the insulating bonding portion is started in a state where there is no gap between the substrates, and bonding between the insulating bonding portion and the semiconductor element and between the insulating bonding portion and the wiring substrate is performed. Therefore, it is possible to suppress a decrease in the conductive performance of the conductive bonding portion due to the material constituting the insulating bonding portion entering between the conductive connection portion and the electrode pad, in other words, mixing into the conductive bonding portion.
- the first joining start temperature is equal to or higher than a sintering start temperature that is a temperature at which at least a part of the material constituting the conductive joint starts a sintering reaction
- the second joining start temperature may be equal to or higher than a sintering start temperature which is a temperature at which at least a part of the material constituting the insulating joint starts a sintering reaction.
- the first joining start temperature is set to be equal to or higher than the temperature at which at least a part of the material constituting the conductive joint starts the sintering reaction
- the second joining start temperature is the insulating joining.
- At least a part of the material constituting the part is set to a temperature equal to or higher than the temperature at which the sintering reaction starts. Therefore, each of the conductive joint and the insulating joint can be joined to another member without heating to the melting point.
- the first joining start temperature may be the melting start temperature of the material constituting the conductive joining portion
- the second joining start temperature may be the melting start temperature of the material constituting the insulating joining portion. If it carries out like this, a conductive junction part and an insulation junction part can be fuse
- the manufacturing method of a semiconductor power module includes a substrate manufacturing step of manufacturing a multilayer substrate having a via and a wiring pattern; and a planar shape for conducting the wiring pattern and the semiconductor element in a first portion corresponding to the via.
- a planar bonding layer for bonding the multilayer substrate and the semiconductor element is formed between the multilayer substrate and the semiconductor element by the bonding portion and the protruding portion. The Therefore, generation
- a temperature at which a material constituting the conductive connection portion starts joining with the semiconductor element is defined as a first joining start temperature; and a material constituting the insulating junction portion Is a temperature at which bonding with the multilayer substrate and the semiconductor element starts, and a temperature higher than the first bonding start temperature is set as a second bonding start temperature; and the bonding step includes the multilayer substrate and the bonding Bonding the conductive connection portion and the protruding portion of the semiconductor element by thermocompression bonding the portion and the semiconductor element at the first bonding start temperature; and the conductive connection portion and the semiconductor element After the bonding with the protruding portion, the multilayer substrate, the bonding portion, and the semiconductor element are thermocompression bonded at the second bonding start temperature, whereby the multilayer substrate, the bonding portion, and A step of bonding the said junction semiconductor device may include a.
- the conductive joint portion is joined before the insulating joint portion. Therefore, the conductive connection portion and the protruding portion of the semiconductor element, and the conductive connection portion and the wiring substrate are joined, that is, between the conductive connection portion and the protruding portion of the semiconductor element, and the conductive connection portion and the wiring substrate. In the state where there is no gap between them, softening deformation of the insulating bonding portion is started, and bonding between the insulating bonding portion and the semiconductor element and between the insulating bonding portion and the wiring board is performed. Therefore, it is possible to suppress a decrease in the conductive performance of the conductive connection portion due to the material constituting the insulating joint portion entering between the conductive connection portion and the protruding portion and mixing into the conductive connection portion.
- the first joining start temperature is equal to or higher than a sintering start temperature at which at least a part of the material constituting the conductive connection portion starts a sintering reaction
- the second joining start temperature may be equal to or higher than a sintering start temperature at which at least a part of the material constituting the insulating joint starts a sintering reaction.
- the first joining start temperature is set to be equal to or higher than a temperature at which at least a part of the material constituting the conductive connection portion starts a sintering reaction
- the second joining start temperature is set to a temperature at which the sintering reaction is started. Therefore, each of the conductive connection portion and the insulating joint portion can be joined to another member without heating to the melting point.
- the first joining start temperature may be the melting start temperature of the material constituting the conductive connection portion
- the second joining start temperature may be the melting start temperature of the material constituting the insulating joint portion. If it carries out like this, a conductive connection part and an insulation junction part can be fuse
- a temperature at which a material constituting the conductive connection portion starts joining with the semiconductor element is a first joining start temperature
- a material constituting the insulating joint is A temperature at which bonding with the multilayer substrate and the semiconductor element starts, and a temperature higher than the first bonding start temperature is defined as a second bonding start temperature
- the first bonding start temperature is: After being held for a predetermined time, the heating may be performed based on a temperature profile that is set so that the second joining start temperature is held for a predetermined time.
- the bonding portion, the wiring board, and the semiconductor element are bonded based on the temperature profile having a stepwise temperature change. Accordingly, diffusion bonding can be performed with a simple configuration while performing multi-stage temperature changes, and manufacturing efficiency can be improved.
- the first disposing step includes a step of disposing an insulating joint having an opening at the first portion on the first surface.
- D1 representing the thickness of the conductive connection portion, the thickness of the insulating joint portion, including the step of fitting the protruding portion into the opening portion and disposing the semiconductor element on the joint portion.
- d3 representing the height of the protruding portion may satisfy d3> d2-d1.
- the semiconductor element can be disposed in the recessed portion while ensuring the electrical connection between the protruding portion and the conductive connecting portion.
- the semiconductor element when the semiconductor element is arranged on the bonding layer, the semiconductor element floats from the surface of the bonding layer. However, the protrusion is melted by the heating at the time of bonding, and the semiconductor element is pressurized in the molten state. The element and the bonding layer are bonded to each other without a gap.
- the insulating bonding portion in the step of disposing the insulating bonding portion, is connected to an end where the multilayer substrate is bonded from an end portion where the semiconductor element is bonded. You may arrange
- the insulating junction is formed in a shape that becomes narrower from the semiconductor element side toward the multilayer substrate side. Therefore, the contact area between the insulating junction and the semiconductor element can be made wider than the contact area between the insulating junction and the semiconductor element when the insulating junction is formed in a substantially columnar shape. Therefore, the thermal diffusion performance from the semiconductor element to the multilayer substrate can be improved while ensuring the bonding strength and insulation performance between the multilayer substrate and the semiconductor element.
- the insulating joint portion in the step of disposing the insulating joint portion, may be disposed so that the insulating joint portion has a tapered shape.
- the insulating junction is formed in a tapered shape. Therefore, the insulating junction can be easily formed in a shape that narrows from the semiconductor element side toward the multilayer substrate side.
- a circuit board includes: a multilayer board on which vias and wiring patterns are formed; and a bonding layer disposed on the first surface of the multilayer board and for bonding a semiconductor element to the multilayer board;
- the bonding layer is disposed at a first portion corresponding to the via, and is electrically connected to the wiring pattern and the semiconductor element, and at least the first surface side is formed in a planar shape; and a conductive connection portion;
- an insulating bonding portion which is disposed in a second portion different from the first portion and which is mainly composed of an inorganic material, and at least the first surface side is formed in a planar shape.
- the semiconductor element and the multilayer substrate are bonded together in a plane, so that generation of a gap between the multilayer substrate and the semiconductor element can be suppressed. Therefore, the thermal diffusion performance from the semiconductor element to the multilayer substrate and the bonding strength between the multilayer substrate and the semiconductor element can be improved.
- the conductive connection portion is formed to be thinner than the insulating bonding portion, and the bonding layer includes a recess formed by the insulating bonding portion and the conductive connecting portion.
- d1 representing the thickness of the conductive connecting portion
- d2 representing the thickness of the insulating junction
- D3 representing the height of the protrusion may satisfy d3> d2-d1.
- the conductive connecting portion and the insulating joint portion in the fitting of the projecting portion into the recess, have the thickness of the conductive connecting portion d1, the insulating joint portion the thickness d2, and the projecting portion of the projecting portion.
- the thickness is expressed as d3, it is formed so as to satisfy d3> d2-d1. Therefore, when the semiconductor element is disposed in the recess, the electrical connection between the protruding portion and the conductive connection portion can be reliably ensured.
- the insulating bonding portion may be formed in a tapered shape from an end portion where the semiconductor element is bonded to an end portion where the multilayer substrate is bonded.
- the insulating junction is formed in a shape that becomes narrower from the semiconductor element side toward the multilayer substrate side. Therefore, the contact area between the insulating junction and the semiconductor element can be made wider than the contact area between the insulating junction and the semiconductor element when the insulating junction is formed in a substantially columnar shape. Therefore, the thermal diffusion performance from the semiconductor element to the multilayer substrate can be improved while ensuring the bonding strength and insulation performance between the multilayer substrate and the semiconductor element.
- the insulating bonding portion may be formed in a tapered shape.
- the insulating junction is formed in a tapered shape. Therefore, the insulating junction can be easily formed in a shape that narrows from the semiconductor element side toward the multilayer substrate side.
- a plurality of constituent elements of each aspect of the present invention described above are not indispensable, and some or all of the effects described in the present specification are to be solved to solve part or all of the above-described problems.
- technical features included in one embodiment of the present invention described above A part or all of the technical features included in the other aspects of the present invention described above may be combined to form an independent form of the present invention.
- Sectional drawing which shows schematic structure of the semiconductor power module 10 in 1st Example.
- the top view which shows the semiconductor power module 30 in 2nd Example.
- Explanatory drawing explaining the semiconductor power module 1010 in 5th Example Process drawing explaining the manufacturing method of the semiconductor power module 1010 in 5th Example. Explanatory drawing explaining the arrangement
- FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor power module 10 in the first embodiment.
- FIG. 2 is an explanatory diagram for explaining the circuit board 20 in the first embodiment.
- the semiconductor power module 10 includes a circuit board 20 and a semiconductor element 130.
- the circuit board 20 includes a ceramic multilayer substrate 100, a bonding layer 110, and a diffusion layer 120.
- the ceramic multilayer substrate 100 is formed of a ceramic material.
- the ceramic material for example, aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), or the like is used.
- the ceramic multilayer substrate 100 is electrically connected between the first surface 105 on which the semiconductor element is mounted and the other second surface 106 facing the surface and on which other electronic components such as a control circuit and a capacitor can be mounted.
- the wiring pattern 109 is formed on the surface of the ceramic multilayer substrate 100 and the surface of the inner layer.
- the wiring pattern formed on the surface of the ceramic multilayer substrate 100 is omitted.
- Electrode lands (not shown) for mounting the semiconductor element 130 and other electronic components are formed on the first surface 105 and the second surface 106 of the ceramic multilayer substrate 100.
- the semiconductor element 130 is electrically connected to the electrode terminal 104 disposed on the second surface 106 via the inner layer via hole 101 and the wiring pattern 109.
- the bonding layer 110 is a planar thin film layer that is disposed on the first surface 105 of the ceramic multilayer substrate 100 and includes a conductive bonding portion 111 and an insulating bonding portion 112.
- the conductive bonding portion 111 includes a conductive connection portion 111a and an electrode pad 131 of the semiconductor element 130, and electrically connects the semiconductor element 130 and the ceramic multilayer substrate 100.
- the conductive connection portion 111a is formed with a conductive metal as a main component, and is formed on the first surface 105 of the ceramic multilayer substrate 100 and corresponding to the inner layer via hole 101 as shown in FIG. Arranged on a portion 107 (indicated by a thick solid line).
- a conductive metal for example, copper, silver, aluminum metal, or the like may be used as the conductive metal.
- the conductive connecting portion 111a is formed thinner than an insulating bonding portion 112 described later, and a recess is formed by the insulating bonding portion 112 and the conductive connecting portion 111a.
- the conductive bonding portion 111 is formed by arranging the electrode pad 131 so as to fit in the recess.
- the electrode pad 131 corresponds to a “projection” in the claims. The same applies to the second to fourth embodiments described below.
- the insulating joint 112 insulates the semiconductor element 130 and the ceramic multilayer substrate 100.
- the insulating bonding portion 112 is disposed on the first surface 105 of the ceramic multilayer substrate 100 and in a second portion 108 (shown by a thick broken line) different from the first portion 107.
- the main component is an insulating inorganic material, and it is formed of powdered glass that is softened by a heating process at the time of mounting a semiconductor element.
- the powder glass is formed as a mixed phase of, for example, ZnO—B 2 O 3 —SiO 2 , silicon oxide, zinc oxide, boron oxide, bismuth oxide, or the like.
- the second portion 108 includes a portion excluding the portion where the conductive joint 111 which is the first portion 107 is disposed.
- the conductive bonding portion 111 and the insulating bonding portion 112 have substantially the same thickness so that the bonding layer 110 becomes a uniform plane. Further, the surface of the bonding layer 110 facing the semiconductor element 130 side is also formed to be a uniform plane.
- the uniform plane includes a slight curve or unevenness
- the bonding layer 110 has a uniform plane means that the bonding layer 110 has a first surface of the ceramic multilayer substrate.
- the surface facing the surface 105 is formed along the shape of the first surface 105, the conductive bonding portion 111 and the insulating bonding portion 112 are continuously formed flat, and the semiconductor of the bonding layer 110
- the surface facing the element 130 side is formed along the shape of the surface facing the bonding layer 110 of the semiconductor element 130.
- the insulating joint 112 includes the filler 115 to such an extent that the insulating performance does not deteriorate.
- the filler 115 includes a metal filler or an inorganic filler made of copper, aluminum powder, or the like.
- the inorganic filler is preferably a high heat dissipation characteristic filler such as ceramics made of boron oxide, alumina, silicon nitride, aluminum nitride or the like.
- the diffusion layer 120 is a layer formed by diffusion bonding between the ceramic multilayer substrate 100 and the bonding layer 110.
- the diffusion layer 120 includes a conductive diffusion part 121 and an insulating diffusion part 122.
- the conductive diffusion portion 121 is formed by diffusion bonding between the ceramic multilayer substrate 100 and the conductive connection portion 111 a of the bonding layer 110.
- the insulating diffusion portion 122 is formed by diffusion bonding between the ceramic multilayer substrate 100 and the insulating bonding portion 112 of the bonding layer 110.
- Insulating diffusion part 122 may contain filler 115, similarly to insulating joining part 112.
- FIG. 1 for convenience of explanation, the boundary between the conductive diffusion portion 121 and the insulating diffusion portion 122 is clearly described, but the boundary between the conductive diffusion portion 121 and the insulating diffusion portion 122 may be ambiguous.
- the semiconductor element 130 includes an electrode pad 131.
- the electrode pad 131 is made of, for example, gold (Au) as a main component.
- the semiconductor element 130 is disposed on the bonding layer 110 such that the electrode pad 131 is in contact with the conductive connection portion 111 a of the bonding layer 110.
- the semiconductor element 130 is electrically connected to the ceramic multilayer substrate 100 via the electrode pad 131 and the conductive connection portion 111a (that is, the conductive joint portion 111).
- FIG. 3 is a process diagram for explaining a method of manufacturing the semiconductor power module 10 in the first embodiment.
- the ceramic multilayer substrate 100 on which the inner layer via hole 101 and the wiring pattern 109 are formed is manufactured (step S10).
- Fabrication of the ceramic multilayer substrate 100 includes forming a thin-film electrode land for mounting the semiconductor element 130 and other electronic components on the surface of the ceramic multilayer substrate 100.
- the electrode land is formed by a printing method using a conductive paste, physical vapor deposition (PVD: Physical Vapor Deposition) or chemical vapor deposition (CVD: Chemical Vapor Deposition).
- step S10 corresponds to the “substrate manufacturing process” in the claims.
- the conductive connection part 111a is arranged on the first surface 105 of the ceramic multilayer substrate 100 and in the first part corresponding to the inner layer via hole 101 (step S12).
- FIG. 3 is an explanatory diagram for explaining the step of arranging the conductive connection portion 111a in step S12.
- a metal protrusion whose main component is a metal species that is melted by a heating process in step S18 to be described later is formed as a conductive connecting portion 111a. This metal protrusion is also called a bump.
- the bump may be formed by a ball mounting method in which a metal formed in a ball shape is disposed at a desired position and is formed into a columnar shape by heat treatment, or the first surface 105 of the ceramic multilayer substrate 100 may be formed.
- the first portion 107 of the first surface 105 may be masked with a photolithographic pattern, and metal bumps may be formed at desired positions by plating.
- the insulating joint 112 is disposed on a second portion different from the first portion on the first surface 105 of the ceramic multilayer substrate 100 on which the conductive connection portion 111a is disposed (step S14). Specifically, powder glass and a thermally decomposable organic binder are kneaded using a solvent such as an organic solvent or water to produce a glass powder paste.
- the first surface 105 is printed by screen printing so as to fill the gap of the conductive connection portion 111a.
- FIG. 5 is an explanatory diagram for explaining screen printing of the insulating joint 112 in step S14.
- the screen printing machine 200 includes a screen 202, a squeegee 203, and a squeegee holder 204.
- an opening is formed only in a portion excluding a portion corresponding to the conductive connection portion 111a, that is, a portion corresponding to the insulating bonding portion 112.
- the glass powder paste 250 is placed on the screen 202 and the squeegee 203 is slid from the screen 202.
- step S12 and step S14 correspond to the “first arrangement step” in the claims.
- the semiconductor element 130 is disposed on the formed joint 110a (step S16). Specifically, the semiconductor element 130 is arranged so that the electrode pad 131 is fitted into a recess formed by the conductive connection portion 111 a and the insulating bonding portion 112. When the conductive connection portion 111a and the electrode pad 131 are in contact with each other, conduction between the semiconductor element 130 and the conductive connection portion 111a is ensured.
- step S16 corresponds to the “second arrangement step” in the claims.
- FIG. 6 is an explanatory diagram for explaining the bonding process of the semiconductor power module 10 in the first embodiment.
- the ceramic multilayer substrate 100, the bonding layer 110, and the semiconductor element 130 are pressurized and heated to a temperature at which the conductive connection portion 111a and the insulating bonding portion 112 are thermally fused.
- the conductive connecting portion 111a, the insulating bonding portion 112, the first surface 105 of the ceramic multilayer substrate 100, and the surface of the semiconductor element 130 made of the conductive bonding portion 111 and the insulating protective film are melted.
- step S18 corresponds to the “joining step” in the claims.
- atoms are bonded at the bonding surface between the ceramic multilayer substrate 100 and the bonding layer 110.
- the diffusion layer 120 is formed, and the ceramic multilayer substrate 100 and the bonding layer 110 are bonded.
- a cut surface cut in a direction perpendicular to the ceramic multilayer substrate 100, the bonding layer 110, and the semiconductor element 130 is composed of a compound semiconductor and a protective layer on the surface thereof.
- the interface between the semiconductor element 130 and the bonding layer 110 and the interface between the bonding layer 110 and the surface of the ceramic multilayer substrate 100 made of a ceramic component (alumina, silicon nitride, aluminum nitride, etc.) are indicated by thick solid lines in FIG. These are arranged in a substantially straight line, and do not include minute defects such as bubbles. Inevitable voids on the order of microns are not included in the defects in the embodiments.
- the size of the bubble determined as a defect may be, for example, 100 ⁇ m or more.
- each of the interfaces has a diffusion layer 120 formed by diffusing constituent components of the bonding layer 110 with respect to the semiconductor element 130 and the ceramic multilayer substrate 100.
- These layers are layers in which surface components of the semiconductor element 130 (components for forming a protective film such as Zr and Ti) and ceramic components (such as aluminum and nitrogen) of the ceramic multilayer substrate 100 are mixed by mapping analysis using EDS, EPMA, and the like. Is defined as the layer in which is formed.
- the bonding layer 110 is formed in a planar shape, that is, the surface of the bonding layer 110 facing the ceramic multilayer substrate 100 is the second surface of the ceramic multilayer substrate 100.
- the surface facing the semiconductor element 130 of the bonding layer 110 is also formed flat along the surface shape of the semiconductor element 130 on the bonding layer 110 side.
- the insulating bonding portion 112 of the bonding layer 110 is formed mainly of an inorganic material such as glass, which has a higher thermal conductivity than the organic material. Therefore, the thermal diffusion performance from the semiconductor element 130 to the ceramic multilayer substrate 100 can be improved.
- Each member is thermally expanded by heating at the time of bonding of the semiconductor power module 10 (step S18 in FIG. 3), and stress is generated between the ceramic multilayer substrate 100 and the bonding layer 110, and between the bonding layer 110 and the semiconductor element 130.
- the linear thermal expansion coefficient of the glass component that is the main component of the insulating joint 112 is higher than that of the metal that is the main component of the conductive connection portion 111a. Close to the coefficient of linear thermal expansion. For this reason, the stress generated at the boundary between the conductive connecting portion 111 a and the ceramic multilayer substrate 100 and the semiconductor element 130 is larger than the stress generated at the boundary between the insulating joint 112 and the ceramic multilayer substrate 100 and the semiconductor element 130.
- the semiconductor power module 10 of the first embodiment since the insulating bonding portion 112 is disposed around the conductive connecting portion 111a, the deformation of the conductive connecting portion 111a can be suppressed by the insulating bonding portion 112. Therefore, the stress generated between the conductive connection portion 111a and the ceramic multilayer substrate 100 and the semiconductor element 130 can be distributed to the interface between the conductive connection portion 111a and the insulating bonding portion 112. Therefore, stress generated in a concentrated manner between the bonding layer 110 and the ceramic multilayer substrate 100 and the semiconductor element 130 can be dispersed, so that damage to the semiconductor power module 10 can be suppressed and the reliability of the semiconductor power module 10 can be improved.
- the diffusion layer 120 is formed between the ceramic multilayer substrate 100 and the bonding layer 110 when the ceramic multilayer substrate 100 and the bonding layer 110 are diffusion bonded. Accordingly, the bonding strength between the ceramic multilayer substrate 100 and the bonding layer 110 can be improved.
- the insulating bonding portion 112 of the bonding layer 110 and the insulating diffusion portion 122 of the diffusion layer 120 include the filler 115 having heat transfer performance and heat dissipation performance.
- the thermal diffusion performance from the element 130 to the ceramic multilayer substrate 100 can be improved.
- Second embodiment In the first embodiment, the semiconductor power module 10 on which only one semiconductor element 130 is mounted has been described. In the second embodiment, a semiconductor power module on which a plurality of semiconductor elements are mounted will be described with reference to FIGS.
- FIG. 7 is a plan view showing the semiconductor power module 30 in the second embodiment.
- FIG. 8 is a cross-sectional view showing a semiconductor power module 30 in the second embodiment.
- FIG. 8 shows a cross section taken along the line AA in FIG.
- the semiconductor power module 30 of the second embodiment includes a ceramic multilayer substrate 300, a bonding layer 310, a diffusion layer 320, and a plurality of (six in the second embodiment) semiconductor elements 330.
- the bonding layer 310 includes a conductive bonding portion 311 including a conductive connection portion 311a and an electrode pad 331 of the semiconductor element 330, and an insulating bonding portion 312.
- the diffusion layer 320 includes a conductive diffusion portion 321 and an insulating diffusion portion 322. .
- the ceramic multilayer substrate 300, the bonding layer 310, the conductive bonding portion 311, the insulating bonding portion 312, the diffusion layer 320, the conductive diffusion portion 321, the insulating diffusion portion 322, and each semiconductor element 330 are each in the first embodiment.
- the ceramic multilayer substrate 100, the bonding layer 110, the conductive bonding portion 111, the insulating bonding portion 112, the diffusion layer 120, the conductive diffusion portion 121, the insulating diffusion portion 122, and the semiconductor element 130 of the example are provided.
- the bonding layer 310 is formed in a planar shape, the semiconductor element 330 and the ceramic multilayer substrate 300 do not involve an organic material having low heat resistance and thermal diffusibility, and are heat resistant. Bonding is performed on a plane formed mainly of an inorganic material having excellent characteristics and thermal diffusivity.
- the semiconductor power module 30 having a high level can be provided.
- the conductive bonding portion has a first bonding start temperature that is a temperature at which the conductive connection portion and the electrode pad of the semiconductor element start bonding, and the insulating bonding portion is connected to the wiring substrate or the semiconductor element. This is a temperature at which bonding is started, and has a second bonding start temperature that is higher than the first bonding start temperature.
- the conductive joint and the insulating joint constituting the joining layer have the same functions and functions as those of the first embodiment except for the joining start temperature. The description will be made with reference to the bonding layer 110, the conductive bonding portion 111, the conductive connection portion 111a, the electrode pad 131, and the insulating bonding portion 112.
- the conductive bonding portion 111 of the bonding layer 110 has a first bonding start temperature that is a temperature at which the conductive connection portion 111a and the electrode pad 131 start bonding.
- the first joining start temperature is a temperature equal to or higher than the sintering start temperature at which at least a part of the material constituting the conductive connection portion 111a or the electrode pad 131 starts the sintering reaction.
- the sintering start temperature is the start temperature of the sintering reaction due to the formation of a liquid phase by at least a part of the components constituting the conductive connection portion 111a or the electrode pad 131 or the reaction of the adhesion interface in the solid phase.
- the reason for setting the first joining start temperature to be equal to or higher than the sintering start temperature is as follows. In other words, even if the conductive joint portion 111 is not melted, sintering adherence proceeds due to the generation of a liquid phase of only a small amount of components, and joining between members is started.
- the conductive connecting portion 111a is formed of tin and the electrode pad 131 is formed of copper and tin, the conductive connecting portion 111a and the electrode pad 131 are melted and softened to perform diffusion bonding.
- the proceeding temperature for example, 300 ° C. is set as the first joining start temperature.
- the insulating bonding portion 112 is a temperature at which the insulating bonding portion 112, the ceramic multilayer substrate 100, and the semiconductor element 130 start bonding, and has a second bonding start temperature that is higher than the first bonding start temperature.
- the second joining start temperature is a temperature equal to or higher than the sintering start temperature at which at least a part of the material constituting the insulating joint 112 starts the sintering reaction.
- the temperature at which at least a part of the material constituting the insulating joint 112 starts a sintering reaction is the liquid phase formation by at least part of the components constituting the insulating joint 112 or the adhesion interface in the solid phase. This is the starting temperature of the sintering reaction.
- the reason for setting the second joining start temperature to be equal to or higher than the sintering start temperature is as follows. In other words, even if the insulating bonding portion 112 is not melted, sintering adherence proceeds due to the generation of a liquid phase of only a small amount of components, and bonding with other members is started.
- the insulating bonding portion 112 is formed of powder glass (softening point: 357 ° C.) made of Bi 2 O 3 and B 2 O 3 , the first bonding start temperature (300 ° C.).
- the temperature at which the insulating bonding portion 112 is softened and diffusion bonding sufficiently proceeds, for example, 450 ° C. is set as the second bonding start temperature.
- the ceramic multilayer substrate 100, the bonding layer 110, and the semiconductor element 130 are bonded by a diffusion bonding process having a stepwise bonding process using a temperature profile having multi-stage temperature changes.
- the outline of the manufacturing process of the semiconductor power module 10 is the same as that of FIG. 3 described in the first embodiment. However, the diffusion bonding process by thermocompression bonding in step S18 is different. The diffusion bonding process in step S18 will be described below.
- the ceramic multilayer substrate 100, the bonding layer 110, and the semiconductor element 130 are heat-pressed and diffusion bonded to manufacture a semiconductor power module.
- Step S18 FIG. 3
- the ceramic multilayer substrate 100, the bonding layer 110, and the semiconductor element 130 are pressurized, and the heating temperature at the time of diffusion bonding is set to be changed in multiple stages. A heat treatment is performed based on the profile.
- the heating temperature is held at the first bonding start temperature for a predetermined time (first bonding step), and then the heating temperature is held at the second bonding start temperature for a predetermined time. (Second bonding step).
- the semiconductor element 130 is pressed against the ceramic multilayer substrate 100 by a pressing jig having an area slightly smaller than the area of the back surface of the semiconductor element 130.
- the first and second joining steps are as follows.
- first bonding step heat treatment is performed while maintaining the first bonding start temperature (300 ° C.) for a predetermined time (for example, about 10 minutes), and occurs between the conductive connection portion 111a and the electrode pad 131. Diffusion bonding proceeds and a conductive bonding portion 111 is formed. Since the softening point (357 ° C.) of the insulating bonding portion 112 is higher than the first bonding start temperature, the insulating bonding portion 112 is not softened in the first bonding step.
- the second bonding step is performed.
- heat treatment is performed at the second bonding start temperature (450 ° C.).
- the softened insulating bonding portion 112 has a gap existing between the semiconductor element 130 and the bonding layer 110 due to the pressing force of the pressing jig applied so that the semiconductor element 130 is in close contact with the ceramic multilayer substrate 100, and Diffusion bonding proceeds while being deformed so as to fill a gap existing between the bonding layer 110 and the ceramic multilayer substrate 100.
- diffusion bonding is performed between the ceramic multilayer substrate 100 and the insulating bonding portion 112 and between the insulating bonding portion 112 and the surface of the semiconductor element 130 in a uniform plane without a gap.
- the semiconductor power module 10 is manufactured.
- the insulating bonding portion is heated at the first bonding start temperature lower than the temperature at which the sintering reaction starts when forming the conductive bonding portion, the insulating bonding is performed.
- the conductive joint portion is joined before the portion. Accordingly, the conductive connection portion 111a and the electrode pad 131 of the semiconductor element, and the conductive joint portion 111 and the ceramic multilayer substrate 100 are bonded, that is, between the conductive connection portion 111a and the electrode pad 131 of the semiconductor element, and the conductive state.
- Softening deformation of the insulating bonding portion 112 starts in a state where no gap exists between the bonding portion 111 and the ceramic multilayer substrate 100, and the insulating bonding portion 112 and the semiconductor element 130, and the insulating bonding portion 112 and the ceramic multilayer substrate 100 Are joined. Therefore, the deterioration of the conductive performance of the conductive joint portion 111 due to the material constituting the insulating joint portion 112 entering between the conductive connection portion 111a and the electrode pad 131 and entering the conductive joint portion 111 can be suppressed. .
- the first junction start temperature is the melting start temperature of the material constituting the conductive junction
- the second junction start temperature constitutes the insulating junction. It is the melting start temperature of the material. Therefore, the conductive joint and the insulating joint can be reliably melted, and the joint strength between each of the conductive joint and the insulating joint and the other member can be improved.
- FIG. 9 is a cross-sectional view showing a semiconductor power module 40 in the fourth embodiment.
- the semiconductor power module 40 of the fourth embodiment includes a ceramic multilayer substrate 400, a bonding layer 410, and a diffusion layer 420, similar to the semiconductor power module 10 of the first embodiment.
- the diffusion layer 420 includes a conductive diffusion part 421 and an insulating diffusion part 422.
- the ceramic multilayer substrate 400, the diffusion layer 420, the conductive diffusion portion 421, the insulating diffusion portion 422, and the semiconductor element 430 are the ceramic multilayer substrate 100, the diffusion layer 120, the conductive diffusion portion 121, and the conductive diffusion portion 121 of the first embodiment, respectively.
- the insulating diffusion unit 122 and the semiconductor element 130 have the same configuration.
- the semiconductor power module 40 of the fourth embodiment is different from the semiconductor power module 10 of the first embodiment in the configuration of the bonding layer 410.
- the bonding layer 410 is a flat thin film, and includes a conductive connection portion 411 a, a conductive bonding portion 411 including an electrode pad 431 of the semiconductor element 430, and an insulating bonding portion 412.
- the insulating bonding portion 412 is formed in a tapered shape in which the area of the surface on the semiconductor element 430 side is larger than the area of the surface on the ceramic multilayer substrate 400 side.
- the conductive connection portion 411a is formed to have a shape corresponding to the tapered shape of the insulating joint portion 412.
- the insulating bonding portion 412 is not limited to a tapered shape, and may have a shape in which the area of the surface on the semiconductor element 430 side is larger than the area of the surface on the ceramic multilayer substrate 400 side.
- a staircase shape or a curved shape may be used.
- the semiconductor power module 40 can be manufactured by the same method as the semiconductor power module 10 of the first embodiment, except for the step of arranging the bonding layer 410 (corresponding to steps S12 and S14 in FIG. 3).
- the bonding layer 410 may be disposed using the following method in the fourth embodiment.
- the insulating bonding portion 412 is arranged by screen printing before the conductive connection portion 411a. At this time, a glass powder paste, which is a material of the insulating bonding portion 412, is printed using a screen having an opening having a tapered shape with a large area on the semiconductor element 430 side.
- a paste mainly composed of a metal species as a material of the conductive connection portion 411a is printed.
- the viscosity of the paste used at this time is adjusted, and after the paste is applied to the semiconductor element 430, the paste is spread over a larger area on the semiconductor element 430 side than the surface of the opening due to the weight of the paste.
- a joint portion including a tapered insulating joint portion 412 and a conductive connection portion 411a having a shape corresponding to the tapered shape of the insulating joint portion 412 is created.
- the planar bonding layer 410 is formed by disposing the semiconductor element 430 so that the electrode pad 431 of the semiconductor element 430 fits into a recess formed by the conductive connection portion 411a and the insulating bonding portion 412.
- the insulating bonding portion 412 of the bonding layer 410 is formed in a tapered shape in which the area of the surface on the semiconductor element 430 side is wider than the area of the surface on the ceramic multilayer substrate 100 side. Therefore, the contact area between the insulating junction 412 and the semiconductor element 430 is larger than that of the insulating junction 112 of the first embodiment. Therefore, the thermal diffusion performance from the semiconductor element 430 to the bonding layer 410 is higher than that of the semiconductor power module 10 of the first embodiment. Therefore, while ensuring the insulation performance between the ceramic multilayer substrate 400 and the semiconductor element 430, the heat diffusion performance can be improved, and the heat radiation of the semiconductor element 430 can be promoted.
- FIG. 10 is a cross-sectional view showing a schematic configuration of a semiconductor power module 1010 in the fifth embodiment.
- FIG. 11 is an explanatory diagram for explaining a semiconductor power module 1010 according to the fifth embodiment.
- the semiconductor power module 1010 includes a ceramic multilayer substrate 500, a bonding layer 510, and a semiconductor element 530.
- the ceramic multilayer substrate 500 is formed of a ceramic material.
- the ceramic material for example, aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), silicon nitride (Si 3 N 4 ), or the like is used.
- the ceramic multilayer substrate 500 has a first surface 505 on which a semiconductor element is mounted and a surface between the other second surface 506 that faces the surface 505 and can be mounted with other electronic components such as a control circuit and a capacitor.
- An inner layer via hole 501 for electrical connection, a wiring pattern 509, and an electrode terminal 504 for external connection arranged on the second surface 506 are provided.
- the wiring pattern 509 is formed on the surface of the ceramic multilayer substrate 500 and the surface of the inner layer.
- Electrode lands (not shown) for mounting the semiconductor element 530 and other electronic components are formed on the first surface 505 and the second surface 506 of the ceramic multilayer substrate 500.
- the semiconductor element 530 is electrically connected to the electrode terminal 504 disposed on the second surface 506 via the inner layer via hole 501 and the wiring pattern 509.
- the bonding layer 510 is a thin film layer that is disposed on the first surface 505 of the ceramic multilayer substrate 500 and includes a conductive connection portion 511, an insulating bonding portion 512, and a protruding portion 535 of a semiconductor element 530 described later.
- the bonding layer 510 has a smooth surface on the first surface 505 side.
- a state in which the protruding portion 535 is not included is also described as the bonding layer 510.
- the projecting portion 535 corresponds to the “projecting portion” in the claims. The same applies to the sixth embodiment described below.
- the insulating junction 512 insulates the semiconductor element 530 and the ceramic multilayer substrate 500 from each other.
- the insulating bonding portion 512 is disposed on the first surface 505 of the ceramic multilayer substrate 500, and an opening 515 is formed in a portion 507 (shown by a thick solid line) corresponding to the inner layer via hole 501.
- the insulating bonding portion 512 is disposed on the first surface 505 of the ceramic multilayer substrate 500 and on a portion 508 (shown by a thick broken line) excluding the portion 507 corresponding to the inner layer via hole 501.
- the insulating bonding portion 512 is formed of a glass composition containing an insulating inorganic material as a main component. For example, silicon oxide, zinc oxide, or the like may be used as the insulating inorganic material.
- the conductive connection portion 511 electrically connects the semiconductor element 530 and the ceramic multilayer substrate 500. As shown in FIG. 11, the conductive connection portion 511 is disposed in the opening 515 and on the first surface 505 of the ceramic multilayer substrate 500. In other words, the conductive connection portion 511 is disposed on the portion 507 corresponding to the inner layer via hole 501.
- the conductive connection portion 511 is formed using a conductive metal as a main component. For example, copper, silver, aluminum metal, or the like may be used as the conductive metal.
- the conductive connection portion 511 has at least a joining surface with the first surface 505 formed in a planar shape.
- the bonding layer 510 also has a recess 516 formed by a conductive connection portion 511 and an insulating bonding portion 512.
- the recess 516 has a volume that is equal to or greater than the total volume of the metal protrusions 535 formed in the semiconductor element 530, which will be described later, and the thickness of the conductive connection portion 511 is d1 as shown in FIGS.
- the projecting portion 535 is d3, and the allowable value of the height variation of the projecting portion 535 caused by warping of the ceramic multilayer substrate 500 is d4, the projecting portion
- the height d3 of 535 is larger than the height obtained by adding d4 to the height (d2-d1) of the recess 516 formed by the insulating joint portion 512 and the conductive connection portion 511, that is, d3 ⁇ It is designed to satisfy (d2 ⁇ d1) + d4.
- the ceramic multilayer substrate 500 may be slightly warped at the time of manufacture, if the height in the thickness direction of the recessed portion 516 is equal to the height in the thickness direction of the protruding portion 535, the warp of the ceramic multilayer substrate 500 is small. As a result, a gap may be formed between the tip of the projecting portion 535 on the side of the recessed portion 516 and the recessed portion 516 facing the protruding portion 535. That is, the electrical connection between the protruding portion 535 and the conductive connection portion 511 cannot be secured.
- the height in the thickness direction of the recess 516 takes into account the height variation d4 in the thickness direction of the ceramic multilayer substrate 500, that is, d3> d2-d1, so that the semiconductor element 530 into the recess 516 is satisfied.
- the electrical connection between the projecting portion 535 and the conductive connection portion 511 can be reliably ensured. Even if a slight warp or the like occurs in the ceramic multilayer substrate 500, a variation in the height of the bonding surface of d3- (d2-d1) or less is allowed.
- d1 and d2 are simply expressed as thicknesses.
- the thicknesses of the conductive connection portions 511 and the insulating bonding portions 512 may not be completely uniform. Variations may occur.
- the protruding portion 535 of the semiconductor element 530 is not only formed in a planar shape as shown in the fifth embodiment, but may be formed in a spherical shape, for example. Therefore, d1 to d3 may be defined as follows. That is, d1 represents the maximum value of the distance from the first surface 505 of the ceramic multilayer substrate 500 to the surface of the conductive connection portion 511 on the semiconductor element 530 side in the conductive connection portion 511, and d2 represents the ceramic multilayer substrate 500.
- the semiconductor element 530 includes the protrusion 535 as described above, and the protrusion 535 includes an electrode pad 531 and a metal bump 533.
- the electrode pad 531 is formed, for example, using gold (Au) as a main component.
- the bump 533 is formed in a protruding shape on the electrode pad 531.
- the bump 533 may be formed in advance by placing a metal column processed into a bump shape at a desired position, or a paste mainly composed of a metal species such as aluminum metal or silver oxide is used as the electrode pad 531. Further, it may be formed by a method of transferring by a photolithographic pattern or a method of printing by screen printing.
- the semiconductor element 530 is disposed on the bonding layer 510 so that the protruding portion 535 is accommodated in the recessed portion 516.
- the semiconductor element 530 is integrally bonded to the ceramic multilayer substrate 500 and the bonding layer 510 by heating and pressurization, the ceramic multilayer substrate 500 and the semiconductor element 530 are connected to the conductive connection portion 511, the protruding portion 535, that is, the bump. 533 and the electrode pad 531 are electrically connected.
- the bump 533 and the conductive connection portion 511 are described without change in shape before and after bonding. However, the bump 533 and the conductive connection portion 511 are recessed 516 due to heat deformation at the time of bonding.
- the space portion is deformed so as to be filled, and the interface between the insulating bonding portion 512 and the semiconductor element 530 is formed in a planar shape.
- the difference between the volume of the recess 516 and the volume of the protrusion 535 shown in FIG. 10 is smaller than the volume of the recess 516 before integration with the semiconductor element 530.
- the bonding strength between the semiconductor element 530 and the ceramic multilayer substrate 500 is exhibited by the insulating bonding portion 512 in addition to the projecting portion 535 and the conductive connection portion 511, and the difference in thermal expansion of each member due to the heat generated when the semiconductor element 530 is driven. The resulting stress is distributed to the conductive connection portion 511 and the insulating joint portion 512.
- Heat generated during operation of the semiconductor element 530 is diffused to the ceramic multilayer substrate 500 through the protruding portions 535 and the conductive connection portions 511, and is diffused to the ceramic multilayer substrate 500 through the insulating bonding portions 512. As a result, the temperature rise of the semiconductor element is suppressed.
- the protrusion 535 and the depression 516 are preferably formed so that the volume of the protrusion 535 and the volume of the depression 516 are equal. However, if the electrical connection is ensured, the depression The volume of 516 may be larger than the volume of the protruding portion 535.
- FIG. 12 is a process diagram illustrating a method for manufacturing the semiconductor power module 1010 in the fifth embodiment.
- the ceramic multilayer substrate 500 in which the inner layer via hole 501 and the wiring pattern 509 are formed is manufactured (step S100).
- Fabrication of the ceramic multilayer substrate 500 includes forming a thin-film electrode land for mounting the semiconductor element 530 and other electronic components on the surface of the ceramic multilayer substrate 500.
- the electrode land is formed by a printing method using a conductive paste, physical vapor deposition (PVD: Physical Vapor Deposition) or chemical vapor deposition (CVD: Chemical Vapor Deposition).
- step S100 corresponds to the “substrate manufacturing process” in the claims.
- the insulating bonding portion 512 is disposed on the first surface 505 of the produced ceramic multilayer substrate 500 (step S102). An arrangement process of the insulating bonding portion 512 will be described with reference to FIG.
- FIG. 13 is an explanatory diagram for explaining an arrangement process of the insulating bonding portion 512 in step S102.
- a glass powder paste 518 is produced by kneading powder glass, which is the main component of the insulating joint 512, and a thermally decomposable organic binder using a solvent such as an organic solvent or water, as shown in FIG. Then, it is applied onto the first surface 505 of the ceramic multilayer substrate 500.
- An opening 515 is formed in the insulating joint 512 formed on the ceramic multilayer substrate 500 (step S104). The step of forming the opening 515 will be described with reference to FIG.
- FIG. 14 is an explanatory diagram for explaining the process of forming the opening 515 in step S104.
- the ceramic multilayer substrate 500 coated with the glass powder paste (insulating joint 512) is heated at a temperature at which the resist is thermally decomposed (eg, 700 ° C. or higher) and below the softening point of the glass powder (eg, 600 ° C. or lower).
- a temperature at which the resist is thermally decomposed eg, 700 ° C. or higher
- the softening point of the glass powder eg, 600 ° C. or lower.
- an opening 515 is formed in a portion 507 corresponding to the inner layer via hole 501.
- the paste that will be the insulating bonding portion 512 is processed to form the opening.
- the aspect of forming the opening is defined as “the insulating bonding portion having the opening on the first surface”. It is included in “the step of arranging in”.
- the recess 516 having a volume larger than the volume of the conductive protrusion 535 formed in the semiconductor element 530 is thinner than the insulating junction 512 so as to be formed in the opening 515 of the insulating junction 512.
- the conductive connection portion 511 is disposed in the opening 515 (step S106). Specifically, a part of the opening 515 is filled with a paste mainly composed of a metal species that is melted by a heating process in step S112, which will be described later. At this time, the paste is printed so that the recessed portion 516 is formed by the conductive connection portion 511 and the insulating joint portion 512.
- FIG. 15 is an explanatory diagram for explaining an arrangement process of the conductive connection portion 511 in step S106.
- the screen printing machine 600 includes a screen 602, a squeegee 603, and a squeegee holder 604.
- the screen 602 has a through hole only in a portion 507 corresponding to the inner layer via hole 501, that is, a portion corresponding to the opening 515 formed in the insulating bonding portion 512.
- a paste 650 containing metal as a main component is placed on a screen 602, and a squeegee 603 is slid from the screen 602.
- the paste 650 passes through the through-hole of the screen and is transferred onto the first surface 505 of the ceramic multilayer substrate 500 in the opening 515 of the insulating joint 512.
- the conductive connection portion 511 is disposed in the opening portion 515, the inner peripheral surface 515a of the opening portion 515 of the insulating joint portion 512 and the surface 511a on the opposite side of the surface of the conductive connection portion 511 on the ceramic multilayer substrate 500 side.
- a recess 516 is formed.
- steps S102 to S106 correspond to the “first arrangement step” in the claims.
- the ceramic multilayer substrate 500, the conductive connection portion 511, and the insulating bonding portion 512 are temporarily laminated (bonded) by the bonding force of the organic binder contained in the printing paste in advance to constitute the circuit board 1020.
- a bump 533 is formed on the electrode pad 531 of the semiconductor element 530 (step S108).
- the bump 533 is formed so that the total volume of the electrode pad 531 and the bump 533 is equal to or less than the volume of the recess 516.
- a metal bump formed of a metal species that melts in the heating process of step S110, which will be described later, such as aluminum metal, silver oxide, copper, nano gold warehouse, or solder alloy is disposed on the electrode pad 531.
- the bump may be formed by a ball mounting method in which a metal formed in a ball shape is disposed at a desired position and is formed into a columnar shape by heat treatment, or a metal that becomes a bump at a position corresponding to the semiconductor element 530 in advance.
- a paste containing the above-described metal species as a main component may be printed by screen printing, or a metal bump may be formed at a desired position by plating using a photolithography pattern and plating.
- the semiconductor element 530 is disposed on the bonding layer 510 so that the protruding portion 535 of the semiconductor element 530 is disposed in the recess 516 of the bonding layer 510 (step S110), and the ceramic multilayer substrate 500, the bonding layer 510, and the semiconductor are disposed.
- the element 530 is thermocompression bonded to manufacture a semiconductor power module (step S112).
- step S108 and step S110 correspond to the “second arrangement step” in the claims
- step S112 corresponds to the “joining step” in the claims.
- FIG. 16 is an explanatory diagram for explaining the bonding process of the semiconductor power module 1010 in the fifth embodiment.
- the ceramic multilayer substrate 500, the bonding layer 510, and the semiconductor element 530 are pressurized and heated to a temperature at which the conductive connection portion 511, the insulating bonding portion 512, and the bump 533 are heat-sealed.
- the conductive connection portion 511, the insulating bonding portion 512, and the first surface 505 of the ceramic multilayer substrate 500 are melted, and between the ceramic multilayer substrate 500 and the bonding layer 510 and between the bonding layer 510 and the semiconductor element 530.
- the gaps are diffusion-bonded on a uniform plane without voids.
- the temperature at which the conductive connection portion 511 and the insulating bonding portion 512 are thermally fused is, for example, aluminum metal having a melting point of 660 ° C. as the material of the conductive connection portion 511 and the bump 533 and the softening point 640 as the material of the insulating bonding portion 512.
- the material is heated to a temperature of 670 ° C. at which both materials are thermally fused, and the ceramic multilayer substrate including the bonding layer 510 and the semiconductor element 530 are subjected to a pressure of about 500 kPa. Pressure bonding.
- the ceramic multilayer substrate 500 and the bonding layer 510 Due to the pressurization and heating, diffusion of atoms occurs at the bonding surface between the ceramic multilayer substrate 500 and the bonding layer 510, and the ceramic multilayer substrate 500 and the bonding layer 510 are bonded. Also, the bumps 533 and the conductive connection portions 511 of the semiconductor element 530 are also melted and bonded by heating.
- the cut surface cut in the direction perpendicular to the ceramic multilayer substrate 500, the bonding layer 510, and the semiconductor element 530 is composed of the compound semiconductor and the protective layer on the surface.
- the interface between the semiconductor element 530 and the bonding layer 510 and the interface between the bonding layer 510 and the surface of the ceramic multilayer substrate 500 made of a ceramic component (alumina, silicon nitride, aluminum nitride, etc.) are shown by thick solid lines in FIG. These are arranged in a substantially straight line, and do not include minute defects such as bubbles. Inevitable voids on the order of microns are not included in the defects in the embodiments.
- the size of the bubble determined as a defect may be, for example, 500 ⁇ m or more.
- the semiconductor power module 1010 of the fifth embodiment described above when the protrusion 535 is fitted into the opening 515, the thickness d1 of the conductive connection portion 511, the thickness d2 of the insulating joint 512, and the protrusion
- the thickness d3 of the portion 535 in the stacking direction is formed so as to satisfy d3> d2-d1. Therefore, when the semiconductor element 530 is disposed in the recess 516, the electrical connection between the protruding portion 535 and the conductive connection portion 511 can be reliably ensured.
- the bonding layer 510 has the recess 516 having a volume equal to or larger than the volume of the protruding portion 535 formed in the semiconductor element 530.
- the bonding surface between the bonding layer 510 and the semiconductor element 530 is substantially flat.
- the ceramic multilayer substrate 500 and the bonding layer 510 are bonded in a plane. Accordingly, it is possible to suppress the generation of voids in the bonding surface between the ceramic multilayer substrate 500 and the bonding layer 510 and the bonding surface between the bonding layer 510 and the semiconductor element 530. Therefore, it is possible to improve the bonding strength between the ceramic multilayer substrate 500 and the bonding layer 510 and the thermal diffusion performance from the semiconductor element to the ceramic multilayer substrate 500.
- Example 6 F1.
- General configuration of the semiconductor power module: 17 and 18 are cross-sectional views illustrating the configuration of the semiconductor power module 1030 in the sixth embodiment.
- the semiconductor power module 1030 of the sixth embodiment includes a ceramic multilayer substrate 700, a bonding layer 710, and a semiconductor element 730.
- the ceramic multilayer substrate 700 and the semiconductor element 730 have the same configurations as the ceramic multilayer substrate 500 and the semiconductor element 530 of the fifth embodiment, respectively.
- the semiconductor power module 1030 is different from the semiconductor power module 1010 of the fifth embodiment in the configuration of the bonding layer 710.
- the bonding layer 710 includes a conductive connection portion 711, an insulating bonding portion 712, and a depression 716 formed by the conductive connection portion 711 and the insulating bonding portion 712.
- the bonding surface of the bonding layer 710 and the ceramic multilayer substrate 700 is formed in a flat shape.
- An opening 715 is formed in the insulating bonding portion 712 at a portion corresponding to the inner layer via hole 701 of the ceramic multilayer substrate 700.
- the insulating bonding portion 712 is formed on the semiconductor element 730 side as shown by a circle C in FIG.
- the taper is tapered from the end toward the end on the ceramic multilayer substrate 700 side.
- the depression 716 is formed by disposing the conductive connection portion 711 in the opening 715.
- the recess 716 has a volume that is equal to or greater than the volume of the protrusion 735 formed by the electrode pad 731 and the bump 733 of the semiconductor element 730.
- the semiconductor power module 1030 may be manufactured by a method for manufacturing the semiconductor power module 1010 of the fifth embodiment. Moreover, in order to produce a taper-shaped part, you may divide and manufacture the formation of the insulation junction part 712 and the conductive connection part 711 in multiple times. Specifically, printing is performed using a screen mask so that a paste of glass powder that is a material of the insulating bonding portion 712 is formed to be thinner than a desired thickness of the insulating bonding portion 712. The screen mask used at this time is masked only at the portion corresponding to the opening 715. Subsequently, a conductive joint 711 is formed in the opening 715.
- a metal bump 733 is formed on the electrode pad 731 of the semiconductor element 730.
- the bump 733 is formed so that the total volume of the electrode pad 731 and the bump 733 is equal to or less than the volume of the recess 716.
- the semiconductor element 730 is disposed on the bonding layer 710 so that the protruding portion 735 is disposed in the recess 716, and the ceramic multilayer substrate 700, the bonding layer 710, and the semiconductor element 730 are bonded by heating and pressurizing (FIG. 12 corresponding to steps S110 and S112).
- the insulating bonding portion 712 of the bonding layer 710 is formed in a thin taper shape from the semiconductor element 730 side toward the ceramic multilayer substrate 500 side. Compared with the insulating junction 512, the contact area between the insulating junction 712 and the semiconductor element 730 is increased. Therefore, the thermal diffusion performance from the semiconductor element 730 to the bonding layer 710 is higher than that of the semiconductor power module 1010 of the fifth embodiment. Therefore, the thermal diffusion performance can be improved while ensuring the insulation performance between the ceramic multilayer substrate 700 and the semiconductor element 730, and the heat dissipation of the semiconductor element 730 can be promoted.
- the semiconductor element 730 is bonded to the semiconductor multilayer substrate 700 on which the bonding layer 710 is formed.
- the bonding area between 730 and the insulating bonding portion 712 is sufficiently compensated regardless of the degree of filling due to the deformation of the bump 733.
- the bonding strength between the semiconductor element 730 and the ceramic multilayer substrate 700 is ensured to be stable without variation depending on the production lot.
- Insulating junction 112 is formed. Specifically, powder glass and a thermally decomposable organic binder (for example, a butyral binder that softens at a temperature of about 80 ° C. and thermally decomposes at a temperature of about 250 ° C.) are mixed with a solvent such as an organic solvent or water. The slurry is kneaded to form a slurry, and the slurry is molded into a sheet shape by a technique such as sheet casting by the doctor blade method or extrusion molding. A through hole is formed in a portion of the sheet corresponding to the conductive joint 111 by machining such as laser or microcomputer punch. As described above, the insulating bonding portion 112 is manufactured as a glass sheet in which a through hole is formed.
- a thermally decomposable organic binder for example, a butyral binder that softens at a temperature of about 80 ° C. and thermally decomposes at a temperature of about 250 ° C.
- the ceramic multilayer substrate 100 is disposed so that the first surface 105 of the ceramic multilayer substrate 100 faces the desired surface of the insulating bonding portion 112, and both of them are softened by the softening temperature of the organic binder contained in the insulating bonding portion sheet. Temporary adhesion is performed by the bonding force of the organic binder contained in the insulating joint 112 formed in a sheet shape by heating and pressurizing as described above.
- the conductive connection part 111a is formed.
- the paste for forming the conductive connection portion 111a is filled into the through hole of the manufactured insulating bonding portion 112 by screen printing.
- the paste contains metal as a main component.
- a metal species such as aluminum metal, silver oxide, copper, nanometal, or solder alloy that melts in the heating process in step S18 in FIG. It is formed by kneading the adhesive with a solvent such as an organic solvent or water.
- the filling of the paste is not limited to screen printing, and for example, a method such as ejection by a dispenser may be used.
- the semiconductor element 130 has a melting point of glass or metal that is a main component constituting the insulating bonding portion 112 and the conductive connecting portion 111a. After heating to temperature and pressure bonding, the organic binder component contained in the insulating bonding portion 112 is removed by thermal decomposition, and then the semiconductor power module 10 having the diffusion layer 120 formed thereon is manufactured (FIG. 1). Step S18).
- the planar bonding layer 110 can also be manufactured by the manufacturing method described above. Therefore, the semiconductor element 130 and the bonding layer 110, and the bonding layer 110 and the ceramic multilayer substrate 100 can be bonded to each other, and the heat conduction performance from the semiconductor element 130 to the ceramic multilayer substrate 100, and the ceramic multilayer substrate 100 and the semiconductor can be bonded. The bonding strength with the element 130 can be improved.
- Modification 2 As a method for manufacturing the semiconductor power module 10, for example, the manufactured insulating joint 112 is temporarily stacked on the ceramic multilayer substrate 100 without forming a through hole in which the conductive connection portion 111a is formed, and the laser processing is performed on the multilayer substrate 100.
- a through-hole in which the conductive bonding portion 111a is formed with a bonding layer may be provided in the insulating bonding portion 112 in the temporarily bonded state. By doing so, it is possible to suppress the crushing of the through hole at the time of provisional pressure bonding, and it is possible to accurately control the caliber size of the insulating joint 111a. Further, a tapered through hole can be formed by obliquely applying laser light.
- the ceramic multilayer substrate 100 and the bonding layer 110 are temporarily laminated in advance by the bonding force of the organic binder, and then the semiconductor element 130 is stacked and bonded by pressing and heating. Then, a sheet formed by filling holes formed in the insulating junction 112 formed in a sheet shape in advance with the conductive connection portion 111a is manufactured, and is sandwiched between the ceramic multilayer substrate 100 and the semiconductor element 130, and then heated.
- the semiconductor power module 10 may be manufactured by pressure bonding. By doing so, it is possible to reduce the amount of the organic binder added to the bonding layer 110, and to prevent the bonding layer 110 from being deteriorated by organic residues.
- Modification 4 In the first embodiment, a temperature at which the material constituting the conductive junction 111 is sufficiently melted is used as the first joining start temperature, and the material constituting the insulating junction 112 is sufficiently used as the second joining start temperature. Although the softening temperature is used, it suffices that at least a part of the constituent materials is equal to or higher than the temperature at which the sintering reaction starts. In this way, each of the conductive bonding portion 111 and the insulating bonding portion 112 can be bonded to another member without heating to the melting point. Therefore, it is possible to reduce the temperature of the manufacturing process.
- the second bonding start temperature is the start temperature of the sintering reaction of the powder glass. It may be a certain 495 ° C. or higher.
- FIG. 19 is an explanatory diagram showing a schematic configuration of the semiconductor power 1040 in the fifth modification.
- the semiconductor power 1040 includes a circuit board 1045 and a semiconductor element 830.
- the circuit board 1045 includes a ceramic multilayer substrate 800, a bonding layer 810, and a diffusion layer 820.
- the bonding layer 810 includes a conductive connection portion 811 and an insulating bonding portion 812.
- the ceramic multilayer substrate 800, the bonding layer 810, the conductive connection portion 811 and the semiconductor element 830 have the same configurations as the ceramic multilayer substrate 500, the bonding layer 510, the conductive connection portion 511 and the semiconductor element 530 of the fifth embodiment. Is provided.
- the insulating bonding portion 812 includes a filler 815 made of a metal material or an inorganic material to the extent that the insulating performance does not deteriorate.
- a filler 815 made of a metal material or an inorganic material to the extent that the insulating performance does not deteriorate.
- the insulating bonding part 812 has the same configuration as the insulating bonding part 512 of the fifth embodiment except that the filler 815 is contained.
- the diffusion layer 820 is a layer formed by diffusion bonding between the ceramic multilayer substrate 800 and the bonding layer 810.
- the diffusion layer 820 includes a conductive diffusion part 821 and an insulating diffusion part 822.
- the conductive diffusion portion 821 is formed by diffusion bonding between the ceramic multilayer substrate 800 and the conductive connection portion 811 of the bonding layer 810.
- the insulating diffusion portion 822 is formed by diffusion bonding between the ceramic multilayer substrate 800 and the insulating bonding portion 812 of the bonding layer 810.
- the insulating diffusion portion 822 may contain a filler 815 similarly to the insulating bonding portion 812.
- FIG. 19 for convenience of explanation, the boundary between the conductive diffusion portion 821 and the insulating diffusion portion 822 is clearly described, but the boundary between the conductive diffusion portion 821 and the insulating diffusion portion 822 may be ambiguous.
- FIG. 20 is an explanatory diagram for explaining the arrangement process of the bonding layer 810 in the fifth modification.
- This arrangement process is a process following step S100 of FIG. 12 of the fifth embodiment.
- the conductive connection portion 811 is disposed at a portion 807 corresponding to the inner layer via hole 801.
- a paste mainly composed of a metal species that is melted by the heating process in step S110 in FIG. 12 is formed on the portion 807 of the first surface 805 of the ceramic multilayer substrate 800 by screen printing.
- a transfer method using a photolithographic pattern may be used.
- the insulating bonding portion 812 is disposed on a portion 808 different from the portion 807 on the first surface 805 of the ceramic multilayer substrate 800 on which the conductive connection portion 811 is disposed.
- powder glass and a thermally decomposable organic binder are kneaded using a solvent such as an organic solvent or water to produce a glass powder paste.
- the portion 808 is printed by screen printing so as to fill the gap of the conductive connection portion 811 on the first surface 805.
- the glass powder paste constituting the insulating bonding portion 812 is printed so as to have a thickness greater than that of the conductive connection portion 811.
- the recess 816 (FIG. 19) is formed by disposing the conductive connection portion 811 and the insulating joint portion 812.
- the diffusion layer 820 is formed between the ceramic multilayer substrate 800 and the bonding layer 810 during the diffusion bonding of the ceramic multilayer substrate 800 and the bonding layer 810. Accordingly, the bonding strength between the ceramic multilayer substrate 800 and the bonding layer 810 can be improved.
- the filler 815 is included in the insulating bonding portion 812 of the bonding layer 810 and the insulating diffusion portion 822 of the diffusion layer 820, thermal diffusion from the semiconductor element 830 to the ceramic multilayer substrate 800 is performed. Performance can be improved.
- FIG. 21 is a plan view showing a semiconductor power module 1050 in the sixth modification.
- FIG. 22 is a cross-sectional view showing a semiconductor power module 1050 in the sixth modification.
- FIG. 22 shows a cross section taken along the line DD in FIG.
- the semiconductor power module 1050 of Modification 6 includes a ceramic multilayer substrate 900, a bonding layer 910, and a plurality (six in Modification 6) of semiconductor elements 930.
- the bonding layer 910 includes a conductive connection portion 911 and an insulating bonding portion 912.
- the semiconductor element 930 includes a projecting portion 935 including electrode pads 531 and bumps 533.
- the ceramic multilayer substrate 900, the bonding layer 910, the conductive connection portion 911, the insulating bonding portion 912, and each semiconductor element 930 are respectively the ceramic multilayer substrate 500, the bonding layer 510, and the conductive connection portion 511 of the fifth embodiment.
- the same structure as the insulating junction 512 and the semiconductor element 530 is provided.
- the semiconductor power module 1050 of Modification 6 since the bonding layer 910 is formed in a planar shape, the semiconductor element 930 and the ceramic multilayer substrate 900 are not affected by an organic material having low heat resistance or thermal diffusivity, and have heat resistance characteristics. And a plane formed by an inorganic material having excellent thermal diffusivity.
- a high-power semiconductor power module 1050 can be provided.
- the semiconductor power module 1010 may be manufactured by the following method. Below, the process following step S100 is demonstrated. In addition, the code
- Insulating junction 512 is formed. Specifically, powder glass and a thermally decomposable organic binder (for example, a butyral binder that softens at a temperature of about 80 ° C. and thermally decomposes at a temperature of about 250 ° C.) are mixed with a solvent such as an organic solvent or water. The slurry is kneaded to form a slurry, and the slurry is molded into a sheet shape by a technique such as sheet casting by the doctor blade method or extrusion molding. An opening 515 is formed in a portion of the sheet corresponding to the conductive connection portion 511 by machining such as a laser or a microcomputer punch. As described above, the insulating bonding portion 512 is manufactured as a glass sheet in which the opening 515 is formed.
- a thermally decomposable organic binder for example, a butyral binder that softens at a temperature of about 80 ° C. and thermally decomposes at a temperature of about
- the ceramic multilayer substrate 500 is disposed so that the first surface 105 of the ceramic multilayer substrate 500 faces the desired surface of the insulating bonding portion 512, and the softening temperature of the organic binder contained in the insulating bonding portion sheet. Temporary adhesion is performed by the bonding force of the organic binder contained in the insulating bonding portion 512 formed in a sheet shape by heating and pressurizing as described above.
- the conductive connection portion 511 is formed. Specifically, a paste for forming the conductive connection portion 511 is partially filled by screen printing in the through-hole of the manufactured insulating joint portion 512.
- the paste contains a metal as a main component.
- a metal species such as aluminum metal, silver oxide, copper, nanometal, or solder alloy that melts in the heating process in step S112 in FIG. It is formed by kneading an adhesive with a solvent such as an organic solvent or water.
- the filling of the paste is not limited to screen printing, and for example, a method such as ejection by a dispenser may be used.
- the recess 516 is formed by disposing the conductive connection portion 511 in the opening 515.
- the protrusion 535 is aligned with the depression 516 on the surface of the bonding layer 110 where the depression 516 is formed, and the semiconductor element 530 is disposed.
- the semiconductor element 530 has a glass or metal melting point higher than the melting point of the metal that constitutes the insulating joining portion 512 and the conductive connecting portion 511. After heating to temperature and pressure bonding, the organic binder component contained in the insulating bonding part 512 is removed by thermal decomposition, and the semiconductor power module 1010 is manufactured (step S112 in FIG. 12).
- the planar bonding layer 510 can also be manufactured by the manufacturing method described above. Accordingly, the semiconductor element 530 and the bonding layer 510, and the bonding layer 510 and the ceramic multilayer substrate 500 can be bonded to each other, and the heat conduction performance from the semiconductor element 530 to the ceramic multilayer substrate 500, and the ceramic multilayer substrate 500 and the semiconductor can be bonded. The bonding strength with the element 530 can be improved.
- the ceramic multilayer substrate 500, the conductive connection portion 511, and the insulating joint portion 512 are preliminarily laminated by the joining force of the organic binder, and then the semiconductor element 530 is laminated, and then the pressure and heating are performed to join.
- a sheet formed by previously filling holes formed in the insulating junction 512 formed in a sheet shape with the conductive connection portion 511 is manufactured, and the ceramic multilayer substrate 500 and the semiconductor element 530 are used.
- the semiconductor power module 1010 may be manufactured by sandwiching and heating and pressure bonding. By doing so, it is possible to reduce the amount of the organic binder added to the bonding layer 510, and to prevent deterioration of the bonding layer 510 due to organic residues.
- Modification 9 In the modified example 7, the glass sheet in which the opening 515 is formed in advance by machining such as laser or microcomputer punch is disposed on the ceramic multilayer substrate 500 and heat-pressed. However, as in the modified example 2, the glass sheet is formed on the ceramic multilayer substrate 500.
- the opening 515 may be formed by laser processing or the like after heat-pressing a glass sheet having no holes. By doing so, deformation of the opening 515 due to deformation during thermocompression bonding can be suppressed, and the opening 515 can be formed with an accurate aperture.
- the protruding portion 535 may have a height that is greater than the depth of the recess 516 in the stacking direction. In this way, when the semiconductor element 530 is disposed in the recess 516, the electrical connection between the protruding portion 535 and the conductive connection portion 511 can be reliably ensured. Note that in the case where the protruding portion 535 is formed to have a height larger than the depth of the depression portion 516 in the stacking direction, the semiconductor element 530 is bonded to the bonding layer when the semiconductor element 530 is disposed on the bonding layer 510. The bump 533 is melted and heated in the molten state by heating at the time of bonding, but the semiconductor element 530 and the bonding layer 510 are bonded to each other without a gap.
- the present invention is not limited to the above-described embodiments, examples, and modifications, and can be realized with various configurations without departing from the spirit of the invention.
- the technical features in the embodiments, examples, and modifications corresponding to the technical features in the embodiments described in the summary section of the invention are to solve some or all of the above-described problems, or In order to achieve part or all of the above effects, replacement or combination can be performed as appropriate. Further, if the technical feature is not described as essential in the present specification, it can be deleted as appropriate.
- Semiconductor element 400 Ceramic multilayer substrate 410 ... Junction layer 411 ... Conductive junction 412 ... Insulation junction 420 ... Diffusion layer 430 ... Semiconductor element 500 ... Ceramic multilayer substrate 501 ... Inner layer via hole 504 ... Electrode terminal 505 ... first surface 506 ... second surface 509 ... wiring pattern 510 ... bonding layer 511 ... conductive connecting portion 512 ... insulating bonding portion 515 ... opening 515a ... inner peripheral surface 516 ... hollow portion 518 ... glass powder paste DESCRIPTION OF SYMBOLS 530 ... Semiconductor element 531 ... Electrode pad 533 ... Bump 535 ... Projection part 600 ... Screen printer 602 ...
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Abstract
Description
A1.半導体パワーモジュールの概略構成:
図1は、第1実施例における半導体パワーモジュール10の概略構成を示す断面図である。図2は、第1実施例における回路基板20について説明する説明図である。半導体パワーモジュール10は、回路基板20と、半導体素子130とを備える。回路基板20は、セラミックス多層基板100と、接合層110と、拡散層120とを備える。
半導体パワーモジュール10の製造方法を、図3~図6を用いて説明する。図3は、第1実施例における半導体パワーモジュール10の製造方法を説明する工程図である。
第1実施例では、半導体素子130が一つのみ搭載された半導体パワーモジュール10について説明した。第2実施例では、複数の半導体素子が搭載された半導体パワーモジュールについて、図7および図8を参照して説明する。
図7は、第2実施例における半導体パワーモジュール30を示す平面図である。図8は、第2実施例における半導体パワーモジュール30を示す断面図である。図8は、図7におけるA-A断面で切断した断面を示す。
第3実施例では、導電接合部は、導電接続部と半導体素子の電極パッドとが接合を開始する温度である第1の接合開始温度を有し、絶縁接合部は、配線基板や半導体素子と接合を開始する温度であって、第1の接合開始温度よりも高い第2の接合開始温度を有する。なお、第3実施例において、接合層を構成する導電接合部、絶縁接合部は、接合開始温度以外は、第1実施例の各々と同様の作用・機能を有するので、第1実施例における符号(接合層110、導電接合部111、導電接続部111a、電極パッド131、絶縁接合部112)を用いて説明する。
接合層110の導電接合部111は、導電接続部111aと電極パッド131とが接合を開始する温度である第1の接合開始温度を有する。第1の接合開始温度とは、導電接続部111aもしくは電極パッド131を構成する材料の少なくとも一部が焼結反応を開始する焼結開始温度以上の温度である。焼結開始温度とは、導電接続部111aまたは電極パッド131を構成する成分の少なくとも一部による液相の形成、もしくは、固相での接着界面の反応による焼結反応の開始温度である。第1の接合開始温度を焼結開始温度以上とした理由は次の通りである。すなわち、導電接合部111が溶融していなくとも、ごく一部の成分の液相発生によって、焼結固着が進行し、部材間の接合が開始されるからである。
第3実施例では、多段階の温度変化を有する温度プロファイルを用いて、段階的な
接合工程を有する拡散接合処理によって、セラミックス多層基板100、接合層110および半導体素子130が接合される。半導体パワーモジュール10の製造工程の概略は、第1実施例において説明した図3と同様である。ただし、ステップS18における加熱圧着による拡散接合の工程が異なる。ステップS18における拡散接合工程について、以下に説明する。
D1.半導体パワーモジュール概略構成:
図9は、第4実施例における半導体パワーモジュール40を示す断面図である。図9に示すように、第4実施例の半導体パワーモジュール40は、第1実施例の半導体パワーモジュール10と同様に、セラミックス多層基板400と、接合層410と、拡散層420を備える。拡散層420は、導電拡散部421と絶縁拡散部422を備える。変形例1において、セラミックス多層基板400、拡散層420、導電拡散部421,絶縁拡散部422および半導体素子430は、それぞれ、第1実施例のセラミックス多層基板100、拡散層120、導電拡散部121、絶縁拡散部122および半導体素子130と同様の構成を備える。
E1.半導体パワーモジュールの概略構成:
図10は、第5実施例における半導体パワーモジュール1010の概略構成を示す断面図である。図11は、第5実施例における半導体パワーモジュール1010について説明する説明図である。半導体パワーモジュール1010は、セラミックス多層基板500と、接合層510と、半導体素子530とを備える。
半導体パワーモジュール1010の製造方法を、図12~図16を用いて説明する。図12は、第5実施例における半導体パワーモジュール1010の製造方法を説明する工程図である。
F1.半導体パワーモジュールの概略構成:
図17および図18は、第6実施例における半導体パワーモジュール1030の構成を説明する断面図である。図17および図18に示すように、第6実施例の半導体パワーモジュール1030は、セラミックス多層基板700と、接合層710と、半導体素子730を備える。第6実施例において、セラミックス多層基板700、半導体素子730は、それぞれ、第5実施例のセラミックス多層基板500、半導体素子530と同様の構成を備える。
G1.変形例1:
第1実施例における、半導体パワーモジュール10の製造方法(図3)に変えて、以下の方法によって、半導体パワーモジュール10を製造してもよい。以下に、ステップS10に続く処理を説明する。なお、各部材の符号は、第1実施例の符号を用いる。
半導体パワーモジュール10の作製方法として、例えば、作製した絶縁接合部112に、導電接続部111aが形成される貫通孔を形成しない状態でセラミックス多層基板100に仮積層し、レーザー加工により多層基板100に仮接着された状態で絶縁接合部112に接合層で導電接合部111aが形成される貫通孔を設けても良い。こうする事で仮圧着時の貫通孔のつぶれを抑制する事ができ、絶縁接合部111aの口径サイズを寄り精確に制御する事が可能となる。またレーザー光を斜めに当てる事によりテーパー形状の貫通孔を形成する事が出来る。
第1実施例では、セラミックス多層基板100と接合層110を予め有機結着材の接合力により仮積層した上で半導体素子130を積層して、加圧および加熱を行い接合しているが、例えば、シート状に形成された絶縁接合部112に形成された空孔を導電接続部111aで予め穴埋めして形成されたシートを作製し、セラミックス多層基板100と半導体素子130で矜持した上で加熱、圧着する事で、半導体パワーモジュール10を作製してもよい。こうすれば、接合層110に含まれる有機結着材の添加量を減少させる事が可能となり、有機残渣による接合層110の劣化などを防ぐ事ができる。
第1実施例では、第1の接合開始温度として、導電接合部111を構成する材料が十分に融解する温度を用い、第2の接合開始温度として、絶縁接合部112を構成する材料が十分に軟化する温度を用いているが、それぞれ、構成材料の少なくとも一部が焼結反応を開始する温度以上であればよい。こうすれば、導電接合部111、絶縁接合部112の各々について、融点まで加熱することなく他部材との接合を行うことができる。よって、製造工程の低温化を図ることができる。例えば、絶縁接合部112がNa2O3とB2O3とSiO2とからなる粉末ガラスから構成されている場合、第2の接合開始温度は、当該粉末ガラスの焼結反応の開始温度である495℃以上であればよい。
図19は、変形例5における半導体パワー1040の概略構成を示す説明図である。半導体パワー1040は、回路基板1045と、半導体素子830とを備える。回路基板1045は、セラミックス多層基板800と、接合層810と、拡散層820とを備え、接合層810は、導電接続部811と絶縁接合部812を備える。変形例4において、セラミックス多層基板800、接合層810、導電接続部811および半導体素子830は、第5実施例のセラミックス多層基板500、接合層510、導電接続部511および半導体素子530と同様の構成を備える。
図21は、変形例6における半導体パワーモジュール1050を示す平面図である。図22は、変形例6における半導体パワーモジュール1050を示す断面図である。図22は、図21におけるD-D断面で切断した断面を示す。
第5実施例における、半導体パワーモジュール1010の製造方法(図12)に変えて、以下の方法によって、半導体パワーモジュール1010を製造してもよい。以下に、ステップS100に続く処理を説明する。なお、各部材の符号は、第5実施例の符号を用いる。
第5実施例では、セラミックス多層基板500と導電接続部511および絶縁接合部512を予め有機結着材の接合力により仮積層した上で半導体素子530を積層して、加圧および加熱を行い接合しているが、例えば、シート状に形成された絶縁接合部512に形成された空孔を導電接続部511で予め穴埋めして形成されたシートを作製し、セラミックス多層基板500と半導体素子530で狭持した上で加熱、圧着する事で、半導体パワーモジュール1010を作製してもよい。こうすれば、接合層510に含まれる有機結着材の添加量を減少させる事が可能となり、有機残渣による接合層510の劣化などを防ぐ事ができる。
変形例7では予めレーザーまたはマイコンパンチなどの機械加工により開口部515を形成したガラスシートを、セラミックス多層基板500に配置し加熱圧着しているが、変形例2のように、セラミックス多層基板500に穴を有さないガラスシートを加熱圧着した後、レーザー加工等により、開口部515を形成しても良い。こうすることで、加熱圧着時の変形による開口部515の変形を抑制し、開口部515を精確な口径にて形成する事ができる。
突状部535は、窪み部516の積層方向の深さよりも大きい高さを有していてもよい。こうすれば、窪み部516内への半導体素子530の配置時、突状部535と導電接続部511との電気的接続を確実に担保できる。なお、突状部535が、窪み部516の積層方向の深さよりも大きい高さを有するように形成されている場合、接合層510上への半導体素子530の配置時に、半導体素子530が接合層510の表面より浮いた状態となるが、接合時の加熱により、バンプ533は溶融し、溶融した状態で加圧され、半導体素子530と接合層510とは空隙のない面で接合される。
100…セラミックス多層基板
101…内層ビアホール
104…電極端子
109…配線パターン
110…接合層
110a…接合部
111…導電接合部
111a…導電接続部
112…絶縁接合部
120…拡散層
121…導電拡散部
122…絶縁拡散部
130…半導体素子
131…電極パッド
202…スクリーン
203…スキージ
204…スキージホルダー
250…ガラス粉末ペースト
300…セラミックス多層基板
310…接合層
320…拡散層
330…半導体素子
400…セラミックス多層基板
410…接合層
411…導電接合部
412…絶縁接合部
420…拡散層
430…半導体素子
500…セラミックス多層基板
501…内層ビアホール
504…電極端子
505…第1の面
506…第2の面
509…配線パターン
510…接合層
511…導電接続部
512…絶縁接合部
515…開口部
515a…内周面
516…窪み部
518…ガラス粉末ペースト
530…半導体素子
531…電極パッド
533…バンプ
535…突状部
600…スクリーン印刷機
602…スクリーン
603…スキージ
604…スキージホルダー
650…ペースト
700…セラミックス多層基板
701…内層ビアホール
710…接合層
711…導電接続部
712…絶縁接合部
715…開口部
716…窪み部
730…半導体素子
731…電極パッド
733…バンプ
735…突状部
800…セラミックス多層基板
801…内層ビアホール
805…第1の面
810…接合層
811…導電接続部
812…絶縁接合部
815…フィラー
815…無機系フィラー
816…窪み部
820…拡散層
821…導電拡散部
822…絶縁拡散部
830…半導体素子
900…セラミックス多層基板
910…接合層
911…導電接合部
912…絶縁接合部
930…半導体素子
935…突状部
1010…半導体パワーモジュール
1020…回路基板
1030…半導体パワーモジュール
1040…半導体パワー
1045…回路基板
1050…半導体パワーモジュール
Claims (15)
- 半導体パワーモジュールであって、
ビアおよび配線パターンが形成された多層基板と、
前記多層基板の第1の面側に配置される半導体素子と、
前記多層基板の第1の面上に形成され、前記多層基板と半導体素子とを接合する接合層と、
を備え、
前記接合層は、
前記ビアに対応する第1の部位に配置されている平面状の導電接合部であって、前記半導体素子に形成されている導電性の突状部と、前記突状部と前記多層基板とを導通する導電接続部と、からなる導電接合部と、
前記第1の部位とは異なる第2の部位に配置され、無機系材料を主成分とする平面状の絶縁接合部と、を有する半導体パワーモジュール。 - 請求項1記載の半導体パワーモジュールであって、
前記多層基板と前記接合層および前記半導体素子と前記接合層とは、拡散接合により接合され、
前記半導体パワーモジュールは、更に、
前記多層基板と前記接合層および前記半導体素子と前記接合層との間に、前記拡散接合時に形成される拡散層を備える、半導体パワーモジュール。 - 請求項1記載の半導体パワーモジュールであって、
前記導電接合部を構成する材料の接合開始温度である第1の接合開始温度は、前記絶縁接合部を構成する材料の接合開始温度である第2の接合開始温度よりも低い、半導体パワーモジュール。 - 請求項3記載の半導体パワーモジュールにおいて、
前記第1の接合開始温度は、前記導電接合部を構成する材料の少なくとも一部が焼結反応を開始する温度である焼結開始温度以上であり、
前記第2の接合開始温度は、前記絶縁接合部を構成する材料の少なくとも一部が焼結反応を開始する温度である焼結開始温度以上である、半導体パワーモジュール。 - 半導体パワーモジュールの製造方法であって、
ビアおよび配線パターンを有する多層基板を作製する基板作製工程と、
前記ビアに対応する第1の部位に、前記配線パターンと半導体素子とを導通する平面状の導電接続部を有し、前記第1の部位とは異なる第2の部位に、平面状の絶縁接合部を有する接合部を、前記多層基板の第1の面上に配置する第1の配置工程と、
前記接合部上に、前記半導体素子を、前記半導体素子に形成されている導電性の突状部と前記導電接続部とが導通可能となるように配置する第2の配置工程と、
前記多層基板、前記接合部および前記半導体素子を、加熱圧着し、前記多層基板と前記接合部、および、前記接合部と前記半導体素子を拡散接合する接合工程と、
を備える半導体パワーモジュールの製造方法。 - 請求項5記載の半導体パワーモジュールの製造方法であって、
前記導電接続部を構成する材料が前記半導体素子と接合を開始する温度を第1の接合開始温度とし、
前記絶縁接合部を構成する材料が前記多層基板および前記半導体素子と接合を開始する温度であって、前記第1の接合開始温度よりも高い温度を第2の接合開始温度とし、
前記接合工程は、
前記多層基板、前記接合部および前記半導体素子を、前記第1の接合開始温度で加熱圧着することにより、前記導電接続部と前記半導体素子の前記突状部とを接合する工程と、
前記導電接続部と前記半導体素子の前記突状部との接合後に、前記多層基板、前記接合部および前記半導体素子を、前記第2の接合開始温度で加熱圧着することにより、前記多層基板と前記接合部、および、前記接合部と前記半導体素子とを接合する工程と、を含む、半導体パワーモジュールの製造方法。 - 請求項6記載の半導体パワーモジュールの製造方法において、
前記第1の接合開始温度は、前記導電接続部を構成する材料の少なくとも一部が焼結反応を開始する焼結開始温度以上であり、
前記第2の接合開始温度は、前記絶縁接合部を構成する材料の少なくとも一部が焼結反応を開始する焼結開始温度以上である、半導体パワーモジュールの製造方法。 - 請求項5記載の半導体パワーモジュールの製造方法であって、
前記導電接続部を構成する材料が前記半導体素子と接合を開始する温度を第1の接合開始温度とし、
前記絶縁接合部を構成する材料が前記多層基板および前記半導体素子と接合を開始する温度であって、前記第1の接合開始温度よりも高い温度を第2の接合開始温度とし、
前記接合工程において、
前記第1の接合開始温度が、所定時間、保持された後、前記第2の接合開始温度が所定時間保持されるように設定されている温度プロファイルに基づき、前記加熱を行う、半導体パワーモジュールの製造方法。 - 請求項5記載の半導体パワーモジュールの製造方法であって、
前記第1の配置工程は、
前記第1の部位に開口部を有する絶縁接合部を、前記第1の面上に配置する工程と、
前記絶縁接合部より薄い前記導電接続部を、前記開口部内に配置する工程と、を含み、
前記第2の配置工程は、
前記半導体素子の前記突状部と前記導電接続部とが導通可能となるように、前記開口部内に前記突状部を嵌りこませて、前記半導体素子を前記接合部上に配置する工程を含み、
前記導電接続部の厚みを表すd1、前記絶縁接合部の厚みを表すd2、および、前記突状部の高さを表すd3が、d3>d2-d1 を満たす、半導体パワーモジュールの製造方法。 - 請求項9記載の半導体パワーモジュールの製造方法であって、
前記絶縁接合部を配置する工程において、
前記絶縁接合部を、前記半導体素子が接合される端部から前記多層基板が接合される端部に向けて先細な形状となるように配置する、半導体パワーモジュールの製造方法。 - 請求項10記載の半導体パワーモジュールの製造方法であって、
前記絶縁接合部を配置する工程において、
前記絶縁接合部がテーパー形状となるように、前記絶縁接合部を配置する、半導体パワーモジュールの製造方法。 - 回路基板であって、
ビアおよび配線パターンが形成された多層基板と、
前記多層基板の第1の面上に配置され、前記多層基板に半導体素子を接合するための接合層と、
を備え、
前記接合層は、
前記ビアに対応する第1の部位に配置され、前記配線パターンと前記半導体素子と導通し、少なくとも前記第1の面側が平面状に形成されている導電接続部と、
前記第1の部位とは異なる第2の部位に配置され、無機系材料を主成分とし、少なくとも前記第1の面側が平面状に形成されている絶縁接合部と、
を有する回路基板。 - 請求項12記載の回路基板であって、
前記導電接続部は、前記絶縁接合部よりも薄く形成されており、
前記接合層は、前記絶縁接合部と前記導電接続部とにより形成される窪み部を有し、
前記半導体素子に形成されている導電性の突状部が前記窪み部へ嵌りこむ前において、前記導電接続部の厚みを表すd1、前記絶縁接合部の厚みを表すd2、および、前記突状部の高さを表すd3が、d3>d2-d1 を満たす、回路基板。 - 請求項12記載の回路基板であって、
前記絶縁接合部は、前記半導体素子が接合される端部から前記多層基板が接合される端部に向けて先細な形状に形成されている、回路基板。 - 請求項12記載の回路基板であって、
前記絶縁接合部は、テーパー形状に形成されている、回路基板。
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