Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
  • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D1/00—Resistors, capacitors or inductors
  • H10D1/40—Resistors
  • H10D1/47—Resistors having no potential barriers
  • H10D1/474—Resistors having no potential barriers comprising refractory metals, transition metals, noble metals, metal compounds or metal alloys, e.g. silicides
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D1/00—Resistors, capacitors or inductors
  • H10D1/60—Capacitors
  • H10D1/62—Capacitors having potential barriers
  • H10D1/66—Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
  • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
  • H10D30/0295—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the source electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
  • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
  • H10D64/251—Source or drain electrodes for field-effect devices
  • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
• • H—ELECTRICITY
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
  • H10D64/251—Source or drain electrodes for field-effect devices
  • H10D64/257—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
  • H10D84/141—VDMOS having built-in components
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
  • H10D84/813—Combinations of field-effect devices and capacitor only
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
  • H10D64/251—Source or drain electrodes for field-effect devices
  • H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies

Definitions

• This relates to semiconductor devices including extended drain metal oxide semiconductor (MOS) transistors.
• MOS metal oxide semiconductor
• a semiconductor device may be part of or contain a circuit which produces undesired voltage excursions, such as a buck converter circuit which receives an input DC voltage and generates an output DC voltage that is lower than the input voltage.
• the semiconductor device may include an extended drain metal oxide semiconductor (MOS) transistor, which, during operation of the circuit, switching of the MOS transistor between the on state and the off state may cause undesirable voltage oscillations, commonly referred to as ringing, at the drain node. It may be desirable to add a snubber to the semiconductor device which damps the ringing. Integrating a snubber in the semiconductor device with desired performance and without significantly increasing fabrication cost and complexity of the semiconductor device may be problematic.
• MOS metal oxide semiconductor
• MOS transistor may be formed with an integrated snubber by a process of forming a drain drift region in an extended drain of the MOS transistor, and forming a snubber capacitor including a capacitor dielectric layer and capacitor plate over the extended drain.
• a snubber resistor is formed over a gate of the MOS transistor and connected in series between the capacitor plate and a source of the MOS transistor.
• the snubber resistor and snubber capacitor form the integrated snubber for the MOS transistor.
• the resistor may be formed concurrently with other elements of the semiconductor device.
• FIGS. 1A - 1C are perspective cross sections illustrating stages in the fabrication of a semiconductor device including an extended drain MOS transistor with a snubber according to an example embodiment.
• FIGS. 2A- 2C are perspective cross sections illustrating stages in the fabrication of a semiconductor device including an extended drain MOS transistor with a snubber according to a modified embodiment.
• FIGS. 3A- 3C are perspective cross sections illustrating stages in the fabrication of a semiconductor device including an extended drain MOS transistor with a snubber according to another modified embodiment.
• FIGS. 4A and 4B are perspective cross sections illustrating stages in the fabrication of a semiconductor device including an extended drain MOS transistor with a snubber according to another modified embodiment.
• MOS transistor may be formed with an integrated snubber integrated into the MOS transistor.
• the semiconductor device may be formed by a process including steps of forming a drain drift region in an extended drain of the MOS transistor
• a snubber capacitor is formed over the drain drift region by forming a capacitor dielectric layer and capacitor plate over the extended drain.
• a snubber resistor is formed over a gate of the MOS transistor and connected in series between the capacitor plate and a source of the MOS transistor.
• the snubber resistor and snubber capacitor form the integrated snubber for the MOS transistor.
• the resistor may be formed concurrently with other elements of the semiconductor device.
• the resistor may be formed concurrently with the capacitor plate.
• the semiconductor device may be a discrete power device which includes the extended drain MOS transistor with the integrated snubber.
• the semiconductor device may be an integrated circuit which includes other circuits, such as sense circuits and/or control circuits, in addition to the extended drain MOS transistor with the integrated snubber.
• FIGS. 1A - 1C illustrate stages in the fabrication of a semiconductor device including an extended drain MOS transistor with a snubber according to an example embodiment.
• the semiconductor device 100 is formed in and on a semiconductor substrate 102 which may be a single crystal silicon wafer, a silicon-on- insulator (SOI) wafer, a hybrid orientation technology (HOT) wafer with regions of different crystal orientations, or other material appropriate for fabrication of the semiconductor device 100.
• Semiconductor material at a top surface of the substrate 102 is p-type.
• Field oxide 104 may be formed at the top surface of the substrate 102.
• the field oxide 104 may include silicon dioxide between 250 and 600 nanometers thick, and may be formed by shallow trench isolation (STI) or local oxidation of silicon (LOCOS) processes. In STI processes, silicon dioxide may be deposited by high density plasma (HDP) or high aspect ratio process (HARP).
• HDP high density plasma
• HTP high aspect ratio process
• the semiconductor device 100 contains the extended drain MOS transistor
• the MOS transistor 106 has an n-type drain drift region 108 extending to the top surface of the substrate 102.
• the drain drift region 108 may be formed, for example, by ion implanting a first set of n-type dopants, such as phosphorus and arsenic, and possibly antimony, at doses from 1 ⁇ 10 11 to 1 ⁇ 10 13 atoms/cm 2 , into an area exposed by a drift region implant mask, such as a photoresist pattern..
• a subsequent anneal process activates at least a portion of the first set of n-type dopants to form the drain drift region 108.
• the drain drift region 108 may extend to a depth between 350 to 1000 nanometers in the substrate 102.
• the drain drift region 108 may be formed concurrently with other components of the
• semiconductor device 100 such as n-type wells for p-channel MOS transistors, not shown.
• the MOS transistor 106 further includes a p-type body region 110 in the substrate 102 abutting the drain drift region 108.
• the body region 110 may be formed, for example, by ion implanting a set of p-type dopants, such as boron and possibly gallium and/or indium, at doses from 1 ⁇ 10 11 to 1 ⁇ 10 14 atoms/cm 2 , into an area exposed by a body region implant mask, such as a photoresist pattern.. A subsequent anneal process activates at least a portion of the p-type dopants to form the body region 110.
• the body region 110 may extend to a depth between 300 to 1000 nanometers in the substrate 102.
• the body region 110 may be formed concurrently with other components of the semiconductor device 100 such as p-type wells for n-channel MOS transistors, not shown.
• the anneal process to activate the p- type dopants may be performed concurrently with the anneal process to activate the first set of n-type dopants in the drain drift region 108.
• a gate dielectric layer 112 of the MOS transistor 106 is formed over the substrate 102 overlapping a portion of the body region 110 and a portion of the drain drift region 108.
• the gate dielectric layer 112 may be one or more layers of silicon dioxide, silicon oxy-nitride, aluminum oxide, aluminum oxy-nitride, hafnium oxide, hafnium silicate, hafnium silicon oxy-nitride, zirconium oxide, zirconium silicate, zirconium silicon oxy- nitride, a combination of the aforementioned materials, or other insulating material.
• the gate dielectric layer 112 may include nitrogen as a result of exposure to a nitrogen containing plasma or a nitrogen containing ambient gas at temperatures between 50 C and 800 C.
• the gate dielectric layer 112 may be formed by any of a variety of gate dielectric formation processes, for example thermal oxidation, plasma nitridation of an oxide layer, and/or dielectric material deposition by atomic layer deposition (ALD).
• the gate dielectric layer 112 may be, for example, between 10 and 80 nanometers thick.
• a gate 114 of the MOS transistor 106 is formed on the gate dielectric layer
• the gate 114 may include, for example, one or more layers of polycrystalline silicon, commonly referred to as polysilicon, metal silicide such as tungsten silicide, titanium silicide, cobalt silicide and/or nickel silicide, and/or metal such as aluminum, tungsten and/or titanium nitride.
• polysilicon commonly referred to as polysilicon
• metal silicide such as tungsten silicide, titanium silicide, cobalt silicide and/or nickel silicide
• metal such as aluminum, tungsten and/or titanium nitride.
• Optional gate sidewalls 116 may be formed on lateral surfaces of the gate 114, for example by deposition of one or more conformal layers of silicon nitride and/or silicon dioxide on a top and lateral surfaces of the gate 114 and the top surface of the substrate 102, followed by removal of the conformal layer material from the top surface of the gate 114 and the top surface of the substrate 102 by anisotropic etching methods such as reactive ion etching (RIE), leaving the conformal layer material on the lateral surfaces of the gate 114 so as to form the gate sidewalls 116.
• RIE reactive ion etching
• the MOS transistor 106 also includes an n-type source region 118 and possibly an optional n-type drain contact region 120.
• the source region 118 is formed in the substrate 102 adjacent to the gate 114 opposite from the drain drift region 108.
• the drain contact region 120 is formed in the substrate 102 contacting the drain drift region 108 opposite from the gate 114.
• the source region 118 and the drain contact region 120 may be formed, for example, by ion implanting a second set of n-type dopants, such as phosphorus and arsenic, and possibly antimony, at a total dose between 3 ⁇ 10 14 and 1 ⁇ 10 16 atoms/cm 2 into an area exposed by a source/drain implant mask, such as a photoresist pattern.
• a subsequent source/drain anneal process activates a portion of the second set of n-type dopants to form the source region 118 and the drain contact region 120.
• the source region 118 and the drain contact region 120 may extend from the top surface of the substrate 102 to a depth between 100 and 500 nanometers.
• the source region 118 and the drain contact region 120 may be formed concurrently with other components of the semiconductor device 100 such as source/drain regions for other n-channel MOS transistors, not shown.
• a layer or metal silicide, not shown, such as titanium silicide, cobalt silicide or nickel silicide, may be formed on the source region 118 and the drain contact region 120.
• An element of the field oxide 104 may be disposed in the drain drift region
• the drain contact region 120 extends under the field oxide 104.
• a snubber capacitor dielectric layer 122 is formed over the drain drift region 108 adjacent to the gate 114.
• the snubber capacitor dielectric layer 122 may optionally overlap the field oxide element 104 disposed in the drain drift region 108 if present.
• the snubber capacitor dielectric layer 122 may include, for example, one or more layers of silicon dioxide, silicon oxy-nitride, aluminum oxide, aluminum oxy-nitride, hafnium oxide, hafnium silicate, hafnium silicon oxy-nitride, zirconium oxide, zirconium silicate, zirconium silicon oxy-nitride, a combination of the aforementioned materials, or other insulating material.
• the snubber capacitor dielectric layer 122 may be, for example, between 10 and 200 nanometers thick.
• the snubber capacitor dielectric layer 122 may be formed by any of a variety of gate dielectric formation processes, for example thermal oxidation, plasma nitridation of an oxide layer, and/or dielectric material deposition by ALD.
• a snubber capacitor plate 124 is formed over the snubber capacitor dielectric layer 122 so as to be electrically isolated from the drain drift region 108.
• the snubber capacitor plate 124 may be formed of any electrically conductive material, such as one or more layers of polysilicon, tungsten, aluminum, titanium, tantalum, titanium tungsten, metal silicide, titanium nitride, tantalum nitride, and/or tungsten nitride.
• the snubber capacitor plate 124 may be, for example between 1 and 10 microns wide in a direction perpendicular to a lateral boundary of the gate 114.
• the snubber capacitor plate 124 may be formed concurrently with other components in the semiconductor device 100 such as decoupling capacitor plates, not shown.
• the snubber capacitor plate 124, the snubber capacitor dielectric layer 122 and the drain drift region 108 form a snubber capacitor 126.
• a pre -metal dielectric (PMD) layer is formed over an existing top surface of the semiconductor device 100.
• the PMD layer may be, for example, a dielectric layer stack including a PMD liner, a PMD main layer, and an optional PMD cap layer.
• the PMD liner may be silicon nitride or silicon dioxide, 10 to 100 nanometers thick, deposited by plasma enhanced chemical vapor deposition (PECVD) on the existing top surface of the
• the PMD main layer may be a layer of silicon dioxide formed by a HARP process followed by a layer of silicon dioxide, phospho-silicate glass (PSG) or boro-phospho-silicate glass (BPSG), 100 to 1000 nanometers thick, deposited by a PECVD process on a top surface of the PMD liner, and sometimes leveled by a chemical-mechanical polish (CMP) process.
• the optional PMD cap layer may be 10 to 100 nanometers of a hard material such as silicon nitride, silicon carbide nitride or silicon carbide, formed on a top surface of the PMD main layer.
• the PMD layer is not shown in FIG. 1C to more clearly illustrate the other elements of the MOS transistor 106.
• one or more snubber capacitor contacts 128 are formed through the PMD layer so as to make electrical contact with the snubber capacitor plate 124.
• One or more snubber source contacts 130 are formed in the PMD layer so as to make electrical contact with the source region 118.
• the snubber capacitor contacts 128 and snubber source contacts 130 may be formed concurrently.
• One or more transistor drain contacts 132 are formed through the PMD layer so as to make electrical contact with the drain drift region 108, through the drain contact region 120 if present.
• One or more transistor source contacts 134 are formed through the PMD layer so as to make electrical contact with the source region 118.
• the transistor drain contacts 132 and the transistor source contacts 134 may be formed concurrently, and may be formed concurrently with the snubber capacitor contacts 128 and the snubber source contacts 130.
• the transistor drain contacts 132, the transistor source contacts 134, the snubber capacitor contacts 128 and the snubber source contacts 130 may be formed, for example, by defining contact areas on a top surface of the PMD with a contact photoresist pattern, not shown, etching contact holes in the contact areas by removing PMD layer material using etching methods such as RIE to expose the snubber capacitor plate 124, the source region 118 and the drain contact region 120, and filling the contact holes with a contact liner, such as titanium and titanium nitride, and a contact fill metal, such as tungsten, followed by removal of the contact fill metal and contact liner from the top surface of the PMD layer using etching and/or CMP methods.
• a contact liner such as titanium and titanium nitride
• a contact fill metal such as tungsten
• a snubber resistor link 136 is formed over the PMD layer so as to make electrical contact with the snubber capacitor contacts 128 and the snubber source contacts 130.
• a drain interconnect 138 is formed over the PMD layer so as to make electrical contact with the transistor drain contacts 132 and a source interconnect 140 is formed over the PMD layer so as to make electrical contact with the transistor source contacts 134.
• the drain interconnect 138, the source interconnect 140 and the snubber resistor link 136 are formed concurrently, and may be formed concurrently with other interconnects, not shown, in the semiconductor device 100.
• the drain interconnect 138, the source interconnect 140 and the snubber resistor link 136 may be formed using an aluminum metallization process, which includes forming a layer of barrier metal such as titanium tungsten or titanium nitride between 5 and 15 nanometers thick on the PMD layer, forming a layer of aluminum interconnect metal such as an alloy of 96 percent aluminum, 2 percent silicon and 2 percent copper between 100 and 1500 nanometers thick on the layer of barrier metal, and forming a layer of cap metal such as titanium tungsten or titanium nitride between 5 and 15 nanometers thick on the layer of aluminum interconnect metal.
• barrier metal such as titanium tungsten or titanium nitride between 5 and 15 nanometers thick on the PMD layer
• aluminum interconnect metal such as an alloy of 96 percent aluminum, 2 percent silicon and 2 percent copper between 100 and 1500 nanometers thick on the layer of barrier metal
• cap metal such as titanium tungsten or titanium nitride between 5 and 15 nanometers thick on the layer of aluminum interconnect metal.
• a metallization etch mask such as a photoresist pattern is formed over the layer of cap metal so as to expose the layer of cap metal in areas to remove unwanted metal.
• a metallization etch process is performed, such as an RIE step including fluorine to remove the cap metal in the exposed area, a subsequent RIE step including chlorine to etch the aluminum interconnect metal with fluorine to passivate lateral surfaces of the etched aluminum interconnect metal, followed by another RIE step including fluorine to etch the barrier metal, so as to leave an interconnect element.
• the drain interconnect 138, the source interconnect 140 and the snubber resistor link 136 may be formed using a copper damascene interconnect process, which includes forming an interlevel dielectric (ILD) layer such as silicon dioxide or a low-k dielectric over the PMD layer, and etching trenches in the ILD layer, commonly between 100 and 250 nanometers deep, in areas defined for the copper damascene interconnects. The trenches expose top surfaces of the drain interconnect 138, the source interconnect 140 and the snubber resistor link 136.
• ILD interlevel dielectric
• a layer of liner metal such as tantalum nitride is formed on a bottom and sides of the trenches, commonly by physical vapor deposition, atomic layer deposition or chemical vapor deposition.
• a seed layer of copper is formed on the liner metal, commonly by sputtering.
• the trenches are subsequently filled with copper, commonly by electroplating. Copper and liner metal are removed from a top surface of the ILD layer by CMP and etch processes, leaving the copper damascene interconnects in the ILD layer.
• the snubber capacitor contacts 128, the snubber resistor link 136 and the snubber source contacts 130 form a snubber resistor 142 which is connected in series between the snubber capacitor plate 124 and the source region 118.
• One or more resistor apertures 144 may be formed in the snubber resistor link 136 to increase an electrical resistance of the snubber resistor 142.
• a total quantity of the snubber capacitor contacts 128 and/or a total quantity of the snubber source contacts 130 may be selected to provide a desired value of the electrical resistance of the snubber resistor 142.
• the electrical resistance of the snubber resistor 142 may be, for example, between 0.5 ohms and 20 ohms.
• the snubber resistor 142 and the snubber capacitor 126 form an integrated snubber 146.
• FIGS. 2A - 2C illustrate stages in the fabrication of a semiconductor device including an extended drain MOS transistor with a snubber according to a modified example embodiment.
• the semiconductor device 200 is formed in and on a semiconductor substrate 202 as described in reference to FIG. 1 A.
• Field oxide may optionally be formed at the top surface of the substrate 202, as described in reference to FIG. 1 A.
• the MOS transistor 204 has an n-type drain drift region 206, as described in reference to FIG. 1 A, extending to the top surface of the substrate 202.
• the MOS transistor 204 further includes a p-type body region 208 in the substrate 202 abutting the drain drift region 206, as described in reference to FIG. 1A.
• a gate dielectric layer 210, gate 212 and optional gate sidewalls 214 of the MOS transistor 204 are formed over the substrate 202 overlapping a portion of the body region 208 and a portion of the drain drift region 206, as described in reference to FIG. 1 A.
• the MOS transistor 204 also includes an n-type source region 216 and possibly an optional n-type drain contact region 218, as described in reference to FIG. 1 A.
• a snubber capacitor dielectric layer 220 is formed over an existing top surface of the semiconductor device 200.
• the snubber capacitor dielectric layer 220 may be formed of materials described in reference to FIG. IB. In the instant embodiment, the snubber capacitor dielectric layer 220 extends above the drain drift region 206 and over the gate 212 and source region 216.
• a snubber resistor/capacitor layer 222 is formed on the snubber capacitor dielectric layer 220, extending above the drain drift region 206 and over the gate 212 and source region 216.
• the snubber resistor/capacitor layer 222 is patterned so as to be electrically isolated from other components, not shown, in the semiconductor device 200.
• the snubber resistor/capacitor layer 222 may include one or more layers of electrically conductive material such as polysilicon, metal silicide such as tungsten silicide, titanium silicide, cobalt silicide or nickel silicide, metal such as aluminum, tungsten, titanium, tantalum, or metal alloy such as titanium tungsten, titanium nitride, tantalum nitride, nickel chromium, silicon chromium or thin film resistor material such as cermet, a ceramic-metal material.
• electrically conductive material such as polysilicon, metal silicide such as tungsten silicide, titanium silicide, cobalt silicide or nickel silicide, metal such as aluminum, tungsten, titanium, tantalum, or metal alloy such as titanium tungsten, titanium nitride, tantalum nitride, nickel chromium, silicon chromium or thin film resistor material such as cermet, a ceramic-metal material.
• a portion of the snubber resistor/capacitor layer 222 over the drain drift region 206 forms a snubber capacitor plate 224.
• the snubber capacitor plate 224, the snubber capacitor dielectric layer 220 and the drain drift region 206 form a snubber capacitor 226.
• a thickness of the snubber resistor/capacitor layer 222 may be selected so as to provide a desired value of electrical resistance of the snubber resistor 228.
• One or more resistor apertures 230 may be formed in the snubber resistor/capacitor layer 222 so as to increase the electrical resistance of the snubber resistor 228.
• the electrical resistance of the snubber resistor 228 may be, for example, between 0.5 and 20 ohms.
• a PMD layer is formed over an existing top surface of the semiconductor device 200, as described in reference to FIG. 1C. The PMD layer is not shown in FIG. 2C to more clearly illustrate the other elements of the MOS transistor 204.
• one or more transistor drain contacts 232 are formed through the PMD layer so as to make electrical contact with the drain drift region 206, through the drain contact region 218 if present.
• One or more transistor source contacts 234 are formed through the PMD layer so as to make electrical contact with the source region 216 and the snubber resistor 228.
• the transistor drain contacts 232 and the transistor source contacts 234 may be formed as described in reference to FIG. 1C.
• the snubber resistor 228 and the snubber capacitor 226 form an integrated snubber 236.
• FIGS. 3A - 3C illustrate stages in the fabrication of a semiconductor device including an extended drain MOS transistor with a snubber according to another modified example embodiment.
• the semiconductor device 300 is formed in an on a thin semiconductor substrate 302.
• the substrate 302 may be single crystal silicon or a semiconductor allow such as silicon germanium. In the instant embodiment, the substrate 302 is between 5 and 100 microns thick.
• the MOS transistor 304 includes an n-type drain drift region 306 which extends from a top surface of the substrate 302 to, or proximate to, a bottom surface of the substrate 302.
• the MOS transistor 304 may optionally include an n- type drain contact region 308 at the bottom surface of the substrate 302 and contacting the drain drift region 306.
• the drain contact region 308 may be formed by ion implanting the bottom surface of the substrate 302 with n-type dopants and subsequently performing an anneal process to activate at least a portion of the implanted dopants.
• the MOS transistor 304 further includes a drain contact metal layer 310 on, and making electrical connection with, the bottom surface of the substrate 302.
• the MOS transistor 304 includes a p-type body region 312 in the substrate
• MOS transistor 304 also includes an n-type source region 318 formed in the substrate 302 adjacent to the gate 316 opposite from the drain drift region 306, and isolated from the drain drift region 306 by the body region 312.
• a snubber capacitor dielectric layer 320 is formed over an existing top surface of the semiconductor device 300.
• the snubber capacitor dielectric layer 320 may be formed of materials described in reference to FIG. IB.
• the snubber capacitor dielectric layer 320 extends above the drain drift region 306 and over the gate 316 and source region 318.
• a source trench 322 is formed in the substrate 302 through the source region
• a snubber resistor/capacitor layer 324 is formed on the snubber capacitor dielectric layer 320, extending above the drain drift region 306 and over the gate 316 and source region 318, and into the source trench 322 so as to make electrical contact with the source region 318 and the body region 312.
• the snubber resistor/capacitor layer 324 is patterned so as to be electrically isolated from other components, not shown, in the semiconductor device 300.
• the snubber resistor/capacitor layer 324 may be formed of the materials described in reference to FIG. 2C.
• a portion of the snubber resistor/capacitor layer 324 over the drain drift region 306 forms a snubber capacitor plate 326.
• the snubber capacitor plate 326, the snubber capacitor dielectric layer 320 and the drain drift region 306 form a snubber capacitor 328.
• a thickness of the snubber resistor/capacitor layer 324 may be selected so as to provide a desired value of electrical resistance of the snubber resistor 330.
• One or more resistor apertures 332 may be formed in the snubber resistor/capacitor layer 324 so as to increase the electrical resistance of the snubber resistor 330.
• the electrical resistance of the snubber resistor 330 may be, for example, between 0.5 and 20 ohms.
• the snubber resistor 330 and the snubber capacitor 328 form an integrated snubber 334.
• FIGS. 4A and 4B illustrate stages in the fabrication of a semiconductor device including an extended drain MOS transistor with a snubber according to another modified example embodiment.
• the semiconductor device 400 is formed in and on a semiconductor substrate 402 as described in reference to FIG. 1 A.
• Field oxide 404 may be formed at the top surface of the substrate 402, as described in reference to FIG. 1 A, for example to laterally isolate the MOS transistor 406 from other components, not shown, in the semiconductor device 400.
• the MOS transistor 406 has an n-type drain drift region 408, as described in reference to FIG. 1 A, extending to the top surface of the substrate 402.
• the MOS transistor 406 further includes a p-type body region 410 in the substrate 402 abutting the drain drift region 408, as described in reference to FIG. 1A.
• a gate dielectric layer 412, gate 414 and optional gate sidewalls 416 of the MOS transistor 406 are formed over the substrate 402 overlapping a portion of the body region 410 and a portion of the drain drift region 408, as described in reference to FIG. 1 A.
• the MOS transistor 406 also includes an n- type source region 418 and possibly an optional n-type drain contact region 420, as described in reference to FIG. 1 A.
• the drain contact region 420 may be laterally isolated by an additional element of field oxide 404, as depicted in FIG. 4A.
• a snubber capacitor dielectric layer 422 is formed over the drain drift region
• the snubber capacitor dielectric layer 422 may optionally overlap the field oxide element 404 disposed in the drain drift region 408 if present.
• a snubber capacitor plate 424 is formed over the snubber capacitor dielectric layer 422 so as to be electrically isolated from the drain drift region 408, as described in reference to FIG. IB.
• the snubber capacitor plate 424, the snubber capacitor dielectric layer 422 and the drain drift region 408 form a snubber capacitor 426.
• a PMD layer is formed over an existing top surface of the semiconductor device 400, as described in reference to FIG. 1C.
• the PMD layer is not shown in FIG. 4B to more clearly illustrate the other elements of the MOS transistor 406.
• One or more snubber capacitor contacts 428 for example continuous snubber capacitor contacts 428 as depicted in FIG. 4A, are formed through the PMD layer so as to make electrical contact with the snubber capacitor plate 424, as described in reference to FIG. 1C.
• One or more transistor drain contacts 430 are formed through the PMD layer so as to make electrical contact with the drain drift region 408, through the drain contact region 420 if present.
• One or more transistor source contacts 432 are formed through the PMD layer so as to make electrical contact with the source region 418.
• the transistor drain contacts 430, the transistor source contacts 432 and the snubber capacitor contacts 428 may be formed as described in reference to FIG. 1C, using contact trenches for continuous contacts.
• a snubber resistor 434 is formed over the PMD layer so as to make electrical contact with the snubber capacitor contacts 428 and the transistor source contacts 432.
• the snubber resistor 434 is patterned so as be electrically isolated from other components, not shown, in the semiconductor device 400. A portion of the snubber resistor 434 is removed in FIG. 4A to illustrate the transistor source contacts 432.
• the snubber resistor 434 may include one or more layers of electrically conductive material, such as such as polysilicon, metal silicide such as tungsten silicide, titanium silicide, cobalt silicide or nickel silicide, metal such as aluminum, tungsten, titanium, tantalum, or metal alloy such as titanium tungsten, titanium nitride, tantalum nitride, nickel chromium, silicon chromium or thin film resistor material such as cermet.
• One or more resistor apertures 436 may be formed in the snubber resistor 434 so as to increase the electrical resistance of the snubber resistor 434.
• the electrical resistance of the snubber resistor 434 may be, for example, between 0.5 and 20 ohms.
• the snubber resistor 434 and the snubber capacitor 426 form an integrated snubber 438.
• a drain interconnect 440 is formed on the PMD layer so as to make electrical contact with the transistor drain contacts 430.
• a source interconnect 442 is formed on the snubber resistor 434 so as to make electrical contact with the transistor source contacts 432 through the snubber resistor 434.
• the drain interconnect 440 and the source interconnect 442 may be formed by an aluminum metallization process or a copper damascene metallization process, as described in reference to FIG. 1C.

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• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)
• Semiconductor Integrated Circuits (AREA)
• Electrodes Of Semiconductors (AREA)

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• 2012
  • 2012-07-03 US US13/540,813 patent/US8796745B2/en active Active
  • 2012-07-05 JP JP2014519290A patent/JP6101688B2/ja active Active
  • 2012-07-05 CN CN201280043011.7A patent/CN103782387B/zh active Active
  • 2012-07-05 WO PCT/US2012/045554 patent/WO2013006699A2/en not_active Ceased
• 2014
  • 2014-06-26 US US14/315,701 patent/US9385216B2/en active Active

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