CN111129148A - 半导体装置的形成方法 - Google Patents

半导体装置的形成方法 Download PDF

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Publication number
CN111129148A
CN111129148A CN201911053141.9A CN201911053141A CN111129148A CN 111129148 A CN111129148 A CN 111129148A CN 201911053141 A CN201911053141 A CN 201911053141A CN 111129148 A CN111129148 A CN 111129148A
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layer
contact
air gap
source
gate
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杨世海
李凯璿
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种半导体装置的形成方法，包括：提供第一晶体管，其包含第一栅极结构以及与第一栅极结构相邻的源极/漏极结构。沿着位于源极/漏极结构上的接点开口的侧壁表面形成空洞。在形成空洞之后，沉积牺牲层于空洞中包含的接点开口的侧壁表面与下表面上，其中牺牲层填入空洞。沿着接点开口的下表面移除牺牲层的第一部分，以露出源极/漏极结构的一部分。形成金属插塞于露出的源极/漏极结构的部分上。移除牺牲层的保留部分，以形成气隙于金属插塞与第一栅极结构之间。之后沉积密封层于气隙上，以形成气隙间隔物。

Description

半导体装置的形成方法
技术领域
本发明实施例一般涉及半导体装置与其制作方法，更特别涉及形成气隙于源极/漏极接点结构与周围的金属栅极之间。
背景技术
电子产业已经历对更小且更快的半导体装置的需求持续增加，且半导体装置支援的大量复杂功能同时增加。综上所述，半导体产业的持续趋势为形成低成本、高效能、与低能耗的集成电路。这些目标的主要实现方法为缩小半导体集成电路的尺寸(比如最小结构尺寸)，进而改善产能并降低相关成本。然而尺寸缩小亦增加半导体形成工艺的复杂度。为了实现半导体集成电路与装置中的持续进展，半导体的形成工艺与技术亦需类似进展。
举例来说，随着装置尺寸缩小，内连线如源极/漏极接点插塞与附近的栅极之间的耦合电容增加。耦合电容增加会劣化装置效能。为了降低耦合电容，可在源极/漏极结构与附近的栅极之间采用较低介电常数的绝缘材料如低介电常数的介电层与气隙。然而这些材料经证明为难以制作。在一些例子中，低介电常数的介电材料硬脆、不稳定、且难以沉积，其对蚀刻、退火、与研磨等工艺敏感，且难以控制气隙形成。
因此现有技术仍未完全符合所有方面的需求。
发明内容
本发明一实施例提供的半导体装置的形成方法，包括：提供第一晶体管，其包含第一栅极结构以及与第一栅极结构相邻的源极/漏极结构；沿着位于源极/漏极结构上的接点开口的侧壁表面形成空洞；在形成空洞之后，沉积牺牲层于空洞中包含的接点开口的侧壁表面与下表面上，其中牺牲层填入空洞；沿着接点开口的下表面移除牺牲层的第一部分，以露出源极/漏极结构的一部分；形成接点结构于露出的源极/漏极结构的部分上；移除牺牲层的保留部分，以形成气隙于接点结构与第一栅极结构之间；以及沉积密封层于气隙上，以形成气隙间隔物。
本发明一实施例提供的半导体装置的形成方法，包括：提供第一晶体管，其包括第一栅极结构；第二晶体管，其包括第二栅极结构；源极/漏极结构，位于第一栅极结构与第二栅极结构之间并与第一栅极结构与第二栅极结构的每一者相邻；以及接点开口，位于源极/漏极结构上；形成第一空洞于接点开口的第一侧壁表面上，以及第二开口于接点开口的第二侧壁表面上；沿着第一空洞与第二空洞中包含的第一侧壁表面与第二侧壁表面沉积牺牲层；形成接点结构于源极/漏极结构上，其中接点结构位于沿着第一侧壁表面的牺牲层与沿着第二侧壁表面的牺牲层之间；在形成接点结构之后，自第一侧壁表面与第二侧壁表面移除牺牲层，以形成位于接点结构与第一栅极结构之间的第一气隙与位于接点结构与第二栅极结构之间的第二气隙；以及沉积密封层于第一气隙与第二气隙上，以形成与接点结构相邻的多个气隙间隔物。
本发明一实施例提供的半导体装置，包括：栅极结构，以及与栅极结构相邻的源极/漏极结构；接点结构，位于源极/漏极结构上并与栅极结构相邻；以及气隙间隔物，包括密封层形成于空洞上，其中气隙间隔物位于接点结构与栅极结构之间，且其中空洞包括弧形侧壁轮廓。
附图说明
图1是本发明多种实施例中，形成半导体装置的方法的流程图。
图2、图3、图4、图5、图6、图7、图8、图9、图10、图11、图12、图13、与图14是本发明多种实施例中，制作半导体装置的多种阶段的剖视图。
附图标记说明：
θ 倾斜角度
D1、D2 距离
L1、L2 部分
T1、T2 厚度
100 方法
102 基板
106 源极/漏极结构
110 层间介电层
112 栅极间隔物
116a、116b 栅极堆叠
118 接点蚀刻停止层
120 硬遮罩层
200 装置
302 接点开口
402 聚合物层
404 悬吊区
502 蚀刻工艺
504、902 空洞
702 牺牲层
802 阻挡层
1002 金属层
1002A 金属硅化物
1102 金属接点层
1102A 金属插塞
1020、1040、1060、1080、1100、1120、1140、1160、1180、1200、1220 步骤
1302 气隙
1402 密封层
1404 单元
具体实施方式
下述内容提供的不同实施例或实例可实施本发明的不同结构。下述特定构件、与配置的实施例是用以简化本发明内容而非局限本发明。举例来说，形成第一构件于第二构件上的叙述包含两者直接接触的实施例，或两者之间隔有其他额外构件而非直接接触的实施例。另一方面，本发明的多个实例可重复采用相同标号以求简洁，但多种实施例及/或设置中具有相同标号的元件并不必然具有相同的对应关系。此外，可由不同比例任意示出多种结构，使附图简化与清楚。
此外，空间性的相对用语如“下方”、“其下”、“较下方”、“上方”、“较上方”或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件，而非局限于图示方向。举例来说，若附图中的装置翻转，则位于其他元件下方或之下的元件，将转为位于其他元件上方或之上。因此例示性的用语“下方”可包含上方与下方的方向。元件亦可转动90°或其他角度，因此方向性用语仅用以说明图示中的方向。
本发明实施例一般关于半导体装置与其制作方法，更特别关于形成气隙于源极/漏极接点结构与周围的金属栅极之间。在一些例子中，源极/漏极接点结构的上视形状为圆形、卵形、或矩形。为了说明，源极/漏极接点结构可视作接点结构、接点插塞、金属插塞、通孔、通孔插塞、或金属接点。随着鳍状场效晶体管技术朝向更小的技术节点，鳍状物间距减少对金属栅极与连接至源极/漏极结构(如外延的源极/漏极结构)的相邻接点插塞之间所用的材料造成明显限制。为了使金属栅极与接点插塞之间的耦合电容最小化，气隙有助于降低耦合电容，因为空气的介电常数(等于1)小于其他介电材料的介电常数。然而在形成接点插塞之前即形成气隙的话，后续形成接点插塞的方法易于损伤气隙。举例来说，在形成接点插塞时若未完全对准图案化接点插塞所用的遮罩与下方的层状物构件，则可能发生层叠偏移。层叠偏移可能使接点孔的位置非常靠近(若未接触)相邻的金属栅极。在此例中，蚀刻接点孔或露出已密封的气隙，而露出的气隙会部分或完全填有氮化物衬垫层，其形成于蚀刻接点孔之后。气隙因此丧失其降低耦合电容的目的。
本发明实施例比现有技术提供更多优点，但应理解其他实施例可提供不同优点，此处不必说明所有优点，且所有实施例不需具有特定优点。举例来说，此处所述的实施例可在形成接点插塞之后形成气隙(而非在形成接点插塞之前或同时形成气隙)，以缓解现有方法的多种缺点。举例来说，可选择性移除虚置结构以形成气隙，且虚置结构与接点插塞相邻。通过虚置结构材料与直接接触虚置结构的其他材料之间的蚀刻选择性，可实施选择性移除虚置结构。此外，此处接露在接点插塞后形成气隙的方法提供自对准的气隙，因为气隙位置取决于虚置结构的位置。在至少一些之前的实施方式中，与接点插塞相邻的气隙在不缩小接点金属尺寸(如钴接点金属尺寸)的情况下，提供插入额外牺牲层所用的有限空间。在此例中，可减少装置的有效电容，但会增加有效电阻。在本发明一些实施例中，可采用聚合物盖干蚀刻方法(与源极/漏极干蚀刻促使近接法类似)形成大幅促进的接点气隙间隔物，以形成较大的气隙间隔物(比如较大体积的气隙)并增加接点金属的关键尺寸(比如钴接点金属的关键尺寸)，即同时改善电容与电阻。如此一来，可有效降低金属堆叠与接点插塞之间的耦合电容。一般而言，此处提供的多种实施例改善有效电容与有效电阻，移除金属栅极至源极/漏极接点的金属短路风险、并提供可控制的气隙体积及改良的气隙密封。本发明实施例的额外细节将提供如下，且本技术领域中技术人员由本发明实施例可轻易思及额外优点及/或其他优点。
图1是一些实施例中，形成含有接点气隙的装置200所用的方法100的流程图。方法100将搭配图2至图14详述于下，其显示制作的多种阶段的装置200的剖视图。应理解的是在方法100之前、之中、与之后可实施额外步骤，且方法100的多种实施例可置换或省略一些所述的工艺步骤。可以理解的式，方法100的部分可为已知的互补式金属氧化物半导体技术工艺流程，而此处仅简述一些工艺。
在一些实施例中，装置200可为或包含鳍状场效晶体管装置，其可包含于微处理器、存储器单元、及/或其他集成电路装置中。装置200可为制作下述芯片时的中间装置：集成电路芯片、单芯片系统、或其他种类的芯片或其部分，其可包含多种被动与主动的半导体装置如电阻、电容、电感、二极管、p型晶体管、n型晶体管、金属氧化物半导体晶体管、互补式金属氧化物半导体晶体管、双极晶体管、高电压或低电压晶体管、高频晶体管、应变的半导体装置、绝缘层上硅装置、部分空乏的绝缘层上硅装置、完全空乏的绝缘层上硅装置、其他合适装置或构件、或上述的组合。本技术领域中技术人员应理解半导体装置或构件的其他实施例可得利于本发明实施例。此外，在后段工艺时形成的内连线可连接多个半导体电路及/或装置。亦应注意的是，已简化图2至图14使附图清楚，以利理解本发明实施例的发明概念。可添加额外结构至装置200，且装置200的其他实施例可置换、调整、或省略一些所述结构。
方法100一开始的步骤1020提供装置200，其包括栅极堆叠与源极/漏极结构。如图2所示的一实施例中，步骤1020提供装置200，其中装置200包括基板102、源极/漏极结构106、层间介电层110、栅极间隔物112、栅极堆叠116a与116b、接点蚀刻停止层118、与硬遮罩层120。
基板102可包含半导体基板如硅基板。基板102可包含多种层状物，包含导电或绝缘层形成于半导体基板上。基板102可包含多种掺杂设置，端视本技术领域已知的设计需求而定。基板102亦可包含其他半导体如锗、碳化硅、硅锗、或钻石。在其他实施例中，基板102可包含半导体化合物及/或半导体合金。此外，一些实施例中的基板102可包含外延层，可具有应力以增进效能、可包含绝缘层上硅结构、及/或可具有其他合适的增进结构。
在装置200包含鳍状场效晶体管装置的例子中，基板102可包含一或多个自基板102延伸的鳍状物单元。一或多个鳍状物单元与基板102类似，可包含硅或另一半导体元素如锗；半导体化合物如碳化硅、砷化镓、磷化镓、磷化铟、砷化铟、及/或锑化铟；半导体合金如硅锗、磷砷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟、磷砷化镓铟、或上述的组合。
在多种实施例中，源极/漏极结构106位于基板102中，且可包含n型掺杂是以用于n型场效晶体管、p型掺杂的硅锗以用于p型场效晶体管、或其他合适材料。源极/漏极结构106的形成方法可为蚀刻开口在与栅极间隔物112相邻的主动区中，接着外延成长半导体材料于开口中。可原位掺杂或异位掺杂外延成长的半导体材料。源极/漏极结构106可具有任何合适形状，且可完全或部分埋置于基板102中。举例来说，外延的源极/漏极结构106可高于、等高、或低于基板102的上表面，端视外延成长量而定。在装置200含有鳍状场效晶体管装置的实施例中，源极/漏极结构106可隆起高于鳍状物的上表面、与鳍状物的上表面等高、或维持低于鳍状物的上表面，端视外延成长的量而定。
栅极堆叠116a与116b可各自包含栅极介电层，以及形成于栅极介电层上的金属层。在一些实施例中，栅极介电层可包含界面层形成于装置200的栅极堆叠116a与116b之下的通道区上，以及高介电常数的介电层形成于界面层上。界面层可包含介电材料如氧化硅或氮氧化硅。高介电常数的介电层可包含氧化铪、氧化钛、氧化铪锆、氧化钽、氧化铪硅、氧化锆、氧化锆硅、上述的组合、或其他合适材料。在其他实施例中，栅极介电层可包含氧化硅或另一合适介电层。栅极介电层的形成方法可为化学氧化、热氧化、原子层沉积、物理气相沉积、化学气相沉积、及/或其他合适方法。金属层形成于栅极介电层上，且金属层可包含导电层如钨、氮化钛、氮化钽、氮化钨、铼、铱、钌、钼、铝、铜、钴、镍、上述的组合、及/或其他合适组成。在一些实施例中，金属层可包含第一组金属材料以用于n型装置(如n型鳍状场效晶体管)与第二阻金属材料以用于p型装置(如p型鳍状场效晶体管)。因此装置200可包含双功函数金属栅极的设置。在一些实施例中，金属层可改为包含多晶硅。金属层的形成方法可采用物理气相沉积、化学气相沉积、电子束蒸镀、及/或其他合适工艺。
栅极堆叠116a与116b的形成方法可为任何合适工艺，比如栅极优先工艺或栅极后制工艺。在栅极优先工艺的例子中，形成源极/漏极结构106之前可先沉积并图案化多种材料层，以形成栅极堆叠116a与116b。在栅极后制工艺(又称做栅极置换工艺)的例子中，先形成暂时的栅极结构(有时称做虚置栅极)。在形成源极/漏极结构106之后，接着移除暂时的栅极结构并置换为栅极堆叠116a与116b。
在多种例子中，硬遮罩层120可形成于栅极堆叠116a与116b上。在一些实施例中，硬遮罩层120可包含氧化物层(如氧化硅)与形成于氧化物层上的氮化物层(如氮化硅)。在一些例子中，氧化物层可包含热成长氧化物、化学气相沉积的氧化物、及/或原子层沉积的氧化物，且氮化物可包含化学气相沉积或其他合适技术所沉积的氮化物层。
在一些实施例中，栅极间隔物112形成于硬遮罩层120与栅极堆叠116a与116b的侧壁上。栅极间隔物112可包括介电材料如氧化硅、氮化硅、碳化硅、氮氧化硅、或上述的组合。此外，栅极间隔物112可包括单层或多层结构。在多种实施例中，栅极间隔物112的形成方法为沉积(如化学气相沉积或物理气相沉积)与蚀刻工艺。
接点蚀刻停止层118位于与栅极间隔物112相邻处。在一些例子中，接点蚀刻停止层118位于源极/漏极结构106上。在一些实施例中，接点蚀刻停止层118可包含氮化硅、氧化硅、氮氧化硅、及/或其他材料。接点蚀刻停止层118的形成方法可为一或多种方法如等离子体辅助化学气相沉积、原子层沉积、及/或其他合适方法。在一些实施例中，层间介电层110形成于接点蚀刻停止层118上，且可包含材料如四乙氧硅烷的氧化物、未掺杂的硅酸盐玻璃、或掺杂的氧化硅如硼磷硅酸盐玻璃、掺杂氟的硅酸盐玻璃、磷硅酸盐玻璃、硼硅酸盐玻璃、低介电常数的介电材料、及/或其他合适的介电材料。在多种实施例中，层间介电层110的形成方法可为可流动的化学气相沉积、等离子体辅助化学气相沉积、或其他合适方法。
方法100的步骤1040进行接点光微影(photolithography)与蚀刻工艺，以形成接点开口并露出源极/漏极结构。如图2与图3所示的一些实施例中，步骤1040进行的接点光微影步骤可包括形成光刻胶层于装置200(图2)上、曝光光刻胶至一图案(比如采用接点开口掩模)、进行曝光后烘烤工艺、与显影光刻胶以形成图案化的光刻胶层于装置200上。在一些实施例中，形成图案化的光刻胶层之后可进行接点蚀刻工艺，以形成接点开口302(图3)并露出源极/漏极结构106的部分L1。在一些例子中，接点蚀刻工艺可包含湿蚀刻、干蚀刻、或上述的组合。在一些实施例中，形成接点开口302之后可移除图案化的光刻胶层，且移除方法可采用溶剂、光刻胶剥除、灰化、或其他合适技术。值得注意的是，形成接点开口302的方法如接点蚀刻工艺，可能会蚀刻层间介电层110与接点蚀刻停止层118。
接着进行方法100的步骤1060以形成聚合物层于栅极堆叠上。如图3与图4所示的一实施例中，步骤1060可形成聚合物层402于栅极堆叠116a与116b上。具体而言，如图4所示，聚合物层402可形成于硬遮罩层120上、栅极间隔物112上、以及与栅极间隔物112相邻并接触栅极间隔物112的接点蚀刻停止层118的一部分上，使聚合物层402悬吊于栅极堆叠116a与116b(比如悬吊于栅极间隔物112与接点蚀刻停止层118)以形成悬吊区404。在所述例子中，聚合物层402的悬吊物，造成接点开口302的侧壁表面的至少一部分上的聚合物层402。在一些实施例中，悬吊区404可包含距离D1，即聚合物层402在接点开口302的顶部延伸至接点开口302中的距离。在一些例子中，悬吊区404的尺寸可包含距离D2，其定义聚合物层402覆盖的接点开口302的侧壁表面的部分。在一些实施例中，聚合物层402的厚度为约5nm至20nm，其中聚合物层402的厚度至少取决于悬吊区404的尺寸(比如距离D1及/或距离D2)。在多种例子中，聚合物层402可包含碳氟化合物为主的聚合物、聚甲基丙烯酸甲酯、或氟聚合物如全氟化烷氧基烷。聚合物层402亦可包含单一聚合物、多种聚合物的混掺物、或单体与聚合物的混掺物。此外，一些例子的聚合物层402可包含多种官能基如螯合官能基或其他合适的官能基。在一些实施例中，聚合物层402的形成工艺可采用多种方法如旋转涂布工艺、气相沉积工艺、或其他合适工艺。在一些实施例中，可进行烘烤工艺以自聚合物层402移除溶剂。可在后续阶段移除聚合物层402如下述，且移除方法可采用合适溶剂、湿蚀刻、灰化工艺、或上述的组合。
方法100的步骤1080进行蚀刻工艺，以形成空洞于接点开口的侧壁表面中。如图4与图5所示的一实施例中，步骤1080可进行蚀刻工艺502以形成空洞504于接点开口302的侧壁表面中。在一些实施例中，蚀刻工艺502可包含干蚀刻工艺如反应性离子蚀刻工艺或其他合适的蚀刻工艺。蚀刻工艺可采用多种化学物种如氟、氯、氧、或其他合适物种。在一些例子中，可最佳化蚀刻至成以蚀刻接点蚀刻停止层118与栅极间隔物112的一或两者。此外，可由倾斜角度θ进行蚀刻工艺502，其为相对于垂直于装置200的表面所测量的角度。在一些实施例中，倾斜角度θ小于约45度。在一些例子中，倾斜角度θ为约30度至45度。在多种实施例中，空洞504的轮廓取决于悬吊区404的尺寸(如上述)与蚀刻工艺502的倾斜角度θ。此外，可调整空洞504的轮廓以控制后续形成的气隙间隔物的尺寸。此外，多种实施例的空洞504的轮廓可包含弧形的侧壁轮廓。在一些例子中，由于空洞504的弧形侧壁轮廓，之后形成的气隙间隔物宽度(比如沿着图5的X方向)，可随着深度(比如图5的Y方向)变化。举例来说，气隙间隔物的中间部分的宽度，可大于气隙间隔物的顶部与底部部分的宽度。
此外，多种实施例的空洞504之后可用于形成较大的气隙间隔物(比如较大体积的气隙)，如下详述。形成空洞504的步骤亦可露出源极/漏极结构106的部分L2，且部分L2大于形成接点开口302(见图3)时原本露出的源极/漏极结构106的部分L1。如此一来，形成空洞504的步骤亦增加接点金属的关键尺寸(如钴接点金属的关键尺寸)。因此形成空洞504可同时改善装置200的电容与电阻。
在形成空洞504之后，方法100的步骤1100移除聚合物层。如图5与图6所示的一实施例中，步骤1100可采用合适的溶剂、湿蚀刻、灰化工艺、或上述的组合移除聚合物层402。
接着进行方法100的步骤1120，以沉积牺牲层与阻挡层。如图6至图8所示的一实施例中，步骤1120沉积牺牲层702(见图7)于装置200上。具体而言，牺牲层702沉积于装置的上表面上(比如硬遮罩层120、栅极间隔物112、与接点蚀刻停止层118上)，以及接点开口302的下表面与侧壁表面上，包含沉积于空洞504中以使空洞504实质上填有牺牲层702。在一些例子中，牺牲层702包括硅、锗、硅锗、低密度的氮化硅、低密度的氧化硅、及/或其他合适材料。由于之后选择性地蚀刻牺牲层702以形成气隙(如步骤1200)，需调整或最佳化牺牲层702的组成已用于选择性蚀刻工艺。在多种例子中，牺牲层702的形成工艺可为一或多种方法如等离子体辅助化学气相沉积、原子层沉积、及/或其他合适的沉积或氧化工艺。
在多种实施例中，可调整牺牲层702的厚度与空洞504(如上述)的轮廓，以控制后续形成的气隙间隔物的尺寸。在图7所示的一些例子中，牺牲层702具有厚度T1(沿着硬遮罩层120、栅极间隔物112、与接点蚀刻停止层118的上表面，并沿着聚合物层402的悬吊区404之前覆盖的接点开口302的侧壁表面的一部分，如图4所示)。在一些实施例中，厚度T1可为约1nm至6nm，以确保牺牲层702连续并提供后续形成的结构(比如下述的金属插塞1102A)所用的足够工艺容许范围。牺牲层702亦具有沿着空洞504的厚度T2。举例来说，沿着接点开口302的侧壁的不同位置所测量的厚度T2可能不同。然而由于空洞504，厚度T2一般大于厚度T1。在一些实施例中，厚度T2可为约2nm至10nm，可比至少一些现存技术提供体积更大的气隙间隔物，并维持接点金属的关键尺寸。
在现有的实施方式中(比如无空洞504)，牺牲层702的厚度足以提供充足的气隙间隔物，但薄到提供足够体积以形成可信的金属接点结构于接点开口中。如此一来，至少一些现有方法提供有限空间以插入额外牺牲层或增加现有牺牲层的厚度，而不会缩小接点金属的尺寸。与此相较，本发明实施例提供空洞504，可有效增加牺牲层702的厚度(比如沿着含空洞504的接点开口302的侧壁的一部分)，因此可加大气隙间隔物的体积(如下述)，并维持接点金属增加的关键尺寸。
在步骤1120的其他实施例中，阻挡层802(见图8)沉积于牺牲层702上。在一些实施例中，阻挡层802包括含氮化物的层状物，比如掺杂碳的氮化硅、高密度的氮化硅、及/或其他合适材料。在多种例子中，阻挡层802的厚度可介于约1nm至6nm之间。在一些例子中，阻挡层802的形成工艺可为一或多种方法如等离子体辅助化学气相沉积、原子层沉积、及/或其他合适工艺。在一些实施例中，阻挡层802包含在整个装置200上通常具有顺应性厚度的薄层。具体而言，阻挡层802沿着接点开口302的侧壁的顺应性品质，有助于避免后续形成的接点插塞(形成于步骤1180)至栅极堆叠116a与116b的漏电流路径，反之亦然。
接着进行方法100的步骤1140，进行蚀刻工艺以露出源极/漏极结构。如图8与图9所示的一实施例中，步骤1140进行蚀刻工艺，以自栅极结构的上表面(如硬遮罩层120、栅极间隔物112、与接点蚀刻停止层的上表面)实质上移除阻挡层802与牺牲层702，亦自源极/漏极结构106的至少一部分移除阻挡层802与牺牲层702，以形成空洞902并露出源极/漏极结构106。上述蚀刻可包含湿蚀刻、干蚀刻、或上述的组合。在一些实施例中，蚀刻工艺在形成空洞902时，亦可蚀刻源极/漏极结构106的一部分。值得注意的是，在步骤1140的蚀刻工艺之后，可实质上保留阻挡层802与牺牲层702于接点开口302的侧壁上(包括空洞504中)。
接着进行方法100的步骤1160，形成硅化物层以接触露出的源极/漏极结构。如图9与图10所示的一实施例中，步骤1160形成金属层1002于装置200上(包括形成于空洞902中)，使金属层1002接触源极/漏极结构106。在多种实施例中，金属层1002一般可覆盖接点开口302的下表面与侧壁表面，以及栅极结构的上表面(如硬遮罩层120、栅极间隔物112、与接点蚀刻停止层118的上表面)。在一些例子中，金属层1002的沉积方法可采用原子层沉积、化学气相沉积、物理气相沉积、或其他合适工艺。举例来说，金属层1002可包含多种材料如镍、钴、钨、钽、钛、上述的组合、或其他合适材料。在形成金属层1002之后，步骤1160的其他实施例可退火装置200以升高金属层1002的温度，使金属层1002与源极/漏极结构106中的半导体材料反应形成金属硅化物1002A。在一些实施例中，可移除金属层1002的未反应区(如沿着接点开口302的侧壁表面及栅极结构的上表面上的金属层1002)，可保留金属硅化物1002A以接触源极/漏极结构106，且移除方法可为湿或干蚀刻工艺。在多种实施例中，金属硅化物1002A可包括镍硅化物、钴硅化物、钛硅化物、或其他合适材料。
接着进行方法100的步骤1180以形成金属接点层，并进行化学机械平坦化工艺以提供金属插塞。如图11与图12所示的一些实施例中，步骤1180形成金属接点层1102于装置200上。在一些实施例中，金属接点层1102包含铝、钨、铜、钴、钛、镍、钌、上述的组合、或其他合适材料。在一些例子中，金属接点层1102亦可包括导电的氮化物如氮化钽或氮化钛所组成的阻障层。在多种例子中，金属接点层1102的形成方法可为物理气相沉积、化学气相沉积、原子层沉积、电镀、或其他合适方法。金属接点层1102经由金属硅化物1002A电性耦接至源极/漏极结构106。然而在其他实施例中，金属接点层1102可直接连接至源极/漏极结构106，而不需中间的硅化物结构。在形成金属接点层1102之后，步骤1180的其他实施例可进行化学机械平坦化工艺，以移除金属接点层1102的多余部分并平坦化装置200的上表面，即提供金属插塞1102A。在多种例子中，金属插塞1102A可视作接点插塞、通孔、通孔插塞、或金属接点。亦应注意的是，步骤1180的化学机械平坦化工艺设置已露出牺牲层702的上表面(用于后续形成气隙)。此外，化学机械平坦化工艺亦露出阻挡层802的上表面与栅极结构的上表面(如硬遮罩层120的上表面、栅极间隔物112的上表面、与接点蚀刻停止层118的上表面)。
接着进行方法100的步骤1200，移除牺牲层以形成气隙。如图12与图13所示的一实施例中，步骤1200移除牺牲层702的保留部分(由步骤1180的化学机械所露出)，以形成气隙1302。在一些实施例中，牺牲层702的移除方法采用选择性蚀刻工艺，包含干蚀刻、湿蚀刻、反应性离子蚀刻、及/或其他合适工艺。举例来说，气隙1302可形成于金属插塞1102A与相邻的栅极堆叠116a及116b之间，以降低金属插塞与栅极堆叠之间的电容。由于气体的介电常数为约1且低于其他介电材料的介电常数，因此可降低电容。此外，形成空洞504如上述，可使牺牲层702占有较大体积，使步骤1200形成的气隙1302亦占有较大体积并进一步降低电容(与至少一些现存的实施方式相较)。在不存在层叠偏移的一些实施例中，金属插塞1102A的每一侧上的气隙1302可具有实质上类似的尺寸，因此其个别电容可大致相同。然而若有层叠偏移，金属插塞1102A的每一侧上的气隙1302可能具有不同尺寸，因此个别电容可能不同。然而气隙1302的体积增加并降低相关电容，可大幅缓解金属插塞1102A的每一侧上的电容变异(比如层叠偏移)对装置或电路效能的任何影响。此外，由于空洞504具有弧型侧壁轮廓如上述，气隙1302的宽度可随着深度改变。举例来说，气隙1302的中间部分的宽度可大于气隙1302的顶部或底部的宽度。
方法100的步骤1220接着形成密封层以覆盖气隙。如图13与图14所示的一实施例中，步骤1220形成密封层1402于装置200上，使密封层1402覆盖并因此密封气隙1302。在一些实施例中，密封层1402包含氮化硅、氮氧化硅、碳氮化硅、碳氮氧化硅、或其他合适材料。在多种实施例中，密封层1402的沉积方法可采用化学气相沉积、物理气相沉积、原子层沉积、等离子体辅助化学气相沉积、及/或其他合适方法。在一些实施例中，密封层1402的厚度为约3nm至8nm。举例来说，密封层1402可采用任何合适材料，确保完全封住气隙1302以避免任何材料进入气隙1302。一旦形成密封层1402，即完成气隙1302的体积并完成装置200所用的气隙间隔物。在一些实施例中，密封层1402可稍微进入气隙1302(比如进入1nm至4nm)，如单元1404所示。然而气隙1302的上表面开口一般可具有非常小的宽度(比如小于10nm、5nm、3nm、或2nm)，以消除密封层1402深入气隙1302的风险。
装置200可进行后续工艺以形成技术领域中已知的多种结构与区域。举例来说，后续工艺可形成多种接点、通孔、与线路及多层内连线结构(如金属层与层间介电层)于基板上，其设置以连接多种结构以形成功能电路，且功能电路可包含一或多个鳍状场效晶体管装置。在此例中，多层内连线可包含垂直内连线如通孔或接点，以及水平内连线如金属线路。多种内连线结构可采用多种导电材料，包含铜、钨、及/或硅化物。在一例中，可采用镶嵌及/或双镶嵌工艺以形成铜相关的多层内连线结构。
因此此处所述的多种实施例可比现有技术提供多种优点。可以理解的是，此处不必说明所有优点，所有实施例不必具有特定优点，且其他实施例可提供不同优点。举例来说，此处所述的实施例可在形成接点插塞之后形成气隙(而非在形成接点插塞之前或同时形成气隙)，以缓解现有方法的多种缺点。在一些例子中，气隙的形成方法为选择性移除虚置结构，其位于接点插塞周围。通过虚置结构材料与直接接触虚置结构的其他材料之间的蚀刻选择性，可实施选择性移除虚置结构。此外，此处接露在接点插塞后形成气隙的方法提供自对准的气隙，因为气隙位置取决于虚置结构的位置。在一些例子中，接点气隙间隔物的形成方法可采用聚合物盖干蚀刻方法(与源极/漏极干蚀刻促使近接法类似)，以形成较大的气隙间隔物(比如较大体积的气隙)并增加接点金属的关键尺寸(比如钴接点金属的关键尺寸)，即同时改善电容与电阻。如此一来，可有效降低金属堆叠与接点插塞之间的耦合电容。一般而言，此处提供的多种实施例改善有效电容与有效电阻，移除金属栅极至源极/漏极接点的金属短路风险、并提供可控制的气隙体积及改良的气隙密封。在本发明实施例的教示下，本技术领域中技术人员可轻易思及其他实施例与优点。
本发明一实施例提供的半导体装置的形成方法，包括：提供第一晶体管，其包含第一栅极结构以及与第一栅极结构相邻的源极/漏极结构。在一些实施例中，沿着位于源极/漏极结构上的接点开口的侧壁表面形成空洞。在形成空洞之后，沉积牺牲层于空洞中包含的接点开口的侧壁表面与下表面上，其中牺牲层填入空洞。在一些例子中，沿着接点开口的下表面移除牺牲层的第一部分，以露出源极/漏极结构的一部分。形成接点结构于露出的源极/漏极结构的部分上。在一些实施例中，移除牺牲层的保留部分，以形成气隙于接点结构与第一栅极结构之间。之后沉积密封层于气隙上，以形成气隙间隔物。
在一实施例中，牺牲层的保留部分的移除方法采用选择性蚀刻工艺。
在一实施例中，方法还包括：在形成空洞之前，形成聚合物层于第一栅极结构上，其中聚合物层悬吊于第一栅极结构并覆盖接点开口的侧壁表面的至少一部分。
在一实施例中，形成空洞的步骤包括以倾斜角度进行干蚀刻工艺。
在一实施例中，沿着含有空洞的接点开口的第一侧壁表面的牺牲层具有第一厚度，且第一栅极结构上的牺牲层具有第二厚度，且第一厚度大于第二厚度。
在一实施例中，方法还包括：在移除牺牲层的第一部分之前，形成阻挡层于牺牲层上；以及沿着接点开口的下表面移除牺牲层的第一部分与阻挡层的第一部分，以露出源极/漏极结构的部分。
在一实施例中，方法还包括：在露出源极/漏极结构的部分之后与形成接点结构之前，形成硅化物层以接触露出的源极/漏极结构的部分；以及形成接点结构于硅化物层上。
在一实施例中，沿着接点开口的侧壁表面形成空洞的步骤，增加源极/漏极结构的露出区域尺寸。
在一实施例中，方法还包括：形成第二晶体管，其包括第二栅极结构，其中源极/漏极结构位于第一栅极结构与第二栅极结构之间，并与第一栅极结构及第二栅极结构的每一者相邻。
在一实施例中，气隙间隔物的中间部分的第一宽度，大于气隙间隔物的顶部或底部部分的第二宽度。
另一实施例提供的半导体装置的形成方法，包括提供第一晶体管，其包括第一栅极结构；第二晶体管，其包括第二栅极结构；源极/漏极结构，位于第一栅极结构与第二栅极结构的之间并与第一栅极结构与第二栅极结构的每一者相邻；以及接点开口，位于源极/漏极结构上。在一些实施例中，形成第一空洞于接点开口的第一侧壁表面上，以及第二开口于接点开口的第二侧壁表面上。在一些例子中，沿着第一空洞与第二空洞中包含的第一侧壁表面与第二侧壁表面沉积牺牲层。在多种实施例中，形成接点结构于源极/漏极结构上。接点结构位于沿着第一侧壁表面的牺牲层与沿着第二侧壁表面的牺牲层之间。在形成接点结构之后，自第一侧壁表面与第二侧壁表面移除牺牲层，以形成位于接点结构与第一栅极结构之间的第一气隙与位于接点结构与第二栅极结构之间的第二气隙。在一些实施例中，沉积密封层于第一气隙与第二气隙上，以形成与接点结构相邻的多个气隙间隔物。
在一些实施例中，方法还包括在形成第一空洞与第二空洞之前，沉积第一聚合物层于第一栅极结构上并沉积第二聚合物层于第二栅极结构上，其中第一聚合物层悬吊于该第一栅极结构并覆盖接点开口的第一侧壁表面的至少第一部分，且其中第二聚合物层悬吊于该第二栅极结构并覆盖接点开口的第二侧壁表面的至少第二部分。
在一些实施例中，形成第一空洞与第二空洞的步骤还包括蚀刻接点开口的第一侧壁表面的第三部分以形成第一空洞，并蚀刻接点开口的第二侧壁表面的第四部分以形成第二空洞。
在一些实施例中，方法还包括：在形成第一空洞与第二空洞之后，且在形成接点结构之前，沉积牺牲层于第一空洞与第二空洞中包含的接点开口的第一侧壁表面、第二侧壁表面、与下表面上；以及移除牺牲层沿着接点开口的下表面的第一部分，以露出源极/漏极结构的一部分。
在一些实施例中，方法还包括：在露出源极/漏极结构的部分之后且在形成接点结构之前，形成硅化物层以接触源极/漏极结构的露出部分；以及形成接点结构于硅化物层上。
在一些实施例中，方法还包括：在形成接点结构之前，形成阻挡层于沿着第一侧壁表面与第二侧壁表面的牺牲层上；以及形成接点结构于源极/漏极结构上，其中接点结构位于沿着第一侧壁表面的牺牲层上的阻挡层与位于沿着第二侧壁表面的牺牲层上的阻挡层之间。
在一些实施例中，牺牲层在第一侧壁表面与第二侧壁表面的上侧区域中具有第一厚度，其中牺牲层在第一侧壁表面与第二侧壁表面的下侧区域中具有第二厚度，其中第一侧壁表面的下侧区域包括第一空洞而第二侧壁表面的下侧区域包括第二空洞，且其中第一厚度小于第二厚度。
本发明又一实施例提供的半导体装置，包括栅极结构，以及与栅极结构相邻的源极/漏极结构。半导体装置亦包括接点结构，位于源极/漏极结构上并该栅极结构相邻。在一些例子中，半导体装置亦包括气隙间隔物，包括密封层形成于空洞上，其中气隙间隔物位于接点结构与栅极结构之间，且其中空洞包括弧形侧壁轮廓。
在一些实施例中，半导体装置还包括：阻挡层，位于接点结构的侧壁上，其中阻挡层位于接点结构与气隙间隔物之间。
在一些实施例中，半导体装置还包括：硅化物层，接触源极/漏极结构，其中接点结构位于硅化物层上。
上述内容已说明几个实施例的特征，以利本技术领域中技术人员理解详细说明。本技术领域中技术人员应理解，本发明实施例明显可作为设计或调整其他工艺和结构的基础，以实现此处介绍的实施例的相同目的及/或相同优点。本技术领域中技术人员亦应理解，这些等效构造并未脱离本发明实施例的构思与范围，且在不脱离本发明实施例的构思与范围的前提下，可进行多种改变、取代、或变更。

Claims (1)

1.一种半导体装置的形成方法，包括：
提供一第一晶体管，其包含一第一栅极结构以及与该第一栅极结构相邻的一源极/漏极结构；
沿着位于该源极/漏极结构上的一接点开口的一侧壁表面形成一空洞；
在形成该空洞之后，沉积一牺牲层于该空洞中包含的该接点开口的侧壁表面与下表面上，其中该牺牲层填入该空洞；
沿着该接点开口的下表面移除该牺牲层的一第一部分，以露出该源极/漏极结构的一部分；
形成一接点结构于露出的该源极/漏极结构的部分上；
移除该牺牲层的保留部分，以形成一气隙于该接点结构与该第一栅极结构之间；以及
沉积一密封层于该气隙上，以形成一气隙间隔物。
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