WO2013005667A1 - PROCÉDÉ DE FABRICATION D'ÉLÉMENT SEMI-CONDUCTEUR À BASE DE GaN - Google Patents

PROCÉDÉ DE FABRICATION D'ÉLÉMENT SEMI-CONDUCTEUR À BASE DE GaN Download PDF

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WO2013005667A1
WO2013005667A1 PCT/JP2012/066677 JP2012066677W WO2013005667A1 WO 2013005667 A1 WO2013005667 A1 WO 2013005667A1 JP 2012066677 W JP2012066677 W JP 2012066677W WO 2013005667 A1 WO2013005667 A1 WO 2013005667A1
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gan
electrode
protective film
film
electrodes
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PCT/JP2012/066677
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Japanese (ja)
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藤田　耕一郎
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シャープ株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Definitions

  • the present invention relates to a method for manufacturing a GaN-based semiconductor element.
  • Patent Document 1 Japanese Patent Laid-Open No. 2008-306026 discloses a method for manufacturing a GaN-based FET (field effect transistor).
  • an electrode is formed on a GaN-based semiconductor layer, the electrode is heat-treated to form a source / drain electrode as an ohmic electrode, and the source / drain electrode and the GaN-based semiconductor layer are formed on the source / drain electrode.
  • An insulating film (silicon nitride film or the like) is formed, and this insulating film is heat-treated.
  • This current collapse is particularly prominent in a GaN-based semiconductor device, and is a phenomenon in which the on-resistance of a transistor in high-voltage operation is significantly higher than the on-resistance of the transistor in low-voltage operation. .
  • the present inventors formed a SiN insulating film for suppressing current collapse after forming the source / drain electrodes, and when heat treatment is performed in this state, the electrode metal becomes SiN. A problem has been discovered in which it diffuses into the insulating film and causes leakage current via the SiN insulating film.
  • an object of the present invention is to provide a method of manufacturing a GaN-based semiconductor element that can suppress the diffusion of electrode metal into the SiN insulating film, and can achieve both suppression of current collapse and reduction of leakage current.
  • the present invention was created based on the discovery of the phenomenon that the electrode metal diffuses into the silicon nitride film when heat-treating the silicon nitride film that suppresses current collapse with the electrode formed. It has been done.
  • the present inventors have formed a silicon nitride film and heat-treated, and then formed an electrode and heat-treated (ohmic annealing) to form an ohmic electrode. It has been found that it is effective in suppressing diffusion into the film, and that leakage current passing through the silicon nitride film can be reduced.
  • a protective film including a silicon nitride film or a protective film made of a silicon nitride film is formed on a GaN-based stacked body having a heterojunction, Heat treating the protective film, Etching at least a predetermined region of the protective film of the protective film and the GaN-based laminate to remove an ohmic electrode formation region of the GaN-based laminate, Forming an electrode containing Ti / Al or Hf / Al in the ohmic electrode formation region of the GaN-based laminate; The electrode is heat-treated to form an ohmic electrode.
  • a protective film including the silicon nitride film or a protective film made of a silicon nitride film is formed on the GaN-based stacked body, and the protection for suppressing the current collapse is performed.
  • an electrode is formed on the GaN-based laminate, and the electrode is heat treated to form an ohmic electrode.
  • the electrode metal is suppressed from diffusing into the protective film during the heat treatment of the electrode, It has been found that the leakage current passing through the protective film can be reduced.
  • the present invention it is possible to manufacture a GaN-based semiconductor element that can not only suppress current collapse by the protective film but also reduce the leakage current passing through the protective film.
  • “current collapse” is a problem particularly in GaN-based semiconductor devices, and the transistor resistance in high-voltage operation is lower than the on-resistance of the transistor in low-voltage operation. This is a phenomenon in which the on-resistance becomes extremely high.
  • the protective film is A lower layer silicon nitride film formed on the GaN-based laminate, An upper silicon nitride film formed on the lower silicon nitride film; An SiO 2 film or an Al 2 O 3 film formed on the upper silicon nitride film,
  • the upper silicon nitride film is a stoichiometric silicon nitride film.
  • the upper silicon nitride film is stoichiometry, and an SiO 2 film or an Al 2 O 3 film is formed on the upper silicon nitride film. It is possible to suppress the electrode metal from diffusing into the upper layer and the lower layer silicon nitride film of the protective film during the heat treatment, and to further reduce the leakage current passing through the protective film.
  • the stoichiometric silicon nitride film means that Si and N have a composition of 3: 4.
  • the temperature at which the electrode is heat-treated is lower than the temperature at which the protective film is heat-treated.
  • the electrode metal when the electrode is heat-treated, the electrode metal can be prevented from diffusing into the protective film, and the leakage current passing through the protective film can be further reduced.
  • an electrode metal is protected by forming an ohmic electrode after forming a protective film including the silicon nitride film or a protective film made of a silicon nitride film and performing heat treatment. Since diffusion to the film is suppressed and leakage current passing through the protective film can be reduced, a GaN-based semiconductor element capable of both suppressing current collapse and reducing leakage current can be manufactured.
  • (First embodiment) 1 to 5 are cross-sectional views sequentially showing steps of a method of manufacturing a GaN-based HFET (Hetero-junction Field Effect Transistor) according to the first embodiment of the present invention.
  • GaN-based HFET Hetero-junction Field Effect Transistor
  • an undoped AlGaN buffer layer 2, an undoped GaN channel layer 3, and an undoped AlGaN barrier layer 4 are sequentially formed on a Si substrate 1 by using MOCVD (metal organic chemical vapor deposition).
  • MOCVD metal organic chemical vapor deposition
  • the AlGaN buffer layer 2, the GaN channel layer 3 and the AlGaN barrier layer 4 constitute a GaN-based laminate 5.
  • reference numeral 6 indicates a two-dimensional electron gas formed at the interface between the AlGaN barrier layer 4 and the GaN channel layer 3.
  • a SiN protective film 7 which is a silicon nitride film is formed on the AlGaN barrier layer 4 by using a plasma CVD method.
  • the growth temperature of the SiN protective film 7 is 225 ° C. as an example, but may be set in the range of 200 ° C. to 400 ° C.
  • the thickness of the SiN protective film 7 is 150 nm as an example, but may be set in the range of 20 nm to 250 nm.
  • the SiN protective film 7 having a silicon Si ratio larger than that of the stoichiometric silicon nitride film can be formed.
  • current collapse can be further suppressed as compared with a stoichiometric silicon nitride film.
  • a photoresist layer (not shown) is formed on the SiN protective film 7, exposed and developed to form an opening in the photoresist layer, and the photoresist layer in which the opening is formed is used as a mask. Then, dry etching is performed. Thereby, as shown in FIG. 3, openings 10 and 11 are formed in the SiN protective film 7 and recesses 12 and 13 reaching from the AlGaN barrier layer 4 to the GaN channel layer 3 are formed.
  • the recesses 12 and 13 form an ohmic electrode formation region.
  • the method of forming the recesses 12 and 13 is not limited to the above.
  • an AlGaN barrier is formed.
  • the recesses 12 and 13 may be formed by dry etching the layer 4 and the GaN channel layer 3.
  • the SiN protective film 7 is heat-treated.
  • This heat treatment was performed, for example, at 500 ° C. for 5 minutes in a nitrogen atmosphere.
  • the temperature of the heat treatment may be set in the range of 500 ° C. to 700 ° C. as an example.
  • a photoresist (not shown) in which the regions where the source and drain electrodes are to be formed (including regions by the recesses 12 and 13 and the openings 10 and 11) is formed is formed on the photoresist.
  • Ti and Al are deposited in this order, and lift-off provides a source electrode and a drain electrode so as to fill the recesses 12 and 13 and the openings 10 and 11 and have a region overlapping the SiN protective film 7 as shown in FIG.
  • Ti / Al electrodes 15 and 16 are formed.
  • the Ti / Al electrodes 15 and 16 are electrodes having a laminated structure in which a Ti layer and an Al layer are sequentially laminated.
  • the electrodes 15 and 16 are heat-treated to form ohmic electrodes, and the source electrode 15 and the drain electrode 16 are formed.
  • the condition of this heat treatment (ohmic annealing) is set to 500 ° C. for 30 minutes as an example, but the condition of the heat treatment is not limited to this.
  • the heat treatment temperature is set within a range of 400 ° C. to 600 ° C. May be.
  • a mask made of a photoresist is formed by photolithography, and etching is performed to remove a region where the gate electrode of the SiN protective film 7 is to be formed, thereby forming an opening 20.
  • TiN is sputtered over the entire surface so as to fill the opening 20, and a resist pattern (not shown) is formed in an electrode formation region where a gate electrode is to be formed by photolithography.
  • a resist pattern (not shown) is formed in an electrode formation region where a gate electrode is to be formed by photolithography.
  • dry etching or wet etching is performed.
  • Etching is performed to remove the TiN film other than the electrode formation region, and a TiN electrode to be the gate electrode 18 is formed.
  • the undoped AlGaN barrier layer 4 is located immediately below the gate electrode 18, and the junction between the gate electrode 18 and the undoped AlGaN barrier layer 4 is a Schottky junction.
  • the SiN protective film 7 is formed on the GaN-based stacked body 5, and the SiN protective film 7 is heat-treated (for example, 5 ° C. at 500 ° C.).
  • the Ti / Al electrodes 15 and 16 are formed on the GaN-based laminate 5, and the Ti / Al electrodes 15 and 16 are heat-treated to form the source electrode 15 and the drain electrode 16 as ohmic electrodes.
  • the inventors formed the SiN protective film 7 and heat-treated, then formed the Ti / Al electrodes 15 and 16 and heat-treated (ohmic annealing) to form the source electrode 15 and the drain electrode 16 as ohmic electrodes.
  • the electrode metal can be prevented from diffusing into the SiN protective film 7 and the leakage current passing through the SiN protective film 7 can be reduced.
  • the manufacturing method of this embodiment it is possible to manufacture a GaN-based HFET that can simultaneously suppress the current collapse by the SiN protective film 7 and reduce the leakage current passing through the SiN protective film 7.
  • “current collapse” is particularly problematic in GaN-based semiconductor devices, and the on-resistance of a transistor in high-voltage operation is higher than the on-resistance of the transistor in low-voltage operation. It is a phenomenon that ends up.
  • FIG. 7 is a graph comparing the yield (%) of the GaN-based HFET fabricated according to the present embodiment and the yield (%) of the GaN-based HFET fabricated according to the comparative example.
  • the Ti / Al electrodes 15 and 16 are heat-treated (ohmic annealing).
  • the Ti / Al electrodes 15 and 16 are not heat-treated before the Ti / Al electrodes 15 and 16 shown in FIG. This heat treatment (onic annealing) is also used as the heat treatment of the SiN protective film 7.
  • the gate leakage current is measured with the gate voltage Vg set to ⁇ 10 (V), the drain voltage Vd and the source voltage Vs set to 0 (V), and the gate leakage current is 1 ⁇ 10 ⁇ 5 ( When it was within A), it was judged as acceptable, and when the gate leakage current exceeded 1 ⁇ 10 ⁇ 5 (A), it was judged as unacceptable.
  • the gate leakage current was measured at room temperature (25 ° C.). As shown in FIG. 7, the yield (%) of the GaN-based HFET fabricated in this embodiment is 100%, whereas the yield (%) of the GaN-based HFET fabricated in the comparative example is 40%. The yield improvement according to the present embodiment was apparent.
  • FIGS. 9 to 13 are cross-sectional views sequentially showing the steps of the method of manufacturing the GaN-based HFET which is the second embodiment of the present invention.
  • an undoped AlGaN buffer layer 72, an undoped GaN channel layer 73, and an undoped AlGaN barrier layer 74 are sequentially formed on a Si substrate 71 using MOCVD (metal organic chemical vapor deposition).
  • MOCVD metal organic chemical vapor deposition
  • the AlGaN buffer layer 72, the GaN channel layer 73, and the AlGaN barrier layer 74 constitute a GaN-based stacked body 75.
  • reference numeral 76 indicates a two-dimensional electron gas formed at the interface between the AlGaN barrier layer 74 and the GaN channel layer 73.
  • the GaN-based laminate 75 produced in the second embodiment differs from the GaN-based laminate 5 produced in the first embodiment described above in that the thickness of the AlGaN barrier layer 74 is the same as that of the AlGaN of the first embodiment. It is thinner than the thickness of the barrier layer 4 (for example, 30 nm), for example, 10 nm. Thus, ohmic contacts can be made on electrodes 85 and 86 described later without forming the recesses 12 and 13 as in the first embodiment.
  • a SiN protective film 77 which is a silicon nitride film, is formed on the AlGaN barrier layer 74 by plasma CVD.
  • the growth temperature of the SiN protective film 77 is 225 ° C. as an example, but may be set in the range of 200 ° C. to 400 ° C.
  • the thickness of the SiN protective film 77 is 150 nm as an example, but may be set in the range of 20 nm to 250 nm.
  • a photoresist layer (not shown) is formed on the SiN protective film 77, exposed and developed to form an opening in the photoresist layer, and the photoresist layer in which the opening is formed is used as a mask. Then, wet etching is performed. Thus, openings 70 and 71 are formed in the SiN protective film 77 as shown in FIG. The region of the AlGaN barrier layer 74 exposed in the openings 70 and 71 forms an ohmic electrode formation region.
  • the SiN protective film 77 is heat-treated.
  • the temperature of this heat treatment was, for example, 500 ° C. for 5 minutes. Note that the temperature of the heat treatment may be set in a range of 500 ° C. to 700 ° C. as an example.
  • a photoresist (not shown) in which the regions where the source and drain electrodes are to be formed (including the exposed AlGaN barrier layer 74 region) is formed, and Ti is formed on the photoresist.
  • Al are sequentially deposited, and Ti / Al electrodes 85 and 86 are formed by lift-off so as to fill the openings 70 and 71 and to overlap the SiN protective film 77 as shown in FIG.
  • the Ti / Al electrodes 85 and 86 serve as a source electrode and a drain electrode.
  • the Ti / Al electrodes 85 and 86 are electrodes having a laminated structure in which a Ti layer and an Al layer are sequentially laminated.
  • the electrodes 85 and 86 are heat-treated to form ohmic electrodes, and the source electrode 85 and the drain electrode 86 are formed.
  • the condition of this heat treatment (ohmic annealing) is set to 500 ° C. for 30 minutes as an example, but the condition of the heat treatment is not limited to this.
  • the heat treatment temperature is set within a range of 400 ° C. to 600 ° C. May be.
  • a mask made of a photoresist is formed by photolithography, and etching is performed to remove a region where the gate electrode of the SiN protective film 77 is to be formed, thereby forming an opening 90.
  • TiN is sputtered over the entire surface so as to fill the opening 90, and a resist pattern (not shown) is formed in an electrode formation region where a gate electrode is to be formed by photolithography.
  • a resist pattern (not shown) is formed in an electrode formation region where a gate electrode is to be formed by photolithography.
  • dry etching or wet etching is performed.
  • Etching is performed to remove the TiN film other than the electrode formation region, and a TiN electrode to be the gate electrode 88 is formed.
  • An undoped AlGaN barrier layer 74 is located immediately below the gate electrode 88, and the junction between the gate electrode 88 and the undoped AlGaN barrier layer 74 is a Schottky junction.
  • the Si / N protective film 77 formed on the GaN-based stacked body 75 is modified by heat treatment, and then the Ti / Al electrodes 85, 86 are used. Is formed on the GaN-based laminate 75, and the Ti / Al electrode is heat-treated to form a source electrode 85 and a drain electrode 86 as ohmic electrodes.
  • the Ti / Al electrodes 85 and 86 are heat-treated (ohmic annealing) to form the source electrode 85 and the drain electrode 86 as ohmic electrodes.
  • the thickness of the AlGaN barrier layer 74 is made thinner than the thickness of the AlGaN barrier layer 4 of the first embodiment so that the source electrode 85 and the drain electrode 86 can be in ohmic contact.
  • the thickness of the AlGaN barrier layer 74 is equal to the thickness of the AlGaN barrier layer 4, the ohmic contact portion of the AlGaN barrier layer 74 is preliminarily doped with Si so as to be n-type, thereby enabling ohmic contact of the electrode. It is good.
  • the Si substrate is used as the substrate, but a sapphire substrate may be used.
  • a nitride semiconductor layer may be grown on a substrate made of a nitride semiconductor, such as growing an AlGaN layer on the GaN substrate.
  • a buffer layer may be appropriately formed between the substrate and each layer.
  • a hetero improvement layer made of AlN may be formed between the GaN channel layers 3 and 73 and the AlGaN barrier layers 4 and 74.
  • a GaN cap layer may be formed on the AlGaN barrier layers 4 and 74.
  • the gate electrodes 18 and 88 were produced with TiN, you may produce with WN.
  • the gate electrodes 18 and 88 may be made of Pt / Au or Ni / Au.
  • the protective film that suppresses current collapse is the SiN protective film 7, 77 made of a single layer of silicon nitride film (SiN film).
  • the protective film that suppresses current collapse is A lower SiN film having a larger silicon Si ratio than a stoichiometric silicon nitride film and a stoichiometric upper SiN film may be used. In this case, it is possible to suppress the diffusion of the electrode metal by the stoichiometric upper SiN film and to suppress the current collapse by the lower SiN film having a large silicon Si ratio. Further, an SiO 2 film or an Al 2 O 3 film may be formed on the SiN protective films 7 and 77.
  • a protective film 50 in which a lower SiN film 51, an upper SiN film 52 that is stoichiometry, and a SiO 2 film 53 are sequentially stacked may be used as a protective film that suppresses current collapse.
  • the upper SiN film 52 is stoichiometric means that Si and N have a composition of 3: 4.
  • the protective film 50 since the upper SiN film 52 is stoichiometry and the SiO 2 film 53 is formed on the upper SiN film 52, the upper and lower SiN layers of the protective film 50 are heat-treated during the heat treatment of the electrode.
  • the diffusion of the electrode metal into the protective layers 52 and 51 can be suppressed, and the leakage current passing through the protective film 50 can be further reduced.
  • the lower SiN film 51 is a SiN protective film having a silicon Si ratio larger than that of the stoichiometric silicon nitride film, the current collapse can be suppressed as compared with the stoichiometric silicon nitride film.
  • a stoichiometric silicon nitride film may be used. In this case, the leakage current can be further reduced by suppressing the diffusion of the electrode metal.
  • an Al 2 O 3 film may be used instead of the SiO 2 film 53.
  • the heat treatment temperature of the SiN protective films 7 and 77 is set to 500 ° C.
  • the heat treatment temperature of the electrodes 15, 16, 85, and 86 is set to 500 ° C. It is desirable that the heat treatment temperature of the electrodes 15, 16, 85, 86 be lower than the heat treatment temperature of the SiN protective film 77.
  • the heat treatment temperature of the SiN protective film 77 is 500 ° C.
  • the heat treatment temperature of the electrodes 15, 16, 85, 86 be 450 ° C. lower than 500 ° C.
  • the source electrodes 15 and 85 and the drain electrodes 16 and 86 as the ohmic electrodes are Ti / Al electrodes in which a Ti layer and an Al layer are sequentially stacked.
  • a Ti / Al / TiN electrode in which an Al layer and a TiN layer are sequentially laminated may be used.
  • the source electrode and the drain electrode may be Hf / Al electrodes.
  • Ni / Au may be stacked on Ti / Al or Hf / Al, or Pt / Au may be stacked on Ti / Al or Hf / Al. It is good also as what laminated
  • the temperature conditions for the ohmic annealing of the electrodes 15, 16, 85, 86 are set to 500 ° C.
  • the contact resistance ( ⁇ mm) of the electrodes 15, 16, 85, 86 rapidly increases when the temperature of the ohmic annealing is set to 700 ° C. exceeding 600 ° C. Therefore, it is desirable that the ohmic annealing temperature of the electrodes 15, 16, 85, 86 is 600 ° C. or lower.
  • the Ti / Al electrodes 15 and 16 that become the source electrode and the drain electrode are formed by lift-off, but the SiN protective film 7 and the recesses 12 and 13 and the openings 10 and 11 shown in FIG. Then, Ti, Al, and TiN are sequentially sputtered to fill the electrode, and a resist pattern (not shown) is formed in the electrode formation region where the source electrode and the drain electrode are to be formed by photolithography, and this resist pattern is used as a mask.
  • the Ti / Al / TiN electrodes 15 and 16 to be the source electrode and the drain electrode may be formed by performing dry etching or wet etching to remove the Ti, Al, and TiN films other than the electrode formation region.
  • the Ti / Al electrodes 85 and 86 to be the source electrode and the drain electrode are formed by lift-off, but the SiN protective film 77 and the openings 70 and 71 shown in FIG. Ti, Al, TiN films are sequentially sputtered in order, and a resist pattern (not shown) is formed in the electrode formation region where the source electrode and drain electrode are to be formed by photolithography, and dry etching or etching is performed using this resist pattern as a mask.
  • the Ti / Al / TiN electrodes 85 and 86 to be the source electrode and the drain electrode may be formed by performing wet etching to remove the Ti, Al, and TiN films other than the electrode formation region.
  • the GaN-based semiconductor laminate in the manufacturing method of the present invention may include a GaN-based semiconductor layer represented by Al x In y Ga 1-xy N (x ⁇ 0, y ⁇ 0, 0 ⁇ x + y ⁇ 1). . That is, the GaN-based semiconductor laminate in the manufacturing method of the present invention may include AlGaN, GaN, InGaN, and the like.
  • the normally-on type HFET has been described.
  • the normally-off type can achieve the same effect.
  • the Schottky gate has been described, an insulated gate structure may be used.
  • the GaN-based semiconductor element manufactured by the present invention is not limited to the HFET of the above embodiment, but may be a field effect transistor having another configuration.

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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Formation Of Insulating Films (AREA)

Abstract

Selon le procédé de fabrication de transistor à effet de champ à base de GaN de l'invention, un film protecteur SiN (7) formé sur un corps laminé à base de GaN (5) est amélioré par traitement thermique, puis des électrodes Ti/Al (15, 16) sont formées sur le corps laminé à base de GaN (5), et ces électrodes Ti/Al (15, 16) sont soumises à un traitement thermique pour servir d'électrode source (15) et d'électrode drain (16) en tant qu'électrodes ohmiques. Après traitement thermique du film protecteur SiN (7), les électrodes Ti/Al (15, 16) sont soumises à un traitement thermique (recuit ohmique), et l'électrode source (15) ainsi que l'électrode drain (16) sont formées en tant qu'électrodes ohmiques, permettant ainsi d'inhiber la prolifération d'un métal d'électrode dans le film protecteur SiN (7), et de concilier inhibition de chute de courant et diminution de courant de fuite.
PCT/JP2012/066677 2011-07-07 2012-06-29 PROCÉDÉ DE FABRICATION D'ÉLÉMENT SEMI-CONDUCTEUR À BASE DE GaN WO2013005667A1 (fr)

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Application Number Priority Date Filing Date Title
JP2011150971A JP5166576B2 (ja) 2011-07-07 2011-07-07 ＧａＮ系半導体素子の製造方法
JP2011-150971 2011-07-07

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WO2013005667A1 true WO2013005667A1 (fr) 2013-01-10

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