CN109671775B - 形成氮化物半导体器件的工艺 - Google Patents

形成氮化物半导体器件的工艺 Download PDF

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CN109671775B
CN109671775B CN201811202940.3A CN201811202940A CN109671775B CN 109671775 B CN109671775 B CN 109671775B CN 201811202940 A CN201811202940 A CN 201811202940A CN 109671775 B CN109671775 B CN 109671775B
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photoresist
sin film
silicon nitride
nitride film
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CN109671775A (zh
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中野拓真
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Sumitomo Electric Device Innovations Inc
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Abstract

公开了一种形成氮化物半导体器件的工艺。该工艺首先在一温度下通过低压化学气相沉积(LPCVD)技术在半导体层上沉积氮化硅(SiN)膜，然后在SiN膜中形成用于欧姆电极的开口。在SiN膜上制备光刻胶，其中光刻胶提供完全覆盖SiN膜中的开口的开口，该工艺将围绕SiN膜的开口的外围区域暴露于可以蚀刻半导体层的氯(Cl)等离子体以在其中形成凹槽。将用于欧姆电极的金属填充在半导体层中的凹槽内和SiN膜的外围区域。最后，在低于SiN膜的沉积温度的温度下对金属进行合金化。

Description

形成氮化物半导体器件的工艺
相关申请的交叉引用
本申请基于并要求2017年10月16日提交的、申请号为No.2017-200369的日本专利申请的优先权，其全部内容通过引用合并于此。
技术领域
本发明涉及形成半导体器件的工艺，具体地，涉及一种主要由氮化物半导体材料制成的半导体器件。
背景技术
公开号为No.JP2013-123047A的日本专利申请已经公开了形成氮化物半导体器件的工艺。其中所公开的工艺首先利用由低压化学气相沉积(LPCVD)技术形成的绝缘膜来覆盖氮化物半导体层，其中钝化膜包含氮化硅(SiN)；然后，通过蚀刻钝化膜在半导体层中形成凹槽，以部分地暴露半导体层的表面。在凹槽内选择性地生长p型氮化镓(GaN)层，并在p型GaN上形成栅电极，可以形成主要由氮化物半导体材料制成的电子器件。上述在先专利文献已经公开或建议，在高于550℃优选地高于700℃的温度下沉积钝化膜。
另一个公开号为No.JP2001-077204A的在先日本专利申请已经公开了一种异质双极晶体管及其形成工艺。在其中所公开的工艺中，在将SiN膜沉积在衬底上之前，使用氯气(Cl2)和氩气(Ar)的混合气体通过电子回旋共振反应离子蚀刻(ECR-RIE)对衬底进行预处理以增强衬底和SiN膜之间的粘附性。
发明内容
根据本发明的实施例的一个方面涉及形成氮化物半导体器件的工艺。该工艺包括以下步骤：(a)在衬底上外延生长由氮化物半导体材料制成的多个半导体层，其中所述多个半导体层形成半导体叠层；(b)通过低压化学气相沉积(LPCVD)技术在所述半导体叠层上沉积氮化硅(SiN)膜；(c)在所述SiN膜中形成开口；(d)将在所述SiN膜的开口内出现的半导体叠层的表面和围绕所述开口的SiN膜的表面的外围区域暴露于等离子体以在其中形成凹槽，所述等离子体含有氯(Cl)并部分地蚀刻所述半导体叠层；(e)在所述SiN膜的开口内暴露的半导体叠层的表面上和所述SiN膜的表面的外围区域沉积金属；(f)在比沉积温度低的合金化温度下，对所述金属进行合金化以形成与所述半导体叠层非整流接触的电极。
附图说明
通过以下参考附图对本发明优选实施例的详细描述，将更好地理解前述和其他目的、方面和优点，在附图中：
图1是根据本发明的实施例的半导体器件的剖视图；
图2A至图2C是图1中所示的半导体器件在其工艺的各步骤的剖视图；
图3A和图3B是图1中所示的半导体器件在图2C所示步骤之后的步骤的剖视图；
图4A至图4C示出图1中所示的半导体器件在图3B所示步骤之后的各步骤的剖视图；以及
图5是说明半导体器件的传统工艺和结构中留下的主体的剖视图。
具体实施方式
接下来，将参考附图描述根据本发明的实施例。然而，本发明不限于所述实施例，并且具有由所附权利要求指示的范围以及权利要求及其等同物内的所有修改和/或改变。此外，在附图的描述中，彼此相同或相似的数字或符号将指代不具有重复说明的彼此相同或相似的元件。
图1是通过根据本发明的实施例的工艺形成的半导体器件1A的剖视图。半导体器件1A是一种场效应晶体管(FET)，特别是一种主要由氮化物半导体材料制成的高电子迁移率晶体管(HEMT)。该实施例的HEMT 1A包括衬底11、氮化物半导体层12至14、第一氮化硅(SiN)膜21至第三氮化硅膜23以及源电极31、漏电极32和栅电极33。
衬底11由碳化硅(SiC)制成，该碳化硅的主表面具有(0001)晶面。然而，衬底11不限于具有(0001)晶面的SiC，并且可以由其他材料(例如，硅(Si)、氮化镓(GaN)、蓝宝石(Al2O3)等)制成，只要能够在衬底11上进行半导体外延生长即可。从衬底11的一侧起，半导体叠层15可以包括沟道层12、阻挡层13和覆盖层14，每层都顺序生长在衬底11上。沟道层12可以由未掺杂的GaN制成，厚度约为1μm，特别是0.5至1.5μm。阻挡层13可以由n型氮化铝镓(AlGaN)或n型氮化铟铝(InAlN)制成，厚度为20nm，特别是10至30nm。覆盖层14可以由n型GaN制成，厚度为5nm，特别为3至8nm。如此配置的半导体器件1A可以在沟道层12中与阻挡层13的界面处形成二维电子气(2DEG)，其中2DEG成为半导体器件1A的沟道。
具有钝化半导体叠层15的表面的功能的第一SiN膜21覆盖半导体叠层15的整个表面。第一SiN膜21提供源极开口21a和漏极开口21b，半导体叠层15在这些开口中被暴露。具体地，去除各开口21a和21b内的阻挡层13的一部分和整个覆盖层14，以暴露其中的阻挡层13。源电极31不仅填充源极开口21a而且延伸到第一SiN膜21上围绕源极开口21a的外围区域21c。漏电极32具有与源电极31类似的结构。也就是说，漏电极32填充漏极开口21b以与在漏极开口21b内暴露的阻挡层13直接接触并且在第一SiN膜21上围绕漏极开口21b的外围区域21d内延伸。因此，源电极31和漏电极32具有T字形的截面。
如在本说明书中的随后所述，因为那些外围区域21c和21d在形成半导体叠层15中的凹槽的步骤期间被暴露在等离子体中，所以与第一SiN膜21上的其余部分相比，在第一SiN膜21上围绕各个开口21a和21b的外围区域21c和21d显示出第一SiN膜21的粗糙表面。
第二SiN膜22覆盖第一SiN膜21以及源电极31和漏电极32。第一SiN膜21和第二SiN膜22在源极开口21a和漏极开口21b之间提供栅极开口24。栅极开口24贯穿第一SiN膜21和第二SiN膜22，以暴露覆盖层14的表面。也就是说，与源电极31和漏电极32的开口21a和21b不同的栅极开口24内的覆盖层14和阻挡层13未被部分地去除。栅电极33填充栅极开口24以与覆盖层14直接接触，并在围绕栅极开口24的第二SiN膜22上延伸。因此，栅电极33也具有T字形的截面。
第一SiN膜21具有10至100nm的厚度，优选地在本实施例中厚度为20nm。具有至少10nm厚度的第一SiN膜21可以确保半导体叠层15与T形栅电极33的扩展部分之间的间隙，这可以抑制在它们之间引起的寄生电容。此外，由于存在T形栅电极33的悬垂部分，最大厚度为100nm的第一SiN膜21可以有效地减小栅电极33的边缘处的电场强度，这可以减少栅极漏电流。另一方面，第二SiN膜22的厚度优选为40nm；但是，基于半导体器件1A的应用和性能，可以省略第二SiN膜22。
源电极31和漏电极32是一种所谓的欧姆电极，其表现出对阻挡层13的非整流特性。具有约300nm厚度的源电极31和漏电极32可以通过对钽/铝/钽(其可以表示为Ta/Al/Ta)、钛/铝/钛(其可以表示为Ti/Al/Ti)以及钛/铝/镍/金(其可以表示为Ti/Al/Ni/Au)中的一种的层叠金属进行合金化而形成。栅电极33为一种肖特基电极，可以是镍(Ni)和金(Au)的层叠金属，其中Ni作为与覆盖层14的肖特基接触而起作用。第三SiN膜23完全覆盖栅电极33和从栅电极33暴露出的第二SiN膜22。
接下来，将参考图2A至图4C来描述形成半导体器件1A的工艺，这些附图是半导体器件1A在该工艺的各步骤中的剖视图。
首先，如图2A所示，该工艺在衬底11上外延生长半导体层12至14，以形成半导体叠层15。也就是说，该工艺通过MOCVD技术顺序连续地在衬底11上外延生长沟道层12、在沟道层12上外延生长阻挡层13以及在阻挡层13上外延生长覆盖层14。外延生长将三甲基镓(TMG)和氨(NH3)的源材料用于GaN层，将三甲基铝(TMA)、TMG和NH3的源材料用于AlGaN层，以及当阻挡层13由InAlN制成时将三甲基铟(TMI)、TMG和NH3的源材料用于InAlN层。而且，在生长阻挡层13和覆盖层14时单硅烷(SiH4)用作n型掺杂剂的源材料。
然后，如图2B所示，通过LPCVD技术在半导体叠层15上沉积第一SiN膜21。LPCVD技术的示例性条件是：生长温度为700至800℃、生长压力为10至60Pa、以及用于硅(Si)的源材料为二氯硅烷(SiH2Cl2)和用于氮(N)的源材料为NH3。如上所述，第一SiN膜21可以沉积10至100nm的厚度。
然后，在第一SiN膜21中形成源极开口21a和漏极开口21b。具体地，如图2C所示，首先在第一SiN膜21上制备图案化的光刻胶R1，其中图案化的光刻胶R1具有对应于开口21a和21b的开口R1a，其中图2C代表性地示出了用于源极开口21a的仅一个开口R1a。通过使用含氟(F)的反应气体的反应离子刻蚀(RIE)蚀刻在开口R1a内暴露的第一SiN膜21，该工艺可以形成源极开口21a和漏极开口21b，每个开口均具有宽度W1。源极开口21a和漏极开口21b可以具有彼此实质上相同的宽度，但是也可以具有各种彼此不同的宽度。
然后，去除图案化的光刻胶R1，该工艺在第一SiN膜21上制备另一图案化的光刻胶R2，其中另一图案化的光刻胶R2提供对应于源电极31和漏电极32的开口R2a，其中图3A示出了用于源电极31的开口R2a中的仅一个开口。开口R2a具有彼此垂直可区分的两个部分R21和R22，其中上部R22相对于下部R21形成悬垂部分。制备图案化光刻胶R2的光刻技术如下：(a)首先用下光刻胶R21和上光刻胶R22顺序涂覆第一SiN膜21，其中下光刻胶R21的光学灵敏度与上光刻胶R22的光学灵敏度不同；具体地，下光刻胶的灵敏度与上光刻胶R22相比具有更高的灵敏度；(b)同时照射上光刻胶R22和下光刻胶R21；以及(c)显影光刻胶R21和R22，可以获得具有3A所示的截面的图案化光刻胶R2。由于上光刻胶R22和下光刻胶R21之间的光敏性不同，上光刻胶R22形成具有宽度W3的开口R22a，宽度W3小于下光刻胶R21中的开口R21a的宽度W2。并且，上光刻胶R22中的开口R22a的宽度W3大于形成在第一SiN膜21中的开口21a的宽度W1。因此，上光刻胶R22的边缘从第一SiN膜中的开口21a的边缘退回了距离L，该距离等于开口21a的宽度W1与上光刻胶R22的宽度W3之差的一半。因此，光刻胶R2形成对应于源电极31和漏电极32的开口R2a。
本步骤的光刻特征是光刻胶R2中的开口R2a比源极开口21a或漏极开口21b宽。也就是说，上光刻胶R22的开口R22a中的宽度W3大于源极开口21a和漏极开口21b的宽度W1。而且，下光刻胶R21中的开口R21a的宽度W2大于上光刻胶R22中的开口R22a的宽度W3。具体地，上光刻胶R22中的开口R22a的边缘从源极开口21a的边缘和漏极开口21b的边缘退回约0.5μm，优选地0.4至0.7μm，该退回由图3A中的距离L表示。因此，围绕源极开口21a和漏极开口21b的宽度约0.5μm的外围区域21c和21d可以从光刻胶R2中暴露或者通过光刻胶R2变得可见。
然后，如图3B所示，在光刻胶R2的开口R2a内显现的外围区域21c和21d暴露在含有氯(Cl)的等离子体P中；其通常由氯(CL2)或四氯化硅(SiCl4)诱导。因为这种含氯(C1)的等离子体可以蚀刻氮化物半导体材料，所以在源极开口21a和漏极开口21b中暴露的半导体层15部分地被蚀刻。也就是说，在第一SiN膜21中的开口21a和21b中暴露的阻挡层13的一部分和覆盖层14被蚀刻掉一定深度以部分地保留阻挡层13达例如最多10nm的厚度。因此，使用含氯(Cl)气体的等离子体工艺在半导体叠层15的表面中形成凹槽15a。源极电极31和漏极电极32可以形成在凹槽15a内并与阻挡层13直接接触，这可以降低源电极31和漏电极32的接触电阻。
用于部分地蚀刻半导体叠层15的等离子体工艺还可以影响在第一SiN膜21上的光刻胶R2的开口R2a内出现的外围区域21c和21d。具体地，与由光刻胶R2隐藏的第一SiN膜21的表面的其他部分相比，其表面暴露于氯(Cl)等离子体的外围区域21c和21d被粗糙化。与含有镓(Ga)、铝(Al)、铟(In)等的氮化物半导体材料相比，氯等离子体难以蚀刻SiN膜。因此，使用含氯(Cl)气体的上述等离子体工艺几乎不蚀刻第一SiN膜21，实际上最多几乎蚀刻0.3nm的深度，仅使其表面粗糙。
然后，如图4A所示，该工艺通过源极开口21a形成与阻挡层13接触的源电极31，通过漏极开口21b形成也与阻挡层13接触的漏电极32。具体地，在第一SiN膜21中的开口21a内、外围区域21c和21d、第一SiN膜21上和光刻胶R2上顺序沉积用于各电极31和32的金属34，其中金属34包括作为第一金属的Ta、Ti和Ni中的至少一种和作为第二金属的Al。金属34不仅填充半导体叠层15中的凹槽15a，并且覆盖围绕开口21a的外围区域21c和21d，而且积聚在光刻胶R2上。
通过溶剂去除光刻胶R2，也可以去除积聚在光刻胶R2上的残留金属34，这有时被称为剥离工艺，则留下用于源电极31和漏电极32的金属34，如图4B所示。在比第一SiN膜21的沉积温度低的500℃至600℃的温度下，将层叠金属34合金化，可以形成作为非整流接触的源电极31和漏电极32。
接下来，如图4C所示，该工艺沉积作为第二绝缘膜的另一SiN膜22，以便覆盖源电极31和漏电极32以及暴露在源电极31和漏电极32之间的第一SiN膜21。因为在对源电极31和漏电极32进行热处理之后需要处理第二SiN膜22，所以可以例如通过与用于第一SiN膜21的技术不同的等离子体辅助化学气相沉积(p-CVD)技术来沉积第二SiN膜32。该p-CVD技术通常在远低于LPCVD技术的沉积温度的温度下进行沉积，其中本实施例在约300℃的温度下沉积第二SiN膜22。在沉积第二SiN膜22之后，该工艺形成栅电极33。具体地，在第一SiN膜21和第二SiN膜22中形成栅极开口24，然后沉积栅极金属以填充栅极开口24，并且部分地覆盖在栅极开口24外围内的第二SiN膜22，可以形成如图4C所示的具有T形截面的栅电极33。最后，又一SiN膜23(其是第三SiN膜23)覆盖栅电极33和从栅电极33露出的第二SiN膜22。第三SiN膜23也可以通过p-CVD技术形成。因此，可以实现根据本实施例的形成氮化物半导体器件1A的工艺。
将描述根据本发明的优点。当金属34与第一SiN膜21接触时，在将用于源电极31和/或漏电极32的金属合金化以形成非整流接触；金属34中包含的原子可以与SiN膜21中包含的硅(Si)发生反应以产生硅化物材料。在本实施例中，金属34中的铝(Al)可以容易地产生硅化铝(AlSix)。为了防止AlSix的形成，优选地可以通过LPCVD技术在高于700℃的温度下沉积第一SiN膜21，该温度高于合金化温度，其中LPCVD技术可以在降低沉积压力的同时通过提高其沉积温度而形成致密的SiN膜。通过根据本实施例的LPCVD技术沉积的第一SiN膜21变得过于致密，以抑制或基本上防止形成硅化铝(AlSix)，即使当非整流接触的金属34在高于500℃的温度下被合金化时也是如此。然而，致密的SiN膜通常会降低沉积在其上的金属的粘附性。因此，如图5所示，在外围部分A中的SiN膜上沉积的金属容易从SiN膜上剥离。
根据本实施例的工艺，为了解决上述问题，首先在第一SiN膜21中制备具有开口R2a的图案化光刻胶R2，开口R2a的宽度W3大于开口21a和21b的宽度W1，这意味着围绕开口21a和21b的外围区域21c和21d通过光刻胶R2变得可见。因此，在通过等离子体在半导体叠层15中形成凹槽15a期间，第一SiN膜21的外围区域21c和21d暴露于由含氯(Cl)气体形成的等离子体，这可能使第一SiN膜21的外围区域21c和21d的表面粗糙化，以对沉积在其上的金属产生锚定效应。也就是说，用于源电极31和漏电极32的金属可以分别牢固且紧密地与SiN膜21的外围区域21c和21d相接触。因此，即使在高温下对金属34进行合金化处理，源电极31和漏电极32也不会从SiN膜21剥离。
根据本实施例的工艺使用含氟(F)的等离子体来在第一SiN膜21中形成源极开口21a和漏极开口21b。然而，在形成开口21a和21b期间，除了待蚀刻的区域之外，第一SiN膜21被图案化光刻胶R1覆盖。因此，在形成开口21a和21b期间，第一SiN膜21的表面不暴露于等离子体。
此外，暴露于等离子体的外围区域21c和21d可以具有距开口21a和21b的相应边缘约0.5μm的宽度。根据本实施例的工艺在第一SiN膜21中形成具有开口R2a的图案化光刻胶R2，由此开口R2a完全覆盖的开口21a和21b，并且由此具有宽度W3，该宽度W3比开口21a和21b的宽度W1至少大(W3-W1)/2，这可以使图案化光刻胶R2中的开口R2a的边缘从开口21a和21b的边缘退回约0.5μm。
待被转化为源电极31和漏电极32的金属34可以包括Ta层、Ti层和Ni层中的一种作为第一层，并包括Al层作为第二层。如此构造的金属34可以在比第一SiN膜21的沉积温度低的500至600℃的温度下被合金化。在金属34的合金化期间，金属34与外围区域21c和21d中的第一SiN膜21之间的界面也在500℃以上的温度下升温。然而，因为本实施例的第一SiN膜21通过LPCVD技术在高于700℃的温度下沉积，该温度也高于使源电极31和漏电极32的金属34合金化的温度。因此，即使在合金化温度下，外围区域21c和21d中的界面也可以是稳定的，这抑制或基本上防止铝(Al)和硅(Si)之间的相互扩散而产生AlSix。
此外，在半导体叠层15中形成凹槽15a期间，本实施例的工艺完全蚀刻覆盖层14以保留阻挡层13的一部分。利用源电极31和漏电极32的金属34填充凹槽15a，金属34可以与阻挡层13直接接触并降低其接触电阻。
形成凹槽15a的工艺可以使用由Cl2或SiCl4的反应气体产生的等离子体P，其可以确保第一SiN膜21与半导体叠层15的刻蚀速率足够小，使得可以形成凹槽15a，而仅使其外围区域21c和21d中的第一SiN膜21的表面粗糙化。此外，可以通过LPCVD技术在700至800℃的温度、10至60Pa的压力下使用用于硅(Si)的二氯硅烷(SiH2Cl2)的源气体和用于氮(N)的氨(NH3)的源气体来形成第一SiN膜21。因此，根据本实施例的工艺可以形成足够致密且稳定的第一SiN膜21，这可以防止用于源电极31和漏电极32的金属34中包含的铝(Al)与第一SiN膜21中的硅(Si)发生反应，以在它们之间形成硅化铝(AlSix)。
虽然本文已经出于说明的目的描述了本发明的特定实施例，但是对于本领域技术人员来说，许多修改和改变将变得显而易见。例如，尽管该实施例关注高电子迁移率晶体管(HEMT)类型的电子器件，但是本实施例的工艺可以应用于具有通过在高温下合金化形成的电极和SiN膜的其他类型的电子器件。而且，该实施例的工艺仅提供一种用于沉积电极金属的光刻技术。也就是说，使用普通的光刻胶同时实施在半导体叠层中形成凹槽的工艺和用于将SiN膜的表面暴露于等离子体的工艺。然而，这些工艺可以使用相应的图案化光刻胶独立地进行。因此，所附权利要求旨在包含落入本发明的真实精神和范围内的所有这些修改和改变。

Claims (8)

1.一种形成氮化物半导体器件的工艺，包括：
在衬底上外延生长由氮化物半导体材料制成的多个半导体层，所述多个半导体层形成半导体叠层；
在沉积温度下通过低压化学气相沉积技术在所述半导体叠层上沉积氮化硅膜；
在所述氮化硅膜中形成开口；
在形成开口的步骤之后，部分地蚀刻在所述氮化硅膜的开口内出现的所述半导体叠层的表面，以通过使用包含氯离子的等离子体在其中形成凹槽，所述蚀刻使围绕所述开口的氮化硅膜的表面的外围区域粗糙化；
在部分地蚀刻的步骤之后，在半导体叠层的凹槽内和所述氮化硅膜的表面的外围区域上沉积金属；以及
在比所述氮化硅膜的沉积温度低的合金化温度下对所述金属进行合金化以形成与所述半导体叠层非整流接触的电极。
2.根据权利要求1所述的工艺，其中，
沉积所述氮化硅膜的步骤形成具有10nm至100nm厚度的氮化硅膜。
3.根据权利要求1所述的工艺，其中，
部分地蚀刻的步骤将所述外围区域设置为距离所述氮化硅膜中的开口的宽度为0.4μm至0.7μm。
4.根据权利要求1所述的工艺，
其中，沉积金属的步骤包括顺序沉积第一金属层和第二金属层的步骤，所述第一金属层由钽、钛和镍中的一种制成，所述第二金属层由铝制成，并且
其中，合金化所述金属的步骤在500℃至600℃的温度下进行。
5.根据权利要求1所述的工艺，
其中，从所述衬底的一侧起，所述半导体叠层包括由氮化镓制成的沟道层、设置在所述氮化镓沟道层上的阻挡层以及设置在所述阻挡层上的由氮化镓制成的覆盖层，所述阻挡层由氮化铝镓和氮化铟铝中的一种制成，并且
其中，部分地蚀刻的步骤通过蚀刻所述覆盖层和所述阻挡层的一部分来形成所述凹槽。
6.根据权利要求1所述的工艺，其中，
部分地蚀刻的步骤使用由氯和四氯化硅中的一种产生的等离子体。
7.根据权利要求1所述的工艺，其中，
沉积所述氮化硅膜的步骤是在700℃至800℃的沉积温度和10Pa至60Pa的沉积压力下使用用于硅和氮的二氯硅烷和氨作为源气体而进行的。
8.根据权利要求1所述的工艺，其中，
部分地蚀刻的步骤包括以下步骤：
用具有下光刻胶和上光刻胶的光刻胶涂覆所述氮化硅膜的表面，所述下光刻胶的光学灵敏度大于所述上光刻胶的光学灵敏度，
同时照射所述上光刻胶和所述下光刻胶，以及
对所述上光刻胶和所述下光刻胶显影，
其中，所述上光刻胶提供宽度大于所述氮化硅膜中的开口的宽度的开口，以完全暴露所述氮化硅膜中的开口，所述下光刻胶提供宽度大于所述上光刻胶中的开口的宽度的开口，所述上光刻胶相对于所述下光刻胶形成悬垂部分。
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