TW201929041A - 形成氮化物半導體裝置之方法 - Google Patents

形成氮化物半導體裝置之方法 Download PDF

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TW201929041A
TW201929041A TW107136390A TW107136390A TW201929041A TW 201929041 A TW201929041 A TW 201929041A TW 107136390 A TW107136390 A TW 107136390A TW 107136390 A TW107136390 A TW 107136390A TW 201929041 A TW201929041 A TW 201929041A
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sin film
opening
sin
photoresist
semiconductor stack
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中野拓真
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日商住友電工器件創新股份有限公司
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Abstract

本文揭示一種形成氮化物半導體裝置之方法。該方法首先藉由低壓化學氣相沈積(LPCVD)技術在一溫度下將氮化矽(SiN)薄膜沈積於半導體層上，隨後在該SiN薄膜中形成開口以用於歐姆電極。於該SiN薄膜上製備光阻，其中該光阻提供完全覆蓋該SiN薄膜中之該開口的開口，該方法將該SiN薄膜之該開口周圍的周邊區域暴露於氯(Cl)電漿，該氯電漿可蝕刻該半導體層以在其中形成凹部。將用於該歐姆電極之金屬填充於該半導體層之該凹部內及該SiN薄膜之該周邊區域中。最後，在低於該SiN薄膜之該沈積溫度的溫度下使該等金屬合金化。

Description

形成氮化物半導體裝置之方法
本發明係關於一種形成半導體裝置，特定言之主要由氮化物半導體材料製成之半導體裝置的方法。
日本專利申請公開案第JP2013-123047A號已揭示一種形成氮化物半導體裝置之方法。該方法中揭示：首先用藉由低壓化學氣相沈積(LPCVD)技術所形成之絕緣薄膜覆蓋氮化物半導體層，其中該鈍化薄膜含有氮化矽(SiN)；隨後藉由刻蝕該鈍化薄膜以部分暴露該半導體層之表面來在半導體層中形成凹部。在該凹部內選擇性生長p型氮化鎵(GaN)層，且將閘電極形成至該p型GaN上，可形成主要由氮化物半導體材料製成之電子裝置。上文所提及之先前專利文獻已揭示或提出，鈍化薄膜係在高於550℃、較佳地高於700℃之溫度下沈積。
另一先前日本專利申請公開案第JP2001-077204A號已揭示異質雙極電晶體及形成其之方法。該方法中揭示：在將SiN薄膜沈積於基板上之前，藉由電子回旋諧振反應性離子蝕刻(ECR-RIE)使用氯氣(Cl2 )及氬氣(Ar)預處理基板以增強基板與SiN薄膜之間的黏著力。
根據本發明之實施例之態樣係關於一種形成氮化物半導體裝置之方法。該方法包括以下步驟：(a)在基板上磊晶生長由氮化物半導體材料製成之半導體層，其中該半導體層形成半導體堆疊；(b)藉由低壓化學氣相沈積(LPCVD)技術於半導體堆疊上沈積氮化矽(SiN)薄膜；(c)在SiN薄膜中形成開口；(d)將出現在SiN薄膜中之開口內的半導體堆疊之表面及該開口周圍之SiN薄膜之表面之周邊區域暴露於電漿，該電漿含有氯(Cl)離子且部分蝕刻該半導體堆疊以在其中形成凹部；及(e)在暴露於SiN薄膜之開口內的半導體堆疊之表面上及SiN薄膜之表面之周邊區域上沈積金屬；以及(f)在低於沈積溫度之合金化溫度下使該等金屬合金化以抵靠半導體堆疊形成用於非整流接觸的電極。
接下來，將參考圖式來描述根據本發明之實施例。然而，本發明並不受限於實施例且具有所附申請專利範圍所指示之範疇，及在申請專利範圍及其等效物內之所有修改及/或變化。又，在圖式之描述中，彼此相同或類似之數字或符號將在無再次解釋之情況下指代彼此相同或類似之元件。
圖1為藉由根據本發明之實施例之方法所形成的半導體裝置1A之截面視圖。半導體裝置1A為一種場效電晶體(FET)，特定言之，一種主要由氮化物半導體材料製成之高電子遷移率電晶體(HEMT)。實施例之HEMT 1A包括基板11、氮化物半導體層12至14、第一至第三氮化矽(SiN)薄膜21至23以及源電極31、汲電極32及閘電極33。
基板11由具有帶(0001)晶面之主要表面的碳化矽(SiC)製成。然而，基板11不受限於具有(0001)晶面之SiC，且可由例如矽(Si)、氮化鎵(GaN)、藍寶石(Al2 O3 )等等之其他材料製成，只要基板11上能夠實現半導體磊晶生長即可。半導體堆疊15自基板11之一側可包括各自依序生長於基板11上的通道層12、障壁層13及頂蓋層14。通道層12可由厚度約1 μm、具體言之0.5至1.5 μm之未經摻雜GaN製成。障壁層13可由厚度為20 nm、具體言之10至30 nm之n型氮化鋁鎵(AlGaN)或n型氮化銦鋁(InAlN)製成。頂蓋層14可由厚度為5 nm、具體言之3至8 nm之n型GaN製成。因此組態之半導體裝置1A可在抵靠障壁層13之界面處於通道層12中形成二維電子氣體(2DEG)，其中該2DEG變成用於半導體裝置1A之通道。
具有鈍化半導體堆疊15之表面的功能的第一SiN薄膜21覆蓋半導體堆疊15之整個表面。第一SiN薄膜21提供源極開口21a及汲極開口21b，半導體堆疊15暴露於該等開口內。具體言之，開口21a及21b內之整個頂蓋層14及障壁層13之一部分經移除以暴露其中之障壁層13。源電極31不僅填充源極開口21a，而且延伸至源極開口21a周圍第一SiN薄膜21上之周邊區域21c。汲電極32具有類似於源電極31之結構。亦即，汲電極32填充汲極開口21b以與暴露於汲極開口21b內之障壁層13直接接觸且在汲極開口21b周圍第一SiN薄膜21上之周邊區域21d中延伸。因此，源電極31及汲電極32具有T字之截面。
各別開口21a及21b周圍第一SiN薄膜21上之周邊區域21c及21d相較於第一SiN薄膜21上之其餘部分展示第一SiN薄膜21之粗糙化表面，因為如稍後在本說明書中描述，彼等周邊區域21c及21d在於半導體堆疊15中形成凹部之步驟期間經暴露於電漿。
第二SiN薄膜22覆蓋第一SiN薄膜21以及源電極31及汲電極32。第一SiN薄膜21及第二SiN薄膜22於源極開口21a與汲極開口21b之間提供閘極開口24。閘極開口24穿過第一SiN薄膜21及第二SiN薄膜22以暴露頂蓋層14之表面。亦即，頂蓋層14及障壁層13在不同於用於源電極31及汲電極32之開口21a及21b的閘極開口24內未經部分移除。閘電極33填充閘極開口24以與頂蓋層14直接接觸且在閘極開口24周圍於第二SiN薄膜22上延伸。因此，閘電極33亦具有T字之截面。
第一SiN薄膜21之厚度在本實施例中為10至100 nm，較佳地20 nm。厚度為至少10 nm之第一SiN薄膜21可確保半導體堆疊15與T形閘電極33之擴展部分之間的間隙，從而可抑制其間引發之寄生電容。又，厚度為至多100 nm之第一SiN薄膜21可保有藉由T形閘電極33之懸伸端之存在而有效調節閘電極33之邊緣處之電場強度的功能，從而可減少閘極洩漏電流。另一方面，第二SiN薄膜22較佳地具有40 nm之厚度；但可視半導體裝置1A之應用及效能而定省略第二SiN薄膜22。
源電極31及汲電極32為抵靠障壁層13的展示非整流特徵的一種所謂的歐姆電極。厚度約300 nm之源電極31及汲電極32能夠藉由使可表示為Ta/Al/Ta之鉭/鋁/鉭、可表示為Ti/Al/Ti之鈦/鋁/鈦及可表示為Ti/Al/Ni/Au之鈦/鋁/鎳/金中之一者的堆疊金屬合金化而形成。為一種肖特基電極類型的閘電極33可為鎳(Ni)及金(Au)之堆疊金屬，其中Ni充當抵靠頂蓋層14之蕭特基接觸。第三SiN薄膜23完全覆蓋閘電極33及自閘電極33暴露之第二SiN薄膜22。
接下來，將參考圖2A至圖4C描述一種形成半導體裝置1A之方法，其中彼等圖式為半導體裝置1A在方法之各別步驟之截面視圖。
首先，如圖2A中所展示，該方法於基板11上磊晶生長半導體層12至14以形成半導體堆疊15。亦即，該方法藉由MOCVD技術依序及連續地磊晶生長基板11上之通道層12、通道層12上之障壁層13及障壁層13上之頂蓋層14。當障壁層13由InAlN製成時，磊晶生長使用用於GaN層之源材料三甲基鎵(TMG)及氨氣(NH3 )，用於AlGaN層之源材料三甲基鋁(TMA)、TMG及NH3 ，以及用於InAlN層之源材料三甲基銦(TMI)、TMG及NH3 。又，單矽烷(SiH4 )在生長障壁層13及頂蓋層14時用作用於n型摻雜劑之源材料
其後，第一SiN薄膜21如圖2B中所展示藉由LPCVD技術沈積於半導體堆疊15上。LPCVD技術之示範性條件為700至800℃之生長溫度、10至60 Pa之生長壓力及用於矽(Si)之源材料二氯甲矽烷(SiH2 Cl2 )及用於氮(N)之源材料NH3 。如所描述，第一SiN薄膜21可以10至100 nm之厚度沈積。
其後，源極開口21a及汲極開口21b經形成在第一SiN薄膜21中。具體言之，如圖2C中所展示，圖案化光阻R1首先經製備於第一SiN薄膜21上，其中圖案化光阻R1具有對應於開口21a及21b之開口R1a，其中圖2C代表性地說明僅一個用於源極開口21a之開口R1a。藉由反應性離子蝕刻(RIE)使用含氟(F)之反應氣體刻蝕暴露於開口R1a內之第一SiN薄膜21，該方法可形成各自具有寬度W1 之源極開口21a及汲極開口21b。源極21a及汲極21b之開口可具有彼此實質上相同之寬度；但可具有彼此不同之各別寬度。
其後，移除圖案化光阻R1，該方法於第一SiN薄膜21上製備另一圖案化光阻R2，其中另一圖案化光阻R2提供對應於源電極31及汲電極32之開口R2a，其中圖3A說明用於源電極31之開口R2a中之僅一者。開口R2a具有在豎直方向上彼此可區別的兩個部分R21及R22，其中上部部分R22相對於下部部分R21形成懸伸端。製備圖案化光阻R2之光微影技術如下：(a)首先用下部光阻R21及上部光阻R22依序塗佈第一SiN薄膜21，其中下部光阻R21之光學靈敏度不同於上部光阻R22之光學靈敏度；具體言之，相較於上部光阻R22之靈敏度，下部光阻之靈敏度更大；(b)同時照射上部光阻R22及下部光阻R21；以及(c)顯影光阻R21及R22，可獲得具有圖3A中所展示之截面的圖案化光阻R2。由於上部光阻R22與下部光阻R21之間的光敏性之差異，上部光阻R22形成具有寬度W3之開口R22a，該寬度W3小於下部光阻R21中之開口R21a之寬度W2。又，上部光阻R22中之開口R22a之寬度W3大於形成在第一SiN薄膜21中之開口21a之寬度W1。因此，上部光阻R22之邊緣自第一SiN薄膜中之開口21a之邊緣後退距離L，該距離L等於開口21a之寬度W1 與上部光阻R22之寬度W3 之間的差之一半。因此，光阻R2形成對應於源電極31及汲電極32之開口R2a。
本步驟之光微影之特徵在於光阻R2中之開口R2a比源極開口21a或汲極開口21b寬。亦即，上部光阻R22之開口R22a中之寬度W3大於源極開口21a及汲極開口21b之寬度W1。又，下部光阻R21中之開口R21a之寬度W2大於上部光阻R22中之開口R22a之寬度W3。具體言之，上部光阻R22中之開口R22a之邊緣自源極開口21a之邊緣及汲極開口21b之邊緣後退約0.5 μm，較佳地0.4至0.7 μm，其藉由圖3A中的距離L指示。因此，寬度約0.5 μm之源極開口21a及汲極開口21b周圍的周邊區域21c及21d可自光阻R2暴露或經由光阻R2變得可見。
其後，如圖3B中所展示，出現在光阻R2之開口R2a內的周邊區域21c及21d經暴露於含氯(Cl)之電漿P；該電漿P通常藉由氯氣(Cl2 )或四氯化矽(SiCl4 )引發。由於含氯(Cl)之此電漿可蝕刻氮化物半導體材料，故暴露於源極開口21a及汲極開口21b中之半導體層15經部分蝕刻。亦即，暴露於第一SiN薄膜21中的開口21a及21b中之頂蓋層14及障壁層13之部分經蝕刻一深度以留下厚度為例如至多10 nm之部分障壁層13。因此，使用含氯(Cl)之氣體的電漿製程在半導體堆疊15之表面中形成凹部15a。源電極31及汲電極32可經形成於凹部15a內且與障壁層13直接接觸，從而可降低源電極31及汲電極32之接觸電阻。
用於部分刻蝕半導體堆疊15之電漿製程亦可影響出現在光阻R2之開口R2a內的第一SiN薄膜21上之周邊區域21c及21d。具體言之，其表面中暴露於氯(Cl)電漿之周邊區域21c及21d相較於藉由光阻R2隱藏的第一SiN薄膜21之表面之其他部分經粗糙化。相較於含鎵(Ga)、鋁(Al)、銦(In)等等之氮化物半導體材料，氯電漿難以蝕刻SiN薄膜。因此，上文所描述之使用含氯(Cl)之氣體的電漿製程幾乎不蝕刻第一SiN薄膜21 (幾乎至多蝕刻差不多0.3 nm深)，而是僅使其表面粗糙化。
其後，如圖4A中所示，該方法形成經由源極開口21a與障壁層13接觸之源電極31及經由汲極開口21b亦與障壁層13接觸之汲電極32。具體言之，依序在第一SiN薄膜21中之開口21a內、周邊區域21c及21d內、第一SiN薄膜21上及光阻R2上沈積用於電極31及32之金屬34，其中金屬34包括作為第一金屬的Ta、Ti及Ni中之至少一者及作為第二金屬之Al。金屬34不僅填充半導體堆疊15中之凹部15a及覆蓋開口21a周圍之周邊區域21c及21d，而且積聚至光阻R2上。
藉由溶劑移除光阻R2，亦可移除積聚於光阻R2上之殘餘金屬34，其有時被稱作剝離製程，從而留下用於源極31及汲極32之電極之金屬34，如圖4B中所展示。在低於第一SiN薄膜21之沈積溫度的溫度500至600℃下使堆疊金屬34合金化，源極31及汲極32之電極可經形成為非整流接觸。
其後，如圖4C中所展示，該方法沈積作為第二絕緣薄膜之另一SiN薄膜22以便覆蓋源極31及汲極32之電極以及暴露於電極31與32之間的第一SiN薄膜21。第二SiN薄膜32可藉由例如不同於用於第一SiN薄膜21之技術的電漿輔助化學氣相沈積(p-CVD)技術來沈積，因為需要在用於源極31及汲極32之電極的熱製程之後處理第二SiN薄膜22。p-CVD技術一般在遠低於LPCVD技術之沈積溫度的溫度下執行沈積，其中本實施例在約300℃之溫度下沈積第二SiN薄膜22。在沈積第二SiN薄膜22之後，該方法形成閘電極33。具體言之，於第一SiN薄膜21及第二SiN薄膜22中形成閘極開口24、隨後沈積閘極金屬以便填充閘極開口24及部分覆蓋閘極開口24周邊之第二SiN薄膜22，可形成具有如圖4C中所展示之T形截面的閘電極33。最後，為第三SiN薄膜23之另一SiN薄膜23覆蓋閘電極33及自閘電極33暴露之第二SiN薄膜22。第三SiN薄膜23亦可藉由p-CVD技術形成。因此，可完成根據本實施例之形成氮化物半導體裝置1A之方法。
以下將描述根據本發明之優點。當用於源電極31及/或汲電極32之金屬經合金化以由於金屬34與第一SiN薄膜21接觸而形成非整流接觸時，包含於金屬34中之原子可與包含於SiN薄膜21中之矽(Si)反應以產生矽化物物質。在本實施例中，金屬34中之鋁(Al)可容易地產生矽化鋁(AlSix)。為了防止形成AlSix，第一SiN薄膜21可較佳地藉由LPCVD技術在高於700℃之溫度(其高於合金化溫度)下經沈積，其中LPCVD技術可藉由在降低沈積壓力的同時升高其沈積溫度而形成密集型SiN薄膜。根據本實施例之藉由LPCVD技術沈積之第一SiN薄膜21變得極度密集以抑制或實質上防止形成矽化鋁(AlSix)，即使當非整流接觸之金屬34在高於500℃之溫度下經合金化時亦如此。然而，密集型SiN薄膜通常降低其上沈積之金屬之黏著力。因此，沈積於SiN薄膜上周邊部分A中之金屬容易自SiN薄膜剝離，即如圖5中所展示。
根據本實施例之方法，為了解決上文所描述之問題，首先製備具有開口R2a之圖案化光阻R2，該開口R2a之寬度W3大於第一SiN薄膜21中之開口21a及21b之寬度W1，此意謂開口21a及21b周圍之周邊區域21c及21d變得經由光阻R2可見。因此，第一SiN薄膜21之周邊區域21c及21d在藉由電漿於半導體堆疊15中形成凹部15a期間乃經暴露於藉由含氯(Cl)之氣體所形成的電漿，該電漿可使第一SiN薄膜21之周邊區域21c及21d之表面粗糙化以引起其上沈積之金屬的錨定效應。亦即，用於源電極31及汲電極32之金屬可分別牢固且緊密地接觸SiN薄膜21之周邊區域21c及21d。因此，即使在高溫下進行合金化金屬34之製程，源極31及汲極32之電極亦不會自SiN薄膜21剝離。
根據本實施例之方法使用含氟(F)之電漿以供形成第一SiN薄膜21中之源極開口21a及汲極開口21b。然而，除待蝕刻之區域以外，在形成開口21a及21b期間用圖案化光阻R1覆蓋第一SiN薄膜21。因此，第一SiN薄膜21之表面在形成開口21a及21b期間未暴露於電漿。
又，暴露於電漿之周邊區域21c及21d可自開口21a及21b之各別邊緣具有約0.5 μm之寬度。根據本實施例之方法形成具有其開口R2a之圖案化光阻R2，該開口R2a完全覆蓋第一SiN薄膜21中之開口21a及21b且其寬度W3比開口21a及21b之寬度W1大至少(W3-W1)/2，其可使圖案化光阻R2中之開口R2a之邊緣自開口21a及21b之邊緣後退約0.5 μm。
待轉變成源極31及汲極32之電極的金屬34可包括作為第一層的Ta層、Ti層及Ni層中之一者及作為第二層的Al層。因此組態之金屬34可在低於第一SiN薄膜21之沈積溫度的500至600℃之溫度下經合金化。在金屬34之合金化期間，金屬34與周邊21c及21d中之第一SiN薄膜21之間的界面亦升高至高於500℃之溫度。然而，由於本實施例之第一SiN薄膜21係藉由LPCVD技術在高於700℃之溫度下沈積，該溫度亦高於合金化用於源極31及汲極32之電極的金屬34的溫度。因此，周邊區域21c及21d中之界面即使在合金化溫度下亦可為穩定的，從而抑制或實質上阻止鋁(Al)與矽(Si)之間相互擴散而產生AlSix。
又，在於半導體堆疊15中形成凹部15a期間，實施例之方法完全蝕刻頂蓋層14以留下障壁層13之一部分。用用於電極31及32之金屬34填充凹部15a，金屬34可與障壁層13直接接觸且降低其接觸電阻。
形成凹部15a之方法可使用由Cl2 或SiCl4 之反應氣體生成的電漿P，其可確保第一SiN薄膜21與半導體堆疊15之刻蝕比率足夠小，從而可形成凹部15a但僅粗糙化第一SiN薄膜21在其周邊區域21c及21d中之表面。又，第一SiN薄膜21可藉由LPCVD技術在700至800℃之溫度下於10至60 Pa之壓力下使用用於矽(Si)之來源氣體二氯甲矽烷(SiH2 Cl2 )及用於氮(N)之來源氣體氨氣(NH3 )來形成。因此，根據本實施例之方法可形成足夠密集且穩定之第一SiN薄膜21，其可防止包含於用於源極31及汲極32之電極的金屬34中之鋁(Al)與第一SiN薄膜21中之矽(Si)反應以在其間形成矽化鋁(AlSix)。
雖然出於說明之目的，已在本文中描述本發明之特定實施例，但許多修改及變化對於熟習此項技術者將變得顯而易見。舉例而言，雖然該實施例專注於電子裝置類型之高電子遷移率電晶體(HEMT)，但本實施例之方法可適用於具有SiN薄膜及藉由在高溫下使金屬合金化而形成之電極的其他類型之電子裝置。又，該實施例之方法僅提供一種用於沈積用於電極之金屬的光微影。亦即，使用共同光阻同時執行用於在半導體堆疊中形成凹部及用於將SiN薄膜之表面暴露於電漿的製程。然而，彼等製程可使用各別圖案化光阻獨立地執行。因此，所附申請專利範圍意欲涵蓋屬於本發明之真實精神及範疇內之所有此類修改及變化。 相關申請案之交叉參考
本申請案基於且主張於2017年10月16日申請之日本專利申請案第2017-200369號之優先權益，該專利申請案之全部內容以引用之方式併入本文中。
1A‧‧‧半導體裝置
11‧‧‧基板
12‧‧‧通道層
13‧‧‧障壁層
14‧‧‧頂蓋層
15‧‧‧半導體堆疊
15a‧‧‧凹部
21‧‧‧第一SiN薄膜
21a‧‧‧源極開口
21b‧‧‧汲極開口
21c‧‧‧周邊區域
21d‧‧‧周邊區域
22‧‧‧第二SiN薄膜
23‧‧‧第三SiN薄膜
24‧‧‧閘極開口
31‧‧‧源電極
32‧‧‧汲電極
33‧‧‧閘電極
34‧‧‧金屬
A‧‧‧周邊部分
L‧‧‧距離
P‧‧‧電漿
R1‧‧‧圖案化光阻
R1a‧‧‧開口
R2‧‧‧圖案化光阻
R2a‧‧‧開口
R21‧‧‧下部部分
R21a‧‧‧開口
R22‧‧‧上部部分
R22a‧‧‧開口
W1‧‧‧寬度
W2‧‧‧寬度
W3‧‧‧寬度
參考圖式，根據本發明之較佳實施例之以下詳細描述，將較佳地理解前述及其他目的、態樣及優點，其中：
圖1為根據本發明之實施例之半導體裝置的截面視圖。
圖2A至圖2C為圖1中所展示之半導體裝置在其方法之各別步驟處的截面視圖；
圖3A及圖3B為圖1中所展示之半導體裝置在圖2C中所展示之步驟之後的步驟處的截面視圖；
圖4A至圖4C展示圖1中所展示之半導體裝置在圖3B中所展示之步驟之後的各別步驟處的截面視圖；以及
圖5為說明半導體裝置之習知方法及結構中所留下之物體的截面視圖。

Claims (9)

  1. 一種形成氮化物半導體裝置之方法，其包含： 於基板上磊晶生長由氮化物半導體材料製成之半導體層，該半導體層形成半導體堆疊； 藉由低壓化學氣相沈積(LPCVD)技術在沈積溫度下於該半導體堆疊上沈積氮化矽(SiN)薄膜； 在該SiN薄膜中形成開口； 將出現在該SiN薄膜中之該開口內的該半導體堆疊之表面及該開口周圍之該SiN薄膜之表面之周邊區域暴露於電漿，該電漿含有氯(Cl)離子且部分蝕刻該半導體堆疊以在其中形成凹部； 在暴露於該SiN薄膜之該開口中的該半導體堆疊之該凹部及該SiN薄膜之該表面之該周邊區域內沈積金屬；以及 在低於該SiN薄膜之該沈積溫度的合金化溫度下使該等金屬合金化以抵靠該半導體堆疊形成用於非整流接觸的電極。
  2. 如請求項1之方法， 其中該沈積該SiN薄膜之步驟形成具有10至100 nm之厚度的該SiN薄膜。
  3. 如請求項1之方法， 其中該暴露該半導體堆疊之該表面及該SiN薄膜之該周邊區域的步驟設定該周邊區域自該SiN薄膜中之該開口之寬度為0.4至0.7 μm。
  4. 如請求項1之方法， 其中該沈積金屬之步驟包括依序沈積第一金屬層及第二金屬層之步驟，該第一金屬層由鉭(Ta)、鈦(Ti)及鎳(Ni)中之一者製成，該第二金屬層由鋁(Al)製成，且 其中該合金化該等金屬之步驟係於500至600℃之溫度下執行。
  5. 如請求項1之方法， 其中該半導體堆疊自該基板之一側包括由氮化鎵(GaN)製成之通道層、提供於該GaN通道層上之障壁層及提供於該障壁層上的由GaN製成之頂蓋層，該障壁層由氮化鋁鎵(AlGaN)及氮化銦鋁(InAlN)中之一者製成，且 其中該暴露該半導體堆疊之該表面及該SiN薄膜之該表面之該周邊區域的步驟藉由刻蝕該頂蓋層及該障壁層之一部分而形成該凹部。
  6. 如請求項1之方法， 其中該暴露該半導體堆疊之表面及該SiN薄膜之該表面之該周邊區域的步驟使用由氯氣(Cl2 )及四氯化矽(SiCl4 )中之一者生成的電漿。
  7. 如請求項1之方法， 其中該暴露該半導體堆疊之表面及該SiN薄膜之該表面之該周邊區域的步驟使該周邊區域之該表面粗糙化。
  8. 如請求項1之方法， 其中該沈積該SiN薄膜之步驟在700至800℃之該沈積溫度及10至60 Pa之沈積壓力下使用用於矽(Si)以及氮(N)的來源氣體二氯甲矽烷(SiH2 Cl2 )及氨氣(NH3 )來執行。
  9. 如請求項1之方法， 其中該暴露該半導體堆疊之該表面及該SiN薄膜之該表面之該周邊區域的步驟包括以下步驟： 用具有下部光阻及上部光阻之光阻塗佈該SiN薄膜之該表面，該下部光阻之光學靈敏度大於該上部光阻之光學靈敏度， 同時照射該上部光阻及該下部光阻，及 顯影該上部光阻及該下部光阻， 其中該上部光阻提供寬度大於該SiN薄膜中之該開口之寬度的開口以完全暴露該SiN薄膜中之該開口，該下部光阻提供寬度大於該上部光阻中之該開口之寬度的開口，該上部光阻相對於該下部光阻形成懸伸端， 其中藉由該電漿粗糙化的該SiN薄膜之該表面中之該周邊區域為出現在該上部光阻中之該開口中的該SiN薄膜之一部分。
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