TW202025258A - 氮化鎵高電子移動率電晶體的閘極結構的製造方法 - Google Patents

氮化鎵高電子移動率電晶體的閘極結構的製造方法 Download PDF

Info

Publication number
TW202025258A
TW202025258A TW107147081A TW107147081A TW202025258A TW 202025258 A TW202025258 A TW 202025258A TW 107147081 A TW107147081 A TW 107147081A TW 107147081 A TW107147081 A TW 107147081A TW 202025258 A TW202025258 A TW 202025258A
Authority
TW
Taiwan
Prior art keywords
layer
gallium nitride
forming
manufacturing
mask
Prior art date
Application number
TW107147081A
Other languages
English (en)
Other versions
TWI680503B (zh
Inventor
劉莒光
楊弘堃
Original Assignee
杰力科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 杰力科技股份有限公司 filed Critical 杰力科技股份有限公司
Priority to TW107147081A priority Critical patent/TWI680503B/zh
Priority to CN201910141595.5A priority patent/CN111370300B/zh
Priority to US16/361,217 priority patent/US10720506B1/en
Application granted granted Critical
Publication of TWI680503B publication Critical patent/TWI680503B/zh
Publication of TW202025258A publication Critical patent/TW202025258A/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/432—Heterojunction gate for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/452—Ohmic electrodes on AIII-BV compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

一種氮化鎵高電子移動率電晶體的閘極結構的製造方法，包括於基板上依序形成一通道層、一阻障層、一摻雜氮化鎵層、一未摻雜氮化鎵層以及一絕緣層，再移除部分絕緣層，以形成一溝槽。於所述基板上形成一閘極金屬層，覆蓋絕緣層與溝槽，然後在閘極金屬層上形成對準溝槽的一罩幕層，其中罩幕層與絕緣層部分重疊。利用所述罩幕層作為蝕刻罩幕，去除暴露出的閘極金屬層及其下方的絕緣層、未摻雜氮化鎵層以及摻雜氮化鎵層，之後移除罩幕層。

Description

氮化鎵高電子移動率電晶體的閘極結構的製造方法
本發明是有關於一種高電子移動率電晶體的技術，且特別是有關於一種氮化鎵高電子移動率電晶體的閘極結構的製造方法。
氮化鎵高電子移動率電晶體（high electron mobility transistor，HEMT）是利用氮化鋁鎵（AlGaN）與氮化鎵（GaN）的異質結構，於接面處會產生具有高平面電荷密度和高電子遷移率的二維電子氣(two dimensional electron gas，2DEG)，因此適於高功率、高頻率和高溫度運作。
然而，具有高濃度2DEG的HEMT採用常關型（Normally-off）的電路設計，已發現這種氮化鎵高電子移動率電晶體有閘極漏電的問題，導致電晶體的開關在不正常的操作下效能下降或是失效，使可靠度降低。
本發明提供一種氮化鎵高電子移動率電晶體的閘極結構的製造方法，能製作出低閘極漏電的HEMT。
本發明的氮化鎵高電子移動率電晶體的閘極結構的製造方法，包括於基板上依序形成一通道層、一阻障層、一摻雜氮化鎵層以及一未摻雜氮化鎵層，再於所述未摻雜氮化鎵層上形成一絕緣層。藉由移除部分絕緣層形成一溝槽，再於基板上形成一閘極金屬層，覆蓋絕緣層與溝槽，之後在閘極金屬層上形成對準溝槽的一罩幕層，且罩幕層與絕緣層部分重疊。利用所述罩幕層作為蝕刻罩幕，去除暴露出的閘極金屬層及其下方的絕緣層、未摻雜氮化鎵層以及摻雜氮化鎵層，再移除所述罩幕層。
在本發明的一實施例中，上述罩幕層與上述絕緣層的重疊面積佔罩幕層的面積比例在50%以下。
在本發明的一實施例中，上述移除部分絕緣層的步驟之後還可移除露出的未摻雜氮化鎵層，以加深溝槽並露出摻雜氮化鎵層。
在本發明的一實施例中，形成的上述閘極金屬層可直接與溝槽內的摻雜氮化鎵層接觸。
在本發明的一實施例中，形成上述通道層、阻障層、摻雜氮化鎵層以及未摻雜氮化鎵層的方法例如有機金屬化學氣相沉積（MOCVD）。
在本發明的一實施例中，形成上述絕緣層的方法例如有機金屬化學氣相沉積或低壓化學氣相沉積（LPCVD）。
在本發明的一實施例中，上述形成通道層的步驟之前還可先在所述基板上形成一第一緩衝層，再於第一緩衝層上形成一第二緩衝層，其中第二緩衝層比第一緩衝層的晶格更匹配於上述通道層。
在本發明的一實施例中，上述第一緩衝層例如氮化鋁層，且上述第二緩衝層例如氮化鋁鎵（Alx Ga1-x N，x=0.2~1）與氮化鎵的多重疊層。
在本發明的一實施例中，形成上述第一與第二緩衝層例如有機金屬化學氣相沉積。
在本發明的一實施例中，上述移除罩幕層的步驟之後還可包括形成一鈍化層，全面覆蓋閘極金屬層、絕緣層、未摻雜氮化鎵層、摻雜氮化鎵層與阻障層。
基於上述，本發明藉由兩道接近互補的光罩製程，使絕緣層位於閘極金屬層的兩側邊，因此能利用絕緣層阻隔閘極側邊的漏電流，並可通過能與通道層、阻障層與摻雜氮化鎵層一起成長的未摻雜氮化鎵層，來保護摻雜氮化鎵層，確保其不受閘極金屬層或後續源極與汲極製程的影響。因此，本發明所製造的閘極結構能提升氮化鎵高電子移動率電晶體的可靠度。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
以下實施例中所附的圖式是為了能更完整地描述發明概念的示範實施例，但是，仍可使用許多不同的形式來實施本發明，且其不應該被視為受限於所記載的實施例。在圖式中，為了清楚起見，膜層、區域及/或結構元件的相對厚度及位置可能縮小或放大。
圖1A至圖1G是依照本發明的一實施例的一種氮化鎵高電子移動率電晶體的閘極結構的製造流程剖面示意圖。
請先參照圖1A，於基板100上依序形成一通道層102、一阻障層104、一摻雜氮化鎵層106以及一未摻雜氮化鎵層108，其中基板100例如藍寶石（Sapphire）、碳化矽（SiC）、氧化鋅（ZnO）、矽（Si）、氧化鎵（Ga2 O3 ）等材料；通道層102的材料例如氮化鎵（GaN）；阻障層104的材料例如氮化鋁鎵（AlGaN）。在本實施例中，形成通道層102、阻障層104、摻雜氮化鎵層106以及未摻雜氮化鎵層108的方法例如有機金屬化學氣相沉積（MOCVD）或其他磊晶製程。在一實施例中，未摻雜氮化鎵層108的厚度例如小於200埃。此外，在形成通道層102之前，還可先在基板100上形成一第一緩衝層110與一第二緩衝層112，其中第二緩衝層112比第一緩衝層110的晶格更匹配於上述通道層102，以解決基板100與通道層102之間可能具有的晶格不匹配問題。在一實施例中，上述第一緩衝層例如氮化鋁層，且上述第二緩衝層例如氮化鋁鎵（Alx Ga1-x N，x=0.2~1）與氮化鎵的多重疊層。而且，形成第一與第二緩衝層110與112的方法也可以是有機金屬化學氣相沉積或其他磊晶製程。因此，基板100上的各層可採用相同的磊晶製程成長並且只要變更製程參數­（如原料種類、氣體流量等）即可形成膜層。
然後，請參照圖1B，於未摻雜氮化鎵層108上形成一絕緣層114，且絕緣層114的材料例如氮化矽（Si3 N4 ）、氧化鋁（Al2 O3 ）、氧化矽（SiO2 ）、氮化硼（BN）或氮化鋁（AlN），但本發明並不限於此。形成絕緣層114的方法根據材料不同，可以選擇較為簡單的低壓化學氣相沉積（LPCVD）或者有機金屬化學氣相沉積。在一實施例中，絕緣層114的厚度例如小於200埃。
接著，請參照圖1C，藉由移除部分絕緣層形成一溝槽116，且形成的溝槽116一般要比後續形成的閘極要窄一些。溝槽116的形成方式例如利用一層光阻118作為蝕刻罩幕，對圖1B的絕緣層114進行蝕刻，直到露出未摻雜氮化鎵層108，並留下被光阻118覆蓋的絕緣層114a。
隨後，請參照圖1D，在去除剩餘光阻118後，於基板100上形成一整層的閘極金屬層120，覆蓋絕緣層114a與溝槽116，其中閘極金屬層120的材料例如鎳、鉑、氮化鉭、氮化鈦、鎢或前述金屬的合金物。
然後，請參照圖1E，在圖1D的閘極金屬層120上形成對準溝槽116的一罩幕層122，且罩幕層122與絕緣層114a部分重疊，因此罩幕層122基本上與圖1C的光阻118是呈現接近互補的圖案。在本實施例中，罩幕層122可以是光阻或氧化矽之類的硬罩幕材料。然後，利用罩幕層122作為蝕刻罩幕，先去除暴露出的閘極金屬層，並留下被罩幕層122覆蓋的閘極金屬層120a。在一實施例中，罩幕層122與絕緣層114a的重疊面積佔罩幕層122的面積比例在50%以下，例如在30%以下或者在20%以下。由於絕緣層114a是用來斷絕閘極金屬層120a的側壁漏電，所以確保其位置設於閘極金屬層120a兩側即可，絕緣層114a的面積佔比則以不影響元件操作為準，故不限於上述範圍。
接著，請參照圖1F，利用罩幕層122作為蝕刻罩幕，持續移除閘極金屬層120a下方（圖1E中）的絕緣層114a、未摻雜氮化鎵層108以及摻雜氮化鎵層106，而得經蝕刻的絕緣層114b、未摻雜氮化鎵層108a以及摻雜氮化鎵層106a所組成的閘極結構。
然後，請參照圖1G，移除圖1F的罩幕層122。而在移除罩幕層的步驟之後還可形成一鈍化層124全面覆蓋閘極金屬層120a、絕緣層114b、未摻雜氮化鎵層108a、摻雜氮化鎵層106a與阻障層104，其中鈍化層124的材料例如氮化矽或氧化矽，用以緩解基板100表面應力。
若要製作氮化鎵高電子移動率電晶體，可在上述閘極結構形成後再於基板100上形成源極金屬與汲極金屬。
圖2A至圖2D是依照本發明的另一實施例的一種氮化鎵高電子移動率電晶體的閘極結構的製造流程剖面示意圖，其中使用與上一實施例相同的元件符號來代表相同或相似的構件，且所省略的部分技術說明，如各層或區域的位置、尺寸、材料、摻雜與否、功能等均可參照圖1A至圖1G的內容，因此於下文不再贅述。
請先參照圖2A，本實施例的製程可先依循上一實施例中的圖1A至圖1C，故不再贅述。然後，在得到經蝕刻的絕緣層104a之後，可利用光阻118或絕緣層104a作為蝕刻罩幕，繼續移除露出的未摻雜氮化鎵層108b，以加深溝槽116並露出摻雜氮化鎵層106。
接著，請參照圖2B，在去除剩餘光阻118後，於基板100上形成一整層的閘極金屬層120，覆蓋絕緣層114a、未摻雜氮化鎵層108b與溝槽116，且形成的閘極金屬層120直接與溝槽116內的摻雜氮化鎵層106接觸。
然後，請參照圖2C，在圖2B的閘極金屬層120上形成對準溝槽116的一罩幕層122，且罩幕層122與絕緣層114a部分重疊。之後，利用罩幕層122作為蝕刻罩幕，先去除暴露出的閘極金屬層，並留下被罩幕層122覆蓋的閘極金屬層120a。
接著，請參照圖2D，利用罩幕層122作為蝕刻罩幕，持續移除閘極金屬層120a下方（圖2C中）的絕緣層114a、未摻雜氮化鎵層108b以及摻雜氮化鎵層106，而得經蝕刻的絕緣層114b、未摻雜氮化鎵層108c以及摻雜氮化鎵層106a所組成的閘極結構。因此，本實施例中的未摻雜氮化鎵層108c是介於絕緣層114b與摻雜氮化鎵層106a之間。
綜上所述，本發明在形成閘極金屬層之前形成兩層特定膜層並搭配一道光罩製程，即可於閘極金屬層的兩側邊底下形成絕緣層與未摻雜氮化鎵層，因此能利用前述絕緣層阻隔閘極側邊的漏電流，以降低閘極漏電；並可通過前述未摻雜氮化鎵層來保護作為閘極之摻雜氮化鎵層，確保其不受閘極金屬層或後續源極與汲極製程的影響。因此，本發明所製造的閘極結構能提升氮化鎵高電子移動率電晶體的可靠度。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100:基板102:通道層104:阻障層106、106a:摻雜氮化鎵層108、108a、108b、108c:未摻雜氮化鎵層110:第一緩衝層112:第二緩衝層114、114a、114b:絕緣層116:溝槽118:光阻層120、120a:閘極金屬層122:罩幕層124:鈍化層
圖1A至圖1G是依照本發明的一實施例的一種氮化鎵高電子移動率電晶體的閘極結構的製造流程剖面示意圖。 圖2A至圖2D是依照本發明的另一實施例的一種氮化鎵高電子移動率電晶體的閘極結構的製造流程剖面示意圖。
100:基板
102:通道層
104:阻障層
106a:摻雜氮化鎵層
108a:未摻雜氮化鎵層
110:第一緩衝層
112:第二緩衝層
114b:絕緣層
120a:閘極金屬層
122:罩幕層

Claims (10)

  1. 一種氮化鎵高電子移動率電晶體的閘極結構的製造方法，包括： 於基板上依序形成一通道層、一阻障層、一摻雜氮化鎵層以及一未摻雜氮化鎵層； 於所述未摻雜氮化鎵層上形成一絕緣層； 移除部分所述絕緣層，以形成一溝槽； 於所述基板上形成一閘極金屬層，覆蓋所述絕緣層與所述溝槽； 在所述閘極金屬層上形成對準所述溝槽的一罩幕層，且所述罩幕層與所述絕緣層部分重疊； 利用所述罩幕層作為蝕刻罩幕，去除暴露出的所述閘極金屬層及其下方的所述絕緣層、所述未摻雜氮化鎵層以及所述摻雜氮化鎵層；以及 移除所述罩幕層。
  2. 如申請專利範圍第1項所述的製造方法，其中所述罩幕層與所述絕緣層的重疊面積佔所述罩幕層的面積比例在50%以下。
  3. 如申請專利範圍第1項所述的製造方法，其中移除部分所述絕緣層之後更包括：移除露出的所述未摻雜氮化鎵層，以加深所述溝槽並露出所述摻雜氮化鎵層。
  4. 如申請專利範圍第3項所述的製造方法，其中形成的所述閘極金屬層直接與所述溝槽內的所述摻雜氮化鎵層接觸。
  5. 如申請專利範圍第1項所述的製造方法，其中形成所述通道層、所述阻障層、所述摻雜氮化鎵層以及所述未摻雜氮化鎵層的方法包括有機金屬化學氣相沉積。
  6. 如申請專利範圍第1項所述的製造方法，其中形成所述絕緣層的方法包括有機金屬化學氣相沉積或低壓化學氣相沉積。
  7. 如申請專利範圍第1項所述的製造方法，其中在形成所述通道層之前更包括： 於所述基板上形成一第一緩衝層；以及 於所述第一緩衝層上形成一第二緩衝層，其中所述第二緩衝層比所述第一緩衝層的晶格更匹配於所述通道層。
  8. 如申請專利範圍第7項所述的製造方法，其中所述通道層為氮化鎵層，所述第一緩衝層為氮化鋁層，且所述第二緩衝層為氮化鋁鎵與氮化鎵的多重疊層。
  9. 如申請專利範圍第7項所述的製造方法，其中形成所述第一緩衝層與所述第二緩衝層的方法包括有機金屬化學氣相沉積。
  10. 如申請專利範圍第1項所述的製造方法，其中移除所述罩幕層之後更包括形成一鈍化層，全面覆蓋所述閘極金屬層、所述絕緣層、所述未摻雜氮化鎵層、所述摻雜氮化鎵層與所述阻障層。
TW107147081A 2018-12-26 2018-12-26 氮化鎵高電子移動率電晶體的閘極結構的製造方法 TWI680503B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW107147081A TWI680503B (zh) 2018-12-26 2018-12-26 氮化鎵高電子移動率電晶體的閘極結構的製造方法
CN201910141595.5A CN111370300B (zh) 2018-12-26 2019-02-26 氮化镓高电子移动率晶体管的栅极结构的制造方法
US16/361,217 US10720506B1 (en) 2018-12-26 2019-03-22 Method of manufacturing gate structure for gallium nitride high electron mobility transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW107147081A TWI680503B (zh) 2018-12-26 2018-12-26 氮化鎵高電子移動率電晶體的閘極結構的製造方法

Publications (2)

Publication Number Publication Date
TWI680503B TWI680503B (zh) 2019-12-21
TW202025258A true TW202025258A (zh) 2020-07-01

Family

ID=69582489

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107147081A TWI680503B (zh) 2018-12-26 2018-12-26 氮化鎵高電子移動率電晶體的閘極結構的製造方法

Country Status (3)

Country Link
US (1) US10720506B1 (zh)
CN (1) CN111370300B (zh)
TW (1) TWI680503B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI779425B (zh) * 2020-12-17 2022-10-01 杰力科技股份有限公司 氮化鎵高電子移動率電晶體的閘極結構

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220376042A1 (en) * 2021-04-12 2022-11-24 Innoscience (Suzhou) Technology Co., Ltd. Semiconductor device and method for manufacturing the same
CN113628963B (zh) * 2021-08-05 2024-03-08 苏州英嘉通半导体有限公司 Ⅲ族氮化物增强型hemt器件及其制造方法
CN115911108A (zh) * 2021-09-30 2023-04-04 华为数字能源技术有限公司 一种半导体器件及其制造方法

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3078821B2 (ja) * 1990-05-30 2000-08-21 豊田合成株式会社 半導体のドライエッチング方法
EP2267784B1 (en) * 2001-07-24 2020-04-29 Cree, Inc. INSULATING GATE AlGaN/GaN HEMT
US6867078B1 (en) * 2003-11-19 2005-03-15 Freescale Semiconductor, Inc. Method for forming a microwave field effect transistor with high operating voltage
JP4845872B2 (ja) * 2005-01-25 2011-12-28 富士通株式会社 Ｍｉｓ構造を有する半導体装置及びその製造方法
JP5332113B2 (ja) * 2007-02-15 2013-11-06 富士通株式会社 半導体装置及びその製造方法
TWI514568B (zh) * 2009-04-08 2015-12-21 Efficient Power Conversion Corp 增強模式氮化鎵高電子遷移率電晶體元件及其製造方法
US8390000B2 (en) * 2009-08-28 2013-03-05 Transphorm Inc. Semiconductor devices with field plates
WO2011118099A1 (ja) * 2010-03-26 2011-09-29 日本電気株式会社 電界効果トランジスタ、電界効果トランジスタの製造方法、および電子装置
US8604486B2 (en) 2011-06-10 2013-12-10 International Rectifier Corporation Enhancement mode group III-V high electron mobility transistor (HEMT) and method for fabrication
GB201112330D0 (en) * 2011-07-18 2011-08-31 Epigan Nv Method for growing III-V epitaxial layers and semiconductor structure
KR101834802B1 (ko) * 2011-09-01 2018-04-13 엘지이노텍 주식회사 반도체 소자
JP5790461B2 (ja) * 2011-12-07 2015-10-07 富士通株式会社 化合物半導体装置及びその製造方法
JP2014072388A (ja) * 2012-09-28 2014-04-21 Fujitsu Ltd 化合物半導体装置及びその製造方法
CN103872119B (zh) * 2012-12-17 2016-08-24 立锜科技股份有限公司 高电子迁移率晶体管及其制造方法
TW201513341A (zh) 2013-08-01 2015-04-01 Efficient Power Conversion Corp 用於增強模式氮化鎵電晶體之具有自對準凸出部的閘極
US9425301B2 (en) 2014-04-30 2016-08-23 Taiwan Semiconductor Manufacturing Co., Ltd. Sidewall passivation for HEMT devices
US9318593B2 (en) 2014-07-21 2016-04-19 Transphorm Inc. Forming enhancement mode III-nitride devices
KR101750158B1 (ko) * 2014-12-26 2017-06-22 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Hemt-호환가능 측면 정류기 구조물
US9679762B2 (en) * 2015-03-17 2017-06-13 Toshiba Corporation Access conductivity enhanced high electron mobility transistor
WO2017051530A1 (ja) * 2015-09-25 2017-03-30 パナソニックＩｐマネジメント株式会社 半導体装置
US10038085B2 (en) * 2016-01-08 2018-07-31 Infineon Technologies Austria Ag High electron mobility transistor with carrier injection mitigation gate structure
CN107230625A (zh) * 2016-03-25 2017-10-03 北京大学 氮化镓晶体管及其制造方法
WO2017201063A1 (en) * 2016-05-16 2017-11-23 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Metal nitride alloy contact for semiconductor
US10211328B2 (en) * 2016-09-20 2019-02-19 Board Of Trustees Of The University Of Illinois Normally-off cubic phase GaN (c-GaN) HEMT having a gate electrode dielectrically insulated from a c-AlGaN capping layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI779425B (zh) * 2020-12-17 2022-10-01 杰力科技股份有限公司 氮化鎵高電子移動率電晶體的閘極結構

Also Published As

Publication number Publication date
TWI680503B (zh) 2019-12-21
CN111370300A (zh) 2020-07-03
US10720506B1 (en) 2020-07-21
CN111370300B (zh) 2022-11-04
US20200212197A1 (en) 2020-07-02

Similar Documents

Publication Publication Date Title
US11404557B2 (en) Method of forming a high electron mobility transistor
US8507920B2 (en) Semiconductor structure and method of forming the same
US9236465B2 (en) High electron mobility transistor and method of forming the same
KR101202497B1 (ko) 보호층 및 저손상 리세스를 갖는 질화물계 트랜지스터 및 그의 제조 방법
US9793371B2 (en) Method of forming a high electron mobility transistor
US8624296B1 (en) High electron mobility transistor including an embedded flourine region
US9418901B2 (en) Semiconductor device containing HEMT and MISFET and method of forming the same
TWI680503B (zh) 氮化鎵高電子移動率電晶體的閘極結構的製造方法
US9263565B2 (en) Method of forming a semiconductor structure
US9018677B2 (en) Semiconductor structure and method of forming the same
CN103296077A (zh) 半导体结构及其形成方法
CN113140630B (zh) 增强型HEMT的p型氮化物栅的制备方法及应用其制备增强型氮化物HEMT的方法
TW202010125A (zh) 半導體裝置及其製造方法
TWI832676B (zh) 高電子遷移率電晶體之製造方法