US20200212197A1 - Method of manufacturing gate structure for gallium nitride high electron mobility transistor - Google Patents
Method of manufacturing gate structure for gallium nitride high electron mobility transistor Download PDFInfo
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- US20200212197A1 US20200212197A1 US16/361,217 US201916361217A US2020212197A1 US 20200212197 A1 US20200212197 A1 US 20200212197A1 US 201916361217 A US201916361217 A US 201916361217A US 2020212197 A1 US2020212197 A1 US 2020212197A1
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- gallium nitride
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- 229910002601 GaN Inorganic materials 0.000 title claims abstract description 84
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 title claims abstract description 82
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 45
- 239000002184 metal Substances 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 230000004888 barrier function Effects 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 17
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 5
- 238000002161 passivation Methods 0.000 claims description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical group Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 3
- 239000000463 material Substances 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
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Definitions
- the present disclosure relates to a technique of high electron mobility transistor (HEMT), and more particularly to a method for manufacturing a gate structure for a gallium nitride HEMT.
- HEMT high electron mobility transistor
- HEMT gallium nitride high electron mobility transistor
- AlGaN aluminum gallium nitride
- GaN gallium nitride
- 2DEG two-dimensional electron gas
- the gallium nitride HEMT with a high concentration of 2DEG adopts a normally-off circuit design.
- serious leakage at gate has occurred in such a gallium nitride HEMT, which causes low or fail switch of transistor under abnormal operation, resulting in low reliability.
- the disclosure provides a method for manufacturing a gate structure for gallium nitride high electron mobility transistor (HEMT), which is capable of producing an HEMT with low gate leakage.
- HEMT gallium nitride high electron mobility transistor
- the method for manufacturing a gate structure for gallium nitride HEMT includes orderly forming a channel layer, a barrier layer, a doped gallium nitride layer, and an undoped gallium nitride layer on a substrate, and then forming an insulating layer on the undoped gallium nitride layer, forming a trench by removing a portion of the insulating layer, forming a gate metal layer on the substrate, covering the insulating layer and the trench, and then forming a mask layer aligned with the trench on the gate metal layer, wherein the mask layer partially overlaps the insulating layer.
- the mask layer as an etching mask, the exposed gate metal layer and the underlying insulating layer, the undoped gallium nitride layer and the doped gallium nitride layer are removed, and then the mask layer is removed.
- the overlapping area of the mask layer and the insulating layer accounts for 50% or less of the area of the mask layer.
- the step of removing a portion of the insulating layer may further be followed by removing the exposed undoped gallium nitride layer to deepen the trench and expose the doped gallium nitride layer.
- the formed gate metal layer may be in direct contact with the doped gallium nitride layer in the trench.
- a method of forming the channel layer, the barrier layer, the doped gallium nitride layer, and the undoped gallium nitride layer includes, for example, metal organic chemical vapor deposition (MOCVD).
- MOCVD metal organic chemical vapor deposition
- the method of forming the above insulating layer includes, for example, metal organic chemical vapor deposition or low pressure chemical vapor deposition (LPCVD).
- LPCVD low pressure chemical vapor deposition
- the step of forming the channel layer may further be preceded by forming a first buffer layer on the substrate, and then forming a second buffer layer on the first buffer layer, wherein the lattice of the second buffer layer is more matching with the channel layer than the lattice of the first buffer layer.
- the first buffer layer is, for example, an aluminum nitride layer
- the first and second buffer layers are formed by, for example, metal organic chemical vapor deposition.
- the step of removing the mask layer may further be followed by forming a passivation layer which completely covers the gate metal layer, the insulating layer, the undoped gallium nitride layer, the doped gallium nitride layer and the barrier layer.
- the insulating layer is formed on both sides of the gate metal layer by two photomask processes that are nearly complementary to each other, so that the current leakage at the side of gate can be blocked through the insulating layer, and the doped gallium nitride layer can be protected by the undoped gallium nitride layer that can grow together with the channel layer, the barrier layer and the doped gallium nitride layer, thereby ensuring that the doped gallium nitride layer is not affected by the subsequent manufacturing process of gate metal layer and/or source and drain. Therefore, the gate structure manufactured by the present disclosure can improve the reliability of a gallium nitride HEMT.
- FIGS. 1A-1G are schematic cross-sectional views showing a manufacturing process of a gate structure for a gallium nitride HEMT according to an embodiment of the disclosure.
- FIGS. 2A -2D are schematic cross-sectional views showing a manufacturing process of a gate structure for a gallium nitride HEMT according to another embodiment of the disclosure.
- FIGS. 1A-1G are schematic cross-sectional views showing a manufacturing process of a gate structure for a gallium nitride high electron mobility transistor (HEMT) according to an embodiment of the disclosure.
- HEMT gallium nitride high electron mobility transistor
- a channel layer 102 , a barrier layer 104 , a doped gallium nitride layer 106 , and an undoped gallium nitride layer 108 are formed orderly on a substrate 100 , wherein the substrate 100 is sapphire, silicon carbide (SiC), zinc oxide (ZnO), silicon (Si), gallium oxide (Ga 2 O 3 ), etc.
- the material of the channel layer 102 is, for example, gallium nitride (GaN).
- the material of the barrier layer 104 is, for example, aluminum gallium nitride (AlGaN).
- the method of forming the channel layer 102 , the barrier layer 104 , the doped gallium nitride layer 106 , and the undoped gallium nitride layer 108 includes, for example, metal organic chemical vapor deposition (MOCVD) or other epitaxial process.
- MOCVD metal organic chemical vapor deposition
- the thickness of the undoped gallium nitride layer 108 is, for example, less than 200 angstroms.
- a first buffer layer 110 and a second buffer layer 112 may be formed on the substrate 100 , wherein the lattice of the second buffer layer 112 is more matching with the channel layer 102 than the lattice of the first buffer layer 110 , thereby solving the lattice mismatch problem between the substrate 100 and the channel layer 102 .
- the first buffer layer is, for example, an aluminum nitride layer
- the method of forming the first and second buffer layers 110 and 112 may also be a metal organic chemical vapor deposition (MOCVD) or other epitaxial process. Therefore, each layer on the substrate 100 can be grown through the same epitaxial process and the film layer can be formed by changing process parameters (such as material, gas flow rate, etc.).
- MOCVD metal organic chemical vapor deposition
- an insulating layer 114 is formed on the undoped gallium nitride layer 108 , and the material of the insulating layer 114 is, for example, silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), silicon oxide (SiO 2 ), boron nitride (BN) or aluminum nitride (AlN), but the disclosure is not limited thereto.
- the method of forming the insulating layer 114 may be selected from simple low pressure chemical vapor deposition (LPCVD) or metal organic chemical vapor deposition (MOCVD) depending on the material.
- the thickness of the insulating layer 114 is, for example, less than 200 angstroms.
- a trench 116 is formed by removing a portion of the insulating layer, and the formed trench 116 is typically narrower than the subsequently formed gate.
- the trench 116 is formed by, for example, using a photoresist 118 as an etching mask that etches the insulating layer 114 of FIG. 1B until the undoped gallium nitride layer 108 is exposed, leaving the insulating layer 114 a covered by the photoresist 118 .
- an entire gate metal layer 120 is formed on the substrate 100 , covering the insulating layer 114 a and the trench 116 , wherein the material of the gate metal layer 120 is, for example, nickel, platinum, tantalum nitride, titanium nitride, tungsten or an alloy of the foregoing metals.
- a mask layer 122 aligned with the trench 116 is formed on the gate metal layer 120 of FIG. 1D , and the mask layer 122 partially overlaps the insulating layer 114 a, so that the mask layer 122 and the photoresist 118 of FIG. 1C substantially exhibit patterns that are almost complementary to each other.
- the mask layer 122 may be a hard mask material such as photoresist or silicon oxide. Then, using the mask layer 122 as an etching mask, the exposed gate metal layer is removed, and the gate metal layer 120 a covered by the mask layer 122 is left.
- the overlapping area of the mask layer 122 and the insulating layer 114 a accounts for 50% or less of the area of the mask layer 122 , for example, 30% or less or 20% or less. Since the insulating layer 114 a is used to block the sidewall leakage of the gate metal layer 120 a, it will suffice as long as the position of the insulating layer 114 a is disposed on both sides of the gate metal layer 120 a, and the area ratio of the insulating layer 114 a is set on basis of not affecting the operation of elements, and thus not limited to the above range.
- the mask layer 122 is used as an etching mask to continuously remove the insulating layer 114 a, the undoped gallium nitride layer 108 , and the doped gallium nitride layer 106 under the gate metal layer 120 a (in FIG. 1E ), thereby obtaining a gate structure containing an etched insulating layer 114 b, an undoped gallium nitride layer 108 a, and a doped gallium nitride layer 106 a.
- a passivation layer 124 may further be formed to completely cover the gate metal layer 120 a, the insulating layer 114 b, the undoped gallium nitride layer 108 a, the doped gallium nitride layer 106 a and the barrier layer 104 .
- the material of the passivation layer 124 such as silicon nitride or silicon oxide, serves to release the surface stress of the substrate 100 .
- a source metal and a drain metal may be formed on the substrate 100 after the gate structure is formed.
- FIGS. 2A-2D are schematic cross-sectional views showing a manufacturing process of a gate structure for a gallium nitride HEMT according to another embodiment of the disclosure, wherein the same or similar components are denoted by the same reference numerals used in the previous embodiment, and the omitted technical descriptions, such as the position of each layer or region, size, material, doped or not, function, etc. may be derived from the contents of FIGS. 1A-1G , and thus related descriptions are omitted herein.
- the manufacturing process of this embodiment may be derived from FIG. 1A to FIG. 1C in the previous embodiment, and therefore related descriptions are omitted herein.
- the exposed undoped gallium nitride layer 108 b may be removed continuously by using the photoresist 118 or the insulating layer 114 a as the etching mask to deepen the trench 116 and expose the doped gallium nitride layer 106 .
- an entire gate metal layer 120 is formed on the substrate 100 , covering the insulating layer 114 a, the undoped gallium nitride layer 108 b and the trench 116 , and the formed gate metal layer 120 is in direct contact with the doped gallium nitride layer 106 in the trench 116 .
- a mask layer 122 aligned with the trench 116 is formed on the gate metal layer 120 of FIG. 2B , and the mask layer 122 partially overlaps the insulating layer 114 a. Thereafter, the mask layer 122 is used as an etching mask to remove the exposed gate metal layer, leaving the gate metal layer 120 a covered by the mask layer 122 .
- the mask layer 122 is used as an etching mask to continuously remove the insulating layer 114 a, the undoped gallium nitride layer 108 b and the doped gallium nitride layer 106 under the gate metal layer 120 a (in FIG. 2C ), thereby obtaining a gate structure containing an etched insulating layer 114 b, an undoped gallium nitride layer 108 c, and a doped gallium nitride layer 106 a. Therefore, the undoped gallium nitride layer 108 c in this embodiment is disposed between the insulating layer 114 b and the doped gallium nitride layer 106 a.
- two specific film layers are formed before forming a gate metal layer in combination with a mask manufacturing process to form an insulating layer and an undoped gallium nitride layer under both sides of the gate metal layer.
- the foregoing insulating layer to block current leakage on the side of the gate to reduce gate leakage
- the undoped gallium nitride layer can be used to protect the doped gallium nitride layer which serves as a gate to ensure that the doped gallium nitride layer is not affected by the subsequent manufacturing process of the gate metal layer or source and drain. Therefore, the gate structure manufactured by the present disclosure can improve the reliability of gallium nitride HEMT.
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Abstract
Description
- This application claims the priority benefit of Taiwan application serial no. 107147081, filed on Dec. 26, 2018. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.
- The present disclosure relates to a technique of high electron mobility transistor (HEMT), and more particularly to a method for manufacturing a gate structure for a gallium nitride HEMT.
- In gallium nitride high electron mobility transistor (HEMT), a heterogeneous structure including aluminum gallium nitride (AlGaN) and gallium nitride (GaN) is utilized to generate two-dimensional electron gas (2DEG) having high planar charge density and high electron mobility at the junction therebetween, and thus the gallium nitride HEMT is suitable for operation under high power, high frequency and high temperature.
- The gallium nitride HEMT with a high concentration of 2DEG adopts a normally-off circuit design. However, serious leakage at gate has occurred in such a gallium nitride HEMT, which causes low or fail switch of transistor under abnormal operation, resulting in low reliability.
- The disclosure provides a method for manufacturing a gate structure for gallium nitride high electron mobility transistor (HEMT), which is capable of producing an HEMT with low gate leakage.
- The method for manufacturing a gate structure for gallium nitride HEMT includes orderly forming a channel layer, a barrier layer, a doped gallium nitride layer, and an undoped gallium nitride layer on a substrate, and then forming an insulating layer on the undoped gallium nitride layer, forming a trench by removing a portion of the insulating layer, forming a gate metal layer on the substrate, covering the insulating layer and the trench, and then forming a mask layer aligned with the trench on the gate metal layer, wherein the mask layer partially overlaps the insulating layer. By using the mask layer as an etching mask, the exposed gate metal layer and the underlying insulating layer, the undoped gallium nitride layer and the doped gallium nitride layer are removed, and then the mask layer is removed.
- In an embodiment of the disclosure, the overlapping area of the mask layer and the insulating layer accounts for 50% or less of the area of the mask layer.
- In an embodiment of the disclosure, the step of removing a portion of the insulating layer may further be followed by removing the exposed undoped gallium nitride layer to deepen the trench and expose the doped gallium nitride layer.
- In an embodiment of the disclosure, the formed gate metal layer may be in direct contact with the doped gallium nitride layer in the trench.
- In an embodiment of the disclosure, a method of forming the channel layer, the barrier layer, the doped gallium nitride layer, and the undoped gallium nitride layer includes, for example, metal organic chemical vapor deposition (MOCVD).
- In an embodiment of the disclosure, the method of forming the above insulating layer includes, for example, metal organic chemical vapor deposition or low pressure chemical vapor deposition (LPCVD).
- In an embodiment of the present disclosure, the step of forming the channel layer may further be preceded by forming a first buffer layer on the substrate, and then forming a second buffer layer on the first buffer layer, wherein the lattice of the second buffer layer is more matching with the channel layer than the lattice of the first buffer layer.
- In an embodiment of the disclosure, the first buffer layer is, for example, an aluminum nitride layer, and the second buffer layer is, for example, a multi-stack layer of aluminum gallium nitride (AlxGa1−xN, x=0.2˜1) and gallium nitride.
- In an embodiment of the disclosure, the first and second buffer layers are formed by, for example, metal organic chemical vapor deposition.
- In an embodiment of the disclosure, the step of removing the mask layer may further be followed by forming a passivation layer which completely covers the gate metal layer, the insulating layer, the undoped gallium nitride layer, the doped gallium nitride layer and the barrier layer.
- Based on the above, according to the present disclosure, the insulating layer is formed on both sides of the gate metal layer by two photomask processes that are nearly complementary to each other, so that the current leakage at the side of gate can be blocked through the insulating layer, and the doped gallium nitride layer can be protected by the undoped gallium nitride layer that can grow together with the channel layer, the barrier layer and the doped gallium nitride layer, thereby ensuring that the doped gallium nitride layer is not affected by the subsequent manufacturing process of gate metal layer and/or source and drain. Therefore, the gate structure manufactured by the present disclosure can improve the reliability of a gallium nitride HEMT.
- To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
- The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
-
FIGS. 1A-1G are schematic cross-sectional views showing a manufacturing process of a gate structure for a gallium nitride HEMT according to an embodiment of the disclosure. -
FIGS. 2A -2D are schematic cross-sectional views showing a manufacturing process of a gate structure for a gallium nitride HEMT according to another embodiment of the disclosure. - The drawings in the following embodiments are exemplary embodiments intended to provide a more complete description of the disclosure, but the disclosure may be implemented in many different forms and should not be construed as being limited to the provided embodiments. In the drawings, the relative thickness and location of layers, regions, and/or structural elements may be reduced or exaggerated for clarity.
-
FIGS. 1A-1G are schematic cross-sectional views showing a manufacturing process of a gate structure for a gallium nitride high electron mobility transistor (HEMT) according to an embodiment of the disclosure. - Referring to
FIG. 1A , achannel layer 102, abarrier layer 104, a dopedgallium nitride layer 106, and an undopedgallium nitride layer 108 are formed orderly on asubstrate 100, wherein thesubstrate 100 is sapphire, silicon carbide (SiC), zinc oxide (ZnO), silicon (Si), gallium oxide (Ga2O3), etc. The material of thechannel layer 102 is, for example, gallium nitride (GaN). The material of thebarrier layer 104 is, for example, aluminum gallium nitride (AlGaN). In the present embodiment, the method of forming thechannel layer 102, thebarrier layer 104, the dopedgallium nitride layer 106, and the undopedgallium nitride layer 108 includes, for example, metal organic chemical vapor deposition (MOCVD) or other epitaxial process. In an embodiment, the thickness of the undopedgallium nitride layer 108 is, for example, less than 200 angstroms. In addition, before forming thechannel layer 102, afirst buffer layer 110 and asecond buffer layer 112 may be formed on thesubstrate 100, wherein the lattice of thesecond buffer layer 112 is more matching with thechannel layer 102 than the lattice of thefirst buffer layer 110, thereby solving the lattice mismatch problem between thesubstrate 100 and thechannel layer 102. In an embodiment, the first buffer layer is, for example, an aluminum nitride layer, and the second buffer layer is, for example, a multi-stack layer of aluminum gallium nitride (AlxGa1−xN, x=0.2˜1) and gallium nitride. Moreover, the method of forming the first andsecond buffer layers substrate 100 can be grown through the same epitaxial process and the film layer can be formed by changing process parameters (such as material, gas flow rate, etc.). - Then, referring to
FIG. 1B , aninsulating layer 114 is formed on the undopedgallium nitride layer 108, and the material of theinsulating layer 114 is, for example, silicon nitride (Si3N4), aluminum oxide (Al2O3), silicon oxide (SiO2), boron nitride (BN) or aluminum nitride (AlN), but the disclosure is not limited thereto. The method of forming theinsulating layer 114 may be selected from simple low pressure chemical vapor deposition (LPCVD) or metal organic chemical vapor deposition (MOCVD) depending on the material. In an embodiment, the thickness of theinsulating layer 114 is, for example, less than 200 angstroms. - Next, referring to
FIG. 1C , atrench 116 is formed by removing a portion of the insulating layer, and the formedtrench 116 is typically narrower than the subsequently formed gate. Thetrench 116 is formed by, for example, using aphotoresist 118 as an etching mask that etches theinsulating layer 114 ofFIG. 1B until the undopedgallium nitride layer 108 is exposed, leaving theinsulating layer 114 a covered by thephotoresist 118. - Subsequently, referring to
FIG. 1D , after removing theremaining photoresist 118, an entiregate metal layer 120 is formed on thesubstrate 100, covering theinsulating layer 114 a and thetrench 116, wherein the material of thegate metal layer 120 is, for example, nickel, platinum, tantalum nitride, titanium nitride, tungsten or an alloy of the foregoing metals. - Then, referring to
FIG. 1E , amask layer 122 aligned with thetrench 116 is formed on thegate metal layer 120 ofFIG. 1D , and themask layer 122 partially overlaps theinsulating layer 114 a, so that themask layer 122 and thephotoresist 118 ofFIG. 1C substantially exhibit patterns that are almost complementary to each other. In the present embodiment, themask layer 122 may be a hard mask material such as photoresist or silicon oxide. Then, using themask layer 122 as an etching mask, the exposed gate metal layer is removed, and thegate metal layer 120 a covered by themask layer 122 is left. In an embodiment, the overlapping area of themask layer 122 and theinsulating layer 114 a accounts for 50% or less of the area of themask layer 122, for example, 30% or less or 20% or less. Since the insulatinglayer 114 a is used to block the sidewall leakage of thegate metal layer 120 a, it will suffice as long as the position of the insulatinglayer 114 a is disposed on both sides of thegate metal layer 120 a, and the area ratio of the insulatinglayer 114 a is set on basis of not affecting the operation of elements, and thus not limited to the above range. - Next, referring to
FIG. 1F , themask layer 122 is used as an etching mask to continuously remove the insulatinglayer 114 a, the undopedgallium nitride layer 108, and the dopedgallium nitride layer 106 under thegate metal layer 120 a (inFIG. 1E ), thereby obtaining a gate structure containing an etched insulatinglayer 114 b, an undopedgallium nitride layer 108 a, and a dopedgallium nitride layer 106 a. - Then, referring to
FIG. 1G , themask layer 122 of FIG. IF is removed. After the step of removing the mask layer, apassivation layer 124 may further be formed to completely cover thegate metal layer 120 a, the insulatinglayer 114 b, the undopedgallium nitride layer 108 a, the dopedgallium nitride layer 106 a and thebarrier layer 104. The material of thepassivation layer 124, such as silicon nitride or silicon oxide, serves to release the surface stress of thesubstrate 100. - To manufacture a gallium nitride HEMT, a source metal and a drain metal may be formed on the
substrate 100 after the gate structure is formed. -
FIGS. 2A-2D are schematic cross-sectional views showing a manufacturing process of a gate structure for a gallium nitride HEMT according to another embodiment of the disclosure, wherein the same or similar components are denoted by the same reference numerals used in the previous embodiment, and the omitted technical descriptions, such as the position of each layer or region, size, material, doped or not, function, etc. may be derived from the contents ofFIGS. 1A-1G , and thus related descriptions are omitted herein. - Referring to
FIG. 2A , the manufacturing process of this embodiment may be derived fromFIG. 1A toFIG. 1C in the previous embodiment, and therefore related descriptions are omitted herein. Then, after the etched insulatinglayer 114 a is obtained, the exposed undopedgallium nitride layer 108 b may be removed continuously by using thephotoresist 118 or the insulatinglayer 114 a as the etching mask to deepen thetrench 116 and expose the dopedgallium nitride layer 106. - Next, referring to
FIG. 2B , after the remainingphotoresist 118 is removed, an entiregate metal layer 120 is formed on thesubstrate 100, covering the insulatinglayer 114 a, the undopedgallium nitride layer 108 b and thetrench 116, and the formedgate metal layer 120 is in direct contact with the dopedgallium nitride layer 106 in thetrench 116. - Then, referring to
FIG. 2C , amask layer 122 aligned with thetrench 116 is formed on thegate metal layer 120 ofFIG. 2B , and themask layer 122 partially overlaps the insulatinglayer 114 a. Thereafter, themask layer 122 is used as an etching mask to remove the exposed gate metal layer, leaving thegate metal layer 120 a covered by themask layer 122. - Next, referring to
FIG. 2D , themask layer 122 is used as an etching mask to continuously remove the insulatinglayer 114 a, the undopedgallium nitride layer 108 b and the dopedgallium nitride layer 106 under thegate metal layer 120 a (inFIG. 2C ), thereby obtaining a gate structure containing an etched insulatinglayer 114 b, an undopedgallium nitride layer 108 c, and a dopedgallium nitride layer 106 a. Therefore, the undopedgallium nitride layer 108 c in this embodiment is disposed between the insulatinglayer 114 b and the dopedgallium nitride layer 106 a. - In summary, according to the present disclosure, two specific film layers are formed before forming a gate metal layer in combination with a mask manufacturing process to form an insulating layer and an undoped gallium nitride layer under both sides of the gate metal layer. In this manner, it is possible to use the foregoing insulating layer to block current leakage on the side of the gate to reduce gate leakage; and the undoped gallium nitride layer can be used to protect the doped gallium nitride layer which serves as a gate to ensure that the doped gallium nitride layer is not affected by the subsequent manufacturing process of the gate metal layer or source and drain. Therefore, the gate structure manufactured by the present disclosure can improve the reliability of gallium nitride HEMT.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.
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US20220376042A1 (en) * | 2021-04-12 | 2022-11-24 | Innoscience (Suzhou) Technology Co., Ltd. | Semiconductor device and method for manufacturing the same |
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US6867078B1 (en) * | 2003-11-19 | 2005-03-15 | Freescale Semiconductor, Inc. | Method for forming a microwave field effect transistor with high operating voltage |
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US8604486B2 (en) | 2011-06-10 | 2013-12-10 | International Rectifier Corporation | Enhancement mode group III-V high electron mobility transistor (HEMT) and method for fabrication |
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US9425301B2 (en) | 2014-04-30 | 2016-08-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Sidewall passivation for HEMT devices |
US9318593B2 (en) | 2014-07-21 | 2016-04-19 | Transphorm Inc. | Forming enhancement mode III-nitride devices |
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