TW201513341A - 用於增強模式氮化鎵電晶體之具有自對準凸出部的閘極 - Google Patents

用於增強模式氮化鎵電晶體之具有自對準凸出部的閘極 Download PDF

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TW201513341A
TW201513341A TW103125846A TW103125846A TW201513341A TW 201513341 A TW201513341 A TW 201513341A TW 103125846 A TW103125846 A TW 103125846A TW 103125846 A TW103125846 A TW 103125846A TW 201513341 A TW201513341 A TW 201513341A
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gallium nitride
barrier layer
gate
type gate
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Jianjun Cao
Alexander Lidow
Alana Nakata
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Efficient Power Conversion Corp
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Abstract

一種在一閘極接點與一二維電子氣區之間具有減少的閘極漏損電流的增強模式氮化鎵電晶體及其製造方法,增強模式氮化鎵電晶體包括一氮化鎵層、一阻絕層設置於氮化鎵層上,並具有一二維電子氣區形成於氮化鎵層與阻絕層之間的一介面,以及設置於阻絕層的一源極接點與一汲極接點。氮化鎵電晶體更包括一P型閘極材料形成於阻絕層上並且介於源極與該汲極接點之間;以及一閘極金屬設置於P型閘極材料上,其中,P型閘極材料包括一對自對準的凸出部分別延伸朝向源極接點與汲極接點。

Description

用於增強模式氮化鎵電晶體之具有自對準凸出部的閘極
本發明主張2013年8月1日提申之美國臨時申請案61/860,976優先權,其全部內容於本案中一併列入參照。
本發明普遍是關於電晶體,並且,更具體地,是在閘極與二維電子氣區之間具有減少的閘極漏損電流的增強模式氮化鎵電晶體。
氮化鎵半導體裝置由於可在高頻切換以攜帶大電流以及支援高電壓的能力而越來越被需要,這些裝置的發展已被普遍地用在高動力/高頻應用。被製造用於這些形式的應用的裝置是基於顯現高電子遷移率並且被視為如異質接面場效電晶體(Heterojunction Field Effect Transistors,HFET)、高速電子遷移率電晶體(High Electron Mobility Transistors,HEMT),或調變摻雜場效電晶體(Modulation Doped Field Effect Transistors,MODFET)多樣的一般性的裝置結構。這些型式的裝置可典型地在例如100Hz至100GHz的高頻運作時,禁受例如30伏至2000伏的高電壓。
一氮化鎵HEMT裝置包括具有至少兩氮化層的一氮化物半導體。不同的材料形成於半導體上或於一緩衝 層上使該些層具有不同的能帶間隙。在相鄰的氮化層的不同材料亦產生極化,其貢獻至一接近該兩層之接合處的導電性二維電子氣(two Dimensional Electron Gas,2DEG)區,尤其是具有較窄能帶的層。
造成極化的氮化層典型地包括係鄰近一層氮化鎵之氮化鋁鎵的一阻絕層以包括2DEG,其允許電荷流經裝置。該阻絕層可參雜或不參雜。由於2DEG區在零閘極偏壓的狀態下存在於閘極,大部分的氮化物裝置通常位在或耗盡型式裝置。若該2DEG區在零施加閘極偏壓的狀態下位在閘極下方被耗盡(即,被移除),該裝置可為一增強模式裝置。增強模式裝置為常閉(normally off)並且是需要的,由於其提供的增加的安全性,並且由於較容易以簡單、低成本驅動電路的方式控制。一增強模式裝置需要一正偏壓供應於閘極,以傳導電流。
圖1示出一傳統增強模式氮化鎵電晶體的示意圖,如圖所示,一P型材料101用於作為閘極103,於0V偏壓時,P型材料101耗損位於閘極103下方的2DEG 102,且該裝置處於一OFF狀態。該電晶體藉由供應一正電壓至該閘極103以轉為ON。圖2示出一傳統增強模式氮化鎵電晶體的兩閘極漏損電流路徑201、202的示意圖,該第一閘極漏損電流路徑201沿著P型閘極材料101的側壁流動,而該第二閘極漏損電流路徑202流過該P型閘極材料101的凸塊。
圖3A與圖3B示出兩測試結構300A、300B的示意圖,其設計以決定用於一增強模式氮化鎵電晶體可能導致 較低的閘極漏損電流的結構型式。具體的,圖3A所示的電晶體結構300A設計當相較於圖3B所示的電晶體結構300B具有一較大的閘極表面區域與較小的閘極邊緣。在此範例中,電晶體結構300A具有140,000μm2的一閘極表面與2,500μm的邊緣,而電晶體結構300B具有84,000μm2的一閘極表面與247,000μm的邊緣。
圖4分別示出圖3A與圖3B所示的電晶體結構300A、300B的閘極漏損電流的比較曲線圖。如圖所示,結構300B具有一較高於結構300A的閘極漏損電流,表示閘極漏損電流是沿著閘極邊緣,例如圖2所示的路徑201決定。
因此,本發明的一個目的在於提供一種增強模式氮化鎵電晶體,其在閘極103與2DEG 102之間具有減少的閘極漏損電流。
本文所揭露一種增強模式氮化鎵電晶體與其製造方法為在一閘極接點與一2DEG區之間具有減少的閘極漏損電流的增強模式氮化鎵電晶體與其製造方法。該增強模式氮化鎵電晶體包括一氮化鎵層;一阻絕層設置於該氮化鎵層上,並具有一2DEG區形成於該氮化鎵層與該阻絕層之間的一介面;以及設置於該阻絕層的一源極接點與一汲極接點;該氮化鎵電晶體更包括一P型閘極材料形成於該阻絕層上並且介於該源極與該汲極接點之間;以及一閘極金屬設置於該P型閘極材料上,其中,該P型閘極材料包括包含一對自對準的凸出部延伸分別朝向該源極接點與該汲極 接點。
本文所揭露的用於製造該增強模式氮化鎵電晶體的方法包括形成一氮化鎵層的步驟;形成一阻絕層於該氮化鎵層上的步驟;沉積一P型閘極材料於該阻絕層上的步驟;沉積一閘極金屬於該P型閘極材料上的步驟;形成一光阻於該閘極金屬上的步驟;蝕刻該閘極金屬與該P型閘極材料的步驟;以及等向蝕刻該閘極金屬以形成一對凸出部於該P型閘極材料上位於該閘極金屬下方的步驟。
101‧‧‧P型閘極材料
102‧‧‧二維電子氣(2DEG)
103‧‧‧閘極
201、202‧‧‧閘極漏損電流路徑
300A、300B‧‧‧電晶體結構
501、601‧‧‧氮化鎵基體層
502、602‧‧‧阻絕層
503、603‧‧‧P型閘極材料
504、604‧‧‧閘極金屬
505‧‧‧閘極電流路徑
506‧‧‧凸出部
510‧‧‧源極金屬
512‧‧‧汲極金屬
605‧‧‧光阻
配合參閱圖式,本發明的特徵、目地與優點將可由以下的說明更清楚了解,圖式中,相同的元件是以相同的編號表示,其中:圖1為一示意圖,示出一傳統增強模式氮化鎵電晶體。
圖2為一示意圖,示出一傳統增強模式氮化鎵電晶體的兩閘極漏損電流路徑。
圖3A為一示意圖,示出一增強模式氮化鎵電晶體的測試結構。
圖3B為一示意圖,示出另一增強模式氮化鎵電晶體的測試結構。
圖4為一曲線圖,比較圖3A與圖3B所示的結構的閘極漏損電流。
圖5為一示意圖,示出根據本發明的一範例實施例的一電晶體裝置。
圖6A-6C示出製造根據一範例實施例的具有自對準的凸出部的一電晶體裝置的一閘極的一製程。
圖7A為一截面影像,示出不具有一凸出部的一傳統閘極結構。
圖7B為一截面影像,示出根據一範例實施例的具有自對準的一凸出部的一閘極結構。
圖8為一曲線圖,比較圖7A與圖7B所示的閘極結構的閘極漏損電流。
在以下的詳細說明中,是配合特定實施例參閱。這些實施例是藉由充分詳細的說明,使熟知該技術領域者得以實施。須了解的是,其他實施例也可被應用且那些不同結構、邏輯與電路的改變是可被達成的。在廣義的概念中,以下揭露的詳細說明中,該些特徵的組合並不必需要被實施,反之,僅是教示揭露本案技術的特定代表性範例。
圖5為一示意圖,示出根據本發明的一電晶體裝置的一範例實施例。如圖所示,該電晶體包括一源極金屬510(即,源極接點)與一汲極金屬512(即,汲極接點),與一閘極接點設置於源極與汲極金屬之間。具體的,一氮化鎵基體層501設置有形成於該氮化鎵基體層501上的一阻絕層502,與形成於氮化鎵基體層與阻絕層502之間的介面的一二維電子氣(2DEG)區。在此範例實施例中,阻絕層502形成自氮化鋁鎵(AlGaN)。
如進一步所示,閘極接點包括一P型閘極材料503 形成於阻絕層502上以及包括由位在如以下將詳細描述的P型閘極材料503的頂部角落的一自對準製程建立的凸出部506。一閘極金屬504設置於P型閘極材料503上。如圖所示,閘極金屬504具有較小於P型閘極材料503的寬度(亦即P型閘極材料503的側面之間的寬度)的寬度(亦即介於閘極金屬504的側壁之間的寬度),具體地於閘極金屬504的每一側形成該對水平凸出部506。延伸通過閘極金屬504的側壁的該對凸出部506具有相等或實質相等的寬度,亦即,個別的凸出部由個別的閘極金屬的側壁至P型閘極材料的側面對稱,其歸因於自對準的製程。
使用自對準製程的主要益處在於:(1)允許具有最小化臨界尺寸(CD)的一P型閘極的建立,(2)由於不需要一第二遮罩而降低製造成本,以及(3)建立對稱於設置在P型閘極材料的閘極金屬504的凸出部506。如示出在凸出部506與P型閘極材料503的側面的箭頭(標示參考編號505)所指,當一正電壓Vg施加於閘極金屬504時,閘極電流路徑505首先水平地沿著P型閘極材料503的上緣行進,並且一旦到達凸出部506,電流路徑505遵循沿著P型閘極材料503的對角路徑。此結構導致如下方對應圖8所述的降低的閘極漏損電流。
圖6A-6C示出用於製造根據本發明的一範例實施例的具有自對準的凸出部的一閘極的製程。如圖6A所示,該裝置的基體結構是首先形成有一氮化鎵的基體層601、形成於該氮化鎵層601上的一氮化鋁鎵的阻絕層602,以及一 層P型閘極材料603形成於該阻絕層502上,於P型閘極材料603上,閘極金屬604沉積。
其次,如圖6B所示,一光阻605沉積且該閘極金屬604接著被蝕刻。該P型閘極材料603亦被以形成如圖6B所示的閘極結構的方式被蝕刻。如圖6C所示,該閘極金屬604接著被等向蝕刻,其使得閘極金屬具有小於P型閘極材料603的平坦上表面的寬度。此第二蝕刻步驟形成P型閘極材料603的凸出部506的型態。
最後,該製程包括移除電阻605的一步驟,圖未示出,並且形成如圖5所示具有自對準的凸出部的閘極。應被了解的是,用於汲極與源極接點的接點金屬可利用傳統的製程技術分開沉積,但其結構將不會如本文所描述的,因此不需要模糊本發明的目的。
圖7A-7B示出根據本發明的一範例實施例的一傳統電晶體閘極的一傳輸電子顯微(TEM)截面視圖的影像,以及具有一自對準凸出部的一閘極的X光截面視圖。圖8示出一曲線圖,比較本發明(如圖7B所示)的閘極漏損電流與傳統電晶體(如圖7A所示)的閘極漏損電流,由圖8可清楚地看到,當電晶體裝置處於ON狀態時,具有自對準的凸出部的閘極具有明顯較低於傳統不具有凸出部的閘極的閘極漏損電流。
最後,需注意的是,圖示於圖6A-6C的自對準製程大大的優於使用分離的遮罩形成閘極凸出部。在使用分離的遮罩的製程中,一光阻遮罩在P型閘極材料沉積於該裝 置的阻絕層後應用於未蝕刻的結構。於此狀況中,第一個遮罩用於圖案化並且蝕刻閘極金屬至一最小化臨界尺寸CD。一第二個遮罩接著用於圖案化並且蝕刻P型材料而形成一較閘極金屬寬的臨界尺寸CD。此兩遮罩製程的一個主要缺點在於閘極金屬與P型閘極材料之間不對齊的可能性。
前述的詳細說明與圖示僅為達成本案的特徵與優點的特定實施例的說明。修飾與置換特定的製程條件是可達成的,因此,本發明的實施例並不為前述說明與圖示所限制。
501‧‧‧氮化鎵基體層
502‧‧‧阻絕層
503‧‧‧P型閘極材料
504‧‧‧閘極金屬
505‧‧‧閘極電流路徑
506‧‧‧凸出部
510‧‧‧源極金屬
512‧‧‧汲極金屬

Claims (16)

  1. 一種增強模式氮化鎵電晶體,包含:一氮化鎵層;一阻絕層,設置於該氮化鎵層上,並具有一二維電子氣區形成於該氮化鎵層與該阻絕層之間的一介面處;一P型閘極材料,形成於該阻絕層上,該P型閘極材料具有延伸朝向該阻絕層的側面;以及一閘極金屬,設置於該P型閘極材料上,該閘極金屬具有延伸朝向該P型閘極材料的側壁,其中該P型閘極材料包含一對水平凸出部而其延伸通過該閘極金屬的各別側壁,該對水平凸出部具有分別由該閘極金屬的該等側壁至該P型閘極材料的該等側面之實質相等的寬度。
  2. 如請求項1所述的增強模式氮化鎵電晶體,更包含設置於該阻絕層上的一源極接點以及一汲極接點。
  3. 如請求項2所述的增強模式氮化鎵電晶體,其中該P型閘極材料的該對水平凸出部分別延伸朝向該源極接點與該汲極接點。
  4. 如請求項3所述的增強模式氮化鎵電晶體,其中該P型閘極材料的該等側面分別水平地延伸朝向該源極接點與該汲極接點,且與該阻絕層接觸。
  5. 如請求項1所述的增強模式氮化鎵電晶體,其中該P型閘 極材料的該對水平凸出部為自對準。
  6. 如請求項1所述的增強模式氮化鎵電晶體,其中該阻絕層包含氮化鋁鎵。
  7. 如請求項1所述的增強模式氮化鎵電晶體,其中該P型閘極材料具有一介於該P型閘極材料的側面之間的第一寬度,以及該閘極金屬具有一介於該閘極金屬的側壁之間的第二寬度,該第二寬度小於該第一寬度。
  8. 一種增強模式氮化鎵電晶體,包含:一氮化鎵層;一阻絕層,設置於該氮化鎵層上,並具有一二維電子氣區形成於該氮化鎵層與該阻絕層之間的一介面處;一源極接點與一汲極接點,設置於該阻絕層上;一P型閘極材料,形成於該阻絕層上並且介於該源極與該汲極接點之間;以及一閘極金屬,設置於該P型閘極材料上,其中,該P型閘極材料包含一對自對準的凸出部而其延伸通過該閘極金屬的側壁並且分別朝向該源極接點與該汲極接點。
  9. 如請求項8所述的增強模式氮化鎵電晶體,其中該P型閘極材料更包含分別水平地延伸朝向該源極接點與該汲極接點、且與該阻絕層接觸的側面。
  10. 如請求項8所述的增強模式氮化鎵電晶體,其中該阻絕層包含氮化鋁鎵。
  11. 如請求項8所述的增強模式氮化鎵電晶體,其中該對自對準的凸出部相對於該閘極金屬呈對稱。
  12. 一種製造一增強模式氮化鎵電晶體的方法,該方法包含:形成一氮化鎵層;形成一阻絕層於該氮化鎵層上;沉積一P型閘極材料於該阻絕層上;沉積一閘極金屬於該P型閘極材料上;形成一光阻於該閘極金屬上;蝕刻該閘極金屬與該P型閘極材料;以及等向蝕刻該閘極金屬,以形成在該P型閘極材料上、且在該閘極金屬下方的一對凸出部。
  13. 如請求項12所述的方法,其中等向蝕刻該閘極金屬的步驟包含:蝕刻該閘極金屬以減少該閘極金屬的寬度,使得該閘極金屬的寬度小於該P型閘極材料的寬度。
  14. 如請求項12所述的方法,更包含:沉積該等源極與汲極接點於該阻絕層上。
  15. 如請求項12所述的方法,其中蝕刻該P型材料的步驟包含:形成該P型閘極材料中之分別水平地延伸朝向該源極接點與該汲極接點、並且接觸該阻絕層的側面。
  16. 如請求項12所述的方法,其中該P型閘極材料的該對水平凸出部為自對準。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10186591B2 (en) 2015-06-26 2019-01-22 Toyota Jidosha Kabushiki Kaisha Nitride semiconductor device

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10401852B2 (en) * 2015-11-04 2019-09-03 Zoox, Inc. Teleoperation system and method for trajectory modification of autonomous vehicles
US20180088749A1 (en) * 2016-09-26 2018-03-29 Uber Technologies, Inc. Customized content generation for a user interface for a network service
US10339808B2 (en) * 2017-04-03 2019-07-02 Here Global B.V. Predicting parking vacancies based on activity codes
WO2018231928A1 (en) * 2017-06-15 2018-12-20 Efficient Power Conversion Corporation ENHANCEMENT-MODE GaN TRANSISTOR WITH SELECTIVE AND NONSELECTIVE ETCH LAYERS FOR IMPROVED UNIFORMITY IN GaN SPACER THICKNESS
TWI679770B (zh) 2018-12-26 2019-12-11 杰力科技股份有限公司 氮化鎵高電子移動率電晶體及其閘極結構
TWI680503B (zh) 2018-12-26 2019-12-21 杰力科技股份有限公司 氮化鎵高電子移動率電晶體的閘極結構的製造方法
CN109817710A (zh) * 2018-12-29 2019-05-28 英诺赛科(珠海)科技有限公司 高电子迁移率晶体管及其制造方法
CN109727863A (zh) * 2019-01-02 2019-05-07 北京大学深圳研究生院 一种基于自对准工艺的AlGan/GaN HEMT器件结构及制作方法
EP3686935A1 (en) 2019-01-23 2020-07-29 IMEC vzw Enhancement-mode high electron mobility transistor
US10818787B1 (en) 2019-04-18 2020-10-27 Semiconductor Components Industries, Llc Electronic device including a high electron mobility transistor including a gate electrode and a dielectric film
KR20210074871A (ko) 2019-12-12 2021-06-22 삼성전자주식회사 반도체 장치 및 그 제조 방법
US20230043312A1 (en) * 2020-01-24 2023-02-09 Rohm Co., Ltd. Method for manufacturing nitride semiconductor device and nitride semiconductor device
WO2021208020A1 (en) * 2020-04-16 2021-10-21 Innoscience (Zhuhai) Technology Co., Ltd. Semiconductor device and fabrication method thereof
CN111682066A (zh) * 2020-06-19 2020-09-18 英诺赛科(珠海)科技有限公司 具有改善栅极漏电流的半导体器件
EP4012782A1 (en) * 2020-12-08 2022-06-15 Imec VZW Method of manufacturing a iii-n enhancement mode hemt device
KR20240047218A (ko) * 2022-10-04 2024-04-12 삼성전자주식회사 반도체 소자 및 이의 제조 방법

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6773944B2 (en) * 2001-11-07 2004-08-10 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
KR100481871B1 (ko) * 2002-12-20 2005-04-11 삼성전자주식회사 플로팅 게이트를 갖는 비휘발성 기억 셀 및 그 형성방법
US6730552B1 (en) * 2003-06-26 2004-05-04 International Business Machines Corporation MOSFET with decoupled halo before extension
JP4866007B2 (ja) * 2005-01-14 2012-02-01 富士通株式会社 化合物半導体装置
JP4705412B2 (ja) * 2005-06-06 2011-06-22 パナソニック株式会社 電界効果トランジスタ及びその製造方法
US7915643B2 (en) * 2007-09-17 2011-03-29 Transphorm Inc. Enhancement mode gallium nitride power devices
US7939880B2 (en) 2008-04-15 2011-05-10 Freescale Semiconductor, Inc. Split gate non-volatile memory cell
TWI514568B (zh) * 2009-04-08 2015-12-21 Efficient Power Conversion Corp 增強模式氮化鎵高電子遷移率電晶體元件及其製造方法
JP2011142182A (ja) * 2010-01-06 2011-07-21 Sharp Corp 電界効果トランジスタ
US8895993B2 (en) 2011-01-31 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Low gate-leakage structure and method for gallium nitride enhancement mode transistor
JP5784440B2 (ja) 2011-09-28 2015-09-24 トランスフォーム・ジャパン株式会社 半導体装置の製造方法及び半導体装置
US8659059B2 (en) * 2011-12-30 2014-02-25 Stmicroelectronics, Inc. Strained transistor structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10186591B2 (en) 2015-06-26 2019-01-22 Toyota Jidosha Kabushiki Kaisha Nitride semiconductor device

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