TWI679770B - 氮化鎵高電子移動率電晶體及其閘極結構 - Google Patents

氮化鎵高電子移動率電晶體及其閘極結構 Download PDF

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TWI679770B
TWI679770B TW107147082A TW107147082A TWI679770B TW I679770 B TWI679770 B TW I679770B TW 107147082 A TW107147082 A TW 107147082A TW 107147082 A TW107147082 A TW 107147082A TW I679770 B TWI679770 B TW I679770B
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gallium nitride
layer
nitride layer
gate structure
electron mobility
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TW202025488A (zh
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劉莒光
Chu-Kuang Liu
楊弘堃
Hung-Kun Yang
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杰力科技股份有限公司
Excelliance Mos Corporation
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Priority to CN201910141573.9A priority patent/CN111370471B/zh
Priority to US16/362,704 priority patent/US10784336B2/en
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Abstract

一種氮化鎵高電子移動率電晶體的閘極結構，包括一異質結構、一摻雜氮化鎵層、一絕緣層、一未摻雜氮化鎵層以及一閘極金屬層。異質結構包括一通道層與位於所述通道層上的一阻障層。摻雜氮化鎵層位於所述阻障層上，絕緣層則位於摻雜氮化鎵層的頂部的兩側邊，且未摻雜氮化鎵層是位於摻雜氮化鎵層與絕緣層之間。閘極金屬層則位於摻雜氮化鎵層上，並覆蓋絕緣層與未摻雜氮化鎵層。所述未摻雜氮化鎵層能保護其下的摻雜氮化鎵層，而絕緣層則具有防止閘極漏電的效果。

Description

氮化鎵高電子移動率電晶體及其閘極結構
本發明是有關於一種高電子移動率電晶體的技術，且特別是有關於一種氮化鎵高電子移動率電晶體及其閘極結構。
氮化鎵高電子移動率電晶體（high electron mobility transistor，HEMT）是利用氮化鋁鎵（AlGaN）與氮化鎵（GaN）的異質結構，於接面處會產生具有高平面電荷密度和高電子遷移率的二維電子氣(two dimensional electron gas，2DEG)，因此適於高功率、高頻率和高溫度運作。
然而，具有高濃度2DEG的HEMT採用常關型（Normally-off）的電路設計，已發現這種氮化鎵高電子移動率電晶體有閘極漏電的問題，導致電晶體的開關在不正常的操作下效能下降或是失效，使可靠度降低。
本發明提供一種氮化鎵高電子移動率電晶體及其閘極結構，能大幅降低閘極漏電。
本發明的氮化鎵高電子移動率電晶體的閘極結構，包括一異質結構、一摻雜氮化鎵層、一絕緣層、一未摻雜氮化鎵層以及一閘極金屬層。異質結構包括一通道層與位於所述通道層上的一阻障層。摻雜氮化鎵層位於所述阻障層上，絕緣層則位於摻雜氮化鎵層的頂部的兩側邊，且未摻雜氮化鎵層是位於摻雜氮化鎵層與絕緣層之間。閘極金屬層則位於摻雜氮化鎵層上，並覆蓋絕緣層與未摻雜氮化鎵層。
在本發明的一實施例中，上述未摻雜氮化鎵層全面覆蓋於所述摻雜氮化鎵層上。
在本發明的另一實施例中，上述未摻雜氮化鎵層覆蓋部分所述摻雜氮化鎵層，而使所述閘極金屬層直接接觸所述摻雜氮化鎵層。
在本發明的一實施例中，上述摻雜氮化鎵層可為p型氮化鎵層或n型氮化鎵層。
在本發明的一實施例中，上述絕緣層的材料例如氮化矽（Si 3N 4）、氧化鋁（Al 2O 3）、氧化矽（SiO 2）、氮化硼（BN）或氮化鋁（AlN）。
在本發明的一實施例中，上述絕緣層的面積佔所述摻雜氮化鎵層的頂部的面積比例約在50%以下。
在本發明的一實施例中，上述摻雜氮化鎵層的底部的面積可大於或等於所述頂部的面積。
在本發明的一實施例中，上述未摻雜氮化鎵層的厚度例如小於200埃。
在本發明的一實施例中，上述閘極金屬層的側面可與上述絕緣層的側面對齊。
在本發明的一實施例中，上述通道層的材料例如氮化鎵（GaN）以及上述阻障層的材料例如氮化鋁鎵（AlGaN）。
本發明的氮化鎵高電子移動率電晶體具有上述閘極結構。
基於上述，本發明藉由設置於閘極金屬層兩側底部的絕緣層，能阻隔閘極側邊的漏電流，並可於絕緣層與摻雜氮化鎵層之間設置未摻雜氮化鎵層，來保護摻雜氮化鎵層，確保其功效。因此，本發明的閘極結構能提升氮化鎵高電子移動率電晶體的可靠度。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
以下實施例中所附的圖式是為了能更完整地描述發明概念的示範實施例，但是，仍可使用許多不同的形式來實施本發明，且其不應該被視為受限於所記載的實施例。在圖式中，為了清楚起見，膜層、區域及/或結構元件的相對厚度及位置可能縮小或放大。
圖1A是依照本發明的第一實施例的一種氮化鎵高電子移動率電晶體之閘極結構的剖面示意圖。
請參照圖1A，第一實施例的閘極結構包括具有通道層102與阻障層104的一異質結構100、一摻雜氮化鎵層106、一絕緣層108、一未摻雜氮化鎵層110以及一閘極金屬層112。在異質結構100中，於通道層102與阻障層104之間的界面處可形成二維電子氣(2DEG)103。摻雜氮化鎵層106則位於阻障層104上、阻障層104位於通道層102上，其中通道層102的材料例如氮化鎵（GaN），阻障層104的材料例如氮化鋁鎵（AlGaN），而作為閘極的摻雜氮化鎵層106可以是p型氮化鎵層或n型氮化鎵層。摻雜氮化鎵層106的底部106b的面積約等於（或大於）頂部106a的面積，但本發明並不限於此。絕緣層108則位於摻雜氮化鎵層106的頂部106a的兩側邊，其中絕緣層108的材料例如氮化矽（Si 3N 4）、氧化鋁（Al 2O 3）、氧化矽（SiO 2）、氮化硼（BN）或氮化鋁（AlN），但本發明並不限於此。在一實施例中，絕緣層108的面積佔摻雜氮化鎵層106的頂部106a的面積比例約在50%以下，例如在30%以下或者在20%以下。由於絕緣層108的效果在於利用其自身的高阻值（resistance）來斷絕閘極金屬層112的側壁漏電，所以本發明的絕緣層108的位置設置在摻雜氮化鎵層106的頂部106a的兩側邊即可確保降低閘極漏電的效果，至於絕緣層108的面積佔比則以不影響元件操作為準，故不限於上述範圍。在一實施例中，閘極金屬層112的側面112a可與絕緣層108的側面108a對齊；或者閘極金屬層112的側面112a也可略為內縮，而不與絕緣層108的側面108a對齊。
請繼續參照圖1A，本實施例的未摻雜氮化鎵層110是位於摻雜氮化鎵層106與絕緣層108之間，並且僅覆蓋部分摻雜氮化鎵層106，所以位於摻雜氮化鎵層106上的閘極金屬層112可直接接觸摻雜氮化鎵層106，並覆蓋絕緣層108與未摻雜氮化鎵層110。未摻雜氮化鎵層110能保其下方的摻雜氮化鎵層106。另外，雖然圖1A中並未繪出，但應知異質結構100一般可藉由磊晶技術（如MBE或MOCVD）在基板（未繪示）上依序成長，且若是基板為藍寶石（Sapphire）、碳化矽（SiC）、氧化鋅（ZnO）、矽（Si）、氧化鎵（Ga 2O 3）等材料，還可在成長異質結構100之前，先在基板上成長用來減低基板與通道層102之間晶格不匹配問題的單層或多層的緩衝結構（未繪示）。
圖1B是第一實施例的另一種氮化鎵高電子移動率電晶體之閘極結構的剖面示意圖。
在圖1B中，未摻雜氮化鎵層110是全面覆蓋於摻雜氮化鎵層106上，其中未摻雜氮化鎵層110的厚度t例如小於200埃。由於未摻雜氮化鎵層110全面覆蓋於摻雜氮化鎵層106表面，因此能進一步保護摻雜氮化鎵層106不受後續閘極金屬製程的影響與破壞。
圖2是依照本發明的第二實施例的一種氮化鎵高電子移動率電晶體之閘極結構的剖面示意圖，其中使用與圖1A相同的元件符號來代表相同或相似的構件，且所省略的部分技術說明，如各層或區域的位置、尺寸、材料、摻雜與否、功能等均可參照圖1A的內容，因此於下文不再贅述。
在圖2中，摻雜氮化鎵層200的底部200b的面積大於頂部200a的面積，所以與第一實施例相比，摻雜氮化鎵層200的側面200c可供漏電的路徑變長，所以能進一步減少閘極漏電。此外，與第一實施例相比，摻雜氮化鎵層200的頂部200a面積變小，則絕緣層108的面積佔比可能會增加；或者，絕緣層108的面積變小。然而，本發明並不限於此。
圖3是圖1A的結構應用於一種氮化鎵高電子移動率電晶體的剖面示意圖，其中使用與圖1A相同的元件符號來代表相同或相似的構件。
請參照圖3，氮化鎵高電子移動率電晶體300可包括第一實施例的閘極結構、源極304a、汲極304b以及覆蓋異質結構100、摻雜氮化鎵層106、絕緣層108、未摻雜氮化鎵層110以及閘極金屬層112的鈍化層302。鈍化層302可用以緩解應力，其材料例如氮化矽或氧化矽。而源極304a與汲極304b則分別形成於閘極金屬層112的兩側，並與阻障層104直接接觸；但本發明並不限於此，在另一實施例中，源極304a與汲極304b可穿過阻障層104而與通道層102直接接觸。
綜上所述，本發明在閘極金屬層兩側底部設置絕緣層與未摻雜氮化鎵層，不但能阻隔閘極側邊的漏電流，還能藉由未摻雜氮化鎵層保護作為閘極的摻雜氮化鎵層，以確保其功效，進而提升氮化鎵高電子移動率電晶體的可靠度。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100‧‧‧異質結構
102‧‧‧通道層
103‧‧‧二維電子氣
104‧‧‧阻障層
106、200‧‧‧摻雜氮化鎵層
106a、200a‧‧‧頂部
106b、200b‧‧‧底部
108‧‧‧絕緣層
108a、112a、200c‧‧‧側面
110‧‧‧未摻雜氮化鎵層
112‧‧‧閘極金屬層
300‧‧‧氮化鎵高電子移動率電晶體
302‧‧‧鈍化層
304a‧‧‧源極
304b‧‧‧汲極
t‧‧‧厚度
圖1A是依照本發明的第一實施例的一種氮化鎵高電子移動率電晶體之閘極結構的剖面示意圖。 圖1B是第一實施例的另一種氮化鎵高電子移動率電晶體之閘極結構的剖面示意圖。 圖2是依照本發明的第二實施例的一種氮化鎵高電子移動率電晶體之閘極結構的剖面示意圖。 圖3是包括圖1A的閘極結構的一種氮化鎵高電子移動率電晶體的剖面示意圖。

Claims (10)

  1. 一種氮化鎵高電子移動率電晶體的閘極結構，包括：一異質結構，包括一通道層與位於所述通道層上的一阻障層；一摻雜氮化鎵層，位於所述阻障層上；一絕緣層，位於所述摻雜氮化鎵層的頂部的兩側邊；一未摻雜氮化鎵層，位於所述摻雜氮化鎵層與所述絕緣層之間；以及一閘極金屬層，位於所述摻雜氮化鎵層上，並覆蓋所述絕緣層與所述未摻雜氮化鎵層，其中所述閘極金屬層的側面與所述絕緣層的側面對齊。
  2. 如申請專利範圍第1項所述的氮化鎵高電子移動率電晶體的閘極結構，其中所述未摻雜氮化鎵層全面覆蓋於所述摻雜氮化鎵層上。
  3. 如申請專利範圍第1項所述的氮化鎵高電子移動率電晶體的閘極結構，其中所述未摻雜氮化鎵層覆蓋部分所述摻雜氮化鎵層，而使所述閘極金屬層直接接觸所述摻雜氮化鎵層。
  4. 如申請專利範圍第1項所述的氮化鎵高電子移動率電晶體的閘極結構，其中所述摻雜氮化鎵層為p型氮化鎵層或n型氮化鎵層。
  5. 如申請專利範圍第1項所述的氮化鎵高電子移動率電晶體的閘極結構，其中所述絕緣層的材料包括氮化矽、氧化鋁、氧化矽、氮化硼或氮化鋁。
  6. 如申請專利範圍第1項所述的氮化鎵高電子移動率電晶體的閘極結構，其中所述絕緣層的面積佔所述摻雜氮化鎵層的所述頂部的面積比例在50%以下。
  7. 如申請專利範圍第1項所述的氮化鎵高電子移動率電晶體的閘極結構，其中所述摻雜氮化鎵層的底部的面積大於或等於所述頂部的面積。
  8. 如申請專利範圍第1項所述的氮化鎵高電子移動率電晶體的閘極結構，其中所述未摻雜氮化鎵層的厚度小於200埃。
  9. 如申請專利範圍第1項所述的氮化鎵高電子移動率電晶體的閘極結構，其中所述通道層的材料包括氮化鎵以及所述阻障層的材料包括氮化鋁鎵。
  10. 一種氮化鎵高電子移動率電晶體，包括如申請專利範圍第1~9項中任一項所述的閘極結構。
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